Semiconductor component and method for forming a semiconductor component

Abstract

Semiconductor component, comprising: a gate trench (206a, 206b) in a semiconductor substrate (201); a source trench (204) in the semiconductor substrate (201), wherein the source trench (204) has a first section (204a) and a second section (204b) below the first section (204a), wherein the first section (204a) of the source trench (204) has a width (205a) and the second section (204b) of the source trench (204) has a width (205b) that is narrower than the width (205a) of the first section (204a), and wherein the first section (204a) of the source trench (204) extends to a depth of the gate trench (206a, 206b); wherein the first section (204a) of the source trench (204) is wider than the gate trench (206a, 206b); and a conductive fill material (216) and a dielectric source trench lining (214) in the source trench (204).

Description

BACKGROUND

[0001] Power semiconductor devices, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), are widely used in power switching devices, such as power supplies, rectifiers, motor control units, etc. Power semiconductor devices can be designed with a trench topology to increase power density.

[0002] Conventional trench-type power semiconductor manufacturing processes often employ multiple masks to enable the formation of complex structures, such as gate and source trenches. Using multiple masks to etch adjacent source and gate trenches of varying dimensions in different steps can be challenging due to errors introduced by mask dimensions and orientation at each masking step. Furthermore, variations in semiconductor manufacturing can often lead to variations in the device's electrical behavior, such as one-state resistance (RDS(on)). DSon ) and breakdown voltage.

[0003] US 2015 / 0 214 355 A1, US 2006 / 0 060 916 A1, US 2011 / 0291 186 A1 and US 2010 / 0 308 400 A1 each disclose a semiconductor device with a gate trench and a source trench of constant width in the semiconductor material.

[0004] Accordingly, there is a need to overcome the disadvantages and weaknesses of the state of the art by providing a manufacturing process that can essentially avoid component defects during the manufacturing of trench-type power semiconductor devices, while improving their electrical performance. BRIEF SUMMARY OF THE INVENTION

[0005] The present invention relates to a method according to claim 13 or 29, which enables combined gate and source trench formation, and a semiconductor device according to claim 1 or claim 21. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a flowchart illustrating a method for forming a semiconductor structure according to an implementation of the present application. Fig. Figure 2A illustrates a cross-sectional view of a section of a semiconductor structure, which follows an initial action in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2B illustrates a cross-sectional view of a section of a semiconductor structure, which is constructed according to an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2C illustrates a cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. 2D illustrates a perspective cross-sectional view of a section of a semiconductor structure, which corresponds to an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2E illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2F illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2G illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2H illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2I illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate action in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2J illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2K illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate action in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2L illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. 2M illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate step in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. 2N illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows an intermediate action in the flowchart of Fig. 1 is processed according to an implementation of the present application. Fig. Figure 2O illustrates a perspective cross-sectional view of a section of a semiconductor structure, which follows a concluding action in the flowchart of Fig. 1 is processed according to an implementation of the present application. DETAILED DESCRIPTION

[0006] Fig. Figure 1 shows a flowchart illustrating an exemplary method for forming an exemplary semiconductor device according to an implementation of the present application. Certain details and features that are obvious to the person skilled in the art have been omitted from the flowchart. For example, an action may consist of one or more sub-actions or may involve specialized equipment or materials, as is known to the person skilled in the art. Actions 170, 172, 174, 176, 178, 180, 182, 184, 186, 188, 190, 192, 194, 196, and 198, which are shown in flowchart 100, are sufficient to describe one implementation of the present inventive concepts. Other implementations of the present inventive concepts may use different actions than those shown in flowchart 100.Furthermore, the semiconductor structures 270, 272, 274, 276, 278, 280, 282, 284, 286, 288, 290, 292, 294, 296 and 298 illustrate the . Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 21, Fig. 2 years Fig. 2K, Fig. 2L, Fig. 2M, Fig. 2N and Fig. 2O the results of performing actions 170, 172, 174, 176, 178, 180, 182, 184, 186, 188, 190, 192, 194, 196, and 198 of flowchart 100, respectively. For example, semiconductor structure 270 is an exemplary structure of a section of a semiconductor device after processing action 170. Semiconductor structure 272 is an exemplary structure of a section of a semiconductor device after processing action 172, semiconductor structure 284 is an exemplary structure of a section of a semiconductor device after processing action 174, and so on.

[0007] We turn to Act 170 in Fig. 1 and the semiconductor structure 270 in Fig. 2A. Action 170 involves forming a structured photoresist mask over a semiconductor substrate. We turn to Fig. 2A. Semiconductor structure 270 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 170 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2A, the semiconductor structure 270 contains a structured photoresist mask 250 over the semiconductor substrate 201.

[0008] As in Fig. As illustrated in Figure 2A, the semiconductor substrate 201 contains a drift region 202 and a drain region 222. The semiconductor substrate 201 can contain any suitable semiconductor material, such as silicon. The drift region 202 is located above the drain region 222, which is located above the drain contact layer 242. In the present implementation, the drain region 222 contains a heavily doped semiconductor material as a drain of a semiconductor device, such as a power MOSFET or an insulated-electrode bipolar transistor (IGBT). As shown in Figure 2A, the drift region 202 is located above the drain region 222, which is located above the drain contact layer 242. Fig. As illustrated in Figure 2A, the drain region 222 is of a first conductivity type and is shown to have, for example, a conductivity of N+. In the present implementation, the drain region 222 can contain an N-type dopant, such as phosphorus or arsenic. In another implementation, the drain region 222 can contain a P-type dopant, such as boron. The drain contact layer 242 is formed at the bottom of the drain region 222.

[0009] The drift region 202 can contain any suitable semiconductor material that can be epitaxially grown on the drift region 202 (for example, an epitaxial layer). For example, the drift region 202 can contain epitaxial silicon grown on the drain region 222. As in Fig. As illustrated in Figure 2A, drift region 202 is of the first conductivity type and is shown to have, for example, a conductivity of N. In one implementation, drift region 202 can be intrinsically an N-type material, or it can be pre-doped to an N-type material, or it can be subsequently doped to an N-type material. In the present implementation, drift region 202 can contain an N-type dopant, such as phosphorus or arsenic. In another implementation, drift region 202 can contain a P-type dopant, such as boron.

[0010] As in Fig. As illustrated in Figure 2A, the structured photoresist mask 250 comprises a first masking layer (for example, a contact island oxide layer) 250a, a second masking layer (for example, a nitride-based layer) 250b, and a third masking layer (for example, an oxide-based layer) 250c. The first masking layer 250a, the second masking layer 250b, and the third masking layer 250c can be formed sequentially over the semiconductor substrate 201. For example, the first masking layer 250a can be formed on the semiconductor substrate 201 by deposition or thermal oxidation. The second masking layer 250b can be formed on the first masking layer 250a by deposition or nitriding. The third masking layer 250c can then be formed on the second masking layer 250b by deposition or thermal oxidation.The thickness of each of the first masking layer 250a, the second masking layer 250b, and the third masking layer 250c can be adapted to the specific requirements of a particular application. Subsequently, the first masking layer 250a, the second masking layer 250b, and the third masking layer 250c can be applied using a trench mask (in . Fig. 2A not explicitly shown) are structured to form a structured photoresist mask 250.

[0011] We turn to Act 172 in Fig. 1 and the semiconductor structure 272 in Fig. 2B. Action 172 involves forming a gate trench and the first section of a source trench to a first depth into the semiconductor substrate. We turn to Fig. 2B. Semiconductor structure 272 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 172 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2B, the semiconductor structure contains 272 gate trenches 206a and 206b and a first section 204a of the source trench 204, which has a depth 203a into the drift region 202 of the semiconductor substrate 201.

[0012] In the present implementation, gate trenches 206a and 206b and a first section 204a of the source trench 204 can be formed by etching the unmasked regions (for example, the regions not covered by the structured photoresist mask 250) of the drift region 202, for example, using anisotropic etching. It should be noted that, unlike a conventional trench-type semiconductor device fabrication process where source trenches are formed after conductive gate-filling materials have been formed in gate trenches, implementations of the present application use a single photolithography masking step to etch both the gate and source trenches in a single-pass trenching process.Because the source and gate trenches are formed in a single processing operation, misalignments between the gate and source trenches can be effectively avoided, allowing for smaller center-to-center distances between cells and a higher cell density.

[0013] As in Fig. As illustrated in Figure 2B, Gate Trenches 206a and 206b and Source Trench 204 extend into Drift Region 202. Each of Gate Trenches 206a and 206b, and the first section 204a of Source Trench 204, essentially contain parallel sidewalls extending into a bottom. In the present implementation, Gate Trenches 206a and 206b, and the first section 204a of Source Trench 204, each contain a U-shaped bottom. In another implementation, Gate Trenches 206a and 206b, and the first section 204a of Source Trench 204, could each contain sloping sidewalls and / or a flat bottom.

[0014] As in Fig. As illustrated in Figure 2B, in the present implementation, the first section 204a of the source trench 204 extends to a depth 203a of the gate trenches 206a and 206b. In another implementation, the first section 204a of the source trench 204 may extend to a depth greater or lesser than the depth 203a of the gate trenches 206a and 206b. It should be noted that the first section 204a of the source trench 204 has a width 205a that is significantly wider than the width 207 of the gate trenches 206a and 206b, where the width 205a and the width 207 are defined by the respective openings in the structured photoresist mask 250 formed in Act 170.

[0015] In the present implementation, the gate trenches 206a and 206b and the source trench 204 can have a strip-like layout, with the gate trenches 206a and 206b and the source trench 204 running essentially parallel to each other in the semiconductor substrate 201. In another implementation, the gate trenches 206a and 206b and the source trench 204 can have a cellular layout, with the gate trenches 206a and 206b forming parts of a continuous cellular trench surrounding the source trench 204 at its center.

[0016] We turn to Act 174 in Fig. 1 and the semiconductor structure 274 in Fig. 2C. Act 174 involves forming a dielectric gate-trough lining in the gate trench and the first section of the source trench. We turn to Fig. 2C to. Semiconductor structure 274 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 174 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2C, the semiconductor structure 274 includes a dielectric gate-trough lining 208 over the structured photoresist mask 250, in gate-troughs 206a and 206b, and in the first section 204a of source-trough 204. The dielectric gate-trough lining 208 lines the respective side walls and bottom of gate-troughs 206a and 206b. The dielectric gate-trough lining 208 is also formed in the first section 204a of source-trough 204, where it lines the side walls and bottom of the first section 204a. In the present implementation, the dielectric gate-trough lining 208 contains silicon dioxide (for example, SiO2). In other implementations, the dielectric gate-trough lining 208 can contain any other suitable dielectric material.

[0017] We turn to Act 176 in Fig. 1 and the semiconductor structure 276 in Fig. 2D to. Action 176 involves forming a conductive gate trench filler material in the gate trench and on the side walls and floor of the first section of the source trench. We turn to Fig. 2D to. Semiconductor structure 276 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 176 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in 2D, the semiconductor structure 276 contains a conductive gate-trough filler material 210 above the structured photoresist mask 250, in the gate trenches 206a and 206b, and on the side walls and bottom of the first section 204a of the source trench 204. The conductive gate-trough filler material 210 fills the entire space in each of the gate trenches 206a and 206b. In contrast, the conductive gate-trough filler material 210 does not fill the entire space in the first section 204a of the source trench 204 because the first section 204a of the source trench 204 is significantly wider than the gate trenches 206a and 206b.Instead, the conductive gate-trough filler material 210 lines only the side walls and bottom of the first section 204a of the source trench 204, making the subsequent removal of the conductive gate-trough filler material 210 from the first section 204a of the source trench 204 significantly easier and faster than removing a conductive gate-trough filler material from a completely filled source trench. In the present implementation, the conductive gate-trough filler material 210 contains doped polycrystalline silicon. In another implementation, a conductive gate-trough filler material 210 can contain any suitable conductive material, such as metallic material.

[0018] We turn to Act 178 in Fig. 1 and the semiconductor structure 278 in Fig. 2E. Action 178 involves forming a gate electrode in the gate trench by removing excess sections of the conductive gate trench filler material. We turn to Fig. 2E to. Semiconductor structure 278 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 178 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2E, the semiconductor structure 278 contains gate electrodes 210a and 210b in the gate grooves 206a and 206b, respectively. The excess sections of the conductive gate-trough filler material 210 on the structured photoresist mask 250, over the gate grooves 206a and 206b, and in the first section 204a of the source groove 204, are removed by a back-etching process, such as gate poly back-etching. It should be noted that in the present implementation, due to the presence of the structured photoresist mask 250 during the back-etching process, no additional mask is used, thus saving manufacturing costs and time.

[0019] We turn to Act 180 in Fig. 1 and the semiconductor structure 280 in Fig. 2F to. Action 180 involves the formation of a dielectric gate-trench capping layer over the gate trenches and in the first section of the source trench. We turn to Fig. 2F to. Semiconductor structure 280 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 180 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2F, the semiconductor structure 280 contains a dielectric gate-trench capping layer 212 over the structured photoresist mask 250, over the gate trenches 206a and 206b, and in the first section 204a of the source trench 204. A dielectric gate-trench capping layer 212 fills the entire space in the openings between the structured photoresist mask 250 over each of the gate trenches 206a and 206b. In contrast, a dielectric gate-trench capping layer 212 does not fill the entire space in the first section 204a of the source trench 204 because the first section 204a of the source trench 204 is significantly wider than the gate trenches 206a and 206b. Instead, a dielectric gate-trough capping layer 212 lines only the side walls and the bottom of the first section 204a of the source trench 204. The dielectric gate-trough capping layer 212 contains any suitable dielectric material, such as silicon dioxide or boron phosphate silicate glass (BPSG).

[0020] We turn to Act 182 in Fig. 1 and the semiconductor structure 282 in Fig. 2G to. Action 182 involves removing the dielectric gate-trough capping layer and the dielectric gate-trough lining from the first section of the source trench. We turn to Fig. 2G to. Semiconductor structure 282 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 182 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2G, the semiconductor structure 282 undergoes a breakdown back-etch, whereby sections of the dielectric gate-trough capping layer 212 and the dielectric gate-trough lining 208C are removed from the first section 204a of the source trench 204. As shown in Fig. As can be seen in Figure 2G, sections of the dielectric gate-trench capping layer 212 above the structured photoresist mask 250 and the gate trenches 206a and 206b are also partially removed as a result of the breakthrough back-etching. In the present implementation, a breakthrough oxide back-etching can be performed to remove the sections of the dielectric gate-trench capping layer 212 and the dielectric gate-trench lining 208C of the first section 204a of the source trench 204. As shown in Figure 2G, the dielectric gate-trench capping layer 212 above the structured photoresist mask 250 and the gate trench trenchments 206a and 206b are also partially removed as a result of the breakthrough back-etching. Fig. As can be seen in step 2G, after the breakdown etching in step 182, the drain region 202 of the semiconductor substrate 201 in the first section 204a of the source trench 204 is exposed. In another implementation, the side walls and bottom of the first section 204a of the source trench 204 can be lined with residual dielectric gate trench lining 208c.

[0021] We turn to Act 184 in Fig. 1 and the semiconductor structure 284 in Fig. 2H to. Act 184 involves the formation of a second section of the Source Trench beneath the first section. We turn to Fig. 2H to. Semiconductor structure 284 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 184 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2H, the semiconductor structure 284 contains the source trench 204, which has a second section 204b below the first section 204a in the drift region 202. In the present implementation, the second section 204b of the source trench 204 can be formed by etching the drift region 202, for example, using anisotropic etching. It should be noted that the second section 204b of the source trench 204 below the first section 204a can be formed essentially without misalignment, since the first section 204a of the source trench 204 is formed in Act 172 along with the gate trenches 206a and 206b.

[0022] As in Fig. As illustrated in Figure 2H, the second section 204b of the source trench 204 extends into the drift region 202 and essentially contains parallel sidewalls that extend into a bottom. In the present implementation, the second section 204b of the source trench 204 has a U-shaped bottom. In another implementation, the second section 204b of the source trench 204 may contain sloping sidewalls and / or a flat bottom.

[0023] As in Fig. As illustrated in Figure 2H, in the present implementation, the first section 204a of the source trench 204 extends to a depth of 203a of the gate trenches 206a and 206b into the drift region 202. The second section 204b of the source trench 204 extends further into the drift region 202 to a depth of 203b below depth 203a. The depth 203b of the second section 204b is significantly greater than the depth 203a of the first section 204a. The first section 204a of the source trench 204 has a width of 205a, while the second section 204b of the source trench 204 has a width of 205b, which is narrower than the width 205a.

[0024] We turn to Act 186 in Fig. 1 and the semiconductor structure 286 in Fig. 2I to. Act 186 involves the formation of a dielectric source trench lining in the source trench. We turn to Fig. 2I to. Semiconductor structure 286 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 186 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2I, the semiconductor structure 286 contains the dielectric source-trough lining 214 in the source-trough 204 and above the dielectric gate-trough capping layer 212. The dielectric source-trough lining 214 lines the sidewalls of the first section 204a and the sidewalls and bottom of the second section 204b. In the present implementation, the dielectric source-trough lining 214 contains tetraethyl orthosilicate (TEOS). In other implementations, the dielectric source-trough lining 214 may contain another suitable dielectric material, such as silicon oxide or silicon nitride.

[0025] We turn to Act 188 in Fig. 1 and the semiconductor structure 288 in Fig. 2J to. Act 188 involves training a conductive Source Trench filler in the Source Trench. We turn to Fig. 2J to. Semiconductor structure 288 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 188 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2J, the semiconductor structure 288 contains the conductive source-trough filler material 216 in the source-trough 204 and above the dielectric source-trough lining 214. The conductive source-trough filler material 216 fills the entire space in the first section 204a and the second section 204b of the source-trough 204. In the present implementation, the conductive source-trough filler material 216 contains doped polycrystalline silicon. In another implementation, a conductive gate-trough filler material 210 can contain any suitable conductive material, such as a metallic material.

[0026] We turn to Act 190 in Fig. 1 and the semiconductor structure 290 in Fig. 2K to. Action 190 involves planarizing the conductive source-trench filling material of the dielectric source-trench lining with the second masking layer of the structured photoresist mask. We turn to Fig. 2K to. Semiconductor structure 290 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 190 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2K, the semiconductor structure 290 contains the conductive source-trough filler material 216 and the dielectric source-trough lining 214 in the source-trough 204, the gate electrode 210a and the dielectric gate-trough lining 208a in the gate-trough 206a, and the gate electrode 210b and the dielectric gate-trough lining 208b in the gate-trough 206b. The semiconductor structure 290 also contains the dielectric gate-trough cap 212a over the gate-trough 206a and the dielectric gate-trough cap 212b over the gate-trough 206b. As shown in Fig. As illustrated in Figure 2K, excess sections of the conductive source-trough filler material 216 of the dielectric source-trough lining 214, the dielectric gate-trough cap layer 212, and the third masking layer (for example, an oxide-based layer) 250c of the structured photoresist mask 250 are removed, for example, by chemical-mechanical polishing (CMP). As a result, the conductive source-trough filler material 216, the dielectric source-trough lining 214, the dielectric gate-trough caps 212a and 212b, and the second masking layer 250b have a coplanar top surface.

[0027] We turn to Act 192 in Fig. 1 and the semiconductor structure 292 in Fig. 2L to. Action 192 involves removing the second masking layer of the photoresist mask. We turn to Fig. 2L to. Semiconductor structure 292 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 192 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2L, the second masking layer (for example, a nitride-based layer) 250b in the semiconductor structure 290 is removed, for example, by etching, such that an opening is formed between the dielectric gate trench cap 212a and the source trench 204 for a contact trench to be formed subsequently. Similarly, another opening is formed between the source trench 204 and the dielectric gate trench cap 212b for a contact trench to be formed subsequently.

[0028] We turn to Act 194 in Fig. 1 and the semiconductor structure 294 in Fig. 2M to. Action 194 includes forming a base region and a source region in the semiconductor substrate, forming a conformal spacer layer over the gate trench and the source trench, and forming the source-trough sidewall spacers and the gate-trough sidewall spacers. We turn Fig. 2M to. Semiconductor structure 294 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 194 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2M, the semiconductor structure 294 includes a base region 218 and a source region 220 in the semiconductor substrate 201 above the drift region 202. The semiconductor structure 294 also includes a conformal spacer layer 224, which covers the first masking layer (for example, a contact island oxide layer) 250a, dielectric gate trench caps 212a and 212b, the dielectric source trench lining 214, and the conductive source trench filler 216. Furthermore, the semiconductor structure 294 includes gate-trough sidewall spacers 226a and 226b above the gate-trough 206a, source-trough sidewall spacers 228a and 228b above the source-trough 204, and gate-trough sidewall spacers 226c and 226d above the gate-trough 206b.

[0029] In the present implementation, the base region 218 can be formed by implanting a channel dopant into the semiconductor substrate 201. For example, the base region 218 is located between the gate groove 206a and the source groove 204, and between the source groove 204 and the gate groove 206b. In the present implementation, the base region 218 is of the second conductivity type and is shown to have, for example, a conductivity of ¹³P. In the present implementation, the base region 218 can contain a ¹³P dopant, such as boron. In another implementation, the base region 218 can contain an ¹⁰N dopant, such as phosphorus or arsenic. For example, a P-type dopant, such as boron ions, can be inserted through the first masking layer (for example, a contact island oxide layer) 250a and implanted into the semiconductor substrate 201.In other implementations, N-type dopant materials and other suitable implantation techniques can be used to form the basal region 218. The implantation energy and dopant concentration can vary based on the specific requirements of a particular application.

[0030] A source dopant is then implanted through the first masking layer (for example, a contact island oxide layer) 250a and into the semiconductor substrate 201 to form a source region 220 above the base region 218. For example, the source region 220 is located between the gate trench 206a and the source trench 204, and between the source trench 204 and the gate trench 206b, above the base region 218. In the present implementation, the source region 220 is of the first conductivity type and is shown to have, for example, a conductivity of N+. In the present implementation, the source region 220 can contain an N-type dopant, such as phosphorus or arsenic. In another implementation, the source region 220 can contain a P-type dopant, such as boron.For example, an N-type dopant, such as phosphorus or arsenic, can be implanted through the first masking layer (for example, a contact island oxide layer) 250a and into the semiconductor substrate 201. In other implementations, P-type dopant materials and other suitable implantation methods can be used to form the source region 220. The implantation energy and dopant concentration can be varied based on the specific requirements of a particular application.

[0031] As in Fig. As illustrated in Figure 2M, a conformal spacer layer 224 is formed over the first masking layer (for example, a contact island oxide layer) 250a, the dielectric gate trench caps 212a and 212b, the dielectric source trench filler 214, and the conductive source trench filler 216. In this implementation, the conformal spacer layer 224 contains dielectric material, such as silicon oxide. The conformal spacer layer 224 can be formed using any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or evaporation. The gate trench sidewall spacers 226a and 226b are formed along the sidewalls of the conformal spacer layer 224 over the gate trench 206a.The source-trough sidewall spacers 228a and 228b are formed along the sidewalls of the conformal spacer layer 224 above the source-trough 204. The gate-trough sidewall spacers 226c and 226d are formed along the sidewalls of the conformal spacer layer 224 above the gate-trough 206b.

[0032] We turn to Act 196 in Fig. 1 and the semiconductor structure 296 in Fig. 2N to. Action 196 involves removing sections of the conformal spacer layer to expose the conductive source trench filler and form a contact trench. We turn to Fig. 2N to. Semiconductor structure 296 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 196 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2N, the semiconductor structure 296 includes a contact trench 229a between the gate trench 206a and the source trench 204, and a contact trench 229b between the source trench 204 and the gate trench 206b. An oxide back-etch can be performed to remove sections of a conformal spacer layer 224 and expose the conductive source trench filler material 216 on its top surface. Then, a contact etch can be performed to form contact trenches 229a and 229b by etching through the conformal spacer layer 224, the first masking layer (for example, a contact island oxide layer) 250a, and the source region 220, and into the base region 218. The contact trench 229a is self-aligning between the gate trench 206a and the source trench 204, while the contact trench 229b is self-aligning between the source trench 204 and the gate trench 206b.

[0033] As a result of the single-photolithography masking operation employed during the fabrication process according to implementations of the present application, the source trench 204 is spaced such that it is essentially centered between adjacent gate trenches 206a and 206b. Consequently, the contact trenches 229a and 229b between the respective gate and source trenches are self-aligning. The subsequently formed body contacts and source contacts in the respective contact trenches 229a and 229b are, in turn, also self-aligning between the respective gate and source trenches. This self-alignment process means that the source and body contacts are not constrained by conventional fabrication processes, such as photolithography, and can have reduced widths, thereby increasing the cell density.

[0034] We turn to Act 198 in Fig. 1 and the semiconductor structure 298 in Fig. 20 to. Action 198 involves establishing body contact and source contact in the contact trench. We turn to Fig. 20 to. Semiconductor structure 298 illustrates a cross-sectional view of a section of a semiconductor structure after completion of action 198 in flowchart 100 of Fig. 1 according to an implementation of the present disclosure. As in Fig. As illustrated in Figure 2O, the semiconductor structure contains 298 body contacts 232a and 232b in contact grooves 229a and 229b respectively.

[0035] As in Fig. As illustrated in Figure 20, the semiconductor structure 298 contains the semiconductor substrate 201, which has the drain region 222, the drift region 202, the base region 218, the source region 220, the source contact 230, and body contacts 232a and 232b. The semiconductor structure 298 also contains the source trench 204, which has the first section 204a and the second section 204b, and the gate trenches 206a and 206b in the semiconductor substrate 201. The source trench 204 extends through the base region 218 and into the drift region 202. The gate trenches 206a and 206b also extend through the base region 218 and into the drift region 202. As shown in Figure 20, the semiconductor structure 298 contains the source trench 204, which has the first section 204a and the second section 204b, and the gate trenches 206a and 206b. Fig. As illustrated in Figure 20, the body contacts 232a and 232b are located near a top surface of the semiconductor substrate 201. The source region 220 is also located near the top surface of the semiconductor substrate 201. The semiconductor structure 298 also includes the drain contact layer 242, which is coupled to the drain region 222, and the source contact 230, which is coupled to the source region 220, body contacts 232a and 232b, and the conductive source-trough filler material 216 in the source-trough 204.

[0036] As in Fig. As illustrated in Figure 20, the body contacts 232a and 232b and the source region 220 are located near the top of the semiconductor substrate 201 and above the base region 218. The base region 218 is located above the drift region 202, which is located above the drain region 222. In the present implementation, the drain region 222, the drift region 202, the base region 218, the source region 220, and the body contacts 232a and 232b can each contain semiconductor material, such as silicon. In the present implementation, the drain region 222 is formed in the semiconductor substrate 201, such as a silicon substrate. The drain region 222 is of the first conductivity type and is shown, for example, to have a conductivity of N+. The drift region 202 contains epitaxial silicon grown on the drain region 222.Drift region 202 is of the first conductivity type and is shown, for example, to have a conductivity of N-. Base region 218 is of the second conductivity type and is shown, for example, to have a conductivity of P. Source region 220 is of the first conductivity type and is shown, for example, to have a conductivity of N+. Body contacts 232a and 232b are of the second conductivity type and are shown, for example, to have a conductivity of P+. However, in another implementation, drain region 222, drift region 202, base region 218, source region 220, and body contacts 232a and 232b could each contain the opposite conductivity type and be configured in different ways without deviating from the scope of protection of this disclosure.

[0037] As in Fig. As illustrated in Figure 20, gate trenches 206a and 206b extend through basal region 218 and into drift region 202. Gate trenches 206a and 206b each have opposite sidewalls that (in this example) are substantially parallel to each other and extend into a bottom. Gate trench 206a contains the dielectric gate trench lining 208a, which lines its sidewalls and bottom, and the gate electrode 210a. Gate trench 206b contains the dielectric gate trench lining 208b, which lines its sidewalls and bottom, and the gate electrode 210b. The dielectric gate trench linings 208a and 208b can contain any suitable dielectric material, such as silicon dioxide. The gate electrodes 210a and 210b can contain any suitable conductive material, such as doped polycrystalline silicon, metal and / or metal alloy.The dielectric gate trench caps 212a and 212b are formed over the gate trenches 206a and 206b, respectively. The dielectric gate trench caps 212a and 212b contain dielectric material and electrically insulate the respective gate electrodes 210a and 210b from the source contact 230.

[0038] As in Fig. As illustrated in Figure 20, the source trench 204 extends through the basal region 218 and into the drift region 202. The source trench 204 contains the first section 204a, which has a depth 203a and a width 205a, and the second section 204b, which has a depth 203b and a width 205b, where the depth 203b is greater than the depth 203a and the width 205a is greater than the width 205b. The source trench 204 contains the dielectric source trench lining 214, which lines the sidewalls of the first section 204a and the sidewalls and bottom of the second section 204b. The dielectric source trench lining 214 can contain any suitable dielectric material, such as silicon dioxide. The conductive source trench filler material 216 can contain any suitable conductive material, such as doped polycrystalline silicon, metal and / or metal alloy.

[0039] As in Fig. As illustrated in Figure 20, body contacts 232a and 232b are located in contact trenches 229a and 229b, respectively, above the base region 218. The body contacts 232a and 232b can be formed by implanting a P-type dopant into contact trenches 229a and 229b, respectively. The source contact 230 can be formed as a continuous layer above the conformal spacer layer 224, the dielectric gate trench caps 212a and 212b, the body contacts 232a and 232b, the dielectric source trench lining 214, and the conductive source trench filler 216. Source contact 230 is coupled to source region 220 between gate trench 206a and source trench 204 and between source trench 204 and gate trench 206b.For example, section 230a of source contact 230 between gate trench 206a and source trench 204 is self-aligning, while section 230b of source contact 230 between source trench 204 and gate trench 206b is also self-aligning. Source contact 230 is also coupled to base region 218 by body contacts 232a and 232b. In the present implementation, source contact 230 contains conductive material, such as metal and / or metal alloy.

[0040] As in Fig. As illustrated in Figure 2O, the first masking layer 250a and the conformal spacer layer 224 are located above the source region 220 to provide sufficient screening and separation between the conductive source trench filler material 216 and the gate electrodes 210a and 210b. Furthermore, in the semiconductor structure 298, the source contact 230 is located on the body contacts 232a and 232b, the source region 220, and the conductive source-trough filler material 216 in the source-trough 204. The drain contact layer 242 is located below the body contacts 232a and 232b and is electrically connected to the drain region 222. The source contact 230 and the drain contact layer 242 contain conductive material, such as metal and / or metal alloy, and are used to establish a current path between the drain region 222 and the source region 220 during conduction of the semiconductor structure 298.In the present implementation, the source trench 204, which has the conductive source trench filler material 216, and the gate trenches 206a and 206b, which have the gate electrodes 210a and 210b respectively, are configured to achieve a charge equalization effect and to enable two-dimensional depletion in the drift region 202 during the operation of the semiconductor device, such as a power MOSFET or an IGBT.

[0041] As in Fig. As shown in Figure 20, the source trench 204 is spaced such that it is essentially centered between adjacent gate trenches 206a and 206b, which is the result of the single photolithography masking operation used during the fabrication process according to implementations of the present application. Therefore, misalignments between the gate and source trenches can be essentially avoided. The single photolithography masking operation also enables self-aligning body and source contacts to further eliminate alignment constraints that exist during contact formation.

[0042] As in Fig.As illustrated in Figure 20, contact trenches 229a and 229b between the respective gate and source trenches are self-aligning. The body contacts 232a and 232b and the source contact 230 (for example, sections 230a and 230b) in their respective contact trenches 229a and 229b are also self-aligning between the respective gate and source trenches. This self-alignment mechanism means that the source and body contacts are not limited by conventional manufacturing processes, such as photolithography, and can have reduced widths, thereby increasing cell density. Furthermore, implementations of the present application enable improved electrical performance, such as a lower RDS(on). DSon , and nodes with lower voltages for charge balancing of power semiconductor devices, such as MOSFETs, IGBTs and the like.

Claims

[1] Semiconductor device comprising: a gate trench (206a, 206b) in a semiconductor substrate (201); a source trench (204) in the semiconductor substrate (201), wherein the source trench (204) has a first section (204a) and a second section (204b) below the first section (204a), wherein the first section (204a) of the source trench (204) has a width (205a) and the second section (204b) of the source trench (204) has a width (205b) that is narrower than the width (205a) of the first section (204a), and wherein the first section (204a) of the source trench (204) extends to a depth of the gate trench (206a, 206b); wherein the first section (204a) of the source trench (204) is wider than the gate trench (206a, 206b); and a conductive fill material (216) and a dielectric source trench lining (214) in the source trench (204). [2] Semiconductor device according to claim 1, further comprising a gate electrode (210a, 210b) and a dielectric gate trench lining (208a, 208b) in the gate trench (206a, 206b). [3] Semiconductor device according to one of claims 1 to 2, further comprising a source region (220) between the gate trench (206a, 206b) and the source trench (204). [4] Semiconductor device according to one of claims 1 to 3, further comprising a base region (218) between the gate trench (206a, 206b) and the source trench (204). [5] Semiconductor device according to one of claims 1 to 4, further comprising a source contact (230) coupled to a source region (220) between the gate trench (206a, 206b) and the source trench (204). [6] Semiconductor device according to any one of claims 1 to 5, wherein a depth of the second section (204b) is greater than a first depth of the first section (204a). [7] Semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device comprises a MOSFET. [8] Semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device comprises an IGBT. [9] Semiconductor device according to any one of claims 4 to 8, wherein the base region (218) and a drift region (202) are planar. [10] Semiconductor device according to one of claims 3 to 8, wherein a drift region (202) is formed in a Si epitaxial layer. [11] Semiconductor device according to claim 10, wherein the base region (218) comprises a first implanted region of the Si epitaxial layer. [12] Semiconductor device according to claim 11, wherein the source region (220) has a second implanted region of the Si epitaxial layer above the first implanted region. [13] Method for forming a semiconductor device, wherein the method comprises: Forming a gate trench (206a, 206b) and a first section (204a) of a source trench (204) in a semiconductor substrate (201), wherein the first section (204a) of the source trench (204) is wider than the gate trench (206a, 206b); Forming a gate electrode (210a, 210b) in the gate trench (206a, 206b); Forming a second section (204b) of the source trench (204) below the first section (204a), wherein the first section (204a) of the source trench (204) has a width (205a) and the second section (204b) of the source trench (204) has a width (205b) that is narrower than the width (205a) of the first section (204a); Forming a dielectric source trench lining (214) in the source trench (204); and Forming a conductive fill material (216) in the source trench (204). [14] Method according to claim 13, further comprising forming a base region (218) and a source region (220) in the semiconductor substrate (201). [15] Method according to claim 14, further comprising forming a source contact (230) coupled to the source region (220) and the base region (218). [16] Method according to claim 15, wherein the source contact (230) between the source trench (204) and the gate trench (206a, 206b) is self-aligning. [17] Method according to any one of claims 13 to 16, further comprising forming a dielectric gate-trough lining (208a, 208b) in the gate-trough (206a, 206b). [18] Method according to any one of claims 13 to 17, further comprising forming a structured photoresist mask (250) over the semiconductor substrate (201) to define a width of the first section (204a) of the source trench (204) and a width of the gate trench (206a, 206b). [19] Method according to any one of claims 13 to 18, further comprising forming a contact trench (229a, 229b) between the source trench (204) and the gate trench (206a, 206b). [20] Method according to any one of claims 13 to 19, wherein the depth of the second section (204b) is greater than the first depth of the first section (204a) of the source trench. [21] Semiconductor device comprising: a semiconductor substrate (201) having a drain region (222), a drift region (202) above the drain region (222), a base region (218) above the drift region (202) and a source region (220) above the base region (218), wherein the drain region (222), the drift region (202) and the source region (220) have a first conductivity type and the base region (218) has a second conductivity type which is opposite to the first conductivity type; a gate trench (206a, 206b) in the semiconductor substrate (201) extending into the drift region (202); a source trench (204) in the semiconductor substrate (201) extending into the drift region (202), wherein the source trench (204) has a first section (204a) and a second section (204b) below the first section (204a), wherein the first section (204) is wider than the gate trench (206a, 206b), the first section (204a) of the source trench (204) has a width (205a) and the second section (204b) of the source trench (204) has a width (205b) that is narrower than the width (205a) of the first section (204a), and the first section (204a) of the Source Trench (204) extends to a depth of the Gate Trench (206a, 206b), and a conductive filler material (216) in the source trench (204) which is insulated from the surrounding semiconductor substrate (201) by a dielectric material, wherein the dielectric material lines sidewalls of the first section (204a), sidewalls of the second section (204b) and a bottom of the second section (204b). [22] Semiconductor device according to claim 21, further comprising a gate electrode (210a, 210b) and a dielectric gate trench lining (208a, 208b) in the gate trench (206a, 206b). [23] Semiconductor device according to one of claims 21 to 22, wherein the source region (220) is located between the gate trench (206a, 206b) and the source trench (204). [24] Semiconductor device according to one of claims 21 to 23, wherein the base region (218) and the drift region (202) are planar. [25] Semiconductor device according to one of claims 21 to 24, wherein the drift region (202) is formed in a Si epitaxial layer. [26] Semiconductor device according to claim 25, wherein the base region (218) comprises a first implanted region of the Si epitaxial layer. [27] Semiconductor device according to claim 26, wherein the source region (220) has a second implanted region of the Si epitaxial layer above the first implanted region. [28] Method for forming a semiconductor device, wherein the method comprises: Forming a semiconductor substrate (201) comprising a drain region (222), a drift region (202) above the drain region (222), a base region (218) above the drift region (202) and a source region (220) above the base region (218), wherein the drain region (222), the drift region (202) and the source region (220) have a first conductivity type and the base region (218) has a second conductivity type opposite to the first conductivity type; Forming a gate trench (206a, 206b) and a first section (204a) of a source trench (204) in the semiconductor substrate (201), both of which extend into the drift region (202), wherein the first section (204a) of the source trench (204) is wider than the gate trench (206a, 206b); Forming a gate electrode (210a, 210b) in the gate trench (206a, 206b); Forming a second section (204b) of the source trench (204) below the first section (204a), which extends deeper into the drift region (202) than the first section (204a), wherein the first section (204a) of the source trench (204) has a width (205a) and the second section (204b) of the source trench (204) has a width (205b) that is narrower than the width (205a) of the first section (204a); Lining the side walls of the first section (204a), the side walls of the second section (204b), and a floor of the second section (204b) with a dielectric material; and Forming a conductive fill material (216) in the source trench (204), wherein the conductive fill material (216) is insulated from the surrounding semiconductor substrate (201) by the dielectric material. [29] Method according to claim 28, further comprising forming a source contact (230) coupled to the source region (220) and the base region (218). [30] Method according to claim 28 or 29, further comprising forming a dielectric gate-trough lining (208a, 208b) in the gate-trough (206a, 206b). [31] Method according to any one of claims 28 to 30, further comprising forming a structured photoresist mask over the substrate to define a width of the first section (204a) of the source trench (204) and a width of the gate trench (206a, 206b). [32] Method according to any one of claims 28 to 31, further comprising forming a contact trench (229a, 229b) between the source trench (204) and the gate trench (206a, 206b).

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