Integrated silicon photonics assembly for high data rates and methods for its assembly

Abstract

Integrated component assembly comprising: a printed circuit board, PCB, with a PCB cavity (325) in a first side of the PCB, dimensioned to accommodate an optical fiber (320); several BGA connections (335) that are mechanically and electrically coupled to the PCB on the first side of the PCB; a carrier (365) which is directly mechanically coupled to the PCB on a first side of the carrier (365) via at least one of the BGA connections (335), wherein the carrier (365) comprises a redistribution layer, RDL, (380) which is arranged on the first side of the carrier (365) and comprises several RDL intermediate connections (360); an integrated photonic circuit, PIC, (315) which is arranged between one side of the RDL (380) and the first side of the PCB and which is mechanically coupled to the carrier (365); and a driver IC (310) located between the side of the RDL (380) and the first side of the PCB, which is mechanically coupled to the carrier (365) and which has a first side that (i) is electrically coupled to a first side of the PCB via at least one of the RDL intermediate connections (360) and at least one of the BGA connections (335, 435), and (ii) is electrically coupled to a first side of the PIC (315) via at least one of the RDL intermediate connections (360).

Description

BACKGROUND

[0001] Signal integrity in high-speed applications depends on both the performance of the underlying device and the electronic assembly and interconnection methods. For high-speed optical transceivers, minimizing RF loss due to assembly is beneficial. The maturity of chip-on-board (COB) assembly and interconnection technology using wire bonding makes it a cost-effective option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance related to the length of the bond wires, limiting the system's scalability for higher data throughput.

[0002] US 2002 / 0196997 A1 discloses an assembly that enables both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB), and which, in addition to electrical connections, also features optical waveguide structures. An optically active device can be directly connected to an integrated circuit using solder bead technology. The integrated circuit is then connected to a BGA assembly via flip bonding or wire bonding. The assembly features alignment rails or balls and V-grooves to anchor the alignment rail balls and align the BGA assembly on the PCB. The BGA assembly is bonded to the PCB using reflow soldering technology. SUMMARY

[0003] The technical objective is to provide an improved integrated component assembly. This objective is achieved by means of the subject matter of the independent claims. The dependent claims define some of the possible further exemplary embodiments.

[0004] According to one aspect, the subject matter described in this disclosure relates to an integrated component assembly comprising: a printed circuit board (PCB), a photonic integrated circuit (PIC) mechanically coupled to the PCB on a first side of the PIC, and an integrated driver circuit (driver IC) with a first side. The first side of the driver IC is directly mechanically and electrically coupled to a second side of the PIC via a first set of bump bond connections. The first side of the driver IC is also electrically coupled to the PCB via a second set of bump bond connections.

[0005] According to another aspect, the subject matter described in this disclosure relates to an integrated component assembly comprising: a printed circuit board (PCB) having a PCB cavity in a first side of the PCB dimensioned to accommodate an optical fiber, several BGA interconnects mechanically and electrically coupled to the PCB on the first side of the PCB, and a substrate directly mechanically coupled to the PCB on a first side of the substrate via at least one of the BGA interconnects. The substrate includes a redistribution layer (RDL) arranged on the first side of the substrate and containing several RDL intermediate connections. The integrated component assembly further comprises a photonic integrated circuit (PIC) mechanically coupled to the substrate and a driver IC mechanically coupled to the substrate.The first side of the driver IC is electrically coupled to the first side of the PCB via at least one of the RDL connections and at least one of the BGA connections. The first side of the driver IC is also electrically connected to the first side of the PIC via at least one of the RDL connections.

[0006] According to another aspect, the subject matter described in this disclosure relates to a method for assembling an integrated component assembly, comprising: mechanically coupling an integrated photonic circuit (PIC) to a printed circuit board (PCB) on a first side of the PIC, direct mechanical and electrical coupling of a first side of a driver IC to a second side of the PIC via a first set of bump bond connections, and electrically coupling of the first side of a driver IC to the PCB via a second set of bump bond connections.

[0007] According to another aspect, the subject matter described in this disclosure relates to a method for assembling an integrated component assembly, which includes: mechanically and electrically coupling multiple BGA connections to a printed circuit board (PCB) on the first side of the PCB. The PCB has a PCB cavity dimensioned to accommodate an optical fiber. The method includes mechanically coupling a carrier to the PCB on a first side of the carrier via at least one of the BGA connections. The carrier includes a redistribution layer (RDL) arranged on the first side of the carrier and containing multiple RDL intermediate connections. The method also includes mechanically coupling an integrated photonic circuit (PIC) to the carrier and mechanically coupling a driver IC to the carrier.The method further comprises electrically coupling a first side of the driver ICs to a first side of the PCB via at least one of the RDL intermediate connections and at least one of the BGA connections, and electrically coupling the first side of the driver IC to the first side of the PIC via at least one of the RDL intermediate connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing will become apparent from the following more detailed description of exemplary implementations of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale; rather, the focus is on illustrating implementations of the present invention. Fig. Figure 1A is a top view of a first integrated component assembly configuration according to an exemplary implementation. Fig. 1B is a representation of a side view of the in Fig. 1A shows the first integrated component assembly configuration. Fig. Figure 2A is a top view of a second integrated component assembly configuration according to an exemplary implementation. Fig. 2B is a representation of a side view of the in Fig. 2A shows the second integrated component assembly configuration. Fig. Figure 3A is a representation of a side view of a third configuration of an integrated assembly according to an exemplary implementation. Fig. Figure 3B is a side view representation of a fourth integrated component assembly configuration according to an exemplary implementation. Fig. Figure 4A is a side view representation of a fifth integrated component assembly configuration according to an exemplary implementation. Fig. Figure 4B is a side view representation of a sixth integrated component assembly configuration according to an exemplary implementation. Fig. 5 is a flowchart of a procedure for assembling the in Fig. 1A - Fig. 2B shown integrated component assemblies. Fig. 6 is a flowchart of a procedure for assembling the in Fig. 3A - Fig. 4B shown integrated component assemblies.

[0009] For clarity, not every component can be labeled in every figure. The drawings are not to scale. Identical reference symbols and labels in different figures denote the same elements. DETAILED DESCRIPTION

[0010] Signal integrity in high-speed applications depends on both the performance of the underlying device and the electronic assembly and interconnection methods. For high-speed optical transceivers, minimizing RF loss due to assembly is beneficial. The maturity of chip-on-board (COB) assembly and interconnection technology using wire bonding makes it a cost-effective option for mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance related to the length of the bond wires, limiting the system's scalability for higher data throughput. The electrical issues caused by wire bonding become a bottleneck as the on-board data rate of high-speed optical transceivers increases beyond 25 Gbps / channel.

[0011] Integrated component assemblies according to the present disclosure can be used for the optoelectronic assembly integration of high-speed optical transceivers. Typically, an integrated component assembly of a high-speed optical transceiver includes an integrated driver circuit (driver IC) that is electrically coupled to both a picture integrated circuit (PIC) and a printed circuit board (PCB). In some conventional assembly configurations, the driver IC is connected to the PIC and the PCB via wire bonds. In other conventional assembly configurations, the driver IC may be connected to the PIC via bump bonds and to the PCB via the PIC via wire bonds. However, both of these configurations are electrically limited by the parasitic inductance, which is related to the length of the bond wires.Alternatively, the driver IC can be connected to the PIC via bump bonds, and the PIC can then connect to the PCB. The intermediate connection between the driver ICs and the PCB via the PIC can utilize silicon vias (TSVs) integrated into the PIC. However, limitations of this configuration include the complexity of integrating TSVs into the PIC, as well as the parasitic inductance introduced by stacking the TSV chips.

[0012] Certain high-speed optical transceiver assemblies and assembly methods of this disclosure reduce the assembly-related parasitic inductance with vertically stacked components and flip-chip bonding. Other high-speed optical transceiver assemblies and assembly methods of this disclosure reduce the assembly-related parasitic inductance with a combination of vertically stacked and horizontally tiled components. The integrated component assemblies disclosed herein comprise at least one electronic integrated circuit (EIC), such as a driver chip or driver IC, integrated with a photonic integrated circuit (PIC) on a printed circuit board (PCB). The integrated assemblies also include electrical and physical connections between the various components. The driver IC is electrically connected to both the PIC and the PCB.In some implementations, the PIC can be physically connected to the PCB.

[0013] Fig. Figure 1A is a top view representation of a first integrated component assembly configuration 100 according to an exemplary implementation. Fig. 1B is a representation of a side view of the in Fig. Figure 1A shows the first integrated component assembly configuration 100. The first integrated component assembly configuration 100 comprises a printed circuit board (PCB) 105, a photonic integrated circuit (PIC) 115, an electronic integrated circuit (EIC) such as a driver IC 110, and an interposer 130. The PCB 105 has a top side on which the components are located (also referred to as a first side or component side of the PCB 105). The PCB 105 also has a bottom side or second side. The PIC 115, the driver IC 110, and the interposer 130 each also have a first side and a second side. The driver IC 110 is directly electrically connected to the PIC 115 and indirectly electrically connected to the PCB 105 via the interposer 130.

[0014] The PIC 115 is located on a top-side or component side of the PCB 105. The first side of the PIC 115 is physically connected to the top-side surface of the PCB 105. In some implementations, the first side of the PIC 115 is surface-mounted to the top of the PCB 105. In some implementations, the PIC 115 can be an externally modulated laser (EML), a monolithic tunable laser, a wide tunable laser, or another optical emitter that integrates multiple photonic functions into a single device.

[0015] The driver IC 110 is stacked vertically on the second side of the PIC 115, so that a section of the driver IC 110 overlaps the second side of the PIC 115 and at the same time a section of the driver IC 110 overlaps the interposer 130.

[0016] As mentioned above, the driver IC 110 is electrically connected to both the PIC 115 and the PCB 105. The section of the driver IC 110 that overlaps the second side of the PIC 115 is directly flip-chip connected to the second side of the PIC 115 via one or more hump bonds (BBs) 150. The BBs 150 provide an electrical interface between the driver IC 110 and the PIC 115. The BBs 150 also provide a physical or mechanical interface between the driver IC 110 and the second side of the PIC 115. In addition to the electrical connection with the PIC 115, the driver IC 110 is also electrically connected to the PCB 105. The driver IC 110 is physically connected to the PCB 105 via the interposer 130. The section of the driver IC 110 that overlaps the interposer 130 is directly flipchip connected to a first side of the interposer 130 by means of one or more hump bonds (BBs) 140.The second side of the interposer 130 is physically and electrically connected to the surface of the top side of the PCB 105 via one or more other bump bonds (BBs) 145. The interposer 130, together with the BBs 140 and BBs 145, provides an electrical and mechanical interface between the driver IC 110 and the PCB 105.

[0017] In some implementations, the interposer 130 may comprise a multilayer substrate that further comprises alternating layers of conductors and dielectrics. In some implementations, the interposer 130 may contain glass. In some implementations, the interposer 130 may also comprise one or more plated through-holes (PTHs) 160, and an electrical connection between the driver IC 110 and the PCB 105 via the interposer 130 may include one or more of the PTHs 160. In some implementations, the interposer 130 may contain silicon, and the one or more PTHs 160 may be silicon vias (TSVs). The vertical flip-chip integration of the driver IC 110 with the PIC 115 and the PCB 105, as described in Fig. 1A and Fig. As shown in Figure 1B, this reduces the length of the intermediate connections between the components and thereby reduces the assembly-related parasitic inductance.

[0018] Fig. Figure 2A is a top view representation of a second integrated component assembly configuration 200 according to an exemplary implementation. Fig. 2B is a representation of a side view of the in Fig. Figure 2A shows the second integrated component assembly configuration 200. The second integrated component assembly configuration 200 comprises a printed circuit board (PCB) 205, a photonic integrated circuit (PIC) 215, and an electronic integrated circuit (EIC), such as a driver IC 210. The PCB 205 has a top side on which the components are located (also referred to as a first side or component side of the PCB 205). The PCB 205 also has a bottom side or second side. The PIC 215 has a first side and a second side. The driver IC 210 also has a first side and a second side. The driver IC 210 is electrically connected to both the PIC 215 and the PCB 205.

[0019] The top surface of PCB 205 includes a recess or cavity, such as cavity 225. The PIC 215 is located within cavity 225. The first side of the PIC 215 is physically connected to PCB 205 within cavity 225. In some implementations, the first side of the PIC 215 may be surface-mounted to the bottom of cavity 225. As shown in Fig. Figure 2B shows that when the PIC 215 is positioned within the cavity 225 and the first side of the PIC 215 is physically connected to the bottom of the cavity 225, the second side of the PIC 215 faces the top of the PCB 205. This orientation is achieved either by varying the depth of the cavity or the height of the underfill used when surface-mounting the PIC on the bottom of the cavity 225. As shown in Fig. 1A and Fig. As shown in Figure 1B, the PIC 215 can be an externally modulated laser (EML), a monolithic tunable laser, a widely tunable laser, or another optical emitter that integrates multiple photonic functions into a single device.

[0020] The driver IC 210 is stacked vertically on a second side of the PIC 215, so that one section of the driver IC 210 overlaps the second side of the PIC 215, while one section of the driver IC 210 overlaps the top of the PCB 205.

[0021] As mentioned above, the driver IC 210 is electrically connected to both the PIC 215 and the PCB 205. The section of the driver IC 210 that overlaps the second side of the PIC 215 is directly flip-chip connected to the second side of the PIC 215 via one or more BBs 250. The BBs 250 provide an electrical interface between the driver IC 210 and the PIC 215. The BBs 250 also provide a physical or mechanical interface between the driver IC 210 and the second side of the PIC 215.

[0022] As mentioned above, in addition to its electrical connection to the PIC 215, the driver IC 210 is also electrically connected to the PCB 205. The section of the driver IC 210 that overlaps the PCB 205 is directly flip-chip connected to the component side of the PCB 205 by one or more bump bonds (BBs) 240. The BBs 240 provide an electrical interface between the driver IC 210 and the PCB 205. The BBs 240 also provide a physical or mechanical interface between the driver IC 210 and the component side of the PCB 205.

[0023] By directly flip-chip connecting the driver IC 210 to both the PCB 205 and the PIC 215, i.e., without using an interposer between the driver IC 210 and the PCB 205, the second integrated component assembly 200, which is in Fig. 2A and Fig. Figure 2B shows how to further reduce the parasitic inductance associated with assembly formation.

[0024] Fig. Figure 3A is a side view representation of a third integrated component assembly configuration 300a according to an exemplary implementation. The integrated component assembly configuration 300a comprises a PCB 305a, an electronic integrated circuit (EIC) such as a driver IC 310, a photonic integrated circuit (PIC) 315, and a chip carrier such as the carrier 365. The PCB 305a has a top side on which the components are located (also referred to as a first side or component side of the PCB 305). The PCB 305a also has a bottom side or second side. The PIC 315 has a first side and a second side. The driver IC 310 also has a first side and a second side. The driver IC 310 is electrically connected to both the PIC 315 and the PCB 305a. The 300 assembly configuration also includes several ball lattice array (BGA) connections, such as the BGA connection 335.The BGA connection 335 is physically connected to the top side of the PCB 305a. The carrier 365 has a first side and a second side. The carrier 365 includes a redistribution layer (RDL) 380, which is arranged on a section of the first side of the carrier 365.

[0025] As in Fig. Figure 3A shows the assembly configuration 300a, which contains a combination of vertically stacked and horizontally tiled components. The carrier 365 is connected to the PCB 305a such that the first side of the carrier 365 faces the top surface of the PCB 305a. The carrier 365 is physically and electrically connected to the PCB 305a via one or more of the BGA connections 335.

[0026] The driver IC 310 and the PIC 315 are arranged horizontally in a tile-like pattern and physically connected to the first side of the carrier 365. Therefore, the driver IC 310 and the PIC 315 are located between the first side of the carrier 365 and the top surface of the PCB 305a. The driver IC 310 and the PIC 315 are physically connected to each other on different sections of the first side of the carrier 365. In some implementations, the driver IC 310 and the PIC 315 are horizontally spaced on the carrier 365 according to the chip spacing requirements of the driver IC 310 and the PIC 315. The first side of the driver IC 310 is physically connected to a section of the carrier 365 that contains the RDL 380. The first side of the driver IC is directly flip-chip connected to the RDL 380 via one or more hump bonds (BBs) 340. The BBs 340 provide a mechanical interface between the driver IC 310 and the carrier 365.The first side of the PIC 315 is also directly flip-chip connected to the RDL 380 via one or more BBs 350. The BBs 150 provide a mechanical interface between the first side of the PIC 315 and the first side of the carrier 365.

[0027] The driver IC 310 is electrically connected to both the PIC 315 and the PCB 305a. The driver IC 310 is electrically connected to the PIC 315 via the BBs 340, one or more RDL intermediate connections 360, and the BBs 350. The driver IC 310 is electrically connected to the PCB 305 via one or more RDL intermediate connections 360 and one or more of the BGA connections 335.

[0028] As in Fig. As shown in Figure 3A, a space 327, located adjacent to the PIC 315 and defined by the first side of the support 365 and the top of the PCB 305a, may not be dimensioned to accommodate the optical fiber 320, thus preventing direct optical coupling between the optical fiber 320 and the PIC 315 within the space 327. Accordingly, in Fig. 3A places the optical fiber 320 over the second side of the carrier 365 and couples optically to the PIC 315 via the carrier 365. In some implementations, the carrier 365 can be made of a transparent material such as glass, thus enabling optical coupling between the optical fiber 320 and the PIC 315 via the carrier 365.

[0029] Fig. Figure 3B is a side view representation of a fourth integrated component assembly configuration 300b according to an exemplary implementation. The fourth integrated component assembly configuration 300b is similar to the third integrated component assembly configuration 300a. The integrated component assembly configuration 300b comprises a PCB 305b, an electronic integrated circuit (EIC) such as a driver IC 310, a photonic integrated circuit (PIC) 315, and a chip carrier such as the carrier 365. The PCB 305b has a top side on which the components are arranged (also referred to as a first side or component side of the PCB 305). The PCB 305b also has a bottom side or second side. The PIC 315 has a first side and a second side. The driver IC 310 also has a first side and a second side. The driver IC 310 is electrically connected to both the PIC 315 and the PCB 305b.The assembly configuration 300 also includes several ball grid array (BGA) connections, such as BGA connection 335. BGA connection 335 is physically connected to the top surface of PCB 305a. Carrier 365 has a first side and a second side. Carrier 365 includes a redistribution layer (RDL) 380, which is arranged on a section of the first side of carrier 365.

[0030] As in Fig. As shown in Figure 3B, the assembly configuration 300b contains a combination of vertically stacked and horizontally tiled components. The carrier 365 is connected to the PCB 305b such that the first side of the carrier 365 faces the top surface of the PCB 305b. The carrier 365 is physically and electrically connected to the PCB 305b via one or more of the BGA connections 335.

[0031] The driver IC 310 and the PIC 315 are arranged horizontally in a tile-like pattern and physically connected to the first side of the carrier 365. Therefore, the driver IC 310 and the PIC 315 are located between the first side of the carrier 365 and the top surface of the PCB 305b. The driver IC 310 and the PIC 315 are physically connected to each other on different sections of the first side of the carrier 365. In some implementations, the driver IC 310 and the PIC 315 are horizontally spaced on the carrier 365 according to the chip spacing requirements of the driver IC 310 and the PIC 315. The first side of the driver IC 310 is physically connected to a section of the carrier 365 that contains the RDL 380. The first side of the driver IC 110 is directly flip-chip connected to the RDL 380 via one or more hump bonds (BBs) 340. The BBs 340 provide a mechanical interface between the driver IC 310 and the carrier 365.The first side of the PIC 315 is also directly flip-chip connected to the RDL 380 via one or more BBs (350 bumper bonds). The BBs provide a mechanical interface between the first side of the PIC 315 and the first side of the carrier 365.

[0032] The driver IC 310 is electrically connected to both the PIC 315 and the PCB 305b. The driver IC 310 is electrically connected to the PIC 315 via the BBs 340, one or more RDL intermediate connections 360, and the BBs 350. The driver IC 310 is electrically connected to the PCB 305 via one or more RDL intermediate connections 360 and one or more of the BGA connections 335.

[0033] In some implementations, an optical fiber 320 is directly optically coupled to the PIC 315. In some implementations, the top surface of the PCB 305b may further include a PCB cavity 325 located adjacent to the PIC 315 and opposite the first side of the carrier 365. In some implementations, the PCB cavity 325 may define a fiber cavity 326 adjacent to the PIC 315, between the first side of the carrier 365 and the PCB cavity 325. In some implementations, the fiber cavity 326 is sized to accommodate the optical fiber 320. The fiber cavity enables direct optical coupling between the optical fiber 320 and the PIC 315 within the fiber cavity, thereby reducing the overall height or form factor of the integrated component assembly configuration 300b.

[0034] The integrated component assembly configurations 300a and 300b provide straightforward electrical connections between the PIC 315 and the driver IC 310 without requiring vertical alignment between components or PCB sections, thus simplifying assembly manufacturing while avoiding wire bonds between components and reducing the assembly's inductive load compared to conventional assemblies.

[0035] Fig. Figure 4A shows a side view of a fifth integrated component assembly configuration 400a according to an exemplary implementation. The integrated component assembly configuration 400 comprises a PCB 405a, an electronic integrated circuit (EIC) such as a driver IC 410, a photonic integrated circuit (PIC) 415, and a chip carrier such as the carrier 465. The PCB 405a has a top side on which the components are arranged (also referred to as a first side or component side of the PCB 405). The PCB 405a also has a bottom side or second side. The PIC 415 has a first side and a second side. The driver IC 410 also has a first side and a second side. The driver IC 410 is electrically connected to both the PIC 415 and the PCB 405. The assembly configuration 400 also includes several ball grid array (BGA) interconnects such as the BGA interconnect 435.The BGA interconnect 435 is physically and electrically connected to the top side of the PCB 405. The carrier 465 has a first side and a second side. The carrier 465 includes a redistribution layer (RDL) 480, which is located on a portion of the first side of the carrier 465. In some implementations, the carrier 465, the driver IC 140, and the PIC 415 can be integrated using package-on-package (PoP) technology and assembly formats such as wafer-level assembly with fanning (FO-WLP), laminate-embedded chips, or modular embedded chips. In some implementations, the carrier 465 can be formed from a molding compound that encapsulates the driver IC 410 chip and the PIC 415 chip.

[0036] The driver IC 410 and the PIC 415 are arranged horizontally in a tile-like pattern and embedded in the carrier 465. The first side of the driver IC 410 is physically connected to a section of the first side of the carrier 465 that is equipped with the RDL 480. The first side of the driver IC 410 is directly connected to the RDL 480. The first side of the PIC 415 is also directly connected to the RDL 480.

[0037] The driver IC 410 is electrically connected to the PIC 415 and the PCB 405. The driver IC 410 is electrically connected to the PIC 415 via one or more of the RDL intermediate connections 460. The driver IC 410 is electrically connected to the PCB 405 via one or more of the RDL intermediate connections 460, one or more vias (TMV) 470, and the BGA connection 435. The optical fiber 420, located above the second side of the carrier 465, can be optically coupled directly to the PIC 415.

[0038] Fig. Figure 4B is a representation of a sixth integrated component assembly configuration 400b. The sixth integrated assembly configuration 400b is similar to the fifth integrated component assembly configuration 400a. Unlike the fifth integrated assembly configuration 400a, the sixth integrated assembly configuration 400b includes a PCB 405b, which contains a PCB cavity 425. The PCB cavity 425 defines a fiber cavity 427 between the first side of the carrier 465 and the PCB cavity 425. The fiber cavity 427 is sized to accommodate an optical fiber 420. In some implementations, when the carrier 465 is stacked vertically on top of the PCB 405b, the fiber cavity 427 may be located adjacent to the PIC 415. In some implementations, a first section of the first side of the PIC 415 can overlap the PCB cavity 425, and a second section of the first side of the PIC 415 can overlap the top surface of the PCB 405b.In some implementations, the RDL 480 can be positioned above the second section of the first side of the PIC 415, overlapping the top section of the PCB 405b. As shown in . Fig. As shown in Figure 4B, the fiber cavity 427 enables direct optical coupling between the optical fiber 420 and the PIC 415 within the fiber cavity 427, thereby reducing the overall height and form factor of the integrated component assembly configuration 400b.

[0039] As mentioned above, the integrated assembly configurations 100, 200, 300a and 300b, which are in Fig. Figures 1A-3B show flip-chip connections between components using one or more hump bonds, such as hump bonds (BBs) 140, 145, 150, 240, 250, 340, and 350. In some implementations, the hump bonds can be formed using solder. In other implementations, the hump bonds can be formed using materials other than solder, such as, without limitation, copper, tin, or gold, alloys thereof, or other conductive materials or compositions known to those skilled in the art to be useful in forming hump bonds.

[0040] Fig. 5 is a flowchart of a Procedure 500 which, when executed, will result in the following: Fig. 1A to Fig. The assemblies shown in Figure 2B may result. Method 500 comprises the vertical integration of a PCB, a PIC, and a driver IC. Method 500 includes mechanically coupling an integrated photonic circuit (PIC) to a printed circuit board (PCB) on a first side of the PIC (stage 505), directly mechanically and electrically coupling a first side of a driver IC to a second side of the PIC via a first set of bump bond connections (stage 510), and electrically coupling a first side of a driver IC to the PCB via a second set of bump bond connections (stage 515).

[0041] An exemplary implementation of procedure 500, when executed, results in an assembly with the first assembly configuration 100, which is in Fig. 1A and Fig. Figure 1B shows the process. As mentioned above, Method 500 comprises mechanically coupling an integrated photonic circuit (PIC) 115 to a printed circuit board (PCB) 105 on a first side of the PIC 115 (stage 505). Method 500 further comprises directly mechanically and electrically coupling a first side of a driver IC 110 to a second side of the PIC 115 via a first set of bump bond connections such as the BBs 150 (stage 510). Method 500 further comprises electrically coupling the first side of the driver IC 110 to the PCB 105 via a second set of bump bond connections such as the BBs 140 (stage 515). In some implementations, stage 515 of the method 500 may further include a mechanical coupling of a first side of an interposer 130 to the PCB 105 via a third set of bump bond connections such as the BBs 145.In some implementations, stage 515 of procedure 500 may also include mechanically coupling a second side of the interposer 130 to the first side of the driver IC 110 via the second set of hump bond connections BBs 140. In some implementations, stage 515 of procedure 500 may include electrically coupling the first side of the driver IC 110 to the PCB 105 via the second set of hump bond connections BBs 140, the interposer 130, and the third set of hump bond connections BBs 145.

[0042] An exemplary implementation of procedure 500, when executed, results in an assembly with the second assembly configuration 200, which is in Fig. 2A and Fig. Figure 2B shows the method. Method 500 comprises mechanically coupling an integrated photonic circuit (PIC) 215 to a printed circuit board (PCB) 205 on a first side of the PIC 215 (stage 505). In some implementations, stage 505 of method 500 may include arranging the PIC 215 within a PCB cavity 225 in a first side of the PCB 205 and surface bonding the PIC 215 to the bottom of the PCB cavity 225 such that the first side of the PIC 215 faces the bottom of the PCB cavity 225. Method 500 further comprises direct mechanical and electrical coupling of a first side of a driver IC 210 to a second side of the PIC 215 via a first set of bump bond connections such as the BBs 250 (stage 510). Method 500 further includes electrically coupling the first side of the driver IC 210 to the PCB 205 via a second set of bump bond connections such as the BBs 240 (stage 515).In some implementations, stage 515 of procedure 500 may further include electrically coupling the first side of the driver IC 215 to the PCB 205 via the second set of hump bond connections such as the BBs 240, the interposer 230 and a third set of hump bond connections such as the BBs 245.

[0043] Fig. 6 is a flowchart of a procedure 600 which, when executed, will be in the Fig. 3B and Fig. The fourth and sixth assembly configurations 300b and 400b shown in Figure 4B may result. Method 600 comprises horizontally tiling a PIC and a driver IC relative to each other and vertically integrating the PIC and the driver IC with a PCB. Method 600 comprises mechanically and electrically coupling multiple BGA connections to a printed circuit board (PCB) on the first side of the PCB (Step 605). The PCB has a PCB cavity sized to accommodate an optical fiber. Method 600 further comprises mechanically coupling a carrier to the PCB on a first side of the carrier via at least one of the BGA connections, wherein the carrier includes a redistribution layer (RDL) arranged on the first side of the carrier and comprising multiple RDL intermediate connections (Step 610).Method 600 further comprises mechanically coupling an integrated photonic circuit (PIC) to the carrier (step 615) and mechanically coupling a driver IC to the carrier (step 620). Method 600 further comprises electrically coupling a first side of the driver IC to a first side of the PCB via at least one of the RDL intermediate connections and at least one of the BGA connections (step 625). Method 600 comprises electrically coupling the first side of the driver IC to the first side of the PIC via at least one of the RDL intermediate connections (step 630).

[0044] An exemplary implementation of procedure 600, when executed, results in an assembly with the fourth assembly configuration 300b, which is in Fig. Figure 3B shows the method 600. Method 600 comprises mechanically and electrically coupling several BGA connections, such as BGA connection 335, to a printed circuit board (PCB) 305b on the first side of the PCB 305b. The PCB 305b has a PCB cavity 325 dimensioned to accommodate an optical fiber 320 (stage 605). Method 600 further comprises mechanically coupling a carrier 365 to the PCB 305b on a first side of the carrier 365 via at least one of the BGAs 335, wherein the carrier 365 includes a redistribution layer (RDL) 380 arranged on the first side of the carrier 365 and comprising several RDL intermediate connections 360 (stage 610). Method 600 further comprises a mechanical coupling of an integrated photonic circuit (PIC) 315 to the carrier 365 (stage 615) and a mechanical coupling of a driver IC 310 to the carrier 365 (stage 620).In some implementations, stage 620 of procedure 600 may also include placing the integrated photonic circuit (PIC) 315 between a second side of the RDL 380 and the first side of the PCB 305b, and mechanically coupling a first side of the PIC 315 to the second side of the RDL 380 via at least one first bump bond connection, such as the BBs 350. The procedure includes electrically coupling a first side of the driver IC 310 to a first side of the PCB 305b via at least one of the RDL intermediate connections 360 and at least one of the BGA 335 (stage 625). In some implementations, stage 625 of procedure 600 may include placing the driver IC 310 between a second side of the RDL 380 and the first side of the PCB 305b. Method 600 further includes electrically coupling the first side of the driver IC 310 with the first side of the PIC 315 via at least one of the RDL intermediate connections 360 (stage 630).In some implementations, stage 630 of procedure 600 may also include mechanical and electrical coupling of the first side of the driver IC 365 to the second side of the RDL 380 via several second hump bond connections, such as the BBs 340. In some implementations, stage 630 of procedure 600 may include electrical coupling of the first side of the driver IC 310 to the first side of the PIC 315 via at least one of the first hump bond connections, such as the BBs 340, at least one of the RDL intermediate connections 360, and at least one of the second hump bond connections, such as the BBs 350.

[0045] In some implementations, when executed, procedure 600 results in the assembly containing the... Fig.The sixth assembly configuration shown in Figure 4B is included. Method 600 comprises mechanically and electrically coupling several BGA connections, such as the BGA connection 435, to a printed circuit board (PCB) 405b on the first side of the PCB 405b, wherein the PCB 405b has a PCB cavity 425 dimensioned to accommodate an optical fiber 420 (stage 605). Method 600 also comprises mechanically coupling a carrier 465 to the PCB 405b on a first side of the carrier 465 via at least one BGA connection 435, wherein the carrier 465 includes a redistribution layer (RDL) 480 arranged on the first side of the carrier 465 and comprising several RDL intermediate connections 460 (stage 610). Method 600 further comprises a mechanical coupling of an integrated photonic circuit (PIC) 415 to the carrier 465 (stage 615) and a mechanical coupling of a driver IC 410 to the carrier 465 (stage 620).In some implementations, stage 620 of method 600 may further include placing the integrated photonic circuit (PIC) 415 within the carrier 465 and placing the driver IC 410 within the carrier 465. In some implementations, stage 620 of method 600 may further include placing the PIC 415 in the PCB cavity 425 in the first side of the PCB 415 such that a first section of the first side of the PIC 415 overlaps the PCB cavity 425 and a second section of the first side of the PIC 415 overlaps the first side of the PCB 405b. The RDL 480 is arranged above the first side of the PIC 415 and the first side of the driver IC 410. The method includes electrically coupling a first side of the driver IC 410 with a first side of the PCB 405b via at least one of the RDL intermediate connections 460 and at least one BGA connection 435 (stage 625).Method 600 further comprises electrically coupling the first side of the driver IC 410 to the first side of the PIC 415 via at least one of the RDL intermediate connections 460 (stage 630). In some implementations, the RDL 480 may be arranged over the second section of the first side of the PIC 415, which overlaps the PCB 405b.

[0046] As mentioned above, procedures 500 and 600 may involve forming electrical and / or mechanical connections between components by flip-chip joining the components with one or more bump bonds. In some implementations, the bump bonds may be formed using solder. In other implementations, the bump bonds may be formed using materials other than solder, such as, without limitation, copper, tin, or gold, alloys thereof, or other conductive materials or compositions known by those skilled in the art to be useful for forming bump bonds.

[0047] Although this patent specification contains many specific implementation details, these should not be interpreted as limitations on the scope of an invention or the claimable, but rather as descriptions of features that may be specific to certain embodiments. Certain features described in this specification in connection with separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in connection with a single embodiment may also be implemented separately in several embodiments or in any suitable subcombination.Although features described above may be such that they act in certain combinations and may even be initially claimed in this way, in some cases one or more features from a claimed combination may be removed from the combination and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0048] Although operations are depicted in a specific order in the drawings, this should not be interpreted as requiring that such operations be performed in the shown order or sequentially, or that all depicted operations must be performed to achieve desirable results. Multitasking and parallel processing may be advantageous under certain circumstances. Furthermore, the separation of different system modules and components in the embodiments described above should not be interpreted as requiring such separation in all embodiments. It should be understood that the described program components and systems can generally be integrated together in a single software product or packaged across multiple software products.

[0049] References to "or" can be interpreted as inclusive, so that any terms described using "or" can refer to a single term, more than one term, or all of the terms described. The terms "first," "second," "third," etc., are not necessarily intended to indicate an order and are generally used only to distinguish between similar or identical objects or elements.

[0050] Numerous variations of the implementations described in this disclosure are obvious to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the intent or scope of this disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are to be granted the broadest scope consistent with this disclosure, the principles, and the novel features disclosed herein.

[0051] Signal integrity in high-speed applications depends on both the performance of the underlying device and the electronic assembly and interconnection methods. The maturity of chip-on-board (COB) assembly and interconnection technology using wire bonding makes it a cost-effective option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance related to the length of the bond wires, limiting the system's scalability for higher data throughput. A high-speed optical transceiver assembly according to a first proposed configuration minimizes the assembly-related parasitic inductance through vertical integration of components using flip-chip bonding.An optical high-speed transceiver assembly according to a second proposed configuration minimizes the assembly-related parasitic inductance by horizontally tiling components using a chip carrier and flip-chip bonding.

Claims

[1] Integrated component assembly comprising: a printed circuit board, PCB, with a PCB cavity (325) in a first side of the PCB, dimensioned to accommodate an optical fiber (320); several BGA connections (335) that are mechanically and electrically coupled to the PCB on the first side of the PCB; a carrier (365) which is directly mechanically coupled to the PCB on a first side of the carrier (365) via at least one of the BGA connections (335), wherein the carrier (365) comprises a redistribution layer, RDL, (380) which is arranged on the first side of the carrier (365) and comprises several RDL intermediate connections (360); an integrated photonic circuit, PIC, (315) which is arranged between one side of the RDL (380) and the first side of the PCB and which is mechanically coupled to the carrier (365); and a driver IC (310) located between the side of the RDL (380) and the first side of the PCB, which is mechanically coupled to the carrier (365) and which has a first side that (i) is electrically coupled to a first side of the PCB via at least one of the RDL intermediate connections (360) and at least one of the BGA connections (335, 435), and (ii) is electrically coupled to a first side of the PIC (315) via at least one of the RDL intermediate connections (360). [2] Integrated component assembly according to claim 1, wherein the first side of the PIC (315) is mechanically coupled to the side of the RDL (380); the first side of the driver IC (310) (i) is mechanically and electrically coupled to the side of the RDL (380); and (ii) is electrically coupled to the first side of the PIC (315), at least one of the RDL intermediate connections (360). [3] Integrated component assembly according to claim 1 or claim 2, wherein the PCB cavity (325) is arranged adjacent to the PIC (315). [4] Method for assembling an integrated component assembly, the method comprising: mechanical and electrical coupling of several BGA connections (335) to a printed circuit board, PCB, on the first side of the PCB, wherein the PCB has a PCB cavity (325) dimensioned to accommodate an optical fiber (320); mechanically coupling a carrier (365) to the PCB on a first side of the carrier (365) via at least one of the BGA connections (335) wherein the carrier (365) comprises a redistribution layer, RDL, (480) arranged on the first side of the carrier (365) and comprising several RDL intermediate connections (360); Arranging an integrated photonic circuit, PIC, (315) between a second side of the RDL (380) and the first side of the PCB; mechanical coupling of the integrated photonic circuit, PIC, (315) with the carrier (365); Arranging a driver IC (310) between the side of the RDL (380) and the first side of the PCB; mechanical coupling of the driver IC (310) with the carrier (365); electrical coupling of a first side of the driver IC (310) to a first side of the PCB via at least one of the RDL intermediate connections (360) and at least one of the BGA connections (335); and electrical coupling of the first side of the driver IC (310) with the first side of the PIC (315) via at least one of the RDL intermediate connections (360). [5] The method of claim 4, further comprising: mechanical coupling of a first side of the PIC (315) with the side of the RDL (380); mechanical and electrical coupling of the first side of the driver IC (310) with the side of the RDL (380); and electrical coupling of the first side of the driver IC (310) with the first side of the PIC (315, 415), at least one of the RDL intermediate connections (360). [6] Method according to claim 4 or claim 5, wherein the PCB cavity (325) is arranged adjacent to the PIC (315).

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