Method for forming an SOI substrate

Abstract

A method for forming an SOI substrate, comprising: epitaxial formation of a silicon germanium, hereinafter referred to as SiGe, layer (202) over a sacrificial substrate (204); epitaxial formation of a first active layer (108) on the SiGe layer (202), the first active layer (108) having a composition different from that of the SiGe layer (202); bonding the first active layer (108) to a dielectric layer (104) formed over a first substrate (102); removal of the sacrificial substrate (204) and the SiGe layer (202); etching the first active layer (108) to expose an outer edge of an upper surface of the dielectric layer (104); and forming a connected active layer (108, 110) by epitaxial formation of a second active layer (110) on the first active layer (108), wherein the first active layer (108) and the second active layer (110) have an essentially identical composition.

Description

GENERAL STATE OF THE ARTIntegrated circuits are formed on semiconductor substrates and packaged to form chips or microchips. Traditionally, integrated circuits are formed on bulk semiconductor substrates made of a semiconductor material such as silicon. In recent years, semiconductor-on-insulator (SOI) substrates have been alternatively encountered. SOI substrates include a thin layer of active semiconductor material (e.g., silicon) separated from an underlying handle substrate by a layer of insulating material. The layer of insulating material electrically isolates the thin layer of semiconductor active material from the handle substrate, thereby reducing the leakage currents of the devices formed within the thin layer of semiconductor active material. The thin layer of semiconductor active material may also provide other advantages, such as faster switching times, lower operating currents, and lower profile packaging.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It is noted that various features corresponding to the industry's standard method are not drawn to scale. The dimensions of the various characteristics can actually be arbitrarily increased or decreased to make the explanation clearer. FIGS. 1A through 1C illustrate cross-sectional views of some embodiments of an SOI substrate, in accordance with some aspects of the present disclosure. FIGS. 2-11 illustrate some embodiments of cross-sectional views illustrating a method of forming an SOI substrate according to some aspects of the present disclosure. FIG. 12 illustrates a flow diagram of some embodiments of a method of forming an SOI substrate in accordance with some aspects of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different functions of the stated content. Specific examples of constituent elements and arrangements are described below in order to simplify the present disclosure. For example, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. The spatially relative terms should include, in addition to the orientation depicted in the figures, various orientations of the device or apparatus in use or operation. The apparatus or apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative identifiers used herein may also be appropriately designed. In addition, the terms "first", "second", "third", "fourth" and the like are purely identifying and can therefore be interchanged in various embodiments. For example, while an element (e.g., an opening) may be referred to as a "first" element in some embodiments, the element may be referred to as a "second" element in other embodiments.Semiconductor-on-insulator (SOI) substrates are used in many modern RF devices, including silicon-based photonics and highly accurate microelectromechanical systems (MEMS). Devices formed within an SOI substrate have improved performance and lower profile packaging than devices formed within a bulk substrate. The active semiconductor material within an SOI substrate may ideally have a relaxed monocrystalline lattice, without defects and dislocations. Such a structure in the semiconductor active material promotes more effective power conduction for embedded semiconductor devices.One method that may be used to form an SOI substrate includes epitaxially growing a monocrystalline silicon layer on a silicon germanium (SiGe) layer disposed over a sacrificial substrate. The SiGe layer is subsequently bonded to an oxide layer attached to a handle substrate. The sacrificial substrate and the SiGe layer are then removed using an etching process having an etching selectivity with the monocrystalline silicon layer to leave an SOI substrate including the monocrystalline silicon layer, the oxide layer, and the handle substrate.However, it has been recognized that it is difficult to use this method to form a monocrystalline silicon layer having a desirable thickness on the SiGe layer (e.g., between about 75 nm and about 150 nm for RF applications) due to stresses imposed by lattice deviation from the SiGe layer. For example, the use of a SiGe layer having a low germanium concentration allows the formation of a thick mono-silicon layer over the sacrificial substrate, but also provides poor thickness control of the mono-crystalline silicon layer due to low etch selectivity with the mono-crystalline silicon layer. Alternatively, the use of a SiGe layer having a high germanium concentration results in better control of the overall thickness variation of the monocrystalline silicon layer (since the high germanium concentration provides a higher etch selectivity than silicon for the SiGe layer), but also makes the monocrystalline silicon layer more sensitive to shift defects along an upper surface of the layer by the high stresses arising from the lattice deviation from the SiGe layer (e.g., epitaxial build-up of a monocrystalline silicon layer to a thickness of 70 to 150 nm may result in shifts along an upper surface of the monocrystalline silicon layer). The displacements etch faster than the remainder of the monocrystalline silicon layer, resulting in the formation of gaps along an upper surface of the monocrystalline silicon layer. The gaps may negatively impact the performance of devices within the SOI substrate.The present disclosure describes, in some embodiments, a low cost method of manufacturing an SOI substrate having a monocrystalline active layer substantially free of dislocation defects. The method includes epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate. An active layer is epitaxially formed on the SiGe layer, the active layer having a composition different from the SiGe layer. The sacrificial substrate is turned over and the active layer is bonded to a top surface of a dielectric layer over a first substrate. The sacrificial substrate and the SiGe layer are removed, and selective epitaxial growth is then performed to increase a thickness of the active layer. By using selective epitaxial growth to increase a thickness of the active layer after removing the SiGe layer, the active layer can be formed to a large thickness without causing dislocation defects in the active layer. Further, the SiGe may have a high germanium concentration that provides good etch selectivity to improve the total thickness variation (TTV) of the active layer.FIG. 1A illustrates a cross-sectional view of some embodiments of a disclosed SOI substrate having a monocrystalline active layer substantially free of displacement defects.The SOI substrate 100 includes a first substrate 102 covered by a dielectric layer 104. The first substrate 102 may be, for example, a bulk silicon structure in the form of a disc-like substrate. In some embodiments, the first substrate 102 has a thickness ranging from about 200 μm to about 1000 μm. The dielectric layer 104 may be, for example, or otherwise include, silicon oxide, silicon carbide, silicon nitride, silicon rich oxide (SRO), or the like.An active layer 106 is directly disposed on the dielectric layer 104. The active layer 106 is disposed on the dielectric layer 104. In some embodiments, the active layer 106 has a thickness thk. In some embodiments, the thickness thk of the active layer 106 may be in a range between about 70 nm and about 150 nm. In some further embodiments, the thickness thkof the active layer may be 106 to about 2000 nm. The active layer 106 comprises a monocrystalline lattice that is relaxed and substantially free of dislocation defects. In some embodiments, the active layer 106 may comprise monocrystalline silicon. In other embodiments, the active layer 106 may comprise a different semiconductor material. In some embodiments, the active layer 106 may also be a semiconductor compound consisting of elements from two or more different groups of the periodic table. For example, the elements may form binary alloys (two elements, e.g., GaAs), tri-material alloys (three elements, e.g., InGaAs or AlGaAs), or tetra-material alloys (four elements, e.g., AlInGaP).The active layer 106 has a maximum width 114 defined by sidewalls that are laterally inwardly offset from the outer edge of the dielectric layer 104 by an outer edge width 116. By laterally displacing the active layer 106 inward from the dielectric layer 104, a top surface of the dielectric layer 104 is exposed. In some embodiments, the outer edge width 116 may be between a range of between about 1 mm (millimeters) and about 2 mm.FIG. 1B illustrates a top view of the SOI substrate 100 of FIG. 1A. As illustrated in FIG. 1B, the active layer 106 covers a first ring portion 118 of the top surface 104 sof the dielectric layer 104. The outermost edges of the sidewalls of the active layer 106 define an inner boundary of a second ring portion 120 of the upper surface of the dielectric layer 104. The second ring portion 120 surrounds the first ring portion 118 and extends laterally over the edge width 116 as far as the outermost edge of the dielectric layer 104 and of the first substrate 102. The second ring portion 120 is exposed on the top surface 104 sof the dielectric layer 104 by being revealed by the active layer 106.Referring to FIG. 1C, the sidewalls of the active layer 106 include a lower portion 122 and an upper portion 124, as viewed in cross-section. The lower portion 122 has a substantially linear profile that extends vertically upward from the dielectric layer 104. The upper portion 124 has an angular profile that has a faceted shape 126 that tilts inwardly toward an upper surface 106 sof the active layer 106. The top surface 106 sof the active layer 106 has a narrower width than the maximum width 114 of the active layer 106. In some embodiments, the epitaxial growth of the active layer 106 results in the resulting faceted shape 126 of the upper portion 124 of the sidewalls of the active layer 106. In some embodiments, the crystalline structure of the faceted form 126 may be described by the Miller indices including a value of (1.1.1). In other embodiments, the crystalline structure of the faceted form 126 may be described by Miller indices including various values (e.g., (1,1,0), (0,0,0,1), etc.).Thus, the disclosed SOI substrate 100 includes an active layer 106 that is a continuous active layer of a semiconductor material that is substantially defect-free and has a substantially relaxed lattice structure and a thickness of up to 150 nm or more.FIGS. 2-11 illustrate some embodiments of cross-sectional views corresponding to a method of manufacturing an SOI substrate having a monocrystalline active layer substantially free of displacement defects. The method provides a good overall variation in thickness of a resulting active layer. For example, the total thickness variation of the resulting active layer may be less than about 4 nm. Although FIGS. 2 to 11 are described with reference to a method, it is to be understood that the structures illustrated in FIGS. 2 to 11 are not limited to the method, but may instead be seen separately from the method.As seen in cross-sectional view 200 of FIG. 2, a silicon-germanium (SiGe) layer 202 is epitaxially formed on a top surface 204 sof a sacrificial substrate 204. The sacrificial substrate 204 may be, for example, a bulk silicon structure in the form of a disc-like substrate. Such a substrate may, for example, have a diameter of 1-inch (25 mm); 2-inch (51 mm); 3-inch (76 mm); 4-inch (100 mm); 5-inch (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); or 450 mm (17.7 inches, commonly referred to as "18 inches"). In some embodiments, the sacrificial substrate 204 may have a type-p doping (e.g., a p+ doping). In other embodiments, the sacrificial substrate 204 may have a type n-type doping. In some embodiments, the sacrificial substrate 204 has a thickness in a range between about 200 μm and about 1000 μm.In some embodiments, the SiGe layer 202 may be formed directly on the sacrificial substrate 204 by an epitaxial growth process. In other embodiments, another semiconductor layer (not shown) having a same composition as the sacrificial substrate 204 (e.g., silicon) may be formed prior to forming the SiGe layer 202 over the sacrificial substrate 204. In such embodiments, the additional semiconductor layer may have a reduced doping concentration (e.g., a p-doping) than the sacrificial substrate 204.In various embodiments, the SiGe layer 202 may be formed by an epitaxial growth process such as molecular beam epitaxy, chemical vapor deposition (CVD), or low pressure CVD (LPCVD). During a CVD process, the sacrificial substrate 204 may be exposed to one or more volatile gas precursors that react with and decompose the top surface 204 sof the sacrificial substrate 204 and build up the SiGe layer 202 to a desired thickness 206. In some embodiments, the thickness 206 of the SiGe layer 202 may be in a range between about 20 nm and about 200 nm.In some embodiments, the SiGe layer 202 may include a substantially constant atomic percentage of germanium within the thickness 206 of the SiGe layer 202. In some embodiments, the substantially constant atomic percentage of germanium may be in a range between about 10 and about 100. In some embodiments, the substantially constant atomic percentage of germanium may be in a range between about 25 and about 35. In other embodiments, the SiGe may include a varied atomic percentage of germanium within the thickness 206 of the SiGe layer 202 achieved by varying the precursor gases as the decomposition process builds up the SiGe layer 202. For example, the gas precursors and processing conditions may be initially selected with preference for a high concentration of silicon and a low concentration of germanium, thus promoting less lattice deviation from a top surface 204 sof the underlying sacrificial substrate 204 and improving adhesion to the sacrificial substrate 204. As the SiGe decomposition process progresses, the gas precursors and process conditions may be changed progressively to change the germanium concentration near the top surface 202 sof the SiGe layer 202 to a higher percentage. The relatively high concentration of germanium along the top surface 202 sof the SiGe layer 202 allows for a higher etch selectivity during the subsequent etch process. In some embodiments, a germanium concentration at the sacrificial substrate 204 may be about 0 to 20 atomic percent compared to a silicon concentration. In some embodiments, the germanium concentration at the top surface 202 sof the SiGe layer 202 may be about 10 to 100 atomic percent compared to the silicon concentration.As shown in cross-sectional view 300 of FIG. 3A, a first active layer 108 is epitaxially formed on the SiGe layer 202. The first active layer 108 has a material composition different from the SiGe layer 202. For example, the first active layer 108 may comprise a semiconductor material such as silicon. In some embodiments, the first active layer 108 may comprise a layer of monocrystalline silicon. The first active layer 108 may also be a semiconductor compound consisting of elements of two or more different groups of the periodic table. For example, the elements may form binary alloys (two elements, e.g., GaAs), tri-material alloys (three elements, e.g., InGaAs or AlGaAs), or tetra-material alloys (four elements, e.g., AlInGaP).In various embodiments, the first active layer 108 may be epitaxially grown using vapor phase epitaxy (VPE), molecular beam epitaxy, liquid phase epitaxy, or the like. In some embodiments, a VPE process may deposit silicon by reacting silicon tetrachloride and hydrogen gases at an elevated temperature of about 1200° C. In other embodiments, the VPE process may deposit silicon using silane, dichlorosilane, and / or chlorosilane at a lower temperature of about 650° C. This process does not generate HCl as a byproduct that may inadvertently etch the silicon. The growth rate of the silicon may be controlled to achieve a monocrystalline or polycrystalline silicon structure.The first active layer 108 may be built up to a desired thickness 302. In some embodiments, the thickness 302 of the first active layer 108 may be in a range between about 20 nm and about 50 nm. The thickness 302 of the first active layer 108 may be adjusted based on the atomic percentage of germanium in the SiGe layer 202 such that the first active layer 108 may absorb the stress caused by the SiGe layer 202 without generating shift defects.For example, FIG. 3B illustrates a curve 304 showing a critical thickness (i.e., a thickness over which defects form in a first active layer of epitaxial silicon) as a function of germanium content. As can be seen in FIG. 3B, as the germanium content increases, the thickness to which the first active layer 108 can be formed decreases. For example, at a germanium concentration of 0.3, the first active layer 108 may be formed without defects to a thickness of about 20 nm, while at a germanium concentration of 0.2, the first active layer 108 may be formed without defects to a thickness of about 200 μm.As seen in cross-sectional view 400 of FIG. 4, the sacrificial substrate 204 is inverted and the first active layer 108 is bonded to a top surface 104 sof a dielectric layer 104 of a first substrate 102. In some embodiments, a direct or fusion bonding method may be used. The direct bonding process relies on intermolecular interactions such as van der Waals forces, hydrogen bonds, and covalent bonds to form a bond between two interdigitated surfaces. The connection requires no further or intermediate layers on the surfaces to be bonded. In some embodiments, to increase the bonding force, an oxide layer (not shown) may be formed over the top surface of the dielectric layer 104 prior to bonding, and the oxide layer may then be bonded to the interdigitated surface of the first active layer 108. The direct bonding may be formed at room temperature and may be subsequently annealed at elevated temperature.In some embodiments, the first substrate 102 is provided for structural support, and thus may have a lack of device characteristics and a lack of connection characteristics. In many cases, the first substrate 102 may take the form of a disc-like substrate. In some embodiments, the first substrate 102 may have a same diameter as the sacrificial substrate 204. The first substrate 102 may include a bulk silicon substrate and have a thickness of between about 300 nm and about 1000 nm.As shown in cross-sectional view 500 of FIG. 5, sacrificial substrate 204 is removed after bonding to first substrate 102. In some embodiments, the sacrificial substrate 204 may be removed by etching, physical grinding, and / or a chemical mechanical planarization (CMP) process. The etching process may include wet etching or dry etching. In some embodiments, the etching process may use a wet etchant comprising tetramethylammonium hydroxide (TMAH). In alternative embodiments, the wet etchants may include HNA (hydrofluoric, nitric, and acetic acids), potassium hydroxide (KOH), and / or buffered oxide etchant (BOE). In some embodiments, the wet etching action includes thinning the sacrificial substrate 204, followed by chemical mechanical polishing to remove the sacrificial substrate 204 completely. In some embodiments, the thinning includes a dry etching process.As seen in cross-sectional view 600 of FIG. 6, the SiGe layer 202 is partially removed. In some embodiments, the SiGe layer 202 may be partially removed, leaving a remaining SiGe layer 604 covering a top surface 108 sof the first active layer 108. In some embodiments, a wet etching process using TMAH or KOH may be used to selectively remove a top portion 602 of the SiGe layer 202. The wet etching process is completed before a top surface 108 sof the first active layer 108 is reached, as certain etchants such as TMAH may aggressively etch away an underlying epitaxial material such as silicon faster than a SiGe material, resulting in an undesirably large total thickness variation in the epitaxial material.In some embodiments, the wet etching process used to remove the SiGe layer 202 may also remove the further semiconductor layer (not shown) having the reduced doping concentration compared to the sacrificial substrate 204. Because the TMAH has high etch selectivity between silicon and silicon germanium (e.g., TMAH can etch silicon more than 20 times faster than SiGe), it provides good overall thickness variation in the removal of the additional semiconductor layer.As seen in cross-sectional view 700 of FIG. 7, the remaining SiGe layer 604 is completely removed. In some embodiments, dry or wet etching techniques may be used to remove the remaining SiGe layer 604. The wet or dry etch processes may be chosen to preferentially etch the remaining SiGe layer 604 instead of the first active layer 108. In some embodiments, a dry etching process containing a hydrogen chloride (HCl) etchant may be used. In some embodiments, such an etching process may be performed at a temperature range of 500 to 700° C., and preferably at a temperature closer to 500° C. A process at a lower temperature reduces the occurrence of crystalline changes and defects in the first active layer 108. In other embodiments, a wet etching process comprising HCl may be employed to completely remove the remaining SiGe layer 604.In some embodiments, the dry or wet etching processes may be continued after the remaining SiGe layer 604 is completely removed to remove a thin layer 702 from the top surface 108 sof the first active layer 108, which may contain a stress (i.e., the etchant removes a stressed portion of the first active layer 108). By removing the thin layer 702, the crystalline structure of the first active layer 108 is substantially relaxed. In some embodiments, the thickness of the thin layer 702 that is removed may be in a range between about 5 nm and about 10 nm. In some embodiments, removal of the thin layer 702 may reduce the thickness of the first active layer 108 to be in a range between about 10 nm and about 40 nm.In some embodiments, an initial cleaning process is performed before the remaining SiGe layer 604 is removed. The initial cleaning process removes native oxides that may have formed within the remaining SiGe layer 604 as a result of the partial removal of the SiGe layer 202. In some embodiments, a cleaning process may assist a plasma-enhanced dry etching process and simultaneously expose the remaining SiGe layer 604 to hydrogen, nitrogen trifluoride, and ammonia plasma byproducts. In some embodiments, such a cleaning process may be performed at a temperature below 400° C. to reduce crystalline changes occurring in the first active layer 108As seen in cross-sectional view 800 of FIG. 8, the first active layer 108 is selectively etched to define outermost sidewalls and expose an outer edge width 116 of a top surface 104 sof the dielectric layer 104. In some embodiments, a masking layer 802 may be formed over a disk-shaped first ring portion 118 of the top surface 108 sof the first active layer 108. The masking layer 802 may extend radially from the center of the top surface 108 sof the first active layer 108 to an outer radius covering the first ring portion 118, thereby exposing an outer edge of the first active layer 108 to the etching. In some embodiments, masking layer 802 may include an organic (e.g., photoresist, amorphous carbon, siloxane-based materials, or the like) or an inorganic material (e.g., silicon oxide, silicon nitride, titanium nitride, or the like). In some embodiments, the outer edge width 116 of the dielectric layer may be between about 1 mm and about 2 mm. In some embodiments, the selective etching of the first active layer 108 to expose the outer edge width 116 may be performed using etchants comprising HCl or TMAH.Selectively etching the first active layer 108 to expose the outer edge width 116 effectively reduces the overall thickness variation for the first active layer 108. Prior etching processes used to remove the SiGe layer 202 and a thin layer 702 of the first active layer 108 may result in more erosion and thus more thickness variation of the first active layer 108 at their outer edges. Etching away the outer edges of the first active layer 108 removes the material with localized high thickness variation to a lower total TTV for the first active layer 108. In addition, it removes chip defects along an edge of the first active layer 108 that may occur during bonding of the first active layer 108 to the dielectric layer 104.As shown in cross-sectional view 900 of FIG. 9, a second active layer 110 is epitaxially formed on the first active layer 108. The crystalline structure (i.e., the lattice) of the second active layer substantially duplicates the crystalline structure of the first active layer 108. Because the first active layer 108 is a relaxed layer that is substantially free of dislocation defects, the second active layer 110 can be formed with a desired thickness without forming dislocation defects. In some embodiments, the second active layer 110 and the first active layer 108 together form an active layer 106 that is a continuous active layer. In some embodiments, the active layer 106 comprises Si. In some embodiments, the total thickness of the active layer 106 is about 70 to 150 nm. In other embodiments, the total thickness of the active layer is more than 150 nm.The second active layer 110 leaves an outer edge of the upper surface 104 sof the dielectric layer 104 uncovered by the first active layer 108 or the second active layer 110. After the masking layer 802 is removed, the first active layer 108 (shown by the dashed line) has a substantially planar top surface, substantially vertical sidewalls, and is surrounded by the exposed outer edge width 116 of the top surface 104 sof the dielectric layer 104. The outer edge width 116 extends laterally from the outermost edges of the sidewalls of the first active layer 108 to the outer edges of the dielectric layer 104.The second active layer 110 may be formed by a selective epitaxial growth (SEG) process that uses the first active layer 108 as a seed crystal for growth of the second active layer 110. In some embodiments, the first active layer 108 may comprise silicon and the SEG process may epitaxially build silicon over the exposed surfaces of the first active layer 108. In some embodiments, the SEG process may include precursor gases including dichlorosilane (DCS) with or without HCl; or silane, disilane, or trisilane with HCl. In some embodiments, a cyclic deposition etch protocol may be followed to achieve SEG. Such a process may use silane-based precursor gases and be performed at a temperature below 550° C.In some embodiments, the epitaxially-grown second active layer 110 may be formed to have a faceted shape 126 of the upper portion 124 of the sidewalls of the active layer 106. In some embodiments, the crystal orientation of the faceted shape 126 may be described by the Miller indices and have a value of (1.1.1). In other embodiments, the crystal orientation of the faceted form 126 may be described by Miller indices having different values (e.g., (1.1.0), (0.0.1), etc.). The SEG of the second active layer 110 occurs in a generally isotropic manner and extends roughly in a ratio of one to one in the vertical and lateral directions. In some embodiments, the SEG protocol produces a single crystalline layer Si known as an epitaxial lateral over growth (ELO) layer.The growth of the active layer 110 in the lateral direction results in the second active layer 110 growing over the sidewalls of the first active layer 108 and abutting a portion of the exposed outer edge width 116 of the top surface 104 sof the dielectric layer 104. While some very small actual reduction occurs in the exposed outer edge width 116, the reduction is at a nanometer level and is likely to be about the same as the thickness growth (thk 2- thk 1) of the second active layer 110. The remaining exposed outer edge width 116 remains substantially between about 1 mm and 2 mm.In some embodiments, a cross-sectional profile of the active layer 106 includes sidewalls including a bottom portion 122 and a top portion 124. The lower portion 122 has a substantially linear profile that extends vertically upward from the dielectric layer 104. The upper portion 124 has an angular profile that has a shape of a cone or facet that tilts inwardly toward an upper surface 106 sof the active layer 106. The top surface 106 sof the active layer 106 has a narrower width than the maximum width 114 of the active layer 106. In some embodiments, the orientation and thus the cross-sectional profile of the upper portion 124 of the sidewalls of the active layer 106 may vary depending on the specific materials included and lattice properties of the first and second active layers. In some embodiments, the crystalline structure of the active layer 106 may be described by Miller indices, where the Miller indices include different values, including a value (1.1.1).As shown in cross-sectional view 1000 of FIG. 10, a plurality of semiconductor devices 1002 are formed within the active layer 106. In various embodiments, the plurality of semiconductor devices 1002 may include MOSFETs and / or other field effect transistors (FETs). Although not illustrated, the transistors may take other forms, such as FinFET devices, bipolar junction transistors, or the like.Subsequently, a connection structure 1004 may be formed over the top surface 106 sof the active layer 106. The interconnect structure includes a plurality of metal interconnect layers 1006 (e.g., metal lines, vias, and contacts) connected to a plurality of semiconductor devices 1002 and surrounded by an inter-layer dielectric (ILD) structure 1008. In some embodiments, the metal interconnect layers 1006 may include, for example, copper, tungsten, aluminum, gold, titanium, or titanium nitride. In some embodiments, the ILD structure 1008 may include silicon oxide, silicon nitride, silicon oxynitride, a low-x dielectric, an extreme low-x dielectric, another dielectric, or a combination of the above.As shown in cross-sectional view 1100 of FIG. 11, the substrate is singulated (i.e., scrambled) to form multiple individual dies 1102 from the second substrate 402. In some embodiments, the single die may be singulated from the second substrate 402 by scribing and breaking along scribe lines 1104, by mechanical sawing with a dicing saw, or by laser dicing, or other applicable methods.FIG. 12 illustrates a flow diagram of some embodiments of a method 1200 of forming an SOI substrate.While the disclosed method 1200 is illustrated and described herein as a series of acts or events, it is to be understood that the illustrated order of such acts or events is not to be interpreted in a limiting manner. For example, some acts may occur in different orders and / or concurrently with other acts or events, except those illustrated and / or described herein. Furthermore, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.At 1202, a SiGe layer is epitaxially formed over a sacrificial substrate. FIG. 2 illustrates a cross-sectional view 200 corresponding to some embodiments of act 1202.In 1204, a first active layer is epitaxially formed on the SiGe layer, the first active layer having a composition different from the SiGe layer. FIG. 3 illustrates a cross-sectional view 300 corresponding to some embodiments of act 1204.At 1206, the sacrificial substrate is inverted and the active layer is bonded to a top surface of a dielectric layer formed over a first substrate. FIG. 4 illustrates a cross-sectional view 400 corresponding to some embodiments of act 1206.At 1208, the sacrificial substrate and the SiGe layer are removed. FIGS. 5-7 illustrate cross-sectional views 500- 700 corresponding to some embodiments of act 1208.At 1210, the first active layer is etched to define the outermost sidewalls and expose an outer edge of a top surface of the dielectric layer. FIG. 8 illustrates a cross-sectional view 800 corresponding to some embodiments of act 1210.In 1212, a second active layer is epitaxially formed on the first active layer such that the outer edge width of the upper surface of the dielectric layer remains exposed by the first or second active layer. The first active layer and the second active layer collectively form a continuous active layer. FIG. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1212.In 1214, a plurality of semiconductor devices are formed within the first and second active layers and a connection structure is formed over the semiconductor devices. FIG. 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of act 1214.At 1216, a dicing process is performed to form multiple separate dies. FIG. 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of act 1216.Accordingly, in some embodiments, the present disclosure relates to a method of forming an SOI substrate having a relatively thick (e.g., greater than 75 nm) monocrystalline active layer that is substantially free of displacement defects. The method provides a good overall thickness variation of the active layer (e.g. less than 4 nm).In view of the above, some embodiments of the present application provide a method for manufacturing an SOI substrate. The method includes epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate. A first active layer is formed on the SiGe layer, the first active layer having a composition different from the SiGe layer. The first active layer is bonded to a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed. The first active layer is etched to expose an outer edge of a top surface of the dielectric layer. A continuous active layer is formed by epitaxially forming a second active layer having a substantially same composition on the first active layer, the first active layer, and the second active layer.Further, other embodiments of the present application provide a method that includes epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate. A first active layer comprising a semiconductor material is epitaxially formed at a first thickness on the upper surface of the SiGe layer. The sacrificial substrate is turned over and the active layer is bonded with a dielectric layer formed over a first substrate. The sacrificial substrate and a portion of the SiGe layer are removed while leaving a remaining portion of the SiGe layer covering an upper surface of the first active layer. The remaining portion of the SiGe layer and an upper portion of the first active layer are removed. A second active layer is formed on the first active layer, the first active layer and the second active layer collectively have a second thickness greater than the first thickness.Still further, other embodiments of the present application provide a silicon-on-insulator (SOI) substrate comprising a dielectric layer disposed over a first substrate, the dielectric layer having an outer edge disposed at an outer edge of the first substrate. An active layer covers a first ring portion of the dielectric layer. A second ring portion of the upper surface of the dielectric layer surrounds the first ring portion and extends to the outer edge of the dielectric layer. The second ring portion is exposed by the active layer.

Claims

A method of forming an SOI substrate, comprising: epitaxially forming a silicon-germanium, hereinafter referred to as SiGe, layer (202) over a sacrificial substrate (204); epitaxially forming a first active layer (108) on the SiGe layer (202), the first active layer (108) having a composition different from the SiGe layer (202); bonding the first active layer (108) to a dielectric layer (104) formed over a first substrate (102); removing the sacrificial substrate (204) and the SiGe layer (202); etching the first active layer (108) to expose an outer edge of a top surface of the dielectric layer (104); and forming a continuous active layer (108, 110) by epitaxially forming a second active layer (110) on the first active layer (108), wherein the first active layer (108) and the second active layer (110) have a substantially same composition.The method of claim 1, further comprising: leaving the outer edge width of the top surface of the dielectric layer (104) uncovered by the first (108) or second active layer (110).The method of claim 1 or 2, wherein the contiguous active layer (108, 110) comprises silicon.The method of any preceding claim, wherein the continuous active layer (108, 110) is built up to a thickness in a range between about 70 nm and about 150 nm.The method of any preceding claim, wherein the contiguous active layer (108, 110) has sidewalls having vertically extending lower portions and having upper portions that converge inwardly in a faceted shape onto an upper surface of the contiguous active layer (108, 110).The method of claim 5, wherein a crystalline structure of the contiguous active layer (108, 110) has Miller indices of (1 1 1).The method of any preceding claim, wherein the SiGe layer (202) has a concentration of Ge between about 10 and 100 atomic percent.The method of any preceding claim, wherein the SiGe layer (202) has a concentration of Ge between about 25 and 35 atomic percent.The method of any preceding claim, wherein removing the SiGe layer (202) comprises partially removing the SiGe layer (202) while leaving a remaining portion covering the first active layer (108), and cleaning the remaining portion by simultaneously exposing to hydrogen, nitrogen trifluoride and ammonia plasma, and byproducts.The method of claim 9, wherein removing the SiGe layer (202) further comprises removing the remaining portion of the SiGe layer (202) by a hydrogen chloride etch.The method of claim 10, further comprising: removing a portion of the first active layer (108) after removing the SiGe layer (202) and prior to epitaxially forming the second active layer (110).The method of any preceding claim, wherein the first active layer (108) is built up to a first thickness of about 20 to 50 nm and the SiGe layer (202) is built up to a second thickness of about 20 nm to 200 nm.A method comprising: epitaxially forming a silicon-germanium layer (202) over a sacrificial substrate (204); epitaxially forming a first active layer (108) comprising a semiconductor material to a first thickness on a top surface of the SiGe layer (202); inverting the sacrificial substrate (204); and bonding the first active layer (108) to a dielectric layer (104) formed over a first substrate (102); removing the sacrificial substrate (204) and a portion of the SiGe layer (202) while leaving a remaining portion of the SiGe layer (202) covering a top surface of the first active layer (108); Removing the remaining portion of the SiGe layer (202) and a top portion of the first active layer (108); and forming a second active layer (110) on the first active layer (108), wherein the first active layer (108) and the second active layer (110) collectively have a second thickness that is greater than the first thickness.The method of claim 13, wherein removing the portion of the SiGe layer (202) comprises etching with tetramethylammonium hydroxide or potassium hydroxide.The method of claim 13 or 14, further comprising: etching the first active layer (108) to define outermost sidewalls and expose an outer edge of a surface of the dielectric layer (104) facing the first active layer.The method of any of the preceding claims 13 to 15, wherein removing the remaining portion of the SiGe layer (202) comprises etching with hydrogen chloride.The method of any of the preceding claims 13 to 16, wherein the second active layer (110) has a lower total width along a lowermost surface of the second active layer (110) that is greater than an upper total width along an uppermost surface of the second active layer (110).

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