TEMPERATURE INSTABILITY-DEPENDENT CIRCUIT

Abstract

Circuit (100), comprising: a first vibration damping circuit (104P) coupled between an input / output pad (102) and a buffer circuit (106), wherein the first vibration damping circuit (104P) comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain; and a second vibration damping circuit (104N) coupled between the input / output pad and the buffer circuit (106), wherein the first vibration damping circuit (104P) is configured to increase a voltage received by corresponding gates of a first subset of transistors of the buffer circuit (106) when a voltage applied to the input / output pad (102) is equal to a first supply voltage, and the second vibration damping circuit (104N) is configured to decrease a voltage received by respective gates of a second subset of transistors of the buffer circuit (106) when the voltage applied to the input / output pad (102) is equal to a second supply voltage.

Description

BACKGROUND

[0001] Continuous technological advances have led to a progressive reduction in the physical dimensions of metal-oxide-semiconductor field-effect transistors (MOSFETs). Supply voltages have been reduced accordingly to save energy and to accommodate the reduction in MOSFET physical dimensions, and the corresponding MOSFET threshold voltages (Vths) have also been reduced to mitigate power losses resulting from the lower MOSFET gate voltages. Consequently, a bias temperature instability (BTI) effect, which causes a change in the MOSFET threshold voltage (Vth), has become a problem.

[0002] Circuits for semiconductor devices are known, for example, from DE 689 12 640 T2. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this revelation are best understood from the following detailed description when read with the accompanying figures. It should be noted that various features are not necessarily shown to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for the clarity of the explanation. Fig. Figure 1 illustrates an exemplary block diagram of a circuit with a vibration damper circuit according to some embodiments. Fig. Figure 2A illustrates an exemplary circuit diagram of the vibration damper circuit according to some embodiments. Fig. Figure 2B illustrates another exemplary circuit diagram of the vibration damper circuit according to some embodiments. Fig. Figure 2C illustrates an exemplary comparison of the voltage quantities at different nodes of a vibration damper circuit according to some embodiments. Fig. Figure 2D illustrates a further exemplary comparison of the stress quantities at different nodes of a vibration damper circuit according to some embodiments. Fig. Figure 3 illustrates a flowchart of an exemplary procedure for operating the vibration damper circuit of Fig. 1 according to various embodiments. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0004] The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. It is understood that when, for example, an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or one or more interposed elements may be present.

[0005] A BTI effect is a device degradation mechanism identified in MOSFETs below 100 nm. For example, when the gate of a p-type MOSFET is negatively biased relative to its source at elevated temperature, oxide interface traps form due to the interaction of holes in the reversed-channel layer with the gate oxide. This instability is measured as an increase in the size of the p-type MOSFET, Vth. Higher voltage temperatures generally lead to more pronounced degradation. Similar degradation occurs in n-type MOSFETs when the gate is positively biased relative to its source. The BTI effects observed in p-type and n-type MOSFETs are generally referred to as the "negative VZTA (NBTI) effect" and the "positive BTI (PBTI) effect," respectively. The NBTI / PBTI effect is known to cause a degradation of the reliability performance of the MOSFET due to the change in Vth.

[0006] Such bonding-to-interface (BTI) effects can cause a more serious problem for an input / output (I / O) buffer circuit, as the I / O buffer is typically directly coupled to a bonding pad configured to receive a supply voltage whose magnitude ranges from a minimum rated voltage (e.g., a voltage source or ground voltage (VSS)) to a maximum rated voltage (e.g., a voltage drop or supply voltage (VDD)). Due to such a relatively large change in the magnitude of the received voltage, the I / O buffer, which is configured to prevent noise associated with the supply voltage from being received by a core logic circuit, may fail over its lifetime. Existing techniques for addressing this problem typically rely on predictive models to simulate the BTI effects.To ensure the reliability of I / O buffer circuits, predictive models often lead to an overdesign of various physical features of the I / O buffer circuits, which in turn can cause other problems, such as a trade-off in usable area, a trade-off in time-based performance, etc. Therefore, existing techniques for providing reliable I / O buffer circuits are not entirely satisfactory.

[0007] The present disclosure presents various embodiments of a vibration damping circuit coupled between a bonding pad and an input / output (I / O) buffer circuit. In some embodiments, the vibration damping circuit includes a p-type vibration damping circuit coupled to corresponding gates of a subset of p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) of the I / O buffer circuit, and / or an n-type vibration damping circuit coupled to corresponding gates of a subset of n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) of the I / O buffer circuit.In some embodiments, the p-type vibration damping circuits are configured to increase the lower limit of the voltage swing received by the gates of the pMOSFET subset of the I / O buffer circuit; and the n-type vibration damping circuits are configured to decrease the upper limit of the voltage swing received by the gates of the nMOSFET subset of the I / O buffer circuit. Accordingly, the magnitude of the voltage swing received by the respective gates of the pMOSFET and nMOSFET subsets is reduced. Due to such a small voltage swing magnitude, the aforementioned NBTI and PBTI effects can be significantly reduced from occurring in the coupled I / O buffer circuit.

[0008] Fig. Figure 1 illustrates a block diagram of an exemplary circuit 100 according to various embodiments. The circuit 100 includes a bonding pad 102, a vibration damping circuit 104, an input / output (I / O) buffer circuit 106, and a core logic circuit 108. In some embodiments, the bonding pad 102 is configured to receive a supply voltage from a voltage source (not shown); the vibration damping circuit 104 coupled to the bonding pad 102 is configured to reduce the magnitude of any voltage swing received by the I / O buffer circuit 106; and the I / O buffer circuit 106 coupled to the vibration damping circuit 104 is configured to prevent noise associated with the supply voltage from being received by the coupled core logic circuit 108 (e.g., one of the various digital circuits that perform the main functions of the entire circuit 100).

[0009] In some embodiments, the I / O buffer circuit 106 includes one of several buffer circuits known in the art that can perform the aforementioned function, such as a Schmitt trigger circuit, an inverter circuit, etc. According to some embodiments, the I / O buffer circuit 106 is formed by several pMOSFETs and several nMOSFETs, which are described below. To ensure that the several pMOSFETs and nMOSFETs experience minimal BTI effects, the vibration damping circuit 104 in some embodiments may include a p-type vibration damping circuit 104P and an n-type vibration damping circuit 104N, which are configured to minimize the NBTI effect that may occur in the several pMOSFETs of the I / O buffer circuit 106 and the PBTI effect that may occur in the several nMOSFETs of the I / O buffer circuit 106.

[0010] In particular, the p-type vibration damper circuit 104P is configured in some embodiments to increase the magnitude of a voltage received by corresponding gates of the multiple pMOSFETs of the I / O buffer circuit 106 when the magnitude of the supply voltage received by the bonding pad 102 is equal to a minimum rated voltage, for example, a voltage source (VSS); and the n-type vibration damper circuit 104N is configured to decrease the magnitude of a voltage received by corresponding gates of the multiple nMOSFETs of the I / O buffer circuit 106 when the magnitude of the supply voltage received by the bonding pad 102 is equal to a maximum rated voltage, for example, a voltage drop (VDD).This allows the magnitude of the voltage swing received by the respective gates of the multiple pMOSFETs and nMOSFETs of the I / O buffer circuit 106 to be significantly reduced, which advantageously extends the lifetime of the I / O buffer circuit 106 without making any of the aforementioned compromises (since there is no overdesign of the I / O buffer circuit 106).

[0011] It is noted that, according to some embodiments, the vibration damping circuit 104 can only include one of the p-type vibration damping circuits 104P and the n-type vibration damping circuit 104N. For example, if the multiple nMOSFETs of the I / O buffer circuit 106 do not affect the PBTI effect, the vibration damping circuit 104 cannot include the n-type vibration damping circuit 104N. Similarly, if the multiple pMOSFETs of the I / O buffer circuit 106 do not affect the NBTI effect, the vibration damping circuit 104 cannot include the p-type vibration damping circuit 104P.

[0012] Fig. Figure 2A illustrates schematic diagrams of the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N according to an embodiment of the present disclosure. In the illustrated embodiment of Fig. In 2A, the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N are each coupled between the bonding pad 102 and the I / O buffer circuit 106, which is implemented by a Schmitt trigger circuit. Although the I / O buffer circuit 106 is a Schmitt trigger circuit in Fig. 2A includes, it is understood that the I / O buffer circuit 106 can include any of the buffer circuits known in the art, while it is within the scope of the present disclosure.

[0013] As mentioned above, the bonding pad 102 is configured in some embodiments to receive a supply voltage 201. The magnitude of such a supply voltage 201 can range from a minimum rated voltage (e.g., a voltage source (VSS)) to a maximum rated voltage (e.g., a voltage drop (VDD)). In some embodiments, the p-vibration damping circuit 104P includes a transistor 202 (e.g., a pMOSFET) whose gate is coupled to a supply voltage 203 equal to VSS, corresponding to a low logic state. This turns on the transistor 202, for example, when it operates in a linear conduction mode. It is understood that the transistor 202 can be any other type of transistor (e.g., a bipolar junction transistor (BJT), a high-electron-mobility field-effect transistor (HEMFET), etc.) within the scope of this disclosure.On the other hand, the n-vibration damping circuit 104N includes a transistor 204 (e.g., an nMOSFET) whose gate is coupled to a supply voltage 205 equal to VDD, which corresponds to a high logic state. This turns on the transistor 204, for example, when it operates in a linear conduction mode. It is understood that the transistor 204 can be any other type of transistor (e.g., a bipolar junction transistor (BJT), a high electron mobility field-effect transistor (HEMFET), etc.) within the scope of this disclosure. In some embodiments, the bonding pad 102 is typically coupled to a source of the transistor 202 and a drain of the transistor 204. A drain of the transistor 202 is coupled to a node "X", and a source of the transistor 204 is coupled to a node "Y".

[0014] According to some embodiments, the I / O buffer circuit 106, implemented as a Schmitt trigger circuit, includes transistors M1, M2, M3, M4, M5, and M6. Although in the illustrated embodiment of Fig. 2A Since transistors M1, M2, and M5 are each implemented by a pMOSFET and transistors M3, M4, and M6 are each implemented by an nMOSFET, it is understood that transistors M1 to M6 can be implemented by any other transistor, while remaining within the scope of this disclosure. The I / O buffer circuit 106 is coupled (e.g., biased) between the supply voltages 205 (VDD) and 203 (VSS). In particular, the sources of transistors M1 and M4 are each coupled to the supply voltages 205 (VDD) and 203 (VSS), respectively.The respective gates of transistors M1 and M2 connected to node X form a first input of the I / O buffer circuit 106 (hereinafter "input X"); the respective gates of transistors M3 and M4 connected to node Y form a second input of the I / O buffer circuit 106 (hereinafter "input Y"); and the respective gates of transistors M5 and M6 connected to node "Z" form an output of the I / O buffer circuit 106 (hereinafter "output Z"). In some embodiments, output Z is coupled to the core logic circuit 108. In some embodiments, a drain of transistor M1 is coupled to a source of transistor M2 at a common node that is coupled to a source of transistor M5; a source of transistor M3 is coupled to a drain of transistor M4 at a common node that is coupled to a source of transistor M6. and such stacked transistor pairs (M1 and M2) and (M3 and M4) are coupled to node Z.In some embodiments, the drains of transistors M5 and M6 are each coupled to the supply voltages 203 (VSS) and 205 (VDD).

[0015] In order to cause the vibration damping circuit 104 to reduce the voltage swing received by the I / O buffer circuit 106, the p-type and n-type vibration damping circuit 104P are configured in some embodiments to increase the magnitude of a voltage present at node X when the magnitude of the supply voltage 201 is equal to VSS, and to decrease the magnitude of a voltage present at node Y when the magnitude of the supply voltage 201 is equal to VDD.

[0016] For example, while the magnitude of the voltage present at node X is increased (i.e., when the magnitude of the supply voltage 201 = VSS), since the increased voltage is predefined and essentially small with respect to VDD (which corresponds to the high logic state), the I / O buffer circuit 106 can, in some embodiments, receive the logic state present at node X as a low logic state ("logic 0"). In some embodiments, the increased magnitude of the voltage at node X is essentially equal to a threshold voltage of transistor 202. On the other hand, since the magnitude of the voltage applied to node Y remains at VSS (because transistor 204 is switched on to be in linear conduction mode), the I / O buffer circuit 106 can also, in some embodiments, receive the logic state applied to node Y as logic 0.Thus, at a supply voltage of 201 = VSS, the I / O buffer circuit 106 receives its two inputs (inputs X and Y) as logic 0, but with the voltage at node X increased by the threshold voltage of transistor 202. Fig. Figure 2C illustrates an exemplary comparison of the stress quantities at different nodes of the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N in Fig. 2A according to some embodiments. As in the exemplary comparison 231 of Fig. As shown in 2C, if the voltage magnitude (V_PAD) 201 at pad 102 is equal to VSS, the voltage magnitude (V_PAD_P) at node X is increased by the threshold voltage (Vth(MPa)) of transistor 202.

[0017] While the magnitude of the voltage present at node Y is reduced (i.e., when the magnitude of the supply voltage 201 = VDD), since the reduced voltage is predefined and essentially small with respect to VDD (which corresponds to the high logic state), the I / O buffer circuit 106 can, in some embodiments, receive the logic state present at node Y as a high logic state ("logic 1"). In some embodiments, the reduced magnitude of the voltage at node Y is essentially equal to a threshold voltage of transistor 204. On the other hand, since the magnitude of the voltage applied to node X remains at VDD (because transistor 202 is switched on to be in linear conduction mode), the I / O buffer circuit 106 can also, in some embodiments, receive the logic state applied to node X as logic 1.Thus, at a supply voltage of 201 = VDD, the I / O buffer circuit 106 receives its two inputs (inputs X and Y) as logic 1, but with the voltage at node Y reduced by the threshold voltage of transistor 204. As in the exemplary comparison 232 of . Fig. As shown in 2C, when the voltage magnitude (V_PAD) 201 at pad 102 is equal to VDD, the voltage magnitude (V_PAD_N) at node Y is reduced by the threshold voltage (Vth(MNa)) of transistor 204.

[0018] In some embodiments, the I / O buffer circuit 106, implemented as a Schmitt trigger circuit, functions as a level-sensing comparator with a hysteresis window. Its output (e.g., output Z) transitions from logic 0 to logic 1 when a rising input voltage exceeds an upper switching threshold Vhi, and returns to its original logic state only when the input voltage exceeds a lower threshold Vlo, which is less than Vhi. The difference between the two thresholds, Vhi-Vlo, is the hysteresis window associated with the Schmitt trigger circuit. Since the Schmitt trigger circuit is familiar to those skilled in the art, the operation of the I / O buffer circuit 106 will only be briefly described below.

[0019] During operation, it is assumed that the logic states at inputs X and Y are initially logic 0 (e.g., when the supply voltage 201 = VSS is as described above). Transistors M1 and M2 are switched on, while transistors M3 and M4 are switched off, connecting output Z to VDD, i.e., logic 1. Conversely, transistor M5 remains off and transistor M6 remains on to set node "A" to logic 1.

[0020] Suppose the voltages at nodes X and Y begin to increase (e.g., when the supply voltage 201 transitions to VDD). When the voltages are high enough, transistors M3 and M4 become conductive (i.e., switched on), while transistors M1 and M2 become off. When the conducted transistor M4 connects node A to the supply voltage 203 (VSS, or ground), which in turn grounds output Z through the also-conducting transistor M3, output Z effectively transitions to logic 0. However, transistor M4 must overcome the connection from VDD to node A (via transistor M6) before it can switch output Z to logic 0. The relative magnitudes of transistors M3, M4, and M6 are chosen to set the upper switching threshold Vhi at which output Z transitions from logic 0 to logic 1.Conversely, once output Z is at logic 0, transistor M5 remains switched on due to the ground connection of its gate via transistors M3 and M4, while transistors M1 and M2 remain switched off. For the I / O buffer circuit 106 to reset output Z to logic 1 when the voltages at nodes X and Y drop, transistor M1 must become sufficiently conductive to overcome the grounding effects of transistor M5 and set node "B" to logic 1. This is the point at which the I / O buffer circuit 106 switches back to logic 0, and the relative values ​​of transistors M1, M2, and M5 are chosen such that the lower switching threshold Vlo, at which output Z transitions from logic 1 to logic 0, provides the correct value for the hysteresis window.

[0021] As already mentioned, the magnitude of the supply voltage 201 received by the bonding pad 102 generally ranges from VSS to VDD, which can lead to damage (e.g. BTI effects) to the I / O buffer circuit 106 during its service life. To advantageously minimize the BTI effects, the p-type and n-type vibration damping circuits 104P and 104N of the present disclosure are configured to increase the magnitude of a voltage received by the gates of the p-type transistors of the I / O buffer circuit 106, such as transistors M1 and M2 (i.e., the magnitude of the voltage applied at node X) of VSS when the magnitude of the supply voltage 201 is equal to VSS, and to decrease the magnitude of a voltage received by the gates of the n-type transistors of the I / O buffer circuit 106, such as transistors M3 and M4 (i.e., the magnitude of the voltage applied at node Y) of VDD when the magnitude of the supply voltage 201 is equal to VDD.In particular, the increased voltage magnitude is predefined as the threshold voltage of transistor 202 in the p-type vibration damper circuit 104P; and the decreased voltage magnitude is predefined as the threshold voltage of transistor 204N in the n-type vibration damper circuit 104N. Accordingly, the voltage swing received by transistors M1 and M2 can be advantageously reduced to VDD (if the supply voltage 201 is equal to VDD) minus the sum of the threshold voltage of transistor 202 and VSS (if the supply voltage 201 is equal to VSS); and the voltage swing received by transistors M3 and M4 can be advantageously reduced to VDD minus the threshold voltage of transistor 204 (if the supply voltage 201 is equal to VDD), then minus VSS (if the supply voltage 201 is equal to VSS).

[0022] In one embodiment, the p-type vibration damping circuit 104P can reduce the BTI degradation level of the input buffer from 8.11%, which is equivalent to an overdesign of the I / O buffer circuit to 3.91%. In another embodiment, the p-type vibration damping circuit 104P can achieve a much smaller device size and / or much better time-based performance than an overdesign of the I / O buffer circuit.

[0023] Fig. Figure 2B illustrates schematic diagrams of the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N according to a further embodiment of the present disclosure. In the illustrated embodiment of Fig. 2B, the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N are each coupled between the bonding pad 102 and the I / O buffer circuit 106, which is also implemented by a Schmitt trigger circuit. For the sake of clarity, the explanation of the I / O buffer circuit 106 will not be repeated below.

[0024] In the illustrated embodiment of Fig. 2B includes the p-type vibration damper circuit 104P, transistors 212 and 214; and the n-type vibration damper circuit 104N, transistors 222 and 224. Although transistors 212 and 214 are each supported by a pMOSFET and transistors 222 and 224 are each supported by an nMOSFET in Fig. Since transistors 212 to 224 are implemented as shown in Figure 2B, it is understood that transistors 212 to 224 can be implemented as any other transistor within the scope of this disclosure. In some embodiments, transistors 212 and 214 of the p-type vibration damper circuit 104P are driven and discharged by a supply voltage 215, the magnitude of which (hereinafter referred to as "Vbias_P") is between VSS and VDD; and transistors 222 and 224 of the n-type vibration damper circuit 104N are driven by a supply voltage 225, with the supply voltage 225 at the source, the magnitude of which (hereinafter referred to as "Vbias_N") is between VSS and VDD.

[0025] In particular, the p-type vibration damper circuit 104P from Fig. 2B a source of transistor 212 and a gate of transistor 214 are coupled together with the bonding pad 102, and a drain of transistor 212 and a source of transistor 214 are coupled together with node X (i.e., the respective gates of the pMOSFETs of the I / O buffer circuit 106). In the n-type vibration damper circuit 104N of Fig. 2B are a drain of transistor 222 and a gate of transistor 224 coupled together with the bonding pad 102, and a source of transistor 222 and a drain of transistor 224 are coupled together with node Y (i.e. the respective gates of the nMOSFETs of the I / O buffer circuit 106).

[0026] Similar to the embodiment with reference to Fig. In 2A, the p-type vibration damping circuit 104P and the n-type vibration damping circuit 104N are configured to increase the magnitude of the voltage present at node X when the magnitude of the supply voltage 201 received by the bonding pad 102 is equal to VSS, to cause the vibration damping circuit 104 in some embodiments to reduce the voltage swing received by the I / O buffer circuit 106 and to decrease the magnitude of the voltage present at node Y when the magnitude of the supply voltage 201 is equal to VDD, except that the increased magnitude is determined according to Vbias_P (i.e., the magnitude of the supply voltage 215) and the decreased magnitude according to Vbias_N (i.e., the magnitude of the supply voltage 225).

[0027] For example, when the magnitude of the voltage applied to node X is increased (i.e., when the magnitude of the supply voltage 201 = VSS), transistor 214 is driven by VSS, which corresponds to logic 0. Thus, transistor 214 is turned on. In some embodiments, transistor 212 can be turned off because Vbias_P, at which the gate of transistor 212 is biased, is greater than VSS, at which the source of transistor 212 is biased. Accordingly, the voltage magnitude present at node X is pulled so that it is essentially equal to the voltage at which the drain of transistor 214 is biased, i.e., Vbias_P. In some embodiments, Vbias_P is chosen to be slightly larger than VSS, while the I / O buffer circuit 106 can still receive the logic state present at node X as logic 0. On the other hand, transistor 224 is also driven by VSS, such that transistor 224 is turned off.Transistor 222 is driven by Vbias_N, which is slightly larger than VSS, so that transistor 222 can be switched on according to some embodiments. Thus, the voltage magnitude present at node Y (the voltage applied to the source of transistor 222) is essentially equal to VSS (the voltage applied to the drain of transistor 222), whereby the I / O buffer circuit 106 also receives the logic state present at node Y as logic 0.

[0028] In some embodiments, the magnitude of the voltage applied to node X (the magnitude of the voltage received by transistors M1 and M2) can therefore be increased from VSS to Vbias_P if the supply voltage 201 is equal to VSS. Fig. Figure 2D illustrates an exemplary comparison of the stress quantities at different nodes of the p-type vibration damper circuit 104P and the n-type vibration damper circuit 104N in Fig. 2B according to some embodiments. As in the exemplary comparison 241 of Fig. In 2D representation, when the voltage (V_PAD) 201 at pad 102 equals VSS, the voltage (V_PAD_P) at node X is increased from VSS to Vbias_P. Thus, the voltage swing received by transistors M1 and M2 can be advantageously reduced to VDD (when the supply voltage 201 equals VDD) minus Vbias_P (when the supply voltage 201 equals VSS).

[0029] As the magnitude of the voltage applied to node Y decreases (i.e., when the magnitude of the supply voltage 201 equals VDD), transistor 224 is driven by VDD, corresponding to logic 1. Thus, transistor 224 is turned on. In some embodiments, transistor 222 can be less conductive than transistor 224, since Vbias_N, at which the gate of transistor 222 is biased, is smaller than VDD, at which the gate of transistor 224 is biased. Accordingly, the voltage magnitude present at node Y is pulled so that it is essentially equal to the voltage at which the source of transistor 224 is biased, i.e., Vbias_N. In some embodiments, Vbias_N is chosen to be slightly smaller than VDD, while the I / O buffer circuit 106 can still receive the logic state present at node Y as logic 1.On the other hand, transistor 214 is also controlled via VDD in such a way that transistor 214 is switched off. And transistor 212 is controlled by Vbias_N, which is smaller than VDD, so that transistor 212 can be switched on according to some embodiments. Thus, the voltage magnitude present at node X (the voltage applied to the drain of transistor 212) is essentially equal to VDD (the voltage applied to the source of transistor 212), whereby the I / O buffer circuit 106 also receives the logic state present at node X as logic 1.

[0030] In some embodiments, the magnitude of the voltage applied to node Y (the magnitude of the voltage received by transistors M3 and M4) can therefore be reduced from VDD to Vbias_N if the supply voltage 201 is equal to VDD. As shown in the exemplary comparison 242 of Fig. In 2D representation, when the voltage (V_PAD) 201 at pad 102 equals VDD, the voltage (V_PAD_N) at node Y is reduced from VDD to Vbias_N. Thus, the voltage swing received by transistors M3 and M4 can be advantageously reduced to Vbias_N (when the supply voltage 201 equals VDD) minus VSS (when the supply voltage 201 equals VSS).

[0031] Fig. Figure 3 illustrates a flowchart of an exemplary method 300 for operating the vibration damper circuit 104 according to various embodiments. In different embodiments, the processes of method 300 are described by the respective components in the Fig. The components shown in 1-2B are executed. For illustrative purposes, the following embodiment of method 300 is shown in conjunction with the Fig. 1-2B described. The illustrated embodiment of method 300 is only an example. Therefore, it should be understood that any number of processes can be omitted, rearranged, and / or added while remaining within the scope of this disclosure.

[0032] Procedure 300 begins with step 302, in which an input voltage in the range of VSS to VDD is received. For example, the input voltage could be a supply voltage (e.g., supply voltage 201) received by a bonding pad (e.g., bonding pad 102). As mentioned above, such a supply voltage 201 received by bonding pad 102 typically ranges from VSS, which is a minimum rated voltage, to VDD, which is a maximum rated voltage.

[0033] Procedure 300 continues with step 304, in which the input voltage is determined to be equal to either VSS or VDD. If the supply voltage 201 is equal to VSS, the procedure continues with step 306 and the following step, and if the supply voltage 201 is equal to VDD, the procedure continues with step 310 and the following step, each of which is explained below.

[0034] Referring to the first operation 306, a first voltage received by at least one pMOSFET of an I / O buffer circuit is increased. If the supply voltage 201 is equal to VSS using the same example, the p-type vibration damper circuit 104P of the vibration damper circuit 104 is configured to increase the voltage applied at node X, corresponding to the first voltage described herein, from VSS either by the threshold voltage of transistor 202 (as in Fig. 2A described) or to determine the magnitude of the supply voltage 215, Vbias_P (as described in Fig. to increase (as described in 2B).

[0035] The procedure 300 then continues with process 308, in which the increased first voltage is applied to the at least one pMOSFET of the I / O buffer circuit and VSS is applied to the at least one nMOSFET of the I / O buffer circuit. Continuing with the same example, the pMOSFETs of the I / O buffer circuit 106 (e.g., transistors M1 and M2) receive the increased first voltage, i.e., the voltage applied at node X, as their respective inputs, while the nMOSFETs of the I / O buffer circuit 106 (e.g., transistors M3 and M4) still receive VSS as their respective inputs.

[0036] Referring to operation 310, a second voltage received by at least one nMOSFET of the I / O buffer circuit is reduced. If the supply voltage 201 is equal to VDD using the same example, the n-type vibration damper circuit 104N of the vibration damper circuit 104 is configured to reduce the voltage applied at node Y, corresponding to the second voltage described herein, from VDD either by the threshold voltage of transistor 204 (as in Fig. 2A described) or to determine the magnitude of the supply voltage 225, Vbias_N (as described in Fig. (described in 2B) to reduce.

[0037] The procedure 300 then continues with process 312, in which the reduced second voltage is applied to the at least one nMOSFET of the I / O buffer circuit and VDD to the at least one pMOSFET of the I / O buffer circuit. Continuing with the same example, the nMOSFETs of the I / O buffer circuit 106 (e.g., transistors M1 and M2) receive the reduced second voltage, i.e., the voltage applied to node Y, as their respective inputs, while the pMOSFETs of the I / O buffer circuit 106 (e.g., transistors M1 and M2) still receive VDD as their respective inputs.

[0038] In one embodiment, a circuit includes: a first type of vibration damper circuit coupled between an input / output pad and a buffer circuit, wherein the first vibration damper circuit comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain;and a second type of vibration damper circuit coupled between the input / output pad and the buffer circuit, wherein the first type of vibration damper circuit is configured to increase a voltage received by corresponding gates of a first subset of transistors of the buffer circuit when a voltage applied to the input / output pad equals a first supply voltage, and the second type of vibration damper circuit is configured to decrease a voltage received by corresponding gates of a second subset of transistors of the buffer circuit when the voltage applied to the input / output pad equals a second supply voltage.

[0039] In another embodiment, a circuit comprises: a vibration damping circuit coupled between an input / output pad and a buffer circuit, wherein the vibration damping circuit includes a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain; wherein the vibration damping circuit is configured either to increase an input voltage in response to the input voltage being equal to a first supply voltage and to supply the increased input voltage to the buffer circuit, or to decrease the input voltage in response to the input voltage being equal to a second supply voltage and to supply the decreased input voltage to the buffer circuit.

[0040] In yet another embodiment, a method includes: receiving an input voltage ranging from a first supply voltage to a second supply voltage;and either increasing a first voltage received by at least one p-type metal-oxide-semiconductor field-effect transistor of a buffer circuit in response to the input voltage being equal to the first supply voltage, or decreasing a second voltage received by at least one n-type metal-oxide-semiconductor field-effect transistor of the buffer circuit in response to the input voltage being equal to the second supply voltage, wherein the first voltage is increased to a first bias voltage applied to a gate of a first transistor coupled between the input voltage and the buffer circuit, and wherein the second voltage is decreased to a second bias voltage applied to a gate of a second transistor coupled between the input voltage and the buffer circuit.

Claims

[1] Circuit (100), comprising: a first vibration damping circuit (104P) coupled between an input / output pad (102) and a buffer circuit (106), wherein the first vibration damping circuit (104P) comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain; and a second vibration damping circuit (104N) coupled between the input / output pad and the buffer circuit (106), wherein the first vibration damping circuit (104P) is configured to increase a voltage received by corresponding gates of a first subset of transistors of the buffer circuit (106) when a voltage applied to the input / output pad (102) is equal to a first supply voltage, and the second vibration damping circuit (104N) is configured to decrease a voltage received by respective gates of a second subset of transistors of the buffer circuit (106) when the voltage applied to the input / output pad (102) is equal to a second supply voltage. [2] Circuit according to claim 1, wherein the second supply voltage is greater than the first supply voltage. [3] Circuit according to claim 1 or 2, wherein the first supply voltage is an earth voltage (VSS) and the second supply voltage is a supply voltage (VDD). [4] Circuit according to one of the preceding claims, wherein the first subset of the transistors of the buffer circuit (106) are each p-type metal oxide semiconductor field-effect transistors and the second subset of the transistors of the buffer circuit (106) are each n-type metal oxide semiconductor field-effect transistors. [5] Circuit according to one of the preceding claims, wherein a gate of the first p-type metal oxide semiconductor field-effect transistor is coupled to the first supply voltage, a source of the first p-type metal oxide semiconductor field-effect transistor is coupled to the input / output pad (102) and a drain of the first p-type metal oxide semiconductor field-effect transistor is coupled to the respective gates of the first subset of transistors of the buffer circuit (106). [6] Circuit according to one of the preceding claims, wherein the first bias voltage is higher than the first supply voltage but lower than the second supply voltage. [7] Circuit according to claim 1, wherein a source of the first p-type metal oxide semiconductor field-effect transistor and a gate of the second p-type metal oxide semiconductor field-effect transistor are each coupled to the input / output pad (102), and a drain of the first p-type metal oxide semiconductor field-effect transistor and a source of the second p-type metal oxide semiconductor field-effect transistor are each coupled to the respective gates of the first subset of transistors of the buffer circuit (106). [8] Circuit according to one of the preceding claims, wherein the second vibration damper circuit (104N) comprises an n-type metal oxide semiconductor field-effect transistor, wherein a gate of the n-type metal oxide semiconductor field-effect transistor is coupled to the second supply voltage, a drain of the n-type metal oxide semiconductor field-effect transistor is coupled to the input / output pad (102) and a source of the n-type metal oxide semiconductor field-effect transistor is coupled to the respective gates of the second subset of transistors of the buffer circuit (106). [9] Circuit according to any one of claims 1 to 7, wherein the second vibration damper circuit (104N) comprises a first n-type metal oxide semiconductor field-effect transistor driven by a second bias voltage and a second n-type metal oxide semiconductor field-effect transistor at whose source the second bias voltage is applied, wherein the second bias voltage is higher than the first supply voltage but lower than the second supply voltage. [10] Circuit according to claim 9, wherein a drain of the first n-type metal oxide semiconductor field-effect transistor and a gate of the second n-type metal oxide semiconductor field-effect transistor are each coupled to the input / output pad (102), and a source of the first n-type metal oxide semiconductor field-effect transistor and a source of the second n-type metal oxide semiconductor field-effect transistor are each coupled to the respective gates of the second subset of transistors of the buffer circuit (106). [11] Circuit, comprising: a vibration damping circuit (104) coupled between an input / output pad (102) and a buffer circuit (106); wherein the vibration damping circuit (104) comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage, and a second p-type metal-oxide-semiconductor field-effect transistor, at whose drain the first bias voltage is applied; wherein the vibration damping circuit (104) is configured either to increase an input voltage in response to the input voltage being equal to a first supply voltage and to supply the increased input voltage to the buffer circuit (106), or to decrease the input voltage in response to the input voltage being equal to a second supply voltage and to supply the decreased input voltage to the buffer circuit (106). [12] Circuit according to claim 11, wherein the first p-type metal oxide semiconductor field-effect transistor is configured to increase the input voltage in response to the input voltage being equal to the first supply voltage, and supplies the increased input voltage to the buffer circuit (106). [13] Circuit according to claim 12, wherein the first p-type metal oxide semiconductor field-effect transistor comprises: a gate coupled to the first supply voltage, a source coupled to the input / output pad (102), and a drain coupled to corresponding gates of at least one p-type metal oxide semiconductor field-effect transistor of the buffer circuit (106). [14] Circuit according to claim 11, wherein the vibration damper circuit (104) comprises an n-type metal oxide semiconductor field-effect transistor configured to reduce the input voltage in response to the input voltage being equal to the second supply voltage, and supplies the reduced input voltage to the buffer circuit (106). [15] Circuit according to claim 14, wherein the n-type metal oxide semiconductor field-effect transistor comprises: a gate coupled to the second supply voltage, a drain coupled to the input / output pad, and a source coupled to corresponding gates of at least one n-type metal oxide semiconductor field-effect transistor of the buffer circuit (106). [16] Circuit according to claim 11, wherein the first bias voltage is higher than the first supply voltage but lower than the second supply voltage. [17] Circuit according to claim 11, wherein the vibration damper circuit comprises: a first n-type metal-oxide-semiconductor field-effect transistor driven by a second bias voltage; and a second n-type metal-oxide-semiconductor field-effect transistor, at whose source the second bias voltage is applied; where the second bias voltage is higher than the first supply voltage, but lower than the second supply voltage. [18] Procedures, in full: the reception (302) of an input voltage in the range from a first supply voltage to a second supply voltage; and either increasing (306) a first voltage received by at least one p-type metal-oxide-semiconductor field-effect transistor of a buffer circuit (106) in response to the input voltage being equal to the first supply voltage, or decreasing (310) a second voltage received by at least one n-type metal-oxide-semiconductor field-effect transistor of the buffer circuit (106) in response to the input voltage being equal to the second supply voltage, wherein the first voltage is increased to a first bias voltage applied to a gate of a first transistor coupled between the input voltage and the buffer circuit (106) (308), and wherein the second voltage is reduced to a second bias voltage applied to a gate of a second transistor coupled between the input voltage and the buffer circuit (106) (312). [19] Method according to claim 18, wherein the first supply voltage is an earth voltage (VSS) and the second supply voltage is a supply voltage (VDD). [20] Method according to claim 18 or 19, wherein the first voltage is received from a gate of the at least one p-type metal oxide semiconductor field-effect transistor of the buffer circuit (106) and the second voltage is received from a gate of the at least one n-type metal oxide semiconductor field-effect transistor of the buffer circuit.

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