METHOD FOR BONDING SEMICONDUCTOR WEAPONS

Abstract

Method for bonding semiconductor wafers (102a, 102b), the method comprising: forming a first integrated circuit, IC, (104a-c) over a central region (106) of a first semiconductor wafer (102a); forming a first annular bond support structure (110) over an annular circumferential region (112) of the first semiconductor wafer (102a), wherein the annular circumferential region (112) of the first semiconductor wafer (102a) surrounds the central region (106) of the first semiconductor wafer (102a); and bonding a second semiconductor wafer (102b) to the first semiconductor wafer (102a) such that a second IC arranged on the second semiconductor wafer (102b) is electrically coupled to the first IC, wherein forming the first IC comprises: forming a redistribution dielectric layer (324) over a coupling structure (310), wherein the coupling structure (310) is arranged over the first semiconductor wafer (102a);and forming a bond interface dielectric layer (326) both on the redistribution dielectric layer (324) and on the first annular bond support structure (110), wherein the first annular bond support structure (110) is formed downstream of the redistribution dielectric layer (324).

Description

GENERAL STATE OF THE ARTThe semiconductor industry has continually improved processing capabilities and power consumption of integrated circuits (ICs) by reducing the minimum feature size. In recent years, however, process limitations have made it difficult to continue reducing the minimum feature size. Stacking two-dimensional (2D) ICs into three-dimensional (3D) ICs has appeared as a potential approach to further improve the processing capabilities and power consumption of ICs.US 2014 / 0 264 762 A1 discloses a method for producing a semiconductor device. The method includes providing first and second upper and lower side wafers. The two wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protective seal may be formed in the edge region of the first wafer. The first and second wafers may further be bonded together to form a device stack. The protective seal in the device stack contacts the first and second wafers to form a seal and protects the devices in subsequent processing.US 2016 / 0 093 591 A1 discloses a MEMS bond separation structure for the production of three-dimensional integrated circuits (3D IC) with two or more planes. The MEMS bond separation structure includes a sacrificial MEMS separation layer, which may include a pillar or post structure, or alternatively a continuous sacrificial layer, for bonding and separation.From US 2015 / 0 194 455 A1 a method for producing a semiconductor component is known, wherein the method comprises providing a first chip, and wherein the first chip has a substrate and a plurality of dielectric layers, and wherein the plurality of dielectric layers has metallization layers formed therein. The method includes laminating metallization layers formed therein and bonding a first surface of the plurality of dielectric layers of the first die to a surface of a second die.US 2014 / 0 124 889 A1 describes an integrated circuit system which comprises a first component wafer which is connected to a second component wafer at a connection interface of dielectrics. Each wafer includes a plurality of chips, each chip including a device, a metal stack, and a seal ring formed in an edge region of the chip. The sealing rings included in the chips of a second device wafer each include a first conductive path provided with metal formed in a first opening extending from a back side of the second device wafer through the second device wafer and through the connection interface to the sealing ring of a corresponding chip in the first device wafer.US 2015 / 0 014 820 A1 discloses a production method for a semiconductor component. The method includes forming a first recessed portion around an outer edge of a device wafer at a peripheral edge portion of a first surface of the device wafer, and forming a second recessed portion around an outer edge of a carrier substrate at a bonding surface of the carrier substrate. The first surface of the device wafer and the adhesion surface of the support substrate are adhered together by an adhesive. The device wafer is ground from a second surface side located on a side opposite to the first surface to a depth position reaching a bottom surface of the first recessed portion.US 2012 / 0 193 785 A1 describes multichip housings or multichip modules with stacked chips and continuous through silicon / substrate vias (TSVs) which are produced using "ignition-first" technology. The Ignition First technology may include forming an isolation package in conjunction with a TSV at an early time in the manufacturing process without actually forming the associated TSV. The TSV connected to the insulation housing is formed later in the manufacturing process.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with practice common in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of multiple semiconductor wafers, each of which has bonding support structures disposed over circumferential regions bonded together. FIG. 2 illustrates a cross-sectional view of multiple semiconductor wafers, each of which has bonding support structures disposed over circumferential regions bonded together. FIG. 3 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1. FIG. 4 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1. FIG. 5 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1. FIG. 6 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1. FIG. 7 illustrates a cross-sectional view of some more detailed non-claimed embodiments of at least one of the semiconductor wafers of FIG. 1. FIG. 8 illustrates a design view of some embodiments of at least one of the semiconductor wafers of FIG. 1.FIGS. 9A-9K illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 3 and bonding the semiconductor wafer of FIG. 3 to another semiconductor wafer. FIG. 10 illustrates a top view of some embodiments of the wafer dicing process of FIG. 9K performed on some embodiments of the bonded-together first and second semiconductor wafers of FIGS. 9J to 9K.FIGS. 11A-11I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 4.FIGS. 12A-12I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 5.FIGS. 13A-13I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 6.FIGS. 14A through 14J illustrate a series of cross-sectional views of some non-claimed embodiments of a method of forming the semiconductor wafer of FIG. 7. FIG. 15 illustrates a flow diagram of some embodiments of a method for forming the semiconductor wafer of FIG. 3 and bonding the semiconductor wafer of FIG. 3 to another semiconductor wafer.DETAILED DESCRIPTIONThe present disclosure will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily to scale. It should be understood that this detailed description and corresponding figures do not in any way limit the scope of the present disclosure, and that the detailed description and figures provide only some examples to illustrate some ways in which the inventive concepts may manifest themselves.The present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, for ease of discussion herein, may be used to describe the relationship of an element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation of the device in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein may likewise be interpreted accordingly.A three-dimensional (3D) integrated circuit (IC) includes multiple integrated chip dies stacked and bonded together. One possible manufacturing method of a 3D IC includes a wafer stacking method including bonding a first semiconductor wafer to a second semiconductor wafer. In such a method, a plurality of first 2D ICs are disposed on the first semiconductor wafer and a first bond pattern is disposed over the first 2D ICs. A plurality of second 2D ICs are disposed on the second semiconductor wafer and a second bonding structure is disposed over the plurality of second 2D ICs. The first bonding structure and the second bonding structure may be stacked on top of each other and bonded together (e.g., via eutectic bonding, hybrid bonding, etc.) such that a plurality of 3D ICs are formed, each of which includes a first 2D IC electrically coupled to a second 2D IC. Subsequently, a wafer dicing process (e.g., mechanical sawing, laser cutting, etc.) may be performed on the bonded semiconductor wafers to form multiple separate 3D ICs.One challenge with the above wafer stacking method is non-bonding (NB) regions. NB regions are regions over the first semiconductor wafer and / or regions over the second semiconductor wafer that do not bond to each other during a bonding process (e.g., due to a top surface of the first bonding structure that is not substantially planar between opposing edges of the first semiconductor wafer). Since semiconductor wafers typically have a rounded / frusto-conical slope region, NB regions may exist over a perimeter region of the first semiconductor wafer and / or a perimeter region of the second semiconductor wafer.During bonding, these NB regions may result in insufficient structural support between the first semiconductor wafer and the second semiconductor wafer, which may exacerbate as the number of semiconductor wafers bonded together increases (e.g., stacks of 5 semiconductor wafers). This insufficient structural support may introduce undesirable mechanical stress(s) during bonding and / or during subsequent processing steps of the bonded semiconductor wafers (e.g., stacking and / or bonding additional semiconductor wafers, handling the bonded semiconductor wafers, singulating the bonded semiconductor wafers, etc.). This undesirable mechanical stress may result in mechanical defects (e.g., delamination, cracking, etc.) that reduce the yield of 3D ICs.In various embodiments, the present application is directed to a method of bonding a first semiconductor wafer and a second semiconductor wafer together to reduce NB regions (e.g., a perimeter region) of the first semiconductor wafer. The method includes forming a bond support structure (e.g., a dielectric material layer) over the perimeter region of the first semiconductor wafer. Subsequently, the first semiconductor wafer is bonded to the second semiconductor wafer. By forming the bond support structure over the perimeter region of the first semiconductor wafer, NB areas over the perimeter region of the first semiconductor wafer may be reduced. In some embodiments, due to the bonding support structure having a top surface substantially planar with a top surface of a bonding structure of the first semiconductor wafer, the bonding support structure may reduce NB areas over the perimeter region of the first semiconductor wafer. In other embodiments, the bond support structure may reduce NB areas over the perimeter region of the first semiconductor wafer by being a sub-structure over which the bond structure (or portions of the bond structure) may be formed, such that the bond structure may be formed with a substantially planar top surface extending between opposing edges of the first semiconductor wafer.By reducing the NB regions over the perimeter region of the first semiconductor wafer during bonding, structural support between the first semiconductor wafer and the second semiconductor wafer may be improved. This improved structural support may reduce unwanted mechanical stresses during bonding and / or during subsequent processing steps of the bonded semiconductor wafers. Accordingly, the bonding support structure can improve the yield of 3D ICs.FIG. 1 illustrates a cross-sectional view of multiple semiconductor wafers, each of which has bonding support structures disposed over circumferential regions bonded together.As shown in FIG. 1, multiple semiconductor wafers 102 a- bare bonded together (e.g., via hybrid bonding, eutectic bonding, etc.) to form multiple three-dimensional (3D) integrated circuits (ICs) 101 a- c. For example, a first semiconductor wafer 102 ais bonded to a second semiconductor wafer 102 bto form a first 3D IC 101 a, a second 3D IC 101 b, and a third 3D IC 101 c.A plurality of two-dimensional (2D) integrated circuits (ICs) 104 a- care arranged on each of the semiconductor wafers 102 a- b. For example, a first 2D IC 104 a, a second 2D IC 104 b, and a third 2D IC 104 care disposed on both the first semiconductor wafer 102 aand the second semiconductor wafer 102 b. In some embodiments, multiple 2D ICs 104 a- care arranged in / over central regions 106 of semiconductor wafers 102 a- b, respectively. Further, the bond structures 108 are arranged over the semiconductor wafers 102 a- b, respectively. In some embodiments, the bond structures 108 are arranged over the pluralities of 2D ICs 104 a- c, respectively. In further embodiments, the bond structures 108 are arranged over the central regions 106 of the semiconductor wafers 102 a- b, respectively.The bonding support structures 110 are disposed over each of the semiconductor wafers 102 a- b. The bonding support structures 110 are disposed over circumferential regions 112 of each of the semiconductor wafers 102 a- b. In some embodiments, the bond support structures 112 respectively include a dielectric material layer (e.g., an oxide, a nitride, or the like) that extends around an outer perimeter of the semiconductor wafers 102 a- bas a ring. By forming the bond support structures 110 over the perimeter regions 112 of the semiconductor wafers 102 a- b, the bond support structures 110 may increase a height of the perimeter regions 112 to be substantially equal to a height of the central regions 106 of the semiconductor wafers 102 a- b. By increasing a height of the perimeter regions 112, the bond support structures 110 are configured to reduce NB areas over the perimeter regions 112 of the semiconductor wafers 102 a- b. In some embodiments, the bonding support structures 110 may reduce NB areas over the perimeter regions 112 of the semiconductor wafers 102 abbecause the top surfaces of the bonding support structures 110 are respectively substantially planar with top surfaces of the bonding structures 108. In other embodiments, the bond support structures 110 may reduce NB areas over the perimeter regions 112 of the semiconductor wafers 102 a- bby being sub-structures over which the bond structures 108 (or portions of the bond structures 108) may be formed such that the bond structures 108 may be formed with substantially planar top surfaces that extend between opposite edges of the semiconductor wafers 102 a- b, respectively.By reducing NB areas over the perimeter regions 112 of the semiconductor wafers 102 a- bduring bonding, structural support between the first semiconductor wafer 102 aand the second semiconductor wafer 102 bmay be improved. The improved structural support may reduce unwanted mechanical stresses during bonding and / or during subsequent processing steps of the bonded semiconductor wafers 102 a- b. Accordingly, the bonding support structures 110 may improve the yield of the 3D ICs 101 a- 101 c.FIG. 2 illustrates a cross-sectional view of multiple semiconductor wafers, each of which has bonding support structures disposed over circumferential regions bonded together.As shown in FIG. 2, a plurality of semiconductor wafers 102 a- eare bonded to each other. In some embodiments, the plurality of semiconductor wafers 102 a- ecomprises a first semiconductor wafer 102 a, a second semiconductor wafer 102 b, a third semiconductor wafer 102 c, a fourth semiconductor wafer 102, and a fifth semiconductor wafer 102 e. It is understood that the plurality of semiconductor wafers 102 a- emay include any number of semiconductor wafers.In some embodiments, some of the semiconductor wafers 102 a- ecomprise a first bond structure 108 aand a second bond structure 108 b. For example, the first semiconductor wafer 102 amay include a first bonding structure 108 aarranged on a front side 102 a,fof the first semiconductor wafer 102 aand a second bonding structure 108 barranged on a back side 102 a,bof the first semiconductor wafer 102 a. In further embodiments, the front side (e.g., 102 a, f) of the semiconductor wafers 102 a- emay correspond to the side of the semiconductor wafers 102 a- ein which the 2D ICs 104 a- care arranged. In still further embodiments, the back side (e.g., 102 a, b) of each of the semiconductor wafers 102 a- ecorresponds to a side of the semiconductor wafer opposite the front side (e.g., 102 a, f) of the semiconductor wafer.In some embodiments, some of the semiconductor wafers 102 a- eare coupled to multiple semiconductor wafers. For example, the first semiconductor wafer 102 amay be bonded to the third semiconductor wafer 102 cand the second semiconductor wafer 102 b. In further embodiments, the third semiconductor wafer 102 cis bonded to the first semiconductor wafer 102 avia the second bond structure 108 b. In further embodiments, the bonding support structures 110 may extend along outer edges of the first semiconductor wafers 102 ato the back side 102 a,bof the first semiconductor wafer 102 such that the bonding support structures 110 are sub-structures on which the second bonding structure 106 bmay be partially arranged. Therefore, NB regions between the first semiconductor wafer 102 aand the third semiconductor wafer 102 cmay be reduced.In some embodiments, through substrate vias (TSVS) (not shown) extend through the first semiconductor wafer 102 ato electrically couple the plurality of 2D ICs 104 a- cof the first semiconductor wafer 102 awith the plurality of 2D ICs 104 a- cof the third semiconductor wafer 102 c. In further embodiments, the second semiconductor wafer 102 bis bonded to the first semiconductor wafer 102 avia the first bond structure 108 asuch that the plurality of 2D ICs 104 a- cof the first semiconductor wafer 102 a, the plurality of 2D ICs 104 a- cof the second semiconductor wafer 102 band the plurality of 2D ICs 104 a- cof the third semiconductor wafer 102 care electrically coupled to one another. It should be appreciated that a substantially similar electrical coupling may exist between each of the semiconductor wafers 102 a- eto form multiple 3D ICs 101 a- 101 c.In some embodiments, an input / output (I / O) structure 114 may be disposed on an uppermost (or lowermost) semiconductor wafer (e.g., the second semiconductor wafer 102 b) of the plurality of semiconductor wafers 102 a- e. In further embodiments, the I / O structure 114 includes a plurality of conductive I / O contacts 116 (e.g., pads, solder bumps, etc.) disposed in / over an I / O dielectric layer 118. The I / O structure 114 is configured to provide electrical connections to the 3D ICs 101 a- cand their corresponding semiconductor package. For example, one or more conductive I / O contacts 116 may be electrically coupled to the first 3D IC 101 a. In further embodiments, TSVS (not shown) extend through the uppermost (or lowermost) semiconductor wafers to electrically couple the conductive I / O contacts 116 to the plurality of 2D ICs 104 a- cof the uppermost (or lowermost) semiconductor wafer. In still further embodiments, the 2D ICs 104 a- cof the uppermost (or lowermost) semiconductor wafers may include logic configured to access the semiconductor devices of the other 2D ICs 104 a- cof the 3D ICs 101 a- c, respectively.FIG. 3 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1 While FIG. 3 illustrates a single 2D IC 104, it is apparent that the 2D IC 104 may be one of multiple 2D ICs (see, e.g., FIG. 1 ).As shown in FIG. 3, a 2D IC 104 includes multiple semiconductor devices 302 (e.g., a transistor). In some embodiments, each of the semiconductor devices 302 includes a pair of source / drain regions 304 disposed in the semiconductor wafer 102. In such embodiments, each of the semiconductor devices 302 includes a gate electrode 306 stacked on a gate dielectric 308 and disposed between the source / drain regions 304. In further embodiments, the semiconductor wafer 102 includes any type of semiconductor body (e.g., monocrystalline silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.).According to the invention, a coupling structure 310 is arranged over the semiconductor wafer 102 and the semiconductor devices 302. The interconnect 310 includes a plurality of conductive contacts 312 and a plurality of conductive features 314 (e.g., conductive lines and conductive vias) disposed in a plurality of stacked interlayer dielectric (ILD) layers 316. The interconnect 310 is configured to provide an electrical connection between various semiconductor devices 302 to form circuits for the 2D IC 104. In some embodiments, the coupling structure 310 may be disposed over the central region 106 of the semiconductor wafer 102 and laterally separated from outermost edges of the semiconductor wafer 102 by non-zero distances.In some embodiments, the plurality of stacked ILD layers 316 may include one or more of a low-k dielectric layer (e.g., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, an oxide (e.g., silicon dioxide (SiO 2)) or the like. In further embodiments, the conductive contacts 312 may include, for example, tungsten, copper, or the like. In further embodiments, the conductive features 314 may include, for example, copper, aluminum, or the like. In further embodiments, the plurality of stacked ILD layers 316 may have a substantially planar top surface. In still further embodiments, the plurality of stacked ILD layers 316 may be disposed over the central region 106 of the semiconductor wafer 102 and laterally separated from outermost edges of the semiconductor wafer 102 by non-zero distances.A bond pattern 108 is disposed over the interconnect 310. In some embodiments, the bond structure 108 includes a first etch stop layer 318 disposed on the plurality of stacked ILD layers 316 and top conductive features 314 (e.g., a top conductive line). In further embodiments, the first etch stop layer 318 is a different material than the plurality of stacked ILD layers 316, and may include, for example, silicon nitride (SiN). In further embodiments, the first etch stop layer 318 may have a substantially planar top surface. In still further embodiments, the bond structure 108 may be disposed over the central region 106 of the semiconductor wafer 102 and laterally separated from outermost edges of the semiconductor wafer 102 by non-zero distances.In some embodiments, a bond structure dielectric layer 320 is disposed on the first etch stop layer 318. In further embodiments, the bond structure dielectric layer 320 is a different material than the first etch stop layer 318, and may include, for example, an oxide (e.g., SiO 2), a low-k dielectric, an ultra-low-k dielectric, or the like. In further embodiments, the bond structure dielectric layer 320 may comprise the same material as the plurality of stacked ILD layers 316. In other embodiments, the bond structure dielectric layer 320 may comprise a different material than the plurality of stacked ILD layers 316. In further embodiments, the bond structure dielectric layer 320 may have a substantially planar top surface.In some embodiments, a second etch stop layer 322 is disposed on the bond structure dielectric layer 320. In further embodiments, the second etch stop layer 322 is a different material than the bond structure dielectric layer 320 and may include, for example, SiN. In further embodiments, the second etch stop layer 322 may be the same material as the first etch stop layer 318. In still further embodiments, the second etch stop layer 322 may have a substantially planar top surface.In some embodiments, a redistribution dielectric layer 324 is disposed on the second etch stop layer 322. In further embodiments, redistribution dielectric layer 324 is a different material than second etch stop layer 322 and may include, for example, an oxide (e.g., SiO 2), a low-k dielectric, an ultra-low-k dielectric, or the like. In still further embodiments, redistribution dielectric layer 324 may have a substantially planar top surface.In some embodiments, a bonding interface dielectric layer 326 is disposed on redistribution dielectric layer 324. In further embodiments, the bond interface dielectric layer 326 is a different material than the redistribution dielectric layer 324, and may include, for example, an oxynitride (e.g., silicon oxynitride (SiON)), a nitride (e.g., SiN), an oxide (e.g., SiO 2) or the like. In still further embodiments, the bond interface dielectric layer 326 may have a substantially planar top surface.Further, the bonding structure 108 includes a conductive bond connector 328 and a conductive bond via 330. In some embodiments, the conductive bond connector 328 extends from a top surface of the bond interface dielectric layer 326, through the bond interface dielectric layer 326, through the redistribution dielectric layer 324, and through the second etch stop layer 322 to a top surface of the bond structure dielectric layer 320. In further embodiments, a top surface of the conductive bond connector 328 is substantially planar with the top surface of the bond interface dielectric layer 326. In still further embodiments, the conductive bond connector 328 may include, for example, copper, aluminum, tungsten, another conductive material, or a combination of the foregoing. While FIG. 3 illustrates a single conductive bond connector 328, it is apparent that the bond structure 108 may include multiple conductive bond connectors.The conductive bond via 330 extends from the conductive bond connector 328 to the conductive features 314 such that the conductive bond connector 328 is electrically coupled to the conductive features 314. In some embodiments, the conductive bond via 330 extends through the bond structure dielectric layer 320 and the first etch stop layer 318 to contact a top conductive feature 314 (e.g., a top conductive line). In further embodiments, the conductive bond via 330 includes, for example, copper, aluminum, tungsten, another conductive material, or a combination of the foregoing. In further embodiments, conductive bond via 330 may comprise the same material as conductive bond connector 328. In other embodiments, conductive bond via 330 may comprise a different material than conductive bond connector 328. While FIG. 3 illustrates a single conductive bond via 330, it is apparent that the bond structure 108 may include multiple conductive bond vias, each of which electrically couples a conductive bond connector 328 to a conductive feature 314 (e.g., an uppermost conductive line). Further, it should be appreciated that conductive redistribution lines (not shown) in redistribution dielectric layer 324 may be arranged such that conductive bond via 330 and / or conductive bond connector 328 may be arranged at different locations while still being electrically coupled to a conductive feature 314.As also shown in FIG. 3, in some embodiments, the perimeter regions 112 of the semiconductor wafer 102 include the sloped regions 332 located respectively along opposite outer edges of the semiconductor wafer 102. In some embodiments, the outer edges of the semiconductor wafer 102 have a rounded profile, a frustoconical profile, or the like. In further embodiments, perimeter regions 112 include inner perimeter regions 334, respectively. The inner circumferential regions 334 separate the slope regions 332 from the central region 106 of the semiconductor wafer 102.In some embodiments, a width (e.g., a distance between opposing perimeter regions 112) of the central region 106 of the semiconductor wafer 102 may be between about 92 percent of a width of the semiconductor wafer 102 and about 99.8 percent of the width of the semiconductor wafer 102. In particular, in further embodiments, the width of the central region 106 of the semiconductor wafer 102 may be about 94 percent of the width of the semiconductor wafer 102. In further embodiments, the widths of the perimeter regions 112 (e.g., a distance between the central region 106 and an edge of the semiconductor wafer 102) may be respectively between about 0.1 percent of the width of the semiconductor wafer 102 and about 4 percent of the width of the semiconductor wafer 102, such that the combined widths of opposing perimeter regions 112 may be between about 0.2 percent of the width of the semiconductor wafer and about 8 percent of the width of the semiconductor wafer 102. In particular, in further embodiments, the widths of the perimeter regions 112 may be approximately 3 percent of the width of the semiconductor wafer 102, such that the combined widths of opposing perimeter regions 112 may be approximately 6 percent of the width of the semiconductor wafer 102.The plurality of stacked ILD layers 316 have a lesser thickness (e.g., a substantially zero thickness) along edges of the semiconductor wafer 102 than in a central region 106 of the semiconductor wafer 102. In order to prevent insufficient structural support when the semiconductor wafer 102 is bonded to another wafer (e.g., as shown in FIG. 1 ), bonding support structures 110 are disposed on the semiconductor wafer 102. The bond support structures 110 may include a dielectric material layer disposed along opposite sides of the plurality of stacked ILD layers 316 over the perimeter regions 112 of the semiconductor wafer 102, respectively. In some embodiments, the dielectric material layer may extend from the semiconductor wafer 102 to a top surface of the bond structure 108. In other embodiments, the dielectric material layer may have a top surface above or below the top surface of the bond structure 108. The dielectric material layer is free of conductive interconnect layers (e.g., interconnect wires and / or vias) and / or redistribution layers.In some embodiments, the bonding support structures 110 extend laterally from opposite outer edges of the semiconductor wafer 102 to the central region 106 of the semiconductor wafer 102. In such embodiments, each of the bonding support structures 110 is disposed over one of the sloped regions 332 and one of the inner perimeter regions 334. For example, one of the bonding support structures 110 may be disposed over one of the slope regions 332 and one of the inner circumferential regions 334, and another of the bonding support structures 110 may be disposed over another of the slope regions 332 opposite that of the slope regions 332 and over another of the inner circumferential regions 334 opposite that of the inner circumferential regions 334. In further embodiments, the bond support structures 110 may be disposed over the perimeter regions 112 of the semiconductor wafer 102 and laterally separated from outermost edges of the semiconductor wafer 102 by non-zero distances.In some embodiments, the bonding support structures 110 vertically extend from a top surface of the semiconductor wafer 102 along opposite sidewalls of the plurality of stacked ILD layers 316 and opposite sidewalls of the bonding structure 108. In further embodiments, the bond support structures 110 may contact the semiconductor wafer 102, the plurality of stacked ILD layers 316, the first etch stop layer 318, the bond structure dielectric layer 320, the second etch stop layer 322, the redistribution dielectric layer 324, and the bond interface dielectric layer 326. In further embodiments, upper surfaces of the bond support structures 110 may be substantially planar with the upper surface of the bond interface dielectric layer 326 and / or the conductive bond connector 328 such that the bond structure 108 and the bond support structures 110 provide a substantially planar upper surface between opposing edges of the semiconductor wafer 102. In further embodiments, outer sidewalls of the bond support structures 110 may be substantially vertical. In further embodiments, the outer sidewalls of the bond support structures 110 may be correspondingly vertically aligned with opposing outer edges of the semiconductor wafer 102.In some embodiments, the bond support structures 110 may include, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiON), a carbide (e.g., silicon carbide (SiC)), another dielectric, or a combination of the foregoing. In further embodiments, the bonding support structures 110 may have a height (e.g., a distance from a bottom surface of a bonding support structure 110 to a top surface of the bonding support structure 110) of between about 200 angstroms (Å) and about 10 micrometers (μm). In further embodiments, the bonding support structures 110 may have substantially similar heights. In other embodiments, the bonding support structures 110 may have different heights.In some embodiments, the bond support structures 110 may in particular comprise SiO 2 and have a height between about 1000 Å and about 4 μm or a height between about 4.1 μm and about 10 μm. In further embodiments, the bond support structures 110 may comprise SiON and have a height between about 1000 Å and about 4 μm or a height between about 4.1 μm and about 10 μm. In further embodiments, the bond support structures 110 may comprise SiN and have a height between about 500 Å and about 3 μm or a height between about 3.1 μm and about 9 μm. In further embodiments, the bond support structures 110 may comprise SiC and have a height between about 200 Å and about 2 μm or a height between about 2.1 μm and about 5 μm. In still further embodiments, the heights of the bond support structures 110 may vary accordingly (e.g., by up to about 20,000 Å) across the widths of the bond support structures 110.The differences in materials, widths, and heights of the bond support structures 110 provide the ability to adjust the bond support structures 110 to reduce different α-step profiles (e.g., a difference in height between an uppermost layer disposed over the central region 106 and an uppermost layer disposed over the perimeter regions 112) that may exist between the central region 106 of the semiconductor wafer 102 and the perimeter regions 112. Therefore, the NB regions over the semiconductor wafers can be reduced, although the α-step profile can vary between different semiconductor wafers.In some embodiments, the bond support structures 110 may have a refractive index (RI) greater than undoped silicon glass (USG). In further embodiments, the RI of the bond support structures 110 may be between about 1.65 and about 1.45. In further embodiments, the RI of the bond support structures 110 may be, in particular, approximately 1.6. The different RIs provide the ability to adjust the amount of incident radiation (e.g., photons) propagating through the bond support structures 110. Therefore, the performance of the 2D IC 104 can be improved by allowing / preventing a predetermined amount of the incident radiation from propagating through the bond support structures 110.In some embodiments, an etch rate of the bond support structures 110 may be different from that of the bond interface dielectric layer 326, the conductive bond connector 328, the I / O dielectric layer 118 (see, e.g., FIG. 2 ), and / or the I / O conductive contacts 116 (see, e.g., FIG. 2 ). In other embodiments, the etch rate of the bond support structures 110 may be approximately the same as that of the bond interface dielectric layer 326, the conductive bond connector 328, the I / O dielectric layer 118, and / or the conductive I / O contacts 116. In further embodiments, the bond support structures 110 may have a lower etch rate than that of the USG. The different etch rates provide the ability to adjust the rate at which the bond support structures 110 are etched. Therefore, etching processes (e.g., environmentally friendly wafer processes) may be performed (e.g., before or after bonding) after the bond support structures 110 are formed without excessively / inadequate etching of the bond support structures 110 with respect to the bond interface dielectric layer 326, the conductive bond connector 328, the I / O dielectric layer 118, and / or the conductive I / O contacts 116.FIG. 4 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1.As shown in FIG. 4, in some embodiments, the bond support structures 110 are sub-structures in which portions of the bond structure 108 are disposed. Because the bonding support structures 110 are sub-structures in which portions of the bonding structure 108 are disposed, a top surface of the bonding structure 108 may include a substantially planar top surface that extends over (or beyond) the bonding support structures 110 and between opposing edges of the semiconductor wafer 102.In some embodiments, uppermost surfaces of the bond support structures 110 are spaced from a front side (see, e.g., FIG. 2 ) of the semiconductor wafer 102 by at least about an equal distance as an uppermost surface of the coupling structure 310 from the front side of the semiconductor wafer 102. In further embodiments, the uppermost surfaces of the bond support structures 110 are disposed over an uppermost surface of the second etch stop layer 322. In still further embodiments, outermost surfaces of each of the bond support structures 110 are spaced apart from the central region 106 of the semiconductor wafer 102 by a greater distance than the edges of the semiconductor wafer 102 are spaced apart from the central region 106 of the semiconductor wafer 102.In some embodiments, the bond support structures 110 may have rounded outer sidewalls (e.g., facing away from the central region 106). In further embodiments, the rounded outer sidewalls extend from above a top surface of the second etch stop layer 322 along a radius of curvature to below a centerline axis 336 of the semiconductor wafer 102, wherein the centerline axis 336 extends laterally through the semiconductor wafer 102 and is equally spaced from the front side of the semiconductor wafer 102 and the back side (see, e.g., FIG. 2 ) of the semiconductor wafer 102.In some embodiments, redistribution dielectric layer 324 is disposed on second etch stop layer 322 and bond support structures 110. In further embodiments, redistribution dielectric layer 324 may have a substantially planar bottom surface over central region 106 of semiconductor wafer 102 and may have rounded inner sidewalls lining bond support structures 110 over perimeter regions 112 of semiconductor wafer 102. In further embodiments, redistribution dielectric layer 324 has a substantially planar top surface. In further embodiments, the substantially planar top surface of redistribution dielectric layer 324 extends between opposing edges of semiconductor wafer 102. In further embodiments, the top surface of redistribution dielectric layer 324 may extend beyond outermost surfaces of bond support structures 110. In further embodiments, redistribution dielectric layer 324 may include outer sidewalls that extend beyond outer sidewalls of bond support structures 110. In still further embodiments, the outer sidewalls of the redistribution dielectric layer may be rounded.In some embodiments, the bonding interface dielectric layer 326 is disposed on the redistribution dielectric layer 324 and extends over both the central region 106 and the peripheral regions 112 of the semiconductor wafer 102. In further embodiments, the bonding interface dielectric layer 326 has a substantially planar top surface extending between opposing edges of the semiconductor wafer 102. In further embodiments, the top surface of the bonding interface dielectric layer 326 may extend beyond outermost surfaces of the bonding support structures 110. In further embodiments, the bonding interface dielectric layer 326 may have outer sidewalls that extend beyond outer sidewalls of the redistribution dielectric layer 324. In still further embodiments, the outer sidewalls of the bond interface dielectric layer 326 may be rounded.FIG. 5 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1.As shown in FIG. 5, in some embodiments, the bonding support structures 110 respectively have substantially planar top surfaces. In some embodiments, the substantially planar top surfaces of the bond support structures 110 are substantially planar with the top surface of the second etch stop layer 322. In further embodiments, the substantially planar upper surfaces of the bond support structures 110 may extend from the second etch stop layer 322 to opposite outer edges of the semiconductor wafer 102. In further embodiments, the substantially planar upper surfaces of the bond support structures 110 may extend from the second etch stop layer beyond opposing outer edges of the semiconductor wafer 102. In still further embodiments, the rounded outer sidewalls of the bonding support structures 110 may extend from corresponding planar upper surfaces of the bonding support structures 110 to below the centerline axis (see, e.g., FIG. 4 ) of the semiconductor wafer 102.FIG. 6 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1.As shown in FIG. 6, in some embodiments, each of the bond support structures 110 has rounded outer sidewalls that extend from the top surface of the redistribution dielectric layer 324 to below the centerline axis (see, e.g., FIG. 4 ) of the semiconductor wafer 102. In further embodiments, portions of the bond interface dielectric layer 326 disposed over perimeter regions 112 of the semiconductor wafer 102 may be disposed below a top surface of the bond interface dielectric layer 326. In still further embodiments, the bonding interface dielectric layer 326 may conformally line the redistribution dielectric layer 324 and the bonding support structures 110.FIG. 7 illustrates a cross-sectional view of some more detailed embodiments of at least one of the semiconductor wafers of FIG. 1.As shown in FIG. 7, in some embodiments, multiple ILD layers 316 a- care stacked on the semiconductor wafer 102. For example, a first ILD layer 316 ais disposed on the semiconductor wafer 102, a second ILD layer 316 bis disposed on the first ILD layer 316 a, and a third ILD layer 316 cis disposed on the second ILD layer 316 b. In further embodiments, the ILD layers (e.g., the second ILD layer 316 band the third ILD layer 316 c) stacked on the first ILD layer 316 amay correspond to inter-metal dielectric (IMD) layers. It is apparent that the plurality of ILD layers 316 a- cmay include any number of ILD layers.In some embodiments, the first ILD layer 316 a, the second ILD layer 316 b, the third ILD layer 316 c, the first etch stop layer 318, the bond structure dielectric layer 320, and the second etch stop layer 322 are disposed over the central region 106 and the perimeter regions 112 of the semiconductor wafer 102. In further embodiments, the first ILD layer 316 amay conformally line the semiconductor wafer 102. In further embodiments, the second ILD layer 316 b, the third ILD layer 316 c, the first etch stop layer 318, the bond structure dielectric layer 320, and the second etch stop layer 322 may conformally line each other. In further embodiments, redistribution dielectric layer 324 may conformally line second etch stop layer 322 and extend over both central region 106 and perimeter regions 112 of semiconductor wafer 102. It should be appreciated that any combination of the foregoing layers (e.g., 316 a- c, 318, 320, 322, and / or 324) conformally line each other and extend over both the central region 106 and the perimeter regions 112 of the semiconductor wafer 102.In some embodiments, the bond support structures 110 are located in the perimeter region 112 over one or more of the ILD layers. In some embodiments, the bond support structures 110 are arranged on rounded outer sidewalls of the second etch stop layer 322, for example. In still further embodiments, the bond support structures 110 may include top surfaces disposed over a top surface of the second etch stop layer 322. While FIG. 7 illustrates the bond support structures 110 disposed on the second etch stop layer 322, it is apparent that the bond support structure may be disposed on the first ILD layer 316 a, the second ILD layer 316 b, the third ILD layer 316 c, the first etch stop layer 318, the bond structure dielectric layer 320, or the redistribution dielectric layer 324. It will be further understood that upper surfaces of the bond support structures 110 may be substantially planar (or disposed above) an upper surface of any layer (e.g., 316 a- c, 318, 320, or 324) on which the bond support structures 110 are disposed.FIG. 8 illustrates a design view of some embodiments of at least one of the semiconductor wafers of FIG. 1.As shown in FIG. 8, in some embodiments, the semiconductor wafer 102 may correspond to a disk-shaped semiconductor wafer 102. In further embodiments, a diameter of the central region 106 of the disk-shaped semiconductor wafer 102 may be between about 92 percent of the diameter of the disk-shaped semiconductor wafer 102 and about 99.8 percent of the diameter of the disk-shaped semiconductor wafer 102. In further embodiments, the diameter of the central region 106 of the disk-shaped semiconductor wafer 102 may be, in particular, approximately 94 percent of the diameter of the disk-shaped semiconductor wafer 102.In some embodiments, the perimeter regions 112 of the semiconductor wafer 102 may correspond to an annular perimeter region 112 of the semiconductor wafer 102. In further embodiments, the annular perimeter region 112 may have an annular perimeter region annular thickness T P that is between about 0.1 percent of the diameter of the disk-shaped semiconductor wafer 102 and about 4 percent of the diameter of the disk-shaped semiconductor wafer 102. In further embodiments, the annular perimeter region ring thickness T may be p in particular about 3 percent of the diameter of the disk-shaped semiconductor wafer 102. In still further embodiments, the slope regions 332 may correspond to an annular slope region 332 and the inner perimeter regions 334 may correspond to an annular inner perimeter region 334.In some embodiments, the bonding support structures 110 correspond to an annular bonding support structure 110. In further embodiments, the annular bonding support structure 110 may have an annular bonding support structure annular thickness T R that is between about 0.1 percent of the diameter of the disk-shaped semiconductor wafer 102 and about 4 percent of the diameter of the disk-shaped semiconductor wafer 102. In further embodiments, the annular bond support structure annular thickness T may be R in particular about 3 percent of the diameter of the disk-shaped semiconductor wafer 102.FIGS. 9A-9K illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 3 and bonding the semiconductor wafer of FIG. 3 to another semiconductor wafer.As shown in FIG. 9A, a first etch stop layer 318 is formed on a plurality of stacked ILD layers 316 and on the conductive features 314 disposed in the plurality of stacked ILD layers 316. In some embodiments, the first etch stop layer 318 is formed over a central region 106 of a first semiconductor wafer 102 a. In further embodiments, the first etch stop layer 318 may be formed with sidewalls substantially aligned with sidewalls of the plurality of stacked ILD layers 316.In some embodiments, a process for forming the first etch stop layer 318 may include depositing the first etch stop layer 318 on the plurality of stacked ILD layers 316 and the conductive features 314. In further embodiments, the first etch stop layer 318 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or a combination of the foregoing. In further embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed on the first etch stop layer 318 to planarize a top surface of the first etch stop layer 318.As shown in FIG. 9B, a bond structure dielectric layer 320 is formed on the first etch stop layer 318. In some embodiments, the bond structure dielectric layer 320 is formed over the central region 106 of the first semiconductor wafer 102 a. In further embodiments, the bond structure dielectric layer 320 may be formed with sidewalls substantially aligned with sidewalls of the first etch stop layer 318.In some embodiments, a process for forming the bond structure dielectric layer 320 may include depositing or growing the bond structure dielectric layer 320 on the first etch stop layer 318. In further embodiments, the bond structure dielectric layer 320 may be deposited or grown by CVD, PVD, ALD, sputtering, thermal oxidation, another deposition or growth process, or a combination of the foregoing. In further embodiments, a planarization process (e.g., CMP) may be performed on the bond structure dielectric layer 320 to planarize a top surface of the bond structure dielectric layer 320.As shown in FIG. 9C, a second etch stop layer 322 is formed on the bond structure dielectric layer 320. In some embodiments, the second etch stop layer 322 is formed over the central region 106 of the first semiconductor wafer 102 a. In further embodiments, the second etch stop layer 322 may be formed with sidewalls substantially aligned with sidewalls of the bond structure dielectric layer 320.In some embodiments, a process for forming the second etch stop layer 322 may include depositing the second etch stop layer 322 on the bond structure dielectric layer 320. In further embodiments, the second etch stop layer 322 may be deposited by CVD, PVD, ALD, sputtering, another deposition process, or a combination of the foregoing. In further embodiments, a planarization process (e.g., CMP) may be performed on the second etch stop layer 322 to planarize a top surface of the second etch stop layer 322.As shown in FIG. 9D, a first dielectric layer 902 is formed on the second etch stop layer 322. In some embodiments, the first dielectric layer 902 is formed over the central region 106 of the first semiconductor wafer 102 a. In further embodiments, the first dielectric layer 902 may be formed with sidewalls substantially aligned with sidewalls of the second etch stop layer 322. In further embodiments, the first dielectric layer 902 is a different material than the second etch stop layer 322 and may include, for example, an oxide (e.g., SiO 2), a low-k dielectric, an ultra-low-k dielectric, or the like.In some embodiments, a process for forming the first dielectric layer 902 may include depositing or growing the first dielectric layer 902 on the second etch stop layer 322. In further embodiments, the first dielectric layer 902 may be deposited or grown by CVD, PVD, ALD, sputtering, thermal oxidation, another deposition or growth process, or a combination of the foregoing. In further embodiments, a masking layer (not shown) may be formed over the first dielectric layer 902 (e.g., via a photolithography process). In still further embodiments, with the masking layer in place, an etching process (e.g., wet etching, dry etching, etc.) may be performed on the first dielectric layer 902 to remove any un-masked portions of the first dielectric layer 902 (e.g., regions of the first masking layer 902 disposed over the perimeter regions 112). In such embodiments, the masking layer may be subsequently stripped. It is apparent that the masking / etching process above may be performed on the first etch stop layer 318, the bond structure dielectric layer 320, and / or the second etch stop layer 322 to remove any un-masked portions (e.g., portions disposed over the perimeter regions 112) of the first etch stop layer 318, the bond structure dielectric layer 320, and / or the second etch stop layer 322.As shown in FIG. 9E, a first planarization process 904 process is performed on the first dielectric layer 902 (see, e.g., FIG. 9D ) to form a redistribution dielectric layer 324 having a substantially planar top surface. Redistribution dielectric layer 324 includes the portion of first dielectric layer 902 remaining after first planarization process 904. In some embodiments, the first planarization process 904 may be a CMP process. It should be appreciated that a conductive layer (not shown) may be formed over the first dielectric layer 902 filling conductive redistribution line openings (not shown) disposed in the first dielectric layer 902. It is further apparent that the first planarization process 904 may be performed on the conductive layer and the first dielectric layer 902 to coplanarize the top surface of the redistribution dielectric layer 324 and the conductive layer such that conductive redistribution lines are formed in the redistribution dielectric layer 324 with top surfaces substantially planar with the top surface of the redistribution dielectric layer 324.As shown in FIG. 9F, a second dielectric layer 906 is formed on redistribution dielectric layer 324. In some embodiments, the second dielectric layer 906 is formed over the central region 106 of the first semiconductor wafer 102 a. In further embodiments, the second dielectric layer 906 may be formed with sidewalls substantially aligned with sidewalls of the redistribution dielectric layer 324. In further embodiments, the second dielectric layer 906 is a different material than the redistribution dielectric layer 324, and may include, for example, an oxynitride (e.g., silicon oxynitride (SiON)), an oxide (e.g., SiO 2), a nitride (e.g., SiN), or the like. In further embodiments, a process for forming the second dielectric layer 906 may include depositing or growing the second dielectric layer 906 on the redistribution dielectric layer 324. In still further embodiments, the second dielectric layer 906 may be deposited or grown by CVD, PVD, ALD, sputtering, thermal oxidation, another deposition or growth process, or a combination of the foregoing.As shown in FIG. 9G, an opening 908 extending from a top surface of the second dielectric layer 906 to an uppermost conductive feature 314 is formed over the first semiconductor wafer 102 a. In some embodiments, the opening 908 extends through the second dielectric layer 906, the redistribution dielectric layer 324, the second etch stop layer 322, the bond structure dielectric layer 320, and the first etch stop layer 318 to the uppermost conductive feature 314. In further embodiments, the opening 908 may include a top portion extending from the top surface of the second dielectric layer 906 to a top surface of the bond structure dielectric layer 320, and a bottom portion extending from the top surface of the bond structure dielectric layer 320 to the top conductive feature 314. In such embodiments, a width of the upper portion of the opening 908 may be greater than a width of the lower portion of the opening 908. It will be appreciated that the opening 908 may be one of a plurality of openings extending from the top surface of the second dielectric layer 906 to uppermost conductive features 314.In some embodiments, a process for forming the opening 908 includes performing a selective etch into the second dielectric layer 906, the redistribution dielectric layer 324, the second etch stop layer 322, the bond structure dielectric layer 320, and the first etch stop layer 318. In further embodiments, the selective etching includes forming a masking layer (not shown) on the second dielectric layer 906 (e.g., via a photolithography process). Subsequently, the second dielectric layer 906 is exposed to one or more etchants that remove portions of the second dielectric layer 906, the redistribution dielectric layer 324, the second etch stop layer 322, the bond structure dielectric layer 320, and the first etch stop layer 318 not covered by the masking layer to form the opening 908. The masking layer can then be removed. It should be appreciated that multiple selective etch operations may need to be performed to form the opening 908. For example, a first selective etch may be performed to form the upper portion of the opening 908 and a second selective etch may be performed to form the lower portion of the opening 908.As shown in FIG. 9H, a conductive bond via 330 and a conductive bond connector 328 are formed in the opening 908 (see, e.g., FIG. 9G ). Further, a second planarization process 910 is performed on the second dielectric layer 906 (see, e.g., FIG. 9G ) to form a bond interface dielectric layer 326. The bonding interface dielectric layer 326 includes the portion of the second dielectric layer 906 remaining after the second planarization process 910. In some embodiments, conductive bond via 330 may be formed in the lower portion of opening 908 and conductive bond connector 328 may be formed in the upper portion of opening 908. In further embodiments, the formation of the conductive bond connector 328, the conductive bond via 330, and the bond interface dielectric layer 326 completes the formation of a bond structure 108 and / or a 2D IC 104.In some embodiments, a process for forming the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326 includes depositing a conductive layer (not shown) filling the opening 908 at the second dielectric layer 906. In some embodiments, the conductive layer may include, for example, copper, aluminum, tungsten, another conductive material, or a combination of the foregoing. In further embodiments, the conductive layer may be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, another deposition process, or a combination of the foregoing.Next, the second planarization process 910 is performed on the conductive layer and into the second dielectric layer 906 to form the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326. In some embodiments, the second planarization process 910 coplanarizes a top surface of the conductive bond connector 328 and a top surface of the bond interface dielectric layer 326. In further embodiments, the second planarization process 910 may be a CMP process.As shown in FIG. 9I, bonding support structures 110 are respectively formed over circumferential regions 112 of the first semiconductor wafer 102 a. In some embodiments, the bond support structures 110 include a dielectric material layer formed on the first semiconductor wafer 102 aand extending along sidewalls of the plurality of stacked ILD layers 316, the first etch stop layer 318, the bond structure dielectric layer 320, the second etch stop layer 322, the redistribution dielectric layer 324, and the bond interface dielectric layer 326. In further embodiments, each of the bonding support structures 110 is formed extending over an inner circumferential region 334 and a sloped region 332 of the first semiconductor wafer 102 a. In further embodiments, the bonding support structures 110 are formed with top surfaces that are substantially planar with the top surface of the bonding interface dielectric layer 326. In further embodiments, the bonding support structures 110 may be formed with outer sidewalls substantially aligned with opposing outer edges of the first semiconductor wafer 102 a. In still further embodiments, the outer sidewalls of the bond support structures 110 may be formed extending in a substantially vertical line.In some embodiments, a process for forming the bond support structures 110 may include selectively depositing or growing the bond support structures 110 on the first semiconductor wafer 102 aand over the perimeter regions 112 of the first semiconductor wafer 102 a. In further embodiments, the bond support structures 110 may be selectively deposited or grown by CVD, PVD, ALD, sputtering, thermal oxidation, another deposition or growth process, or a combination of the foregoing. In further embodiments, the bond support structures 110 are selectively deposited by plasma enhanced CVD (PECVD).In some embodiments, the PECVD process includes loading the first semiconductor wafer 102 ainto a processing chamber. Subsequently, one or more processing gases are flown into the processing chamber such that the bond support structures 110 may be selectively deposited over the perimeter regions 112 of the first semiconductor wafer 102 a. In further embodiments, an upper plasma exclusion (PEZ) ring is aligned covering over a front side (see, e.g., FIG. 2 ) of the first semiconductor wafer 102 aand the central region 106 of the first semiconductor wafer 102 a. The upper PEZ ring is configured to prevent the PECVD process from depositing the bond support structures 110 over the central region 106 of the first semiconductor wafer 102 a. In still further embodiments, the upper PEZ ring may be spaced apart from the first semiconductor wafer 102 aby about 0.3 mm to about 0.85 mm during the PECVD process.In some embodiments, during the PECVD process, a lower PEZ ring extending between opposing edges of the first semiconductor wafer 102 ais disposed below a back side (see, e.g., FIG. 2 ) of the first semiconductor wafer 102 a. The lower PEZ ring is configured to prevent the PECVD process from depositing the bond support structures 110 on the backside of the first semiconductor wafer 102 a. In further embodiments, the lower PEZ ring may be spaced apart from the first semiconductor wafer 102 aby about 0.3 mm to about 0.85 mm during the PECVD process.In some embodiments, the one or more processing gases may include, for example, silanes (e.g., silane (SiH 4)), an oxide of nitrogen (e.g., dinitrogen monoxide (N 2 O)), nitrogen gas (N 2) or the like. In further embodiments, the one or more processing gases may be flowed into the processing chamber at a flow rate between about 10 standard cubic centimeters per minute (sccm) and about 3000 sccm. In further embodiments, one of the processing gases is SiH 4 and is flowed into the processing chamber at a flow rate between about 10 sccm and about 500 sccm. In further embodiments, in particular SiH 4 can be flowed into the processing chamber at a volume flow of between about 20 sccm and about 72 sccm. By changing the flow rate of SiH 4 the refractive index (RI) of the bonding support structures 110 can be adjusted. For example, increasing the flow rate (e.g., from about 20 sccm to about 72 sccm) of SiH 4 may increase the RI (e.g., from about 1.475 to about 1.65, respectively) of the bond support structures 110.In some embodiments, one of the processing gases N is 2 and is flowed into the processing chamber at a flow rate between about 100 sccm and about 3000 sccm. In further embodiments, in particular N 2 can be flowed into the processing chamber at a volume flow of between approximately 1092 sccm and approximately 2000 sccm. By changing the flow rate of N 2 the thickness of the heights of the bonding support structures 110 can be adjusted. For example, decreasing the volume flow of N 2( e.g., from about 2000 sccm to about 1092 sccm), may increase the height (e.g., from about 20,000 Å to about 15,000 Å) of the bond support structures 110. In some embodiments, one of the processing gases is N 2 O and is flowed into the processing chamber at a flow rate between about 50 sccm and about 2500 sccm.In some embodiments, the PECVD process may include heating the first semiconductor wafer 102 ato a temperature between about 80° C. and about 410° C. In further embodiments, in particular, the first semiconductor wafer 102 acan be heated to approximately 350° C. In further embodiments, a pressure of the processing chamber may be between about 0.5 Torr and about 6 Torr. In further embodiments, the pressure of the processing chamber may be, in particular, between about 0.9 Torr and about 2 Torr. In further embodiments, the PECVD process may include providing between about 150 watts (W) to about 800 W to a radio frequency (RF) generator to generate a plasma within the processing chamber. In further embodiments, the PECVD process may be performed on the first semiconductor wafer 102 afor about 10 seconds up to about 300 seconds. After the bond support structures 110 are formed, in further embodiments, a planarization process (e.g., CMP) may be performed on the bond support structures 110 such that the top surfaces of the bond support structures 110 are substantially planar with a top surface of the bond structure 108. In still further embodiments, a wafer cleaning process may be performed on the first semiconductor wafer 102 aafter the bond support structures 110 are formed.As shown in FIG. 9J, the first semiconductor wafer 102 ais bonded to a second semiconductor wafer 102 bto form a 3D IC 101. In some embodiments, the first semiconductor wafer 102 ais bonded to the second semiconductor wafer 102 bby bonding the bonding interface dielectric layer 326, the conductive bond connector 328, and the bond support structures 110 of the first semiconductor wafer 102 ato a bonding interface dielectric layer 326, a conductive bond connector 328, and bond support structures 110 of the second semiconductor wafer 102 b, respectively. In further embodiments, bonding the first semiconductor wafer 102 ato the second semiconductor wafer 102 bconstitutes a bonding interface 912 along the bonding interface dielectric layers 326, the conductive bond connectors 328, and the bond support structures 110 of the first and second semiconductor wafers 102 a, 102 b. It is understood that bonding the first semiconductor wafer 102 ato the second semiconductor wafer 102 bmay form multiple 3D ICs.In some embodiments, the bonding interface 912 includes dielectric-to-dielectric bonds between the bonding interface dielectric layers 326 of the first and second semiconductor wafers 102 a, 102 b. In further embodiments, the bonding interface 912 includes conductor-to-conductor bonds between the conductive bond connectors 328 of the first and second semiconductor wafers 102 a, 102 b. In still further embodiments, the bonding interface 912 includes dielectric-to-dielectric bonds between the bonding support structures 110 of the first and second semiconductor wafers 102 a, 102 b.In some embodiments, a process for bonding the first semiconductor wafer 102 ato the second semiconductor wafer 102 bincludes inverting (e.g., turning 180 degrees) the second semiconductor wafer 102 bsuch that the bonding interface dielectric layer 326 of the second semiconductor wafer 102 bfaces the bonding interface dielectric layer 326 of the first semiconductor wafer 102 a. Thereafter, the first semiconductor wafer 102 ais bonded to the second semiconductor wafer 102 bby, for example, hybrid bonding, eutectic bonding, or the like. It is understood that additional semiconductor wafers may be bonded to the first semiconductor wafer 102 aand / or the second semiconductor wafer 102 bby a substantially similar bonding process.Since the bonding support structures 110 are formed over the circumferential regions 112 of the first semiconductor wafer 102 a, NB areas over the circumferential regions 112 of the first semiconductor wafer 102 acan be reduced. By reducing the NB areas over the perimeter regions 112 of the first semiconductor wafer 102 aduring bonding, structural support between the first semiconductor wafer 102 aand the second semiconductor wafer 102 bmay be improved. The improved structural support may reduce unwanted mechanical stresses during bonding and / or during subsequent processing steps of the bonded semiconductor wafers. Accordingly, the bonding support structures 110 may improve the yield of 3D ICs.As also shown in FIG. 9J, an input / output (I / O) structure 114 may be formed on a side of the second semiconductor wafer 102 btoward a side of the second semiconductor wafer 102 bfacing the first semiconductor wafer 102 a. In some embodiments, the I / O structure 114 includes an I / O conductive contact 116 disposed in / over an I / O dielectric layer 118. It should be appreciated that the conductive I / O contact 116 may be one of a plurality of conductive I / O contacts disposed in / over the I / O dielectric layer 118. It is further understood that the I / O structure 114 may be formed on a side of the first semiconductor wafer 102 atoward a side of the first semiconductor wafer 102 afacing the second semiconductor wafer 102 b.In some embodiments, a process for forming the I / O structure 114 includes depositing or growing a dielectric layer (not shown) on the side of the second semiconductor wafer 102 btoward the side of the second semiconductor wafer 102 bfacing the first semiconductor wafer 102 a. In some embodiments, the dielectric layer may include, for example, an oxide (e.g., SiO 2), a nitride (e.g., SiN), an oxynitride (e.g., SiON), or the like. In some embodiments, the dielectric layer may be deposited or grown by CVD, PVD, ALD, sputtering, thermal oxidation, another deposition or growth process, or a combination of the foregoing.Thereafter, an opening (not shown) is formed in the dielectric layer (e.g., via a photolithography process) that extends through the dielectric layer to a substrate via (TSV) (not shown). A conductive layer (not shown) is then deposited over the dielectric layer and filling the opening. In some embodiments, the conductive layer may include, for example, copper, aluminum, tungsten, another conductive material, or a combination of the foregoing. In some embodiments, the conductive layer may be deposited by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, another deposition process, or a combination of the foregoing. A planarization process (e.g., CMP) is then performed on the conductive layer and into the dielectric layer to form the I / O conductive contact 116 and the I / O dielectric layer 118. It should be appreciated that multiple openings may be formed in the dielectric layer and then filled with the conductive layer such that the planarization process forms multiple conductive I / O contacts 116 in the I / O dielectric layer 118.As shown in FIG. 9K, a wafer dicing process 914 is performed on the first and second semiconductor wafers 102 a, 102 bbonded to each other to dicing the 3D IC 101 and thereby form a die including the 3D IC 101. In some embodiments, the wafer dicing process 914 includes performing a series of cuts in the bonded semiconductor wafers to form a plurality of scribe lines 916, each of which is disposed on a side of the 3D IC 101. Subsequently, a mechanical force is applied to the bonded first and second semiconductor wafers 102 a, 102 bto single the die. In further embodiments, the cut may be performed, for example, by mechanical sawing, laser cutting, or the like. It is apparent that the 3D IC 101 may be one of a plurality of 3D ICs, each of which is singulated from the first and second semiconductor wafers 102 a, 102 bconnected to each other by the wafer dicing process 914.FIG. 10 illustrates a top view of some embodiments of the wafer dicing process of FIG. 9K performed on some embodiments of the bonded-together first and second semiconductor wafers of FIGS. 9J to 9K.As shown in FIG. 10, the bonded first and second semiconductor wafers 102 a, 102 b(see, e.g., FIGS. 9J-9K ) include a plurality of 3D ICs 101 arranged in an array. In some embodiments, the array includes multiple rows and columns. The scribe lines 916 are cut into the bonded first and second semiconductor wafers 102 a, 102 bbetween each of the rows and columns to single the bonded first and second semiconductor wafers 102 a, 102 binto a plurality of separate 3D ICs 101. In some embodiments, the scribe lines 916 extend entirely across the bonded-together first and second semiconductor wafers 102 a, 102 bsuch that the scribe lines extend into the bond support structures 110 of the first semiconductor wafer 102 aand / or the bond support structures of the second semiconductor wafer 102 b.In some embodiments (not shown), scribe lines 916 defining a first of the plurality of separate 3D ICs 101 may extend into the bond support structure 110. In such embodiments, the first of the plurality of separate 3D ICs 101 may include a portion of the bond support structure 110 disposed along a side of the singulated IC. For example, the first of the plurality of separate 3D ICs 101 may include a portion of the bond support structure 110 that is vertically disposed between the first and second semiconductor wafers 102 a, 102 b.FIGS. 11A-11I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 4.As shown in FIG. 11A, a first etch stop layer 318 is formed on a plurality of stacked ILD layers 316 and on top conductive features 314. In some embodiments, a process for forming the first etch stop layer 318 may be a substantially similar process as described above (see, e.g., paragraphs

[0078] -

[0079] ) with reference to FIG. 9A.As shown in FIG. 11B, a bond structure dielectric layer 320 is formed on the first etch stop layer 318. In some embodiments, a process for forming the bond structure dielectric layer 320 may be a substantially similar process as described above (see, e.g., paragraphs

[0080] -

[0081] ) with reference to FIG. 9B.As shown in FIG. 11C, a second etch stop layer 322 is formed on the bond structure dielectric layer 320. In some embodiments, a process for forming the second etch stop layer 322 may be a substantially similar process as described above (see, e.g., paragraphs

[0082] -

[0083] ) with reference to FIG. 9C.As shown in FIG. 11D, bonding support structures 110 are formed over perimeter regions 112 of a semiconductor wafer 102. In some embodiments, the bond support structures 110 are formed with top surfaces disposed over a top surface of the second etch stop layer 322. In still further embodiments, the bond support structures 110 may be formed with outer sidewalls spaced a greater distance from the central region 106 of the semiconductor wafer 102 than edges of the semiconductor wafer 102 are spaced from the central region 106 of the semiconductor wafer 102.In some embodiments, the bonding support structures 110 may be formed with rounded outer sidewalls. In further embodiments, the bond support structures 110 may be formed with rounded outer sidewalls extending from above a top surface of the second etch stop layer 322 along a radius of curvature to below a centerline axis (see, e.g., FIG. 4 ) of the semiconductor wafer 102, the centerline axis extending laterally through the semiconductor wafer 102 and being equally spaced from the front side (see, e.g., FIG. 2 ) of the semiconductor wafer 102 and the back side (see, e.g., FIG. 2 ) of the semiconductor wafer 102. In still further embodiments, a process for forming the bond support structures 110 may be a substantially similar process as described above (see, e.g., paragraphs

[0093] -

[0099] ) with reference to FIG. 9I.As shown in FIG. 11E, a first dielectric layer 902 is formed on the second etch stop layer 322 and on the bond support structures 110 such that the first dielectric layer 902 is formed over both the perimeter regions 112 and the central region 106 of the semiconductor wafer 102. In some embodiments, the first dielectric layer 902 may be formed by conformally lining the second etch stop layer 322 and the bond support structures 110. In further embodiments, a process for forming the first dielectric layer 902 may be a substantially similar process as described above (see, e.g., paragraphs

[0084] -

[0085] ) with reference to FIG. 9D.As shown in FIG. 11F, a first planarization process 904 is performed on the first dielectric layer 902 (see, e.g., FIG. 11E ) to form a redistribution dielectric layer 324 having a substantially planar top surface. In some embodiments, the first planarization process 904 may be a substantially similar process as described above with reference to FIG. 9E (see, e.g., paragraph

[0086] ).As shown in FIG. 11G, a second dielectric layer 906 is formed on redistribution dielectric layer 324. In some embodiments, the second dielectric layer 906 is formed over both the perimeter regions 112 and the central region 106 of the semiconductor wafer 102. In further embodiments, the second dielectric layer 906 may be formed by conformally lining the redistribution dielectric layer 324. In still further embodiments, a process for forming the second dielectric layer 906 may be a substantially similar process as described above with reference to FIG. 9F (see, e.g., paragraph

[0087] ).As shown in FIG. 11H, an opening 908 extending from a top surface of the second dielectric layer 906 to an uppermost conductive feature 314 is formed over the first semiconductor wafer 102. In some embodiments, a process for forming the opening 908 may be a substantially similar process as described above with reference to FIG. 9G (see, e.g., paragraphs [0088-0089]).As shown in FIG. 11I, a conductive bond via 330 and a conductive bond connector 328 are formed in the opening 908 (see, e.g., FIG. 11H ). Further, a second planarization process 910 is performed on the second dielectric layer 906 (see, e.g., FIG. 11H ) to form a bond interface dielectric layer 326. In some embodiments, a process for forming the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326 may be a substantially similar process as described above with reference to FIG. 9 (see, e.g., paragraphs [0090-0092]).FIGS. 12A-12I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 5.As shown in FIG. 12A, a first etch stop layer 318 is formed on a plurality of stacked ILD layers 316 and on top conductive features 314. In some embodiments, a process for forming the first etch stop layer 318 may be a substantially similar process as described above with reference to FIG. 9A (see, e.g., paragraph

[0078] -

[0079] ).As shown in FIG. 12B, a bond structure dielectric layer 320 is formed on the first etch stop layer 318. In some embodiments, a process for forming the bond structure dielectric layer 320 may be a substantially similar process as described above with reference to FIG. 9B (see, e.g., paragraph

[0080] -

[0081] ).As shown in FIG. 12C, a second etch stop layer 322 is formed on the bond structure dielectric layer 320. In some embodiments, a process for forming the second etch stop layer 322 may be a substantially similar process as described above with reference to FIG. 9C (see, e.g., paragraph

[0082] -

[0083] ).As also shown in FIG. 12C, the bonding support structures 110 are respectively formed over circumferential regions 112 of a semiconductor wafer 102. In some embodiments, a process for forming the bond support structures 110 may be a substantially similar process as described above with reference to FIG. 11D (see, e.g., paragraphs

[00115] -

[00116] ).As shown in FIG. 12D, a third planarization process 1202 is performed on the bond support structures 110 to collimate top surfaces of the bond support structures 110. In some embodiments, the third planarization process 1202 coplanarizes the top surfaces of the bond support structures 110 with a top surface of the second etch stop layer 322. In further embodiments, the third planarization process 1202 may be a CMP process.As shown in FIG. 12E, a first dielectric layer 902 is formed on the second etch stop layer 322 and on the bond support structures 110. In some embodiments, a process for forming the first dielectric layer 902 may be a substantially similar process as described above with reference to FIG. 11E (see, e.g., paragraph

[00117] ).As shown in FIG. 12F, a first planarization process 904 process is performed on the first dielectric layer 902 (see, e.g., FIG. 12E ) to form a redistribution dielectric layer 324 having a substantially planar top surface. In some embodiments, the first planarization process 904 may be a substantially similar process as described above with reference to FIG. 9E (see, e.g., paragraph

[0086] ).As shown in FIG. 12G, a second dielectric layer 906 is formed on redistribution dielectric layer 324. In some embodiments, a process for forming the second dielectric layer 906 may be a substantially similar process as described above with reference to FIG. 11G (see, e.g., paragraph

[00119] ).As shown in FIG. 12H, an opening 908 extending from a top surface of the second dielectric layer 906 to an uppermost conductive feature 314 is formed over the first semiconductor wafer 102. In some embodiments, a process for forming the opening 908 may be a substantially similar process as described above with reference to FIG. 9G (see, e.g., paragraphs [0088-0089]).As shown in FIG. 12I, a conductive bond via 330 and a conductive bond connector 328 are formed in the opening 908 (see, e.g., FIG. 12H ). Further, a second planarization process 910 is performed on the second dielectric layer 906 (see, e.g., FIG. 12H ) to form a bond interface dielectric layer 326. In some embodiments, a process for forming the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326 may be a substantially similar process as described above with reference to FIG. 9 (see, e.g., paragraphs [0090-0092]).FIGS. 13A-13I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 6.As shown in FIG. 13A, a first etch stop layer 318 is formed on a plurality of stacked ILD layers 316 and on top conductive features 314. In some embodiments, a process for forming the first etch stop layer 318 may be a substantially similar process as described above (see, e.g., paragraphs

[0078] -

[0079] ) with reference to FIG. 9A.As shown in FIG. 13B, a bond structure dielectric layer 320 is formed on the first etch stop layer 318. In some embodiments, a process for forming the bond structure dielectric layer 320 may be a substantially similar process as described above (see, e.g., paragraphs

[0080] -

[0081] ) with reference to FIG. 9B.As shown in FIG. 13C, a second etch stop layer 322 is formed on the bond structure dielectric layer 320. In some embodiments, a process for forming the second etch stop layer 322 may be a substantially similar process as described above (see, e.g., paragraphs

[0082] -

[0083] ) with reference to FIG. 9C.As shown in FIG. 13D, a first dielectric layer 902 is formed on the second etch stop layer 322. In some embodiments, a process for forming the first dielectric layer 902 may be a substantially similar process as described above with reference to FIG. 9D (see, e.g., paragraphs

[0084] -

[0085] ).As shown in FIG. 13E, a first planarization process 904 process is performed on the first dielectric layer 902 (see, e.g., FIG. 13D ) to form a redistribution dielectric layer 324 having a substantially planar top surface. In some embodiments, the first planarization process 904 may be a substantially similar process as described above with reference to FIG. 9E (see, e.g., paragraph

[0086] ).As shown in FIG. 13F, bonding support structures 110 are respectively formed over peripheral regions 112 of a semiconductor wafer 102. In some embodiments, the bond support structures 110 may be formed with outer sidewalls that respectively extend from the top surface of the redistribution dielectric layer 324 along a radius of curvature to below the centerline axis (see, e.g., FIG. 4 ) of the semiconductor wafer 102. In further embodiments, a process for forming the bond support structures 110 may be a substantially similar process as described above with reference to FIG. 11D (see, e.g., paragraphs

[00115] -

[00116] ).As shown in FIG. 13G, a second dielectric layer 906 is formed on redistribution dielectric layer 324 and on bond support structures 110. In some embodiments, the second dielectric layer 906 may be formed by conformally lining the redistribution dielectric layer 324 and the bond support structures 110. In further embodiments, a process for forming the second dielectric layer 906 may be a substantially similar process as described above with reference to FIG. 11G (see, e.g., paragraph

[00119] ).As shown in FIG. 13H, an opening 908 extending from a top surface of the second dielectric layer 906 to an uppermost conductive feature 314 is formed over the first semiconductor wafer 102. In some embodiments, a process for forming the opening 908 may be a substantially similar process as described above with reference to FIG. 9G (see, e.g., paragraphs [0088-0089]).As shown in FIG. 13I, a conductive bond via 330 and a conductive bond connector 328 are formed in the opening 908 (see, e.g., FIG. 13H ). Further, a second planarization process 910 is performed on the second dielectric layer 906 (see, e.g., FIG. 13H ) to form a bond interface dielectric layer 326. In some embodiments, a process for forming the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326 may be a substantially similar process as described above with reference to FIG. 9 (see, e.g., paragraphs [0090-0092]).FIGS. 14A-14I illustrate a series of cross-sectional views of some embodiments of a method of forming the semiconductor wafer of FIG. 7.As shown in FIG. 14A, a first etch stop layer 318 is formed on a third ILD layer 316 cand on top conductive features 314. In some embodiments, the first etch stop layer 318 is formed by conformally lining the third ILD layer 316 csuch that the first etch stop layer 318 is formed over both a central region 106 and peripheral regions 112 of the semiconductor wafer 102. In further embodiments, a process for forming the first etch stop layer 318 may be a substantially similar process as described above with reference to FIG. 9A (see, e.g., paragraphs

[0078] -

[0079] ).As shown in FIG. 14B, a bond structure dielectric layer 320 is formed on the first etch stop layer 318. In some embodiments, the bond structure dielectric layer 320 is formed by conformally lining the first etch stop layer 318, such that the bond structure dielectric layer 320 is formed over both the central region 106 and the perimeter regions 112 of the semiconductor wafer 102. In further embodiments, a process for forming the bond structure dielectric layer 320 may be a substantially similar process as described above with reference to FIG. 9B (see, e.g., paragraphs

[0080] -

[0081] ).As shown in FIG. 14C, a second etch stop layer 322 is formed on the bond structure dielectric layer 320. In some embodiments, the second etch stop layer 322 may be conformally lining the bond structure dielectric layer 320 such that the second etch stop layer 322 is formed over both the central region 106 and between the perimeter regions 112 of the semiconductor wafer 102. In further embodiments, a process for forming the first etch stop layer 322 may be a substantially similar process as described above with reference to FIG. 9C (see, e.g., paragraphs

[0082] -

[0083] ).As shown in FIG. 14D, bonding support structures 110 are formed over the perimeter regions 112 of the semiconductor wafer 102. In some embodiments, the bond support structures 110 are formed on the second etch stop layer 322. In further embodiments, the bond support structures 110 are formed partially on opposing outer sidewalls of the second etch stop layer 322 and partially on a top surface of the second etch stop layer 322. In such embodiments, the bond support structures 110 may be formed with top surfaces disposed over the top surface of the second etch stop layer 322.In some embodiments, the bond support structures 110 may extend along the outer sidewalls of the second etch stop layer 322 such that the bond support structures 110 are also partially disposed on the bond structure dielectric layer 320, the first etch stop layer 318, the third ILD layer 316 c, a second ILD layer 316 b, a first ILD layer 316 a, and / or the semiconductor wafer 102. In further embodiments, a process for forming the bond support structures 110 may be a substantially similar process as described above with reference to FIG. 11D (see, e.g., paragraphs

[00115] -

[00116] ). While FIG. 14D illustrates the bond support structures 110 formed partially on opposing sidewalls and partially on the top surface of the second etch stop layer 322, it is apparent that the bond support structures 110 may be formed partially on opposing sidewalls and partially on a top surface of the third ILD layer 316 c, the first etch stop layer 318, the bond structure dielectric layer 320, a first dielectric layer 902 (see, e.g., FIG. 13D ), a redistribution dielectric layer 324 (see, e.g., FIG. 13E ), a second dielectric layer 906 (see, e.g., FIG. 13G ), a bond interface dielectric layer 326 (see, e.g., FIG. 13I ), or a combination of the foregoing.As shown in FIG. 14E, a third planarization process 1202 is performed on the bond support structures 110 to collimate top surfaces of the bond support structures 110. In some embodiments, the third planarization process 1202 may be a substantially similar process as described above with reference to FIG. 12D (see, e.g., paragraph

[00127] ).As shown in FIG. 14F, a first dielectric layer 902 is formed on the second etch stop layer 322 and on the bond support structures 110. In some embodiments, the first dielectric layer 902 may be formed by conformally lining the second etch stop layer 322 and the bond support structures 110. In further embodiments, a process for forming the first dielectric layer 902 may be a substantially similar process as described above with reference to FIG. 11E (see, e.g., paragraph

[00117] ).As shown in FIG. 14G, a first planarization process 904 process is performed on the first dielectric layer 902 (see, e.g., FIG. 14F ) to form a redistribution dielectric layer 324 having a substantially planar top surface. In some embodiments, the first planarization process 904 may be a substantially similar process as described above with reference to FIG. 9E (see, e.g., paragraph

[0086] ).As shown in FIG. 14H, a second dielectric layer 906 is formed on redistribution dielectric layer 324. In some embodiments, a process for forming the second dielectric layer 906 may be a substantially similar process as described above with reference to FIG. 11G (see, e.g., paragraph

[00119] ).As shown in FIG. 14I, an opening 908 extending from a top surface of the second dielectric layer 906 to an uppermost conductive feature 314 is formed over the first semiconductor wafer 102. In some embodiments, a process for forming the opening 908 may be a substantially similar process as described above with reference to FIG. 9G (see, e.g., paragraphs [0088-0089]).As shown in FIG. 14J, a conductive bond via 330 and a conductive bond connector 328 are formed in the opening 908 (see, e.g., FIG. 13H ). Further, a second planarization process 910 is performed on the second dielectric layer 906 (see, e.g., FIG. 13H ) to form a bond interface dielectric layer 326. In some embodiments, a process for forming the conductive bond via 330, the conductive bond connector 328, and the bond interface dielectric layer 326 may be a substantially similar process as described above with reference to FIG. 9 (see, e.g., paragraphs [0090-0092]).As illustrated in FIG. 15, a flow diagram 1500 of some embodiments of a method for forming the semiconductor wafer of FIG. 3 and bonding the semiconductor wafer of FIG. 3 to another semiconductor wafer is provided. While the flowchart 1500 of FIG. 15 is illustrated and described herein as a series of acts or events, it is understood that the illustrated order of such acts or events is not to be construed as limiting. For example, some acts other than those illustrated and / or described herein may occur in different orders and / or concurrently with other acts or events. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts illustrated herein may be performed in one or more separate acts and / or phases.At 1502, a bond structure is formed over a central region of a first semiconductor wafer, wherein perimeter regions of the first semiconductor wafer are disposed on opposite sides of the central region and extend from the opposite sides of the central region to edges of the first semiconductor wafer. FIGS. 9A-9H illustrate a series of cross-sectional views of some embodiments corresponding to act 1502.At 1504, bonding support structures are formed over the perimeter regions of the first semiconductor wafer, respectively, the bonding support structures having top surfaces substantially planar with a top surface of the bonding support structure. FIG. 9I illustrates a cross-sectional view of some embodiments corresponding to act 1504.At 1506, the first semiconductor wafer is bonded to a second semiconductor wafer. FIG. 9J illustrates a cross-sectional view of some embodiments corresponding to act 1506.By forming bond support structures over the perimeter regions of the first semiconductor wafer, NB areas over the perimeter regions of the first semiconductor wafer may be reduced. In some embodiments, due to the upper surfaces of the bonding support structures being substantially planar with the upper surface of the bonding structure, the bonding support structures may reduce NB areas over the perimeter regions of the first semiconductor wafer. In other embodiments, the bond support structures may reduce NB areas over the perimeter region of the first semiconductor wafer by being a sub-structure over which the bond structure (or portions of the bond structure) may be formed, such that the bond structure may be formed with a substantially planar top surface extending between opposing edges of the first semiconductor wafer.By reducing the NB regions over perimeter regions of the first semiconductor wafer during bonding, structural support between the first semiconductor wafer and the second semiconductor wafer may be improved. The improved structural support may reduce unwanted mechanical stresses during bonding and / or during subsequent processing steps of the bonded first and second semiconductor wafers.At 1508, a wafer dicing process is performed on the bonded-together first and second semiconductor wafers to dicing a die comprising a three-dimensional (3D) integrated circuit (IC) from the bonded-together first and second semiconductor wafers. FIG. 9K illustrates a cross-sectional view of some embodiments corresponding to act 1508.According to the present invention, the present application provides a method for bonding semiconductor wafers. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first annular bonding support structure is formed over an annular peripheral region of the first semiconductor wafer, the annular peripheral region of the first semiconductor wafer enclosing the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer such that a second IC disposed on the second semiconductor wafer is electrically coupled to the first IC. In some embodiments, forming the first IC includes forming an etch stop layer over a coupling structure, the coupling structure being disposed over the first semiconductor wafer, and forming a dielectric layer over the coupling structure and over the first annular bond support structure, the first annular bond support structure being formed after the etch stop layer. In some embodiments, forming the first IC further includes performing a first planarization process on the dielectric layer to form a redistribution dielectric layer. In some embodiments, the redistribution dielectric layer contacts both the etch stop layer and the first ring-shaped bond support structure. In some embodiments, forming the first IC includes forming a bond interface dielectric layer over the redistribution dielectric layer, the bond interface dielectric layer having a substantially planar top surface extending between opposing edges of the first semiconductor wafer. In some embodiments, forming the first IC further includes, before forming the dielectric layer, performing a second planarization process on the first annular bond support structure such that a top surface of the first annular bond support structure is substantially planar with a top surface of the etch stop layer. According to the invention, forming the first IC comprises forming a redistribution dielectric layer over a coupling structure, the coupling structure being disposed over the first semiconductor wafer, and forming a bonding interface dielectric layer on both the redistribution dielectric layer and the first ring-shaped bonding support structure, the first ring-shaped bonding support structure being formed after the redistribution dielectric layer. In some embodiments, the annular bond support structure includes a rounded outer sidewall extending from over a top surface of the redistribution dielectric layer to the first semiconductor wafer. In some embodiments, forming the first IC includes forming a bond structure over a coupling structure, the coupling structure disposed over the first semiconductor wafer, the bond structure including a conductive bond connector disposed in a bond interface dielectric layer, and the first ring-shaped bond support structure formed after the bond structure. In some embodiments, a top surface of the annular bonding support structure is substantially planar with both a top surface of the conductive bond connector and a top surface of the bonding interface dielectric layer. In some embodiments, a diameter of the central region of the first semiconductor wafer is between about 92 percent of a diameter of the first semiconductor wafer and about 99.8 percent of the diameter of the first semiconductor wafer. In some embodiments, the annular bonding support structure has an annular thickness that is between about 0.1 percent of the diameter of the first semiconductor wafer and about 4 percent of the diameter of the first semiconductor wafer. In some embodiments, the method further comprises forming a second annular bonding support structure over an annular perimeter region of the second semiconductor wafer, wherein the annular perimeter region of the second semiconductor wafer encloses a central region of the second semiconductor wafer, wherein the second IC is disposed over the central region of the second semiconductor wafer, and wherein bonding the first semiconductor wafer to the second semiconductor wafer forms a dielectric-to-dielectric bond between the first annular bonding support structure and the second annular bonding support structure.According to the present invention, the present application provides a method for bonding semiconductor wafers. The method includes forming a plurality of stacked interlayer dielectric (ILD) layers on a first side of a first semiconductor wafer. The plurality of stacked ILD layers have a first thickness over a central region of the first semiconductor wafer and a second thickness over peripheral regions of the first semiconductor wafer, the second thickness being less than the first thickness. An annular bond support structure is formed with a dielectric material layer over the perimeter regions after the formation of one or more of the plurality of stacked ILD layers, the dielectric material layer having a sidewall facing a side of one or more of the plurality of stacked ILD layers. A second semiconductor wafer is bonded to the first side of the first semiconductor wafer. In some embodiments, an outermost surface of the annular bond support structure is spaced apart from the central region of the first semiconductor wafer by a greater distance than an edge of the first semiconductor wafer is spaced apart from the central region. In some embodiments, the annular bonding support structure extends from the first side of the first semiconductor wafer beyond a centerline axis of the first semiconductor wafer, the centerline axis extending laterally through the first semiconductor wafer and being equally spaced from the first side of the first semiconductor wafer and a second side of the first semiconductor wafer opposite the first side. In some embodiments, the bonding support structure is free of metal coupling structure layers. In some embodiments of the invention, forming the annular bond support structure includes performing a chemical vapor deposition (CVD) process to selectively form the annular bond support structure over the perimeter regions of the first semiconductor wafer, wherein the annular bond support structure includes an oxide, a nitride, or an oxynitride.

Claims

A method of bonding semiconductor wafers (102a, 102b), the method comprising: forming a first integrated circuit, IC, (104a-c) over a central region (106) of a first semiconductor wafer (102a); forming a first annular bonding support structure (110) over an annular perimeter region (112) of the first semiconductor wafer (102a), wherein the annular perimeter region (112) of the first semiconductor wafer (102a) encloses the central region (106) of the first semiconductor wafer (102a); Bonding a second semiconductor wafer (102b) to the first semiconductor wafer (102a) such that a second IC disposed on the second semiconductor wafer (102b) is electrically coupled to the first IC, wherein forming the first IC comprises: forming a redistribution dielectric layer (324) over a coupling structure (310), wherein the coupling structure (310) is disposed over the first semiconductor wafer (102a); and forming a bonding interface dielectric layer (326) on both the redistribution dielectric layer (324) and the first annular bonding support structure (110), wherein the first annular bonding support structure (110) is formed after the redistribution dielectric layer (324).The method of claim 1, wherein a diameter of the central region (106) of the first semiconductor wafer (102a) is between about 92 percent of a diameter of the first semiconductor wafer (102a) and about 99.8 percent of the diameter of the first semiconductor wafer (102a).The method of claim 2, wherein the annular bonding support structure (110) has an annular thickness that is between about 0.1 percent of the diameter of the first semiconductor wafer (102a) and about 4 percent of the diameter of the first semiconductor wafer (102a).A method of bonding semiconductor wafers (102a, 102b), the method comprising: forming a plurality of stacked interlayer dielectric (ILD) layers (316) on a first side of a first semiconductor wafer (102a), wherein the plurality of stacked ILD layers (316) have a first thickness over a central region (106) of the first semiconductor wafer (102a) and a second thickness over peripheral regions (112) of the first semiconductor wafer (102a), and the second thickness is less than the first thickness; forming an annular bonding support structure (110) comprising a dielectric material layer over the circumferential regions (112) after forming one or more of the plurality of stacked ILD layers (316), the dielectric material layer having a sidewall facing a side of one or more of the plurality of stacked ILD layers (316); and bonding a second semiconductor wafer (102b) to the first side of the first semiconductor wafer (102a), and wherein forming the annular bonding support structure (110) comprises: performing a chemical vapor deposition (CVD) process to selectively form the annular bonding support structure (110) over the circumferential regions (112) of the first semiconductor wafer (102a), the annular bonding support structure (110) comprising an oxide, a nitride, or an oxynitride.The method of claim 4, wherein an outermost surface of the annular bond support structure (110) is spaced apart from the central region (106) of the first semiconductor wafer (102a) a greater distance than an edge of the first semiconductor wafer (102a) is spaced apart from the central region (106).The method of claim 4 or 5, wherein the annular bond support structure (110) extends from the first side of the first semiconductor wafer (102a) beyond a centerline axis (336) of the first semiconductor wafer (102a), the centerline axis (336) extending laterally through the first semiconductor wafer (102a) and being equally spaced from the first side of the first semiconductor wafer (102a) and a second side of the first semiconductor wafer (102a) opposite the first side.The method of any of the preceding claims 4 to 6, wherein the bonding support structure (110) is free of metal coupling structure layers.

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