PARTIAL REMOVAL OF A SEMICONDUCTOR WAFER

Abstract

Process comprising: in a semiconductor body having a first semiconductor layer (10) and a second semiconductor layer (20) adjacent to the first semiconductor layer (10), producing a porous region (12) extending from a first surface (11) into the first semiconductor layer (10); and Removing the porous region (12) by an etching process, wherein with respect to a doping of the first semiconductor layer (10) and a doping of the second semiconductor layer (20) at least one of the following applies: a doping concentration of the second semiconductor layer (20) is less than 10 -2 -times a doping concentration of the first semiconductor layer (10); a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer (10), and wherein the production of the porous region (12) comprises: Bringing a porosifying agent (50) into contact with the first layer (10); and Applying a voltage between the porosifying agent (50) and the first layer (10), wherein bringing the porosifying agent (50) into contact with the first layer (10) comprises attaching a tubular element (31) to the first surface (11) and partially filling a reservoir formed by the tubular element (31) and the first surface (11) with the porosifying agent (50), and wherein applying the voltage comprises applying the voltage between the porosifying agent (50) and an electrode (42) contacting an edge region of the first layer (10) at the first surface (11) outside the tubular member (31).

Description

[0001] This description generally relates to a method for partially removing a semiconductor wafer.

[0002] A semiconductor wafer used to manufacture vertical power semiconductor devices, such as power transistors or power diodes, may comprise a semiconductor substrate and a semiconductor layer, such as an epitaxial layer, formed on the semiconductor substrate. Based on one wafer, multiple semiconductor devices can be manufactured simultaneously, with the wafer subsequently being diced to produce multiple individual semiconductor devices (semiconductor chips). The substrate serves as a carrier for forming the epitaxial layer thereon and mechanically stabilizing the wafer during processing sequences that produce the semiconductor devices. These processing sequences include, for example, forming doped regions in the epitaxial layer, forming passivation layers and / or metallization layers on the one or more epitaxial layers, or the like.

[0003] In some cases, the substrate serves only as a support and is subsequently removed. Another device region, such as a drain region of a MOSFET (metal oxide semiconductor field-effect transistor), a collector region of an IGBT (insulated gate bipolar transistor), or an anode or cathode region of a diode, can be formed in the epitaxial layer after removing the support. Ideally, only the substrate is removed, so the thickness of the semiconductor layer remains unchanged. However, this is difficult to achieve using conventional removal techniques, such as etching or polishing processes.

[0004] US 2017 / 0 170 025 A describes a method for porosifying a semiconductor substrate on which an epitaxial layer doped to a lower degree than the semiconductor substrate is formed. The method comprises placing the substrate in a container containing a porosifying agent and applying a voltage between the epitaxial layer and a plate-shaped electrode arranged in the container below the semiconductor substrate.

[0005] The production of porous silicon by anodic conversion of crystalline silicon using hydrofluoric acid (HF) is fundamentally described in: Beale, M.I.J. [et al.]: Microstructure and formation mechanism of porous silicon. In: Appl. Phys. Lett., Vol. 46, No. 86, 1985.

[0006] US 6 746 932 B2 describes a method for producing a porous region in the region of a first side and in the region of a second side of a semiconductor substrate opposite the first side.

[0007] US 2016 / 0 130 717 A1 describes a process in which a voltage is applied between a chemically active substance in a container and an edge of a material layer to be processed, which is arranged on a carrier. The carrier with the material layer is then immersed in the chemically active substance in such a way that an electrode, via which the voltage is applied to the material layer, remains outside the chemically active substance.

[0008] US 2006 / 0 037 855 A1 describes a device for electrochemically machining a workpiece, such as a wafer. The device comprises several channels, each of which contains an electrode. A voltage can be applied between the electrodes in the channels and another electrode that makes full-surface contact with the workpiece. A liquid is located in the channels, which is brought into contact with different areas of the workpiece via the channels to electrochemically machine the workpiece.

[0009] The object underlying the invention is to precisely and efficiently remove a portion, such as a semiconductor substrate, of a semiconductor wafer while retaining other portions, such as a semiconductor layer previously formed on the substrate. This object is achieved by a method according to claim 1.

[0010] Examples are explained below with the aid of the drawings. The drawings are intended to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The drawings are not to scale. Throughout the drawings, the same reference numerals refer to the same features. Fig. 1 shows a flowchart of an example of a method for partially removing a semiconductor wafer; Fig. 2A - 2C show vertical sectional views of a semiconductor wafer during various process sequences of a method according to claim 1; Fig. 3 shows a plan view of the Fig. 2A shown arrangement; Fig. 4 shows a vertical sectional view of the wafer after another process sequence; Fig. Figure 5 shows a plan view of an example of a wafer according to the Fig. Process step shown in Figure 2C; Fig. Figure 6 shows a vertical sectional view of a wafer after an incomplete porosification process; Fig. 7A - 7B, 8A - 8B, 9A - 9B illustrate different examples of a porosification process; Fig. 10A and Fig. 10B show a horizontal sectional view of electrodes used in the method according to Fig. 9A to 9B can be used; Fig. 11A and Fig. 11B illustrate a porosification process according to another example; Fig. 12A to 12B show a porosification process according to another example; Fig. 13 shows a vertical sectional view of a semiconductor device implemented in the semiconductor wafer before the porosification process; and Fig. 14 shows a vertical sectional view of the Fig. 13 after partial removal of the semiconductor wafer.

[0011] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and show, by way of illustration, examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with one another, unless explicitly stated otherwise.

[0012] Fig. 1 shows a flowchart of an example of a method for partially removing a semiconductor wafer. More specifically, the method relates to at least partially removing a first semiconductor layer of a semiconductor wafer, which comprises the first semiconductor layer and a second semiconductor layer adjacent to the first semiconductor layer. Referring to Fig. 1, the method comprises forming a porous region in the first semiconductor layer of the semiconductor wafer such that the porous region extends from a first surface into the first semiconductor layer. The process for forming the porous region in the first semiconductor layer is hereinafter referred to as the porosification process.

[0013] With respect to a doping of the first semiconductor layer and a doping of the second semiconductor layer, at least one of the following applies: (a) a doping concentration of the second semiconductor layer is less than 10 -2 -times a doping concentration of the first semiconductor layer; (b) a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

[0014] The wafer can satisfy both condition (a) and condition (b), ie the first semiconductor layer and the second semiconductor layer can be layers of complementary doping types and the doping concentration of the second semiconductor layer is less than 10 -2 -(=1E-2) times the doping concentration of the first semiconductor layer, or the wafer can only satisfy one of conditions (a) and (b). The "doping type" is either n or p, so that if the wafer satisfies condition (b), the first semiconductor layer is one of a p-doped (p-type) layer and an n-doped (n-type) layer, and the second semiconductor layer is the other of a p-doped (p-type) layer and an n-doped (n-type) layer. Furthermore, the "doping concentration" is the effective doping concentration.

[0015] According to one example, the doping concentration of the first semiconductor layer is at least 1E3 times or at least 1E4 times the doping concentration of the second semiconductor layer. According to one example, the doping concentration of the first semiconductor layer is higher than 1E18 cm -3 , especially higher than 1E19 cm -3 , and the doping concentration of the second semiconductor layer is lower than 1E16 cm -3 or even lower than 1E14 cm -3 .

[0016] Referring to Fig. 1, the method further comprises removing the porous region by an etching process. A given volume of the porous region has a surface area that is several hundred times the surface area of ​​a non-porous region of the same volume. Due to the larger surface area, the porous region can be etched significantly faster than a non-porous region. Thus, the porous region is completely removed in the etching process, while adjacent non-porous regions are substantially unetched by the etching process. According to one example, the first semiconductor layer and the second semiconductor layer are adapted to one another such that the porous region is formed only in the first semiconductor layer but not in the second semiconductor layer, so that in the overall process, substantially only portions of the first semiconductor wafer are removed.

[0017] The latter is achieved by realizing the first semiconductor layer with a higher doping concentration than the second semiconductor layer, ie by realizing the first semiconductor layer with a doping concentration that is at least 10 2 -times the doping concentration of the second semiconductor layer. In general, the lower the doping concentration of the second semiconductor layer relative to the doping concentration of the first semiconductor layer, the more selective the porosification process. The more selective the porosification process, the smaller the porosified portion of the second semiconductor layer relative to the porosified portion of the first semiconductor layer.

[0018] According to one example, the first semiconductor layer is a semiconductor substrate, and the second semiconductor layer is an epitaxial layer formed on the substrate. According to one example, the second semiconductor layer was formed by implanting and / or diffusing dopant atoms into a semiconductor substrate, wherein a remainder of the substrate forms the first semiconductor layer. In a doped substrate of a first doping type, a second semiconductor layer of the first doping type and with a lower doping concentration than a remainder of the substrate, or a second semiconductor layer of a second doping type complementary to the first doping type, can be formed by implanting and / or diffusing dopant atoms of the second doping type.

[0019] Fig. 2A - 2C illustrate an example of a method according to Fig. 1 in more detail. The Fig. 2A - 2C each show a vertical sectional view of an example of a semiconductor wafer, the Fig. 2A and Fig. 2B further show an arrangement used to create a porous region in the semiconductor wafer.

[0020] Fig. Figure 2A shows the wafer before the porosification process. Referring to Fig. 2A, the wafer comprises a first semiconductor layer 10 and a second semiconductor layer 20 adjacent to the first semiconductor layer 10. According to one example, the first and second semiconductor layers 10, 20 are each a monocrystalline semiconductor layer, so that the wafer is a monocrystalline semiconductor wafer. According to one example, the wafer is made of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like. According to one example, the first and second semiconductor layers 10, 20 are each a doped semiconductor layer, wherein at least one of the above-mentioned conditions (a) and (b) regarding a doping of the first semiconductor layer 10 and a doping of the second semiconductor layer 20 is met.

[0021] The production of the porous region in the first semiconductor layer 10 comprises bringing a porosifying agent 50 into contact with a first surface 11 of the first semiconductor layer 10 and applying a voltage V1 between the first semiconductor layer 10 and the porosifying agent 50. In the Fig. 2A, applying the voltage V1 between the first semiconductor layer 10 and the porosifying agent 50 comprises immersing a first electrode 41 in the porosifying agent 50, contacting the first semiconductor layer 10 with a second electrode 42, and applying the voltage V1 between the first electrode 41 and the second electrode 42. According to one example, the voltage V1 is a direct current (DC) voltage selected from between 1V and 12V. According to another example, a power source (not shown) is connected between the first electrode 41 and the second electrode 42.In any case, a current flows between the first and second electrodes 41, 42 via the porosifying agent 50 and the first semiconductor layer 10, the energy associated with this current causing the porosifying agent 50 to porosify the first semiconductor layer 10 in those areas that are in contact with the agent 50.

[0022] According to one example, the porosifying agent 50 comprises hydrofluoric acid (HF). According to one example, an aqueous solution containing HF is used as the porosifying agent 50. According to another example, the porosifying agent 50 comprises HF and ethanol, such as an aqueous solution containing HF and ethanol. According to one example, a polarity of the voltage V1 is such that an electrical potential of the first electrode 41 is more negative than an electrical potential of the second electrode 42. In this example, the second electrode 42 acts as an anode and the first electrode 41 acts as a cathode in the porosification process.

[0023] The porosifying agent 50 is in the Fig. 2A, a liquid. In this example, contacting the porosifying agent 50 with the first surface 11 of the first semiconductor layer 10 comprises creating a reservoir through the first surface 11 of the first semiconductor layer 10 and a tubular member 31, and at least partially filling the reservoir with the porosifying agent 50. The tubular member 31 is in contact with the first surface 11 of the semiconductor layer 10 and forms sidewalls of the reservoir, and the first surface 11 of the first semiconductor layer 10 forms a bottom of the reservoir.

[0024] After applying the voltage V1, the porosifying agent 50 forms a porous region in the first semiconductor layer 10. Porosification begins at the first surface 11. That is, the porous region 12 is first formed at the first surface 11, where the porosifying agent 50 is first in contact with the first semiconductor layer 10. The porosifying agent 50 penetrates into the porous region 12, so that the porous region 12 extends further into the first semiconductor layer 10. Fig. Figure 2B shows the porous region 12 produced by the porosification process. In this example, the porous region 12 extends in a vertical direction from the first surface 11 of the semiconductor layer 10 through the first semiconductor layer 10 down to the second semiconductor layer 20. In horizontal directions, a dimension of the porous region 12 is essentially given by an area of ​​those portions of the first surface 11 that are in contact with the porosifying agent 50. In other words, the dimension of the porous region 12 in horizontal directions is essentially given by the dimension of the tubular element 31 that forms the reservoir for the porosifying agent 50. The "vertical direction" is a direction perpendicular to the first surface 11 of the first semiconductor layer 10. "Horizontal directions" are directions parallel to the first surface 11.According to one example, the porous region 12 is formed to cover at least 80% of a volume of the first semiconductor layer 10.

[0025] Referring to Fig. 2B, the porous region 12 may extend to the second semiconductor layer 20, but not into the second semiconductor layer 20. That is, the second semiconductor layer 20 may remain substantially unaffected by the porosification process. This may be achieved, as mentioned above, by implementing the first semiconductor layer 10 with a higher doping concentration than the second semiconductor layer 20 and / or with a doping type complementary to a doping type of the first semiconductor layer 10. According to one example, the first semiconductor layer 10 is a p-type layer (p-doped layer) and the second semiconductor layer 20 is an n-type layer (n-doped layer).

[0026] The Fig. 2A-2C illustrate only a portion of the second semiconductor layer, namely a portion adjacent to the first semiconductor layer 10. To largely prevent the porous region from extending into the second semiconductor layer 20, at least the portion of the second semiconductor layer 20 adjacent to the first semiconductor layer 10 has a significantly lower doping concentration than the first semiconductor layer 10. Thus, at a distance from an interface formed between the first semiconductor layer 10 and the second semiconductor layer 20, the second semiconductor layer 20 can have a different doping concentration than at the interface. This is explained further below using an example.

[0027] Fig. Figure 3 shows a top view of the tubular element 31, which, according to one example, forms side walls of the reservoir. In this example, the tubular element 31 forms a circular ring along an edge of the wafer. According to one example, the second electrode 42 is an annular electrode that contacts the first semiconductor layer 10 outside the tubular element 31 along the edge of the first semiconductor layer 10. The first electrode is in Fig. 3 is not shown. The "edge" of the first semiconductor layer 10 is a portion of the first surface 11 that borders an edge surface 14 of the first semiconductor layer 10.

[0028] Fig. Figure 2C shows the wafer after removal of the porosification means and after the etching process. The "porosification means" include the first and second electrodes 41, 42, the porosification means 50, and means for forming the reservoir, such as the tubular element 31 that receives the porosification means 50. In the etching process, the porous region 12 is removed, while non-porous regions remain substantially unaffected. In the Fig. 2B and Fig. In the example shown in Figure 2C, the non-porous region comprises the second semiconductor layer 20 and a portion 13 of the first semiconductor layer 10 that did not come into contact with the porosifying agent 50 during the porosification process. This portion 13 borders the edge surface 14 of the first semiconductor layer 10. In horizontal directions, this portion 13 extends from the edge surface 14 to the tubular element 31 arranged on the first surface 11 during the porosification process. This portion 13 is referred to as the edge region or ring.

[0029] According to one example, the reservoir that receives the porosifying agent 50 is formed on the first surface 11 such that the porosifying agent 50 is in contact with at least 80%, at least 90%, or at least 95% of the first surface 11 of the first semiconductor layer 10 at the beginning of the porosification process. In this case, and if the porous region 12 is formed such that it extends downwards to the second semiconductor layer 20, the edge 13 constitutes less than 20%, less than 10%, or less than 5% of the first semiconductor layer 10. Thus, by the method described in the Fig. 2A - 2C, most of the first semiconductor layer 10 can be removed.

[0030] Furthermore, due to the selectivity of the porosification process, the second semiconductor layer 20 is substantially unaffected by the porosification process and the removal process. That is, most of the first semiconductor layer 10 is removed downwards to the second semiconductor layer 20, while the second semiconductor layer 20 is substantially not removed. Thus, in the vertical direction, the thickness of the removed material is substantially given by the thickness of the first semiconductor layer 10, while the thickness of the second semiconductor layer 20 is substantially maintained. Furthermore, a first surface 21 of the second semiconductor layer 20 obtained by the removal process is substantially defined by an interface between the first semiconductor layer 10 and the second semiconductor layer 20 before the porosification process.In other words, the porosification and removal process essentially ends at this interface. This is independent of possible thickness variations of the first semiconductor layer 10, i.e., independent of whether the surface 11 of the first layer 10 is planar or non-planar.

[0031] The etching process may be a dry etching process, such as a plasma etching process using at least one of Cl2, SF6, HBr, NF3, CF4, or a wet etching process, such as an etching process using a solution of HF and HNO3, a solution of TMAH (tetramethylammonium hydroxide) and alcohol, or a solution of KOH and alcohol.

[0032] According to one example, the wafer comprises a third semiconductor layer 30 (which is shown in the Fig. 2A-2C is shown in dashed lines) adjacent to the second semiconductor layer 20. In this example, the second semiconductor layer 20 may be a relatively thin layer with a thickness of less than 10 micrometers, less than 5 micrometers, or even less than 1 micrometer. According to one example, both the second semiconductor layer 20 and the third semiconductor layer 30 are epitaxial layers. According to one example, the second semiconductor layer is formed by implanting and / or diffusing dopant atoms into the first semiconductor layer 10 (which may be a semiconductor substrate), and the third semiconductor layer 30 is an epitaxial layer grown on the second semiconductor layer 20. According to one example, the method further comprises removing the edge 13. This may comprise a mechanical polishing process, a chemical mechanical polishing (CMP) process, or a laser cutting process.A vertical sectional view of the wafer after removal of the edge 13 is shown in . Fig. 4 shown.

[0033] According to one example, prior to partially removing the first semiconductor layer, a plurality of identical semiconductor devices are fabricated in the second semiconductor layer 20, and the wafer is subsequently diced to form a plurality of individual semiconductor devices. As used herein, "semiconductor device" includes a discrete semiconductor device, such as a transistor, a diode, a thyristor, or the like, but also an integrated circuit comprising multiple devices. Fig. Figure 5 shows a schematic plan view of the wafer after partial removal of the first semiconductor layer 10, that is, after the Fig. 2A to 2C. More precisely, Fig. Figure 5 shows a top view of the edge 13 and the first surface 21 of the second semiconductor layer 20, wherein this first surface is exposed by removing the porous region 12. In Fig. In Figure 5, reference numeral 100 illustrates positions of a plurality of individual semiconductor devices. These semiconductor devices are spaced apart from the edge surface 14 and the edge 13. The wafer is finally divided along dicing lines arranged between the individual semiconductor devices to obtain a plurality of individual semiconductor devices. According to one example, the edge 13 is removed before dividing the wafer.

[0034] According to another example, the wafer is divided without prior removal of the edge 13. By dividing the wafer, the wheel 13 is removed "automatically," so there is no need to remove the wheel 13 beforehand.

[0035] Furthermore, further process steps can be performed after the partial removal of the first semiconductor layer 10 and before dicing the wafer. These process steps include, for example, introducing dopant atoms into the second semiconductor layer via the first surface 21, forming a metallization on the first surface 21, or the like. The edge 13 can help stabilize the wafer during these process steps.

[0036] As stated above, it is desirable to porosify the first semiconductor layer 10 below those portions of the first surface 11 that are in contact with the porosifying agent 50 and that extend downward to the second semiconductor layer 20. It is not desirable for non-porosified regions of the first semiconductor layer 10 to remain after the porosification process, apart from the edge 13. Fig. Figure 6 shows a vertical cross-sectional view of the wafer after an incomplete porosification process. At the end of this porosification process, a non-porosified portion 15 of the first semiconductor layer 10 remains. Within the first semiconductor layer 10, this non-porosified region 15 is surrounded by the porous region 12. In this example, the porous region 12 separates the non-porous region 15 from those portions of the first semiconductor layer 10 that are connected to the second electrode 42.

[0037] To avoid a situation like the one in Fig. To avoid the porosity problem illustrated in Figure 6, it is desirable to control the porosity process such that, during the porosity process, the porous region 12 first contacts the second semiconductor layer 20 at a center of the wafer and then expands further in lateral directions toward the edge surface. Some examples of how this can be achieved are explained below.

[0038] An example of how the porosification process can be improved to avoid a situation like that in Fig. 6 is shown, is in the Fig. 7A-7B. This example includes realizing the first semiconductor layer 10 such that a thickness of the first semiconductor layer 10 has a minimum in the center of the wafer and increases toward the edge surface 13. In this case, the first surface 11 is conical (as in Fig. 7), dished (not shown) or similar. Fig. Figure 7A shows the wafer during the porosification process. A first surface 11 of this type can be obtained, for example, by a polishing or grinding process.

[0039] As shown by Fig. As can be seen in Figure 7A, porosification begins at the first surface 11 below the first electrode 41, and the porous region 12 extends from those portions of the first surface 11 located below the first electrode 41 in the vertical direction and in horizontal directions. Since the semiconductor layer 10 has the smallest thickness in the center of the wafer, the porous region 12 first contacts the second semiconductor layer 20 in the center of the wafer, as shown in Fig. 7A. From there, the porous region 12 continues to expand in horizontal directions until essentially the first semiconductor layer 10 below those portions of the first surface 11 that are in contact with the porosifying agent 50 is completely porosified. Fig. 7A and Fig. In the example illustrated in FIG. 7B, the first electrode 41 has the shape of a plate. According to one example, the first electrode 41 is arranged within the tubular element 31 such that an edge of the plate-shaped first electrode 41 is equidistant from the tubular element. According to one example, an area of ​​the first electrode 41 is at least 50% or at least 75% of a cross-section of the tubular element 31.

[0040] The Fig. 8A and Fig. 8B illustrate another example of a porosification process. In this example, the first electrode 41 has the shape of a needle. That is, a projection of the first electrode 41 onto the first surface 11 is substantially less than a cross-sectional area of ​​the tubular element 31. According to one example, this projection of the needle-shaped first electrode 41 onto the first surface 11 is less than 10% of the cross-sectional area of ​​the tubular element 31. Furthermore, the first electrode 41 is arranged substantially above the center of the wafer during the porosification process.

[0041] Fig. Figure 8A shows the wafer during the porosification process. As can be seen from Fig. As can be seen in Figure 8A, the porous region 12 begins to form below the first electrode 41 at the surface 11 of the first semiconductor layer 10 and spreads from there in the vertical and horizontal directions. In this example, the porous region 12 first contacts the second semiconductor layer 20 at the center of the wafer and spreads from there in horizontal directions.

[0042] The Fig. 9A and Fig. 9B illustrate another example of a porosification process. In this example, the first electrode 41 has a plurality of electrode sections 411-417, with a distance between these electrode sections 411-417 and the first surface 11 increasing as the distance of the respective electrode section from the center of the wafer increases. In other words, the farther an electrode section 411-417 is located from the center of the wafer in the horizontal direction, the farther the respective electrode section is located from the first surface 11 in the vertical direction.

[0043] Fig. 9A shows the wafer during the porosification process. In this example, the porous region 12 extends faster into those regions of the first semiconductor layer 10 where the electrode portions are closer to the first surface 11. Because a distance between the first surface 11 and an electrode portion 411 in the center of the wafer is smaller than the distances between the first surface 11 and other electrode portions 412-417, the porous region 12 has the highest propagation speed in the center of the wafer, so that the porous region 12 contacts the second semiconductor layer 20 in the center of the wafer first. Fig. Figure 9B shows the wafer at the end of the porosification process.

[0044] A first electrode 41, as shown in the Fig. 9A and Fig. 9B, may be in the form of a ribbon-shaped electrode wound into the shape of a spiral. A plan view of such a spiral-shaped first electrode 41 is shown in Fig. 10A.

[0045] According to another example published in Fig. 10B, the electrode 41 comprises several (two or more) concentric electrically conductive rings 41 A -41c. According to one example, these rings are simultaneously connected to the voltage or current source 41.

[0046] According to another example, these rings are 41 A -41 C each via a respective electronic switch 44 A -44 C connected to the voltage or current source 43 and the switches are successively activated (switched on) so that at the beginning of the porosification process an innermost ring 41 Ais connected to the voltage or current source 43, then the directly adjacent ring 41 B is connected to the voltage or current source 43, etc. In other words, the further away a ring 41 A -41 C from a center of the ring configuration, the later in the porosification process it is connected to the voltage or current source 43. In this example, the rings 41 A -41 C have the same distance to the surface 21.

[0047] The Fig. 11A and Fig. 11B illustrate another example of a porosification process. In this example, the first surface 11 of the first semiconductor layer 10 is substantially planar, and the first electrode 41 has a shape such that a distance between the first electrode 41 and the first surface 11 increases toward the tubular element 31. In the porosification process shown in FIGS. Fig. 11A and Fig. In the example shown in Figure 11B, a surface of the first electrode 41 associated with the first surface 11 of the first semiconductor layer is conical. However, this is only an example. According to another example (not shown), this surface is convex or has the shape of a truncated cone. Fig. 11A shows the wafer during the porosification process and Fig. Figure 11B shows the wafer after the porosification process. In this example, the porous region 12 in the first semiconductor layer 10 expands more rapidly in the center of the wafer, so that the porous region 12 first contacts the second semiconductor layer 20 in the center of the wafer.

[0048] The Fig. 12A and Fig. 12B illustrate another example of a porosification process. In this example, the wafer is held by a holder 60, and the holder 60 is arranged in a container 32 that can be filled with the porosifying agent 50. The first electrode 41 can be a plate-shaped electrode that is substantially parallel to the first surface 11 of the first semiconductor layer 10. The holder 60 is arranged in the container 32 such that the first surface 11 is substantially perpendicular to a surface 51 of the porosifying agent 50. During the porosification process, the position of the wafer relative to the surface 51 of the porosifying agent 50 is varied so that the porosifying agent 50 first comes into contact with the first surface 11 of the first semiconductor layer 10 close to a portion of the edge surface 14. This is shown in Fig. 12A.

[0049] The area of ​​the first surface 11 that comes into contact with the porosifying agent 50 increases during the porosification process until the entire area not covered by the holder 60 is in contact with the porosifying agent 50. The position of the wafer relative to the surface 51 of the porosifying agent 50 can be varied by maintaining the position of the wafer within the container 32 and progressively filling the container 32 with the porosifying agent 50. This is shown in the Fig. 12A and Fig. 12B. Alternatively, the container 32 is filled with the porosifying agent so that its fill level is constant, and the wafer is slowly immersed into the porosifying agent 50 at a controlled rate.

[0050] According to one example, the second semiconductor layer 20 is used to integrate semiconductor components therein. In this case, the doping concentration of the second layer 20 is selected such that selective porosification can be achieved and semiconductor components with desired electrical properties are obtained.

[0051] As stated above, one or more semiconductor components can be integrated in the wafer, in particular in the second semiconductor layer 20 of the wafer. Fig. 13 and Fig. 14 show an example of a vertical semiconductor device integrated in the second semiconductor layer 20. Fig. 13 shows the semiconductor device before partial removal of the first semiconductor layer 10, and Fig. 14 shows the semiconductor component after partial removal of the first semiconductor layer 10 and further process steps. Fig. 13 and Fig. 14 each show a portion of a transistor component, wherein, as explained above, multiple transistor components can be integrated in the second semiconductor layer 20. "Integrating a semiconductor component in the second semiconductor layer" in the present sense comprises the fabrication of component structures of the semiconductor component in the second semiconductor layer 20, but also on a second surface 22. "The second surface 22" is a surface facing away from the first semiconductor layer 10.

[0052] For illustrative purposes only, the Fig. 13 and Fig. The transistor device shown in Figure 14 is a vertical transistor device. It should be noted that a transistor device is only one example of a variety of vertical semiconductor devices that can be fabricated based on the second semiconductor layer 20. Other examples include, but are not limited to, a vertical diode, a vertical thyristor, or the like.

[0053] Referring to the Fig. 13 and Fig. 14, the fabrication of the transistor component comprises the fabrication of a plurality of transistor cells 70, wherein these transistor cells 70 each comprise a body region 71 in the second semiconductor layer 20, a source region 72 in the body region 70, and a gate electrode 73 dielectrically insulated from the body region 71 by a gate dielectric 74. In addition, a source electrode 75 is fabricated on the second surface such that it is connected to the source and body regions 72, 71 of the transistor cells 70. This source electrode 75 forms a source node or is connected to a source node S of the transistor component. In addition, the gate electrodes 73 of the individual transistor cells 70 are connected to a common gate node G, wherein connections between the gate electrodes 73 and the gate node G are formed in the Fig. 13 and Fig. 14 are shown only schematically. For illustrative purposes only, the gate electrodes 73 in the Fig. 14, planar gate electrodes are used. That is, the gate electrodes 73 are formed on the second surface 22 and insulated from the source electrode 75. However, this is only one example. According to another example (not shown), the gate electrodes 73 and the gate dielectrics 74 are arranged in trenches in the second semiconductor layer 20.

[0054] The body and source regions 71, 72 can be formed by introducing dopant atoms into the second semiconductor layer 20 via the second surface 22, wherein the introduction of the dopant atoms can comprise at least one of an implantation process and a diffusion process. The second semiconductor layer 20 can be formed by epitaxially growing one or more epitaxial layers on the first semiconductor layer. The second semiconductor layer can have a basic doping. This basic doping can be formed by in-situ doping of the one or more epitaxial layers during the epitaxial growth process.

[0055] Drift regions 79 of the transistor cells may be formed by portions of the second semiconductor layer having the basic doping. Optionally, each transistor cell 70 further comprises a compensation region 76 adjacent to the body region 72. These compensation regions 76 are formed, for example, by implanting and / or diffusing dopant atoms into the one or more epitaxial layers forming the second semiconductor layer 20. Referring to Fig. 13, the drift regions 79 may be formed to extend downward to the first semiconductor layer 10, and the compensation regions may be formed to be spaced apart from the first semiconductor layer 10.

[0056] Optionally, the transistor device also comprises a field stop region 77 (which is shown in the Fig. 13 and Fig. 14 is shown in dashed lines) of the same doping type as the drift region 75, but more highly doped. According to one example, the field stop region 77 is spaced apart from the first semiconductor layer 10. The field stop region 77 can be formed in the process of forming the second semiconductor layer 20 on the first semiconductor layer 10.

[0057] The transistor component can be formed as an n-conducting transistor component or as a p-conducting transistor component. In an n-conducting transistor component, source regions 72 and drift regions 75 are n-doped, and body regions 71 and optional compensation regions 76 are p-doped. In a p-conducting transistor component, the doping types of the individual component regions are complementary to the doping types of the corresponding component regions in an n-conducting transistor component.

[0058] Fig. 14 shows the transistor device after removal of the first semiconductor layer 10 and further process steps. These process steps include introducing dopant atoms into the first surface 21 of the second semiconductor layer 20 to form a drain region 78 and forming a drain metallization 80 on the drain region 78. These process steps can be performed before removing the edge 13 and dividing the wafer, as shown in Fig. 5 is shown.

[0059] The transistor component can be implemented as a MOSFET or an IGBT. In a MOSFET, the drain region 78 has the same doping type as the source and drift regions 72, 79, and in an IGBT, the drain region (which can also be referred to as the collector region) has a doping type that is complementary to the doping type of the source and drift regions 72, 79.

[0060] A relevant feature of a transistor device of the type described in the Fig. 13 and Fig.14 is the on-resistance, which is an electrical resistance of the transistor component between the source metallization 75 and the drain metallization 80 in the on state (switched-on state). The on-resistance depends primarily on a resistance of the drift region 75 between the drain region 78 and the body region 71, wherein this resistance depends on a doping concentration of the drift regions 79 and a length of the drift regions 75, which is the distance between the drain region 78 and the channel regions. "Channel regions" are portions of the body region 72 that border the gate dielectrics 74. In the process of forming the second semiconductor layer 20, the doping concentration of the drift region 79 can be adjusted with high precision.A thickness of the second semiconductor layer 20, which is the dimension of the second semiconductor layer 20 between the first semiconductor layer 10 and the second surface 22, can also be manufactured with high precision. As explained above, the removal method explained above leaves the second semiconductor layer 20 essentially untouched. Therefore, the thickness of the second semiconductor layer 20 is essentially the same before and after the removal of the first semiconductor layer 10. Thus, the removal process results in essentially no thickness variation of the second semiconductor layer 20, and thus essentially no variation in the on-resistance of the transistor component. Essentially no thickness variation includes, for example, that for an 8-inch wafer, thickness variations of the second semiconductor layer 20 are less than 1.5 micrometers or even less than 1 micrometer.

[0061] As stated above, a doping concentration of the second semiconductor layer 20 is less than 1E-2 times the doping concentration of the first semiconductor layer in order to achieve a selective porosification process. In some cases, however, a second semiconductor layer 20 with a doping concentration suitable for achieving a selective porosification process is not suitable for integrating active device regions, such as drift regions of vertical transistor cells, therein. Therefore, as stated above, the wafer may comprise a third semiconductor layer 30 (shown in dashed lines in the drawings) on the second semiconductor layer 20, wherein the second semiconductor layer 20 is a thin layer with a thickness of, for example, less than 10 micrometers.

[0062] In this example, active device regions, such as drift regions 79, body regions 71, and source regions 72, are integrated into the third semiconductor layer 30 (wherein the drift region 79 and the optional compensation regions 60 may be formed during the process of forming the third semiconductor layer 30). The thin second semiconductor layer 20 is removed, for example, before forming the drain region 78. Alternatively, dopant atoms are implanted into the second semiconductor layer 20, for example, to form the drain region 78.

[0063] Although the present description is not so limited, the following numbered examples illustrate one or more aspects of the description. Example 1. A method comprising: in a semiconductor body having a first semiconductor layer and a second semiconductor layer adjacent to the first semiconductor layer, producing a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein with respect to a doping of the first semiconductor layer and a doping of the second semiconductor layer at least one of the following applies: a doping concentration of the second semiconductor layer is less than the 10 -2 -times a doping concentration of the first semiconductor layer; a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer. Example 2. The method of Example 1, wherein the porous region is formed to cover at least 80%, at least 90%, or at least 95% of the volume of the first semiconductor layer. Example 3. The method according to example 1 or 2, wherein the porous region is formed such that in a vertical direction of the first layer, the porous region extends from the first surface to the second surface; and in lateral directions of the first layer, the porous region extends from a center toward an edge surface of the first layer. Example 4. The method of any preceding example, wherein forming the porous region comprises contacting a porosifying agent with the first layer; and applying a voltage between the porosifying agent and the first layer. Example 5. The method of Example 4, wherein contacting the porosifying agent with the first layer comprises: attaching a tubular member to the first surface; partially filling a reservoir formed by the tubular member and the first surface with the porosifying agent. Example 6. The method of Example 4, wherein contacting the porosifying agent with the first layer comprises: immersing the wafer in a container comprising the porosifying agent. Example 7. The method of any one of Examples 4 to 6, wherein applying the voltage comprises applying the voltage between the porosifying agent and an edge region of the first layer. Example 8. The method of example 4 or 5, wherein applying the voltage comprises: immersing a first electrode in the porosifying agent; and applying the voltage between the first electrode and the first layer. Example 9. The method of Example 8, wherein the first electrode is plate-shaped. Example 10. The method of Example 8, wherein the first electrode is needle-shaped. Example 11. The method of example 8, wherein the first electrode is such that a distance between the first electrode and the first surface increases toward an edge region of the first layer. Example 12. The method of Example 9, wherein the first electrode is conical. Example 13. The method of Example 11, wherein the first electrode is spiral-shaped. Example 14. The method of Example 8, wherein the first electrode comprises a plurality of concentric rings. Example 15. A method according to any one of claims 1 to 14, wherein the first surface is substantially planar. Example 16. The method of any one of Examples 1 to 14, wherein the first surface is conical such that a thickness of the first semiconductor layer increases toward an edge of the first layer. Example 17. The method of any preceding example, further comprising: forming a plurality of transistor cells in the second semiconductor layer prior to forming the porous region; and removing the porous region. Example 18. The method of Example 17, further comprising: forming a drain region in the second semiconductor layer after removing the porous region. Example 19. The method of any preceding example, wherein the wafer further comprises a third semiconductor layer on the second semiconductor layer, and wherein the second semiconductor layer has a thickness of less than 10 micrometers, less than 5 micrometers, or less than 1 micrometer. Example 20. The method of Example 19, further comprising: forming a plurality of transistor cells in the third semiconductor layer prior to forming the porous region. Example 21. The method of Example 20, further comprising: removing the second semiconductor layer; and forming a drain region in the third semiconductor layer after removing the porous region. Example 22. The method of Example 20, further comprising: forming a drain region in the second semiconductor layer after removing the porous region.

Claims

[1] Method comprising: in a semiconductor body having a first semiconductor layer (10) and a second semiconductor layer (20) adjacent to the first semiconductor layer (10), producing a porous region (12) extending from a first surface (11) into the first semiconductor layer (10); and Removing the porous region (12) by an etching process, wherein with respect to a doping of the first semiconductor layer (10) and a doping of the second semiconductor layer (20) at least one of the following applies: a doping concentration of the second semiconductor layer (20) is less than 10 -2 -times a doping concentration of the first semiconductor layer (10); a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer (10), and wherein the production of the porous region (12) comprises: Bringing a porosifying agent (50) into contact with the first layer (10); and Applying a voltage between the porosifying agent (50) and the first layer (10), wherein bringing the porosifying agent (50) into contact with the first layer (10) comprises attaching a tubular element (31) to the first surface (11) and partially filling a reservoir formed by the tubular element (31) and the first surface (11) with the porosifying agent (50), and wherein applying the voltage comprises applying the voltage between the porosifying agent (50) and an electrode (42) contacting an edge region of the first layer (10) at the first surface (11) outside the tubular member (31). [2] The method of claim 1, wherein the porous region (12) is formed to cover at least 80%, at least 90% or at least 95% of the volume of the first semiconductor layer (10). [3] Method according to claim 1 or 2, wherein the porous region (12) is produced such that in a vertical direction of the first layer (10), the porous region (12) extends from the first surface (11) to the second surface (20); and in lateral directions of the first layer (10) the porous region (12) extends from a center towards an edge surface (13) of the first layer (10). [4] A method according to any one of the preceding claims, wherein applying the voltage comprises: Immersing a first electrode (41) into the porosifying agent (50); and Applying the voltage between the first electrode (41) and the electrode (42) contacting the first layer (10). [5] A method according to claim 4, wherein the first electrode (41) is plate-shaped. [6] A method according to claim 4, wherein the first electrode (41) is needle-shaped. [7] The method according to claim 4, wherein the first electrode (41) is such that a distance between the first electrode (41) and the first surface (11) increases toward an edge region of the first layer (10). [8] A method according to claim 7, wherein the first electrode (41) is conical. [9] A method according to claim 7, wherein the first electrode (41) is spiral-shaped. [10] Method according to claim 4, wherein the first electrode (41) comprises a plurality of concentric rings (41 A -41 C ). [11] A method according to any one of claims 1 to 10, wherein the first surface (11) is planar. [12] A method according to any one of claims 1 to 10, wherein the first surface (11) is conical such that a thickness of the first semiconductor layer (10) increases towards an edge (14) of the first layer (10). [13] A method according to any one of the preceding claims, further comprising: Producing a plurality of transistor cells (70) in the second semiconductor layer (20) before producing the porous region (12) and removing the porous region (12). [14] The method of claim 13, further comprising: Producing a drain region (79) in the second semiconductor layer (20) after removing the porous region (12). [15] A method according to any one of the preceding claims, wherein the wafer further comprises a third semiconductor layer (30) on the second semiconductor layer (20), and wherein the second semiconductor layer (20) has a thickness of less than 10 micrometers, less than 5 micrometers or less than 1 micrometer. [16] The method of claim 15, further comprising: Producing a plurality of transistor cells (70) in the third semiconductor layer (30) before producing the porous region (12). [17] The method of claim 16, further comprising: Removing the second semiconductor layer (20); and Producing a drain region (79) in the third semiconductor layer (30) after removing the porous region (12). [18] The method of claim 16, further comprising: Producing a drain region (79) in the second semiconductor layer (20) after removing the porous region (12).

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