Substrate arrangement with magnetic feature

Abstract

A substrate arrangement, comprising: a base substrate; one or more connecting elements positioned on a first side of the base substrate, wherein the one or more connecting elements are to be coupled to a semiconductor chip having an integrated voltage regulator (IVR); a magnetic feature formed on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a section of the second side of the base substrate opposite the location where the IVR is to be positioned when the semiconductor chip is coupled to the one or more connecting elements; and a coil that is to be coupled to the IVR, wherein a lateral section of the coil extends through the magnetic feature.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronic circuits. More particularly, the present disclosure relates to substrate designs having a magnetic feature for a fully integrated voltage regulator. BACKGROUND

[0002] The background description provided herein is intended to generally present the context of the disclosure. Unless otherwise noted herein, the materials described in this section are not prior art with respect to the claims in this application and are not admitted as prior art by inclusion in this section.

[0003] Advances in power delivery efficiency have led to the implementation of fully integrated voltage regulators (FIVRs) in semiconductor devices. However, the performance of existing FIVRs implemented in semiconductor devices is limited by the dielectric material surrounding the region where the FIVR is positioned within a semiconductor chip. One previous approach to address this performance limitation was to apply a magnetic film over the entire area of ​​the substrate assembly, with a coil of the FIVR positioned around the substrate assembly. However, this previous approach can compromise the signal integrity of high-speed signals due to the presence of magnetic material. Furthermore, lamination of the magnetic film within the substrate assembly increases the difficulty of manufacturing the substrate assembly.The invention provides a substrate arrangement according to claim 1, a computer device according to claim 8, and a method according to claim 10. Further developments emerge from the dependent claims.

[0004] The documents US 2017 / 0 229 963 A1, US 2015 / 0 036 308 A1, US 2014 / 0 264 732 A1, US 2016 / 0 104 665 A1, US 2016 / 0 036 330 A1 and US 2014 / 0 293 529 A1 describe known semiconductor components. Short description of the drawings

[0005] Embodiments will be readily apparent from the following detailed description taken in conjunction with the accompanying drawings. To simplify this description, like reference numerals designate similar structural elements. Embodiments are illustrated by way of example in the figures of the accompanying drawings. Fig. 1 illustrates a cross-sectional view of an exemplary substrate arrangement with a magnetic feature according to various embodiments. Fig. 2 illustrates a cross-sectional view of an exemplary substrate assembly mounted on a microprocessor chip according to various embodiments. Fig. 3 illustrates a top view of an exemplary magnetic feature with coil elements according to various embodiments. Fig. 4 illustrates a perspective view of the exemplary magnetic feature with coil elements according to various embodiments Fig. 3. Fig. 5 illustrates an exemplary procedure for fabricating a substrate assembly with a magnetic feature according to various embodiments. Fig. 6 illustrates a cross-sectional view of an exemplary resulting base substrate according to step 502. Fig. 7 illustrates a cross-sectional view of the resulting base substrate according to step 504. Fig. Figure 8 illustrates a cross-sectional view of the resulting base substrate according to step 506. Fig. 9 illustrates a cross-sectional view of the resulting base substrate according to step 508. Fig. 10 illustrates a cross-sectional view of the resulting base substrate according to step 510. Fig. 11 illustrates a cross-sectional view of the resulting base substrate according to step 512. Fig. 12 illustrates a cross-sectional view of the resulting base substrate according to step 514. Fig. 13 illustrates an example computing device that may employ the devices and / or methods described herein. DETAILED DESCRIPTION

[0006] Devices, systems, and methods associated with a substrate design having a magnetic feature for a fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements positioned on a first side of the base substrate, wherein the one or more interconnect elements are to be coupled to a semiconductor chip having an integrated voltage regulator (IVR).The substrate assembly may further comprise a magnetic feature positioned on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a portion of the second side of the base substrate that is opposite the location where the IVR is to be positioned when the semiconductor chip is coupled to the one or more interconnect elements.

[0007] In the following detailed description, reference is made to the accompanying drawings, wherein like reference characters designate similar parts throughout, and in which are shown, by way of illustration, embodiments that may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made.

[0008] Aspects of the disclosure are disclosed in the accompanying description. It should be noted that similar elements disclosed below are indicated by similar reference numerals in the drawings.

[0009] Various operations may, in turn, be described as multiple discrete acts or operations in a manner that is helpful in understanding the claimed subject matter. However, the order of description should not be considered to imply that these operations are necessarily order-dependent. More specifically, these operations may not be performed in the order presented. Described operations may be performed in a different order than the described embodiments. Various additional operations may be performed and / or described operations may be omitted from additional embodiments.

[0010] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0011] The description may use the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used herein with respect to embodiments of the present disclosure, are synonymous.

[0012] As used herein, the term “circuitry” may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or a memory (shared, dedicated, or group) executing one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0013] Fig. 1 illustrates a cross-sectional view of an exemplary substrate assembly 100 with a magnetic feature 102 according to various embodiments. The substrate assembly 100 may include a base substrate 104. The base substrate 104 may include a dielectric material. Furthermore, in some embodiments, the base substrate 104 may include one or more build-up films. The build-up films may include dielectric material and may be epoxy-based in some embodiments.

[0014] The base substrate 104 may include one or more conductive elements 112, such as vias, traces, pads, or a combination thereof. The conductive elements 112 may include conductive material such as copper, silver, gold, aluminum, zinc, nickel, tin, or a combination thereof. The conductive elements 112 may extend from the interconnection elements 106 positioned on a first side 108 of the substrate assembly 100 to a second side 110 of the substrate assembly 100 and / or to the magnetic feature 102. One or more interconnection elements 106 may form a structure on the second side 110 of the substrate assembly 100, wherein the structure may be a copper structure. In the illustrated embodiment, the base substrate 104 may include a first conductive element 112a, a second conductive element 112b, a third conductive element 112c, and a fourth conductive element 112d.The first conductive element 112a and the fourth conductive element 112d may extend from corresponding ones of the interconnection elements 106 positioned on the first side 108 of the substrate assembly 100 to the second side 110 of the substrate assembly 100. The second conductive element 112b and the third conductive element 112c may extend from corresponding ones of the interconnection elements 106 positioned on the first side 108 of the substrate assembly 100 to the magnetic feature 102 positioned on the second side 110 of the substrate assembly 100. In other embodiments, the second conductive element 112b and the third conductive element 112c may extend into and / or through the magnetic feature 102.

[0015] The substrate assembly 100 may further include one or more interconnection elements 106 positioned on the first side 108 of the substrate assembly 100. The interconnection elements 106 may be used to attach the substrate assembly 100 to a semiconductor chip with an integrated voltage regulator. In the illustrated embodiment, the interconnection elements 106 are depicted as solder balls forming a ball grid array. However, it should be understood that the interconnection elements 106 may include any type of interconnection element used to attach a substrate to a semiconductor chip, such as wires, pads, and other similar interconnection elements.

[0016] The substrate arrangement 100 may further include the magnetic feature 102. The magnetic feature 102 may be positioned on the second side 110 of the substrate arrangement 100. In some embodiments, the magnetic feature 102 may be positioned on the structure formed by the conductive elements 112, which may be a copper structure. Furthermore, the magnetic feature 102 may extend into the base substrate 104. The magnetic feature 102 may comprise a magnetic material, and may comprise a ferromagnetic material, in some embodiments. The magnetic feature 102 may extend through only a portion of the second side 110 of the substrate arrangement 100. In particular, the magnetic feature 102 may only be positioned at positions that improve an inductance of an inductor coil associated with the voltage regulator of the semiconductor chip.For example, the magnetic feature 102 may extend through only a portion of the second side 110, where coil elements 114 are positioned. The magnetic feature 102 may be positioned on an opposite side of the substrate assembly from where the semiconductor chip is to be coupled to the integrated voltage regulator.

[0017] The substrate assembly 100 may further comprise a coil. The coil may comprise one or more coil elements 114 (as indicated by the Fig. 1) that extend through the magnetic feature 102. In particular, the coil elements 114 may extend through the magnetic feature 102 from a first side of the magnetic feature 102 to a second side of the magnetic feature 102. The magnetic feature 102 may encapsulate the portions of the coil elements 114 that extend through the magnetic feature 102. The coil elements 114 may comprise copper. Each of the coil elements 114 may include a thin strip of copper and / or a copper wire. Further, each of the coil elements 114 may extend parallel to the other coil elements of the coil elements 114.

[0018] Portions of the coil elements 114 may extend outside the magnetic feature 102 on both the first side of the magnetic feature 102 and the second side of the magnetic feature 102, wherein the portions of the coil elements 114 may be coupled to the corresponding ones of the conductive elements 112. The conductive elements 112 to which the coil elements 114 are coupled may extend through the base substrate 104 to the interconnect elements 106 positioned on a first side 108 of the substrate assembly 100, wherein the interconnect elements 106 are intended to couple to the voltage regulator within the semiconductor chip. The coil elements 114, the conductive elements 112, and the interconnect elements 106 may form the coil associated with the voltage regulator.

[0019] The substrate assembly 100 may further include a surface finish 116. The surface finish 116 may be positioned on both the first side 108 and the second side 110 of the substrate assembly 100. The surface finish 116 may extend over portions of the first side 108 and the second side 110 where the magnetic feature 102, the conductive elements 112, and the interconnect elements 106 are not positioned. The surface finish 116 may protect the base substrate 104 from damage. In some embodiments, the surface finish 116 may be omitted.

[0020] Fig. 2 illustrates a cross-sectional view of the exemplary substrate assembly 100 mounted on a microprocessor chip 203 according to various embodiments. In particular, the cross-sectional view of Fig. 2 at 90 degrees from the cross-sectional view of Fig. 1. Furthermore, the description of Fig. 2 refer to a single coil element 114a for simplicity. It should be noted that the single coil element 114a may be representative of the other coil elements 114 within the substrate assembly 100.

[0021] The coil element 114a may extend through the magnetic feature 102 from a first side 202 of the magnetic feature 102 to a second side 204 of the magnetic feature 102. A first portion 206 of the coil element 114a may extend out of the magnetic feature 102 at the first side 202. The first portion 206 of the coil element 114a may be coupled to a first conductive element 208 via a first connection element 210. The first conductive element 208 may include one or more of the features of the conductive elements 112 ( Fig. 1). Furthermore, the first connecting element 210 may include one or more of the features of the connecting elements 106 ( Fig. 1). The first conductive element 208 may extend from the first interconnect element 210, positioned on the second side 110 of the substrate assembly 100, to one of the interconnect elements 106 positioned on the first side 108 of the substrate assembly 100. One of the interconnect elements 106 may couple the first conductive element 208 to the microprocessor chip 203.

[0022] A second portion 212 of the coil element 114a may extend out from the magnetic feature 102 on the second side 204. The second portion 212 of the coil element 114a may be coupled to a second conductive element 214 via a connector 216. The second conductive element 214 may include one or more of the features of the conductive elements 112. Furthermore, the second connector 216 may include one or more of the features of the connectors 106. The second conductive element 214 may extend from the second connector 216 positioned on the second side 110 of the substrate assembly 100 to one of the connectors 106 positioned on the first side 108 of the substrate assembly 100. One of the connectors 106 may couple the second conductive element 214 to the microprocessor chip 203.

[0023] The microprocessor chip 203 may include a microprocessor and may include one or more of the features of the processor 1304 ( Fig. 13). The microprocessor chip 203 may include an integrated voltage regulator 218. The voltage regulator 218 may be fully integrated within the microprocessor chip 203, which may be referred to as a fully integrated voltage regulator (FIVR). In some embodiments, the integrated voltage regulator may include a puck regulator. Having the voltage regulator 218 integrated within the microprocessor chip 203 may provide an increase in battery life, may provide an increase in peak available power, and / or may free up space on a motherboard on which the microprocessor chip 203 is mounted.

[0024] The voltage regulator 218 can receive power from a printed circuit board (PCB) (such as the PCB 1302 ( Fig. 13)) at a first voltage, and may convert the power to one or more other voltages to provide power to components within and / or coupled to the microprocessor chip 203. The voltage regulator 218 may have an inductor coil to produce the power conversion. In the illustrated embodiment, the coil formed by the first conductive element 208, the coil element 114a, and the second conductive element 214 may function as the inductor coil for the voltage regulator 218.Furthermore, the other coil elements 114 and the corresponding conductive elements (such as the conductive elements 112, the first conductive element 208 and / or the second conductive element 214) may be coupled to the first conductive element 208, the coil element 114a and the second conductive element 214 as part of the coil, and may operate as part of the inductance coil for the voltage regulator 218.

[0025] The microprocessor chip 203 may further include programmable connections between the voltage regulator 218 and the conductive elements (such as the conductive elements 112, the first conductive element 208, and / or the second conductive element 214). For example, the microprocessor chip 203 may be programmed to couple the first conductive element 208 to the voltage regulator 218, to couple the second conductive element 214 to another of the conductive elements 112 that is coupled to a second coil element of the coil elements 114, and to couple the other of the conductive elements 112 that is coupled to the second coil element to the voltage regulator 218. Accordingly, the coil element 114a and the second coil element may be connected in series and may cooperatively function as the inductance coil for the voltage regulator 218.The microprocessor chip 203 may be capable of coupling one or more of the coil elements 114 in series to operate as the inductance coil of the voltage regulator 218, wherein the number and / or the particular coil elements 114 to be coupled in series may be selected based on a desired output voltage.

[0026] In other embodiments, the substrate assembly 100 may include one or more conductive traces that couple the coil elements 114 in series. In these embodiments, one of the conductive elements coupled to a first of the coil elements 114 may be coupled to a voltage regulator 218, and one of the conductive elements coupled to a second of the coil elements 114 may be coupled to the voltage regulator 218. Further, in these embodiments, all of the coil elements 114 may be connected in series to function as the inductance coil for the voltage regulator 218. The number of coil elements 114 connected in series may not be adjustable in these embodiments, unlike the embodiments where the microprocessor chip 203 provides programmable connections between the coil elements 114.

[0027] A portion of the magnetic feature 102 may be positioned within the area defined by the loop formed by the first conductive element 208, the coil element 114a, and the second conductive element 214. Accordingly, the portion of the magnetic feature 102 may act as a core within the coil comprising the loop. Because the magnetic feature 102 may provide a higher magnetic permeability than the material of the base substrate 104, the magnetic feature 102 may provide improved performance of the inductor coil compared to prior substrates that do not include the magnetic feature 102. Furthermore, the magnetic feature 102 may provide a higher magnetic permeability than prior magnetic films, which may provide improved performance of the inductor coil compared to substrates using prior magnetic films.In particular, prior art magnetic films may have a magnetic permeability of six, while the magnetic feature 102 may have a magnetic permeability greater than six. In some embodiments, the magnetic permeability of the magnetic feature 102 may be greater than nine. The high magnetic permeability of the magnetic feature 102 may be due to its being formed by a magnetic paste, as described with reference to FIG. Fig. 5 is described.

[0028] Fig. 3 illustrates a top view of an exemplary magnetic feature 302 with coil elements 304 according to various embodiments. The magnetic feature 302 may include one or more of the features of the magnetic feature 102 ( Fig. 1). The magnetic feature 302 may be incorporated in a substrate assembly (such as the substrate assembly 100 ( Fig. 1)) and may be mounted on one side of the substrate assembly opposite a microprocessor chip having a voltage regulator (such as the microprocessor chip 203 ( Fig. 2) with the voltage regulator 218 ( Fig. 2)). In particular, the magnetic feature 302 may be positioned on a side of a base substrate, such as the base substrate 104 ( Fig. 1).

[0029] The coil elements 304 may extend through the magnetic feature 302 from a first side 306 of the magnetic feature 302 to a second side 308 of the magnetic feature 302. First portions 310 of each of the coil elements 304 may extend out of the magnetic feature 302 from the first side 306. Furthermore, second portions 312 of each of the coil elements 304 may extend out of the magnetic feature 302 from the second side 308. Each of the first portions 310 and the second portions 312 may include a coupling element. The coupling elements may be used to couple the coil elements 304 to the corresponding conductive elements (such as the conductive elements 112 ( Fig. 1)) of the base substrate.

[0030] In the illustrated embodiments, the coil elements 304 may include a first coil element 304a, a second coil element 304b, a third coil element 304c, and a fourth coil element 304d. The first coil element 304a may include a first coupling element 314 positioned at a first end of the first coil element 304a and a second coupling element 316 positioned at a second end of the first coil element 304a, the second end being opposite the first end. The first coupling element 314 may couple the first coil element 304a to one of the conductive elements of the base substrate, and the second coupling element 316 may couple the first coil element 304a to another of the conductive elements of the base substrate.

[0031] The second coil element 304b may include a third coupling element 318 positioned at a first end of the second coil element 304b, and a fourth coupling element 320 positioned at a second end of the second coil element 304b, the second end being opposite the first end. The third coupling element 318 may couple the second coil element 304b to one of the conductive elements of the base substrate, and the fourth coupling element 320 may couple the second coil element 304b to another of the conductive elements of the base substrate.

[0032] The third coil element 304c may include a fifth coupling element 322 positioned at a first end of the third coil element 304c, and a sixth coupling element 324 positioned at a second end of the third coil element 304c, the second end being opposite the first end. The fifth coupling element 322 may couple the third coil element 304c to one of the conductive elements of the base substrate, and the sixth coupling element 324 may couple the third coil element 304c to another of the conductive elements of the base substrate.

[0033] The fourth coil element 304d may include a seventh coupling element 326 positioned at a first end of the fourth coil element 304d, and an eighth coupling element 328 positioned at a second end of the fourth coil element 304d, the second end being opposite the first end. The seventh coupling element 326 may couple the fourth coil element 304d to one of the conductive elements of the base substrate, and the eighth coupling element 328 may couple the fourth coil element 304d to another of the conductive elements of the base substrate.

[0034] Fig. 4 illustrates a perspective view of exemplary magnetic feature 302 with coil elements 304 according to various embodiments. Fig. 3. In the illustrated embodiment, the second coupling element 316 of the first coil element 304a is shown extending from the second side 308 of the magnetic feature 302. The second coupling element 316 may include a pillar 402 that extends substantially (within five degrees) perpendicular to the portion of the first coil element 304a that extends through the magnetic feature 302. The pillar 402 may be used to couple the first coil element 304a to a conductive element of a base substrate.

[0035] Each of the coupling elements may include a pillar (such as pillar 402) that may be used to couple each of the coil elements to the respective conductive elements of the base substrate. For example, the first coupling element 314 ( Fig. 3), the third coupling element 318 ( Fig. 3), the fourth coupling element 320 ( Fig. 3), the fifth coupling element 322 ( Fig. 3), the sixth coupling element 324 ( Fig. 3), the seventh coupling element 326 ( Fig. 3) and the eighth coupling element 328 ( Fig. 3) each comprise a column (such as column 402). The columns of each of the coupling elements may extend in the same direction substantially (within five degrees) perpendicular to the portions of the coil elements that extend through the magnetic feature 302.

[0036] Fig. 5 illustrates an exemplary procedure 500 for manufacturing a substrate assembly having a magnetic feature, according to various embodiments. In particular, the procedure 500 may manufacture a substrate assembly having one or more of the features of the substrate assembly 100 ( Fig. 1). Furthermore, the magnetic feature produced by procedure 500 may include one or more of the features of magnetic feature 102 ( Fig. 1) include.

[0037] At step 502, a base substrate may be fabricated. Specifically, one or more build-up films may be attached to a dummy core. The build-up films may comprise a dielectric material. In some embodiments, the build-up films may be epoxy-based. Fabricating the base substrate may further include forming one or more conductive elements within the build-up films.

[0038] Fig. 6 illustrates a cross-sectional view of an exemplary resulting base substrate 602 according to step 502. One or more build films may have been attached to the dummy core 604 to form the base substrate 602. The base substrate 602 may include one or more of the features of the base substrate 104 ( Fig. 1) include.

[0039] Furthermore, one or more of the conductive elements 606 may be formed within the base substrate 602. The conductive elements 606 may include one or more of the features of the conductive elements 112 ( Fig. 1). The conductive elements 606 may have been formed incrementally as each of the build-up films was attached to the dummy core 604. In particular, a first build-up film may have been attached to the dummy core 604, and then a drilling procedure may have been performed to create via recesses within the first build-up film corresponding to each of the conductive elements 606. An electroplating process may then have been performed to create vias within the via recesses. An additional build-up film may have been attached to the first build-up film, and the procedure may then be repeated until the base substrate 602 had a desired thickness. Each of the conductive elements 606 may be formed by one or more vias stacked on top of one another. The conductive elements 606, or a portion thereof, may form a structure on the first side 608 of the base substrate 602.

[0040] In some embodiments, the drilling procedure may have been performed incrementally as all of the build-up films were attached to the dummy core 604, but the electroplating process may have been performed only once a certain number of build-up films were attached to the dummy core 604. For example, a first build-up film may have been attached to the dummy core 604, and then a drilling procedure may have been performed to create via recesses within the first build-up film corresponding to each of the conductive elements 606. A second build-up film may have been attached to the first build-up film, and then another drilling procedure may have been performed to create via recesses within the second build-up film. An electroplating procedure may then have been performed to create vias within the via recesses formed in the first build-up film and the second build-up film.Each of the conductive elements 606 can be formed by one or more vias stacked on top of each other.

[0041] In some embodiments, the build-up films may have been applied to the dummy core 604 prior to the formation of the conductive elements 606. For example, the build-up films may have been applied to produce the base substrate 602 of the desired thickness. A drilling procedure may then be performed to create via recesses for each of the conductive elements 606. An electroplating process may then be performed to create conductive elements 606 in each of the via recesses.

[0042] In operation 504, a magnetic paste may be applied to a surface of the base substrate opposite the dummy core. The magnetic paste may be applied to portions of the surface of the base substrate between the base substrate and locations where the coil elements (such as coil elements 114 ( Fig. 1)) are to be positioned. The magnetic paste can be applied to a different portion of the surface of the base substrate where the coil elements are not to be positioned. The magnetic paste can be applied to the structure created by the conductive elements and / or to the surface of the base substrate. The magnetic paste can then be cured, such as by applying heat, light, chemicals, or a combination thereof to the magnetic paste. Curing the magnetic paste can cause the magnetic paste to harden and can create a magnetic feature on the base substrate.

[0043] Fig. Figure 7 illustrates a cross-sectional view of the resulting base substrate 602 according to step 504. A magnetic feature 702 may have been formed on a surface 704 of the base substrate 602. The surface 704 may be positioned on an opposite side of the base substrate 602 from the dummy core 604. The magnetic feature 702 may cover a portion of the surface adjacent to where the coil elements are to be positioned. In particular, the magnetic feature 702 may be positioned between the base substrate 602 and locations where the coil elements are to be positioned.

[0044] To create the magnetic feature 702, the magnetic paste may have been applied to the position of the magnetic feature 702. In particular, a mask may have been positioned on the surface 704 of the base substrate 602, with the mask having an opening over the portion of the surface 704 on which the magnetic feature 702 was to be formed. The magnetic paste may then have been applied to the surface 704, where the mask may have prevented the magnetic paste from being applied to the surface 704 outside the intended area. Once the magnetic paste was applied, the mask may have been removed, and the magnetic paste may have been cured to create the magnetic feature 702.

[0045] At step 506, one or more additional build-up films may be laminated to the base substrate. The additional build-up films may cover the magnetic feature. The base substrate and the additional build-up films may encapsulate the magnetic feature. The additional build-up films may include dielectric material. In some embodiments, the build-up films may be epoxy-based.

[0046] Fig. Figure 8 illustrates a cross-sectional view of the resulting base substrate 602 according to step 506. The base substrate 602 may include one or more build-up films 802 laminated to the surface 704 of the base substrate 602. The build-up films 802 may cover the magnetic feature 702, resulting in the magnetic feature 702 being encapsulated by the base substrate 602 and the build-up films 802. The build-up films 802 may become a portion of the base substrate 602 when laminated.

[0047] At step 508, a planarization process may be performed on the base substrate. The planarization process may result in the side of the base substrate where the build-up films are positioned being ground to be planar. In particular, the planarization process may be performed to produce a desired thickness of the base substrate 602. The magnetic feature may be exposed by the planarization process.

[0048] Fig. Figure 9 illustrates a cross-sectional view of the resulting base substrate 602 according to step 508. The first side 608 of the base substrate 602 may have been ground to produce a planar surface 904. The magnetic feature 702 may be positioned on the planar surface 904 and may form a portion of the planar surface 904. The base substrate 602 may form the remainder of the planar surface 904.

[0049] At step 510, a next layer structure may be formed on the base substrate. In particular, the next layer structure may be formed at the surface where the magnetic feature is positioned. Forming the next layer structure may include forming one or more vias in the surface. The one or more vias may be formed on the conductive elements formed at the base substrate step 502, thereby extending the conductive elements. The vias may be formed by a drilling process to form via recesses within the base substrate and / or the magnetic feature. An electroplating process may then be applied to deposit conductive material within the via recesses to form the vias.

[0050] Fig. 10 illustrates a cross-sectional view of the resulting base substrate 602 according to step 510. One or more vias 1002 may have been formed within the base substrate 602. The vias 1002 may have been formed on the conductive elements 606 and may extend the conductive elements 606, or a portion thereof, to the first side 608 of the base substrate 602. In some embodiments, one or more vias 1002 may be formed further within the magnetic feature 702.

[0051] At step 512, the dummy core may be removed, and a backend process may be executed. Once the dummy core has been removed, the backend process may form interconnects (such as interconnects 106 ( Fig. 1)) on the side of the base substrate where the dummy core was previously attached. The backend process may further include applying a surface finish (such as surface finish 116 ( Fig. 1)) on the side of the base substrate to which the dummy core was previously attached, wherein the surface finish may not cover the side of the base substrate where the interconnection elements are not positioned. The backend process may further include applying the surface finish to the side of the base substrate where the magnetic feature is positioned, wherein the surface finish may cover the side of the base substrate where the conductive elements 606 and the magnetic feature are not positioned.

[0052] Fig. 11 illustrates a cross-sectional view of the resulting base substrate 602 according to step 512. The dummy core 604 ( Fig. 6) may have been removed from a second side 1102 of the base substrate 602. One or more interconnect elements 1104 may have been formed on the second side 1102 of the base substrate 602 where the dummy core was previously positioned. The interconnect elements 1104 may include one or more of the features of the interconnect elements 106 ( Fig. 1). The connecting elements 1104 may be formed adjacent to the conductive elements 606 and may be coupled to the conductive elements 606.

[0053] Furthermore, the surface finish 1106 may be formed on both the first side 608 and the second side 1102 of the base substrate 602. In particular, the surface finish 1106 may be formed on the portions of the first side 608 of the base substrate 602 where the conductive elements 606 and the magnetic feature 702 are not positioned. Furthermore, the surface finish 1106 may be formed on the portions of the second side 1102 where the connecting elements 1104 are not positioned.

[0054] At step 514, one or more coil elements (such as coil elements 114 ( Fig. 1)) be positioned over a surface of the base substrate where the magnetic feature is positioned. Further, additional magnetic paste may be applied to the surface of the base substrate where the magnetic feature is positioned, wherein the additional magnetic paste is applied to the magnetic feature and encapsulates a portion of the coil elements. The additional magnetic paste may be applied such that portions (such as the first portion 206 ( Fig. 2) and the second section 212 ( Fig. 2)) extend from the additional magnetic paste. The additional magnetic paste can then be cured, such as by applying heat, light, and / or chemicals, and become part of the magnetic feature.

[0055] Fig. Figure 12 illustrates a cross-sectional view of the resulting base substrate 602 according to step 514. One or more coil elements 1202 may have been deposited over the previously formed portions of the magnetic feature 702 shown in Fig. 10, such that the previously formed portions of the magnetic feature 702 would be positioned between the coil elements 1202 and the base substrate 602. Furthermore, the coil elements 1202 may have been coupled to one or more of the conductive elements 606, similar to the coupling of the coil element 114a to the first conductive element 208 and the second conductive element 214 shown in Fig. 2 and are described with reference to the same.

[0056] Additional magnetic paste may have been applied to the first side 608 of the base substrate 602. The additional magnetic paste may have been applied to the previously formed portions of the magnetic feature 702 and to the conductive elements 606 extending through the previously formed portions of the magnetic feature 702. A mask may have been positioned on the surface 1204 of the base substrate 602, with the mask having an opening over the portion of the surface 1204 where the additional magnetic paste was to have been applied. The magnetic paste may then have been applied to the surface 1204, where the mask may have prevented the magnetic paste from being applied to the surface 1204 outside of the intended area.The additional magnetic paste may encapsulate the coil elements 1202 with portions of the coil elements 1202 extending out of the first side and the second side of the additional magnetic paste, such as the first portions 310 extending out of the first side 306 and the second portions 312 extending out of the second side 308, as shown in FIG. Fig. 3. Once the magnetic paste was applied, the mask may have been removed and the additional magnetic paste may have been cured to form the magnetic feature 702 shown in Fig. 12 is shown.

[0057] In some embodiments, the magnetic paste may not be applied. In these embodiments, the coil elements 1202 may be applied over the previously formed portions of the magnetic feature 702 shown in Fig. 10, and may not be encapsulated by the magnetic feature 702.

[0058] Fig.13 illustrates an example computing device 1300 that may employ the devices and / or methods described herein (e.g., substrate assembly 100), according to various embodiments. As shown, computing device 1300 may include a number of components, such as one or more processors 1304 (not shown) and at least one communication chip 1306. In various embodiments, the one or more processors 1304 may each include one or more processor cores. The one or more processors 1304 may further include one or more integrated voltage regulators 1360. The one or more voltage regulators 1360 may be fully integrated into the one or more processors 1304. In various embodiments, the at least one communication chip 1306 may be physically and electrically coupled to the one or more processors 1304.In further implementations, the communication chip 1306 may be part of the one or more processors 1304. In various embodiments, the computing device 1300 may include a printed circuit board (PCB) 1302. For these embodiments, the one or more processors 1304 and the communication chip 1306 may be disposed thereon. In alternative embodiments, the various components may be coupled without the use of the PCB 1302.

[0059] Depending on its applications, the computing device 1300 may include other components that may or may not be physically and electrically coupled to the PCB 1302. These other components include, but are not limited to, a memory controller 1326, volatile memory (e.g., dynamic random access memory (DRAM) 1320), non-volatile memory such as read-only memory (ROM) 1324, flash memory 1322, a storage device 1354 (e.g.,a hard disk drive (HDD), an I / O controller 1341, a digital signal processor (not shown), a crypto processor (not shown), a graphics processor 1330, one or more antennas 1328, a display (not shown), a touchscreen display 1332, a touchscreen controller 1346, a battery 1336, an audio codec (not shown), a video codec (not shown), a GPS device (GPS; global positioning system) 1340, a compass 1342, an accelerometer (not shown), a gyroscope (not shown), a speaker 1350, a camera 1352, and a mass storage device (such as a hard disk drive, an SSD drive (SSD), a CD (compact disk), a DVD (digital versatile disk)) (not shown), and so on.

[0060] In some embodiments, the one or more processors 1304, the flash memory 1322, and / or the storage device 1354 may include firmware (not shown) associated with them that stores programming instructions configured to enable the computing device 1300, in response to execution of the programming instructions by the one or more processors 1304, to perform all or selected aspects of the methods described herein. In various embodiments, these aspects may additionally or alternatively be implemented using hardware separate from the one or more processors 1304, the flash memory 1322, or the storage device 1354.

[0061] In various embodiments, the one or more processors 1304 may include one or more of the substrate assemblies 100. In particular, one or more processors of the one or more processors 1304 that include the one or more voltage regulators 1360 may include the one or more substrate assemblies 100. In particular, the one or more substrate assemblies 100 may be implemented as an inductance coil of the one or more voltage regulators 1360, wherein the one or more of the conductive elements 112 and the coil elements 114 may operate as a coil for the one or more voltage regulators 1360.

[0062] Communication chips 1306 may enable wired and / or wireless communication for transferring data to and from computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although they may not in some embodiments. Communication chip 1306 may incorporate any number of wireless standards or protocols, including, but not limited to, IEEE 802.20, Long Term Evolution (LTE), LTE-Advanced (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), Evolved High Speed ​​Packet Access (HSPA+), Evolved High Speed ​​Downlink Packet Access (HSDPA+), Evolved High Speed ​​Uplink Packet Access (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Bluetooth, derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 1300 may include a plurality of communication chips 1306.For example, a first communication chip 1306 may be dedicated for shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1306 may be dedicated for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0063] In various implementations, computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a PDA (personal digital assistant), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit (e.g., a game console or an automotive entertainment unit), a digital camera, an appliance, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.

[0064] Example 1 may include a substrate assembly comprising a base substrate, one or more interconnection elements positioned on a first side of the base substrate, the one or more interconnection elements to be coupled to a semiconductor die having an integrated voltage regulator (IVR), and a magnetic feature positioned on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a portion of the second side of the base substrate that is opposite the location where the IVR is to be positioned when the semiconductor die is coupled to the one or more interconnection elements.

[0065] Example 2 may include the substrate arrangement of Example 1, wherein a portion of the magnetic feature is to be positioned between the IVR and a portion of a coil associated with the IVR.

[0066] Example 3 may include the substrate assembly of Example 1 or 2, further comprising a coil to be coupled to the IVR, wherein a portion of the coil extends through the magnetic feature.

[0067] Example 4 may include the substrate assembly of Example 3, wherein the magnetic feature encapsulates the portion of the coil.

[0068] Example 5 may include the substrate assembly of Example 1 or 2, wherein the magnetic feature comprises a ferromagnetic material.

[0069] Example 6 may include the substrate assembly of Example 1 or 2, wherein the base substrate comprises a copper structure, and wherein the magnetic feature is positioned on the copper structure.

[0070] Example 7 may include the substrate assembly of Example 1 or 2, wherein a portion of the magnetic feature extends from the second side of the base substrate into the base substrate.

[0071] Example 8 may include the substrate assembly of Example 1 or 2, further comprising the semiconductor chip having the IVR, wherein the semiconductor chip is coupled to the one or more interconnect elements, and a coil is coupled to the IVR, wherein a portion of the magnetic feature is positioned between the IVR and a portion of the coil.

[0072] Example 9 may include the substrate assembly of Example 8, wherein the portion of the coil extends through the magnetic feature.

[0073] Example 10 may include the substrate assembly of Example 9, wherein the magnetic feature encapsulates the portion of the coil.

[0074] Example 11 may include the substrate arrangement of Example 1 or 2, wherein the IVR is a fully integrated voltage regulator.

[0075] Example 12 may include the substrate arrangement according to Example 1 or 2, wherein the semiconductor chip is a microprocessor.

[0076] Example 13 may include a computing device comprising a printed circuit board (PCB), a semiconductor chip coupled to the PCB, the semiconductor chip having an integrated voltage regulator (IVR); and a substrate assembly coupled to the semiconductor chip, wherein a coil extends around a portion of the substrate assembly, the substrate assembly comprising the coil coupled to the IVR, a base substrate, wherein the semiconductor chip is coupled to a first side of the base substrate, and a magnetic feature positioned on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a portion of the second side of the base substrate that is opposite the location where the IVR is positioned.

[0077] Example 14 may include the computing device of Example 13, wherein a portion of the magnetic feature is positioned between the IVR and a portion of the coil.

[0078] Example 15 may include the computing device of example 13 or 14, wherein a portion of the coil extends through the magnetic feature.

[0079] Example 16 may include the computing device of Example 15, wherein the magnetic feature encapsulates the portion of the coil.

[0080] Example 17 may include the computing device of example 13 or 14, wherein the magnetic feature comprises a ferromagnetic material.

[0081] Example 18 may include the computing device of example 13 or 14, wherein the base substrate comprises a copper structure, and wherein the magnetic feature is positioned on the copper structure.

[0082] Example 19 may include the computing device of example 13 or 14, wherein a portion of the magnetic feature extends from the first side of the base substrate into the base substrate.

[0083] Example 20 may include the computing device of example 13 or 14, wherein the IVR is a fully integrated voltage regulator.

[0084] Example 21 may include the computing device of example 13 or 14, wherein the semiconductor chip is a microprocessor.

[0085] Example 22 may include a method of forming a substrate assembly for a semiconductor chip including an integrated voltage regulator (IVR;integrated voltage regulator), comprising forming a base substrate, forming a magnetic feature on a portion of a first side of the base substrate, the portion of the first side being opposite a portion of a second side of the base substrate to which the semiconductor chip is to be coupled, the second side being opposite the first side, applying a build-up film to the first side of the base substrate, the build-up film to cover the magnetic feature, planarizing the first side of the base substrate to remove a portion of the build-up film on the magnetic feature and to expose the magnetic feature, patterning the first side of the base substrate, and forming interconnection elements on the second side of the base substrate, the semiconductor chip being to be coupled to the interconnection elements.

[0086] Example 23 may include the method of Example 22, wherein forming the magnetic feature comprises applying a magnetic paste to the portion of the first side of the base substrate and curing the magnetic paste to produce the magnetic feature.

[0087] Example 24 may include the method of example 22 or 23, wherein the portion of the build film is a first portion, and wherein planarizing the first side of the base structure further causes a second portion of the build film to be a target thickness, wherein the second portion of the build film remains on the first side of the base substrate after planarizing the first side.

[0088] Example 25 may include the method of example 22 or 23, wherein the base substrate includes a dummy core positioned on the second side of the base substrate, and wherein forming the interconnection elements on the second side of the base substrate includes removing the dummy core from the base substrate and forming the interconnection elements on the second side of the base substrate after the dummy core has been removed.

[0089] Example 26 may include the method of any example 22 or 23, further comprising positioning a portion of a coil adjacent to the magnetic feature, wherein the portion of the coil is positioned on the first side of the base structure, and wherein the coil is to couple to the IVR, applying a magnetic paste to the first side of the base substrate, wherein the magnetic paste is to contact the magnetic feature and encapsulate the portion of the coil, and curing the magnetic paste, wherein the cured magnetic paste becomes part of the magnetic feature.

[0090] Example 27 may include the method of any example 22 or 23, wherein the magnetic feature is formed on a copper structure of the base substrate.

[0091] Example 28 may include the method of Example 22 or 23, wherein the magnetic feature comprises a ferromagnetic material.

[0092] Example 29 may include the method of example 22 or 23, wherein the semiconductor chip is a microprocessor.

Claims

[1] A substrate assembly comprising: a base substrate; one or more interconnect elements positioned on a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR); a magnetic feature formed on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a portion of the second side of the base substrate that is opposite the location where the IVR is to be positioned when the semiconductor chip is coupled to the one or more interconnect elements; and a coil to be coupled to the IVR, wherein a lateral portion of the coil extends through the magnetic feature. [2] The substrate assembly of claim 1, wherein the magnetic feature encapsulates the portion of the coil. [3] The substrate assembly of any preceding claim, wherein the magnetic feature comprises a ferromagnetic material. [4] The substrate assembly of any preceding claim, wherein the base substrate comprises a copper structure, and wherein the magnetic feature is positioned on the copper structure. [5] The substrate assembly of any preceding claim, wherein a portion of the magnetic feature extends from the second side of the base substrate into the base substrate. [6] The substrate assembly according to any one of the preceding claims, further comprising: the semiconductor chip having the IVR, wherein the semiconductor chip is coupled to the one or more interconnect elements. [7] The substrate assembly of any preceding claim, wherein the IVR is a fully integrated voltage regulator. [8] A computer device comprising: a printed circuit board (PCB); a semiconductor chip coupled to the PCB, the semiconductor chip having an integrated voltage regulator (IVR); and a substrate assembly coupled to the semiconductor chip, wherein a coil extends around a portion of the substrate assembly, the substrate assembly comprising: the coil coupled to the IVR; a base substrate, wherein the semiconductor chip is coupled to a first side of the base substrate; and a magnetic feature formed on a second side of the base substrate, the second side being opposite the first side, the magnetic feature extending along a portion of the second side of the base substrate that is opposite the location where the IVR is positioned, a lateral portion of the coil extending through the magnetic feature. [9] The computing device of claim 8, wherein the magnetic feature encapsulates the portion of the coil. [10] The computing device of any of claims 8-9, wherein the magnetic feature comprises a ferromagnetic material. [11] A method of forming a substrate assembly for a semiconductor chip having an integrated voltage regulator (IVR), comprising: Forming a base substrate; Forming a magnetic feature on a portion of a first side of the base substrate, the portion of the first side being opposite a portion of a second side of the base substrate to which the semiconductor chip is to be coupled, the second side being opposite the first side; Applying a build-up film to the first side of the base substrate, the build-up film to cover the magnetic feature; Planarizing the first side of the base substrate to remove a portion of the build-up film on the magnetic feature and to expose the magnetic feature; Structuring the first side of the base substrate; and Forming interconnecting elements on the second side of the base substrate, wherein the semiconductor chip is to be coupled to the interconnecting elements. [12] The method of claim 11, forming the magnetic feature comprising: Applying a magnetic paste to the portion of the first side of the base substrate; and Curing the magnetic paste to create the magnetic feature. [13] The method of any one of claims 11-12, wherein the portion of the build-up film is a first portion, and wherein planarizing the first side of the base substrate further causes a second portion of the build-up film to be a target thickness, the second portion of the build-up film remaining on the first side of the base substrate after planarizing the first side. [14] The method according to any one of claims 11-13, wherein the base substrate comprises a dummy core positioned on the second side of the base substrate, and forming the connecting elements on the second side of the base substrate comprising: Removing the dummy core from the base substrate; and Forming the interconnect elements on the second side of the base substrate after the dummy core has been removed. [15] The method according to any one of claims 11-14, further comprising: Positioning a portion of a coil adjacent to the magnetic feature, wherein the portion of the coil is positioned on the first side of the base substrate, and wherein the coil is to couple to the IVR; Applying a magnetic paste to the first side of the base substrate, wherein the magnetic paste is to contact the magnetic feature and encapsulate the portion of the coil; and Curing the magnetic paste, whereby the cured magnetic paste becomes part of the magnetic feature.

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