Memory cell device and method for operating a memory cell device

Abstract

Storage cell device (300), comprising: at least one memory cell (102); one between the at least one memory cell (102) and a reference potential (104 or 106) switched first switch (S1); a switch control logic (330) which is configured to selectively put the first switch (S1) into one of at least three operating states by activating or deactivating a first sub-circuit (330_1T) of the switch control logic (330): • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on-state and higher than in the off-state, further comprising: a second switch (S2) connected between the at least one memory cell (102) and the reference potential (104 or 106); wherein the switch control logic (330) is further configured to selectively place the second switch (S2) into one of at least three operating states by activating or deactivating a second sub-circuit (330_2T) of the switch control logic (330): • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state, wherein the first switch (S1) and the second switch (S2) are connected in parallel.

Description

[0001] The invention relates to a storage cell device and a method for operating a storage cell device.

[0002] The invention relates to memory circuits, in particular memory circuits that offer a low-energy mode. A low-energy mode is understood to be an operating mode with low energy consumption. In some applications, this is also referred to as low-power mode or standby mode. The term "memory" (and related terms) is also commonly used in German for electronic data storage devices.

[0003] The memory cell devices and their associated circuits can be those used for volatile data storage, such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) memory circuits. These require a predetermined holding voltage at their power supply nodes to retain the stored data.

[0004] Products with low energy consumption are based on or contain integrated circuits which themselves can be operated in low-energy mode.

[0005] Wireless products (i.e., electronic devices designed for wireless data exchange, e.g., mobile phones, laptops, or tablets), chip card products (e.g., identification cards such as identity cards, insurance cards such as health insurance cards, or payment cards such as credit cards), automotive products (e.g., an engine control unit for the engine responsible for propelling the vehicle (e.g., an internal combustion engine or an electric motor) and / or for other motors such as power windows), or components or devices used for automated driving and energy management products are examples of such products that can provide a low-energy mode.

[0006] Most integrated circuits have memory circuits for storing data. Therefore, to provide a product with a low-power mode, the memory circuits should be capable of operating with low power consumption.

[0007] A portion of the energy consumption in memory circuits is caused by leakage currents. In automotive microcontroller products, the number of SRAM memory cells roughly doubled during the transition from 40 nm to 28 nm technology. Simultaneously, the leakage current per bit in the SRAM increased (e.g., almost doubled). This means that the leakage current contribution of the SRAM memory nearly quadrupled.

[0008] Memory circuits should provide techniques or technologies to reduce leakage current and enable a low-energy mode that is robust, adjustable, inexpensive in terms of the required (chip) area, and easy to implement, while guaranteeing the preservation of stored data.

[0009] Furthermore, a high peak current should be avoided when switching from low-energy mode to normal operation (also known as active mode, active power mode or active operating mode).

[0010] In Fig. Figure 2A schematically depicts several memory cell devices known in the prior art, each in a variant where a positive voltage supply VDD is switched (a PFET transistor is switched, shown in the column: "VDD switching", PFET-based), and in a variant where a negative voltage supply or a ground connection VSS is switched (an NFET transistor is switched, shown in the column: "VSS switching", NFET-based).

[0011] In a relatively simple memory cell arrangement 200a, 200b (shown in the first row of the Fig. 2A, labelled "power supply off"), allows a supply voltage VDD or VSS of a memory cell array 100 to be switched on or off by means of a transistor 220 connected between the memory cell array 100 and the voltage supply VSS or VDD. However, this means that information stored in the memory cell array 100 is lost when switched off, especially if the memory cell array 100 is volatile.

[0012] One way to provide a reduced operating voltage to the memory cell array 100 for a low-energy mode can be to use a diode.

[0013] In the line labeled "diode mode" of the Fig. Figure 2A shows a memory cell arrangement 201a, 201b, in which a transistor acting as a diode 222 is connected in parallel to the voltage supply VSS or VDD, which can be switched on and off by means of a switch (transistor) 220. When the switch 220 is switched off, a reduced operating voltage for the memory cell array 100 can be provided via the diode 222 in a low-energy mode, thereby reducing leakage currents.

[0014] An example of such a memory cell device 201a, 201b from US 7,110,317 B2 is in Fig. 2B (center) is shown.

[0015] Koji Nii et al. show in their article “A dynamic / static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs” (Digest of Technical Papers - IEEE Symposium on VLSI Technology, September 21, 2016). Fig. 3, reproduced here in Fig. 2B (above), an example in which a reduced operating voltage can be provided by means of a diode 222 connected in series with a main switch 220.

[0016] Such a design, using a main switch 220 and an additional diode 222, means that although chip area must be provided for both components (main switch 220 and diode 222), the diode 222 nevertheless makes only a small contribution to the voltage supply of the memory cell array 100 in an active mode (i.e., during normal operation). Furthermore, the voltage provided by the diode (VSSC or VDDC) cannot be adjusted in low-energy mode. This design also has the disadvantage that the voltage supply of the memory cell array 100 is routed through a series connection of components, resulting in an undesirably increased voltage drop across this series connection, which can only be compensated for by increasing the chip area.

[0017] In Fig. In the third line, 2A shows a so-called "maintenance mode". In this mode, a maintenance voltage VDDRET (or an increased maintenance voltage VSSRET) compared to the operating voltage for normal operation VDD (or VSS) can be switched on via a transistor 224.

[0018] However, the "maintenance mode" requires a separate VDDRET (or VSSRET) power supply on the chip, which consumes chip area and increases wiring complexity. Furthermore, area is needed for a circuit to generate the VDDRET (or VSSRET) voltage.

[0019] However, this design does not allow for situation-dependent adjustment of the VSSRET voltage if the circuit for generating the VSSRET voltage or the VSSRET voltage supply is shared (e.g., by several memory cells).

[0020] A relatively elaborate design is in Fig. 2A in the last line (labeled "Regulator Mode") is shown for a memory circuit 203a, b. A control circuit 228 is provided for controlling a gate of a main switch 220.

[0021] In this design, the 228 control circuit is complex, sensitive to changes / fluctuations, and consumes chip area and additional energy.

[0022] A corresponding design example for a storage circuit 203a according to US 2009 / 0189684 A1 is in Fig. 2B (below) is shown.

[0023] US 6 977 519 B2 discloses a power gate structure comprising an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source-to-source or drain-to-drain, a ground node in signal communication with the drains of the transistors, and a ground rail in signal connection with the sources of the transistors.

[0024] Agarwal et al.: Power Gating with Multiple Sleep Modes. In: ISQED'06, 2006, 1-5 reveals circuits with switches that enable multiple sleep modes, differing in their latency and ability to suppress leakage currents.

[0025] US 5,726,946 A discloses a variable-impedance power supply line and a variable-impedance ground line that supply voltages VCL1 and VSL1, respectively. These voltages are set to a low-impedance state during a standby cycle and a row-related signal reset period, and to a high-impedance state during a valid time period of a column circuit. The supply voltages VCL2 and VSL2 of the variable-impedance power supply line and the variable-impedance ground line are each set to a high-impedance state during the standby cycle and to a low-impedance state during the active cycle and the row-related signal reset period. Inverters operate as the operating supply voltages for voltages VCL1 and VSL2 or VCL2 and VSL1, corresponding to a logic level of an output signal during the standby cycle and the active cycle.

[0026] A memory cell device according to claim 1 and a method for operating a memory cell device according to claim 24 are provided. Further embodiments are described in the dependent claims.

[0027] In various embodiments, a memory cell device is provided with a low-energy mode for its storage elements. The memory cell device can have at least one switching element that provides more than two modes, e.g., ON / OFF / DIODE.

[0028] In contrast, prior art discloses combinations of switching elements in which each switching element provides only one mode (DIODE) or two modes (ON / OFF).

[0029] In various embodiments, a memory cell device is provided. The memory cell device can have at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic configured to selectively put the first switch into one of at least three operating states by activating or deactivating a first sub-circuit of the switch control logic: an on state, an off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0030] The conductive state can be provided by means of a diode, for example by having the first switch a transistor that can be switched on for the on state and off for the off state, and which can be operated in a diode mode for the conductive state.

[0031] Thus, at least three operating states (on state, off state, conductive state) can be implemented using a single switch, saving chip area.

[0032] In various embodiments, the memory cell device can have a second switch connected between the at least one memory cell and the reference potential, wherein the switch control logic can further be configured to selectively put the second switch into one of at least three operating states by activating or deactivating a second sub-circuit of the switch control logic: on state, off state and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0033] In various embodiments, this makes it possible, for example, to adapt a voltage level at VSSC (or VDDC) during a low-energy mode to characteristic properties of the memory cells within the memory array, e.g. by only setting one of the switches to one state while leaving the other switch in another state.

[0034] Furthermore, in various embodiments, the occurrence of high peak currents when switching the storage cell device from a low-energy mode to an active ("ON") mode can be reduced, e.g. by first switching a first switching element before switching on another (e.g. second) switching element.

[0035] In various embodiments, all switching elements can contribute to the power supply in active mode ("power-on mode").

[0036] An "off mode" can be implemented by putting all switching elements into the "off" mode.

[0037] In various embodiments, the earth voltage supply can be switchable, or a positive voltage supply, or both.

[0038] Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

[0039] They show Fig. 1 a schematic representation of a storage cell device according to the state of the art; Fig. 2A a compilation of various schematically represented storage cell devices according to the state of the art; Fig. 2B Examples of state-of-the-art storage cell devices; Fig. 3 a schematic representation of a memory cell device according to various embodiments; Fig. 4 a schematic representation of a memory cell device according to various embodiments; Fig. 5 a schematic representation of a memory cell device according to various embodiments; Fig. 6 a schematic representation of switching states in a memory cell device according to various embodiments; and Fig. 7 a flowchart of a method for operating a storage cell device according to various embodiments.

[0040] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used with reference to the orientation of the described figure(s). Since components of embodiments can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention.It is understood that the features of the various exemplary embodiments described herein can be combined with one another, unless specifically stated otherwise. The following detailed description is therefore not to be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the appended claims.

[0041] Within the scope of this description, the terms "connected," "attached," and "coupled" are used to describe both direct and indirect connections, direct or indirect links, and direct or indirect couplings. In the figures, identical or similar elements are labeled with identical reference symbols where appropriate.

[0042] Various embodiments of devices and methods are described herein. It should be understood that features and properties described in connection with devices also apply to methods, and vice versa.

[0043] Fig. 3 to Fig. Figures 5 each show a schematic representation of a memory cell arrangement 300 according to different embodiments. The embodiments of Fig. 3, Fig. 4 and Fig. The 5 are distinguished as memory cell devices 300a, 300b and 300c respectively. Unless specific features of the respective embodiments are referred to, the general reference numeral 300 is used for the memory cell device.

[0044] A storage cell device 300 as described herein can be used, for example, in the automotive sector, e.g. using 28 nm technology.

[0045] The memory cell device 300 can have at least one memory cell 102, e.g., in the form of a memory cell array 100 (also referred to as memory array 100). The memory cell 102 can be a conventional memory cell 102, e.g., an RRAM, MRAM, PC-RAM, ROM, or flash memory cell, in particular a conventional volatile memory cell 102, e.g., a DRAM or SRAM memory cell. The memory cell array 100 can accordingly be a conventional memory cell array 100, such as that found, for example, in Fig. 1 is shown and described in connection with it, e.g. a memory cell array 100, e.g. an SRAM, DRAM, RRAM, MRAM, PC RAM, ROM or Flash array.

[0046] To operate the memory cell array 100, an operating voltage 108, 110 can be provided at its inputs. This is in Fig. 3 to Fig. 5 also designated with VDDC for a positive or more positive operating voltage 108 and with VSSC for a negative or more negative operating voltage 110 or an earth connection.

[0047] The storage cell device 300 can also have a positive or more positive reference potential 106 (in Fig. 3 to Fig. 5 also referred to as VDD, in analogy to the designation V usually used for a positive supply voltage DD ) and provide a negative or more negative or grounding reference potential 104 (in Fig. 3 to Fig. 5 is labelled VSS, in analogy to the designation V commonly used for a negative supply voltage - often GND. SS ).

[0048] In the event that the unchanged reference potential is applied to one of the inputs of the memory cell array 100, the operating voltage 108 or 110 can be equal to the corresponding reference potential 104 or 106 (in Fig. 3 to Fig. 5 the reference potential 106).

[0049] In various embodiments, the memory cell device 300 can have a first switch S1 connected between the at least one memory cell 102 and a reference potential 104 or 106, and a switch control logic 330. The control logic can be, as in Fig. 4 and Fig. As shown in Figure 5, the control logic 330 can be multi-part and, for example, have a first part 330_1 for controlling the first switch S1, a second part 330_2 for controlling a second switch S2, and so on. To improve clarity, when describing the functionality of the control logic 330, sometimes only the reference symbol of the part of the control logic 330 relevant to the described function is given. It should be understood that specifying only this reference symbol does not make any statement about the functionality (especially inactivity, etc.) of the other parts of the control logic 330, if any.

[0050] The control logic 330_1 can be configured to selectively activate or deactivate the first switch S1 by activating or deactivating a first sub-circuit 330_1T (see Fig. 5) to put the switch control logic 330_1 into one of at least three operating states. The at least three operating states can include an on state, an off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0051] The switch control logic 330_1 can be configured in various embodiments such that the first switch S1 is in the conducting state when the sub-circuit 330_1T is activated. For example, the first switch S1 can be a (first) transistor, e.g., a (first) field-effect transistor, e.g., an NFET as in Fig. 5 or a PFET (not shown). The switch control logic 330_1 can be configured such that, when activated, the sub-circuit 330_1T creates an electrically conductive connection between a controlled output of the first switch S1 and a gate of the first switch S1, so that the first switch S1 (the transistor) is switched as a diode, also known as diode mode or diode-mode state. In diode mode, the conductivity of the transistor (and thus of the first switch S1) is lower than in a fully conducting (closed) state of the transistor and higher than in an insulating (open) state of the transistor.

[0052] When sub-circuit 330_1T is deactivated, the first switch S1 can be in the off state or the on state. For switching between the conducting and off states of the first switch S1, further switches 550 and 552 can be provided in the switch control logic 330_1, by means of which the gate of the first switch S1 can be selectively connected to either the positive reference potential 106 or the negative reference potential 104.

[0053] The switch control logic 330_1 can be configured such that, in the on state, the gate is connected to the reference potential 104 or 106 that closes or keeps closed the first switch S1, and thus connects at least one memory cell 102 to the reference potential 104 or 106 (in Fig. 3 to 5: 104) connects, and that in the off state the gate is connected to the other reference potential 104 or 106, which opens or leaves open the first switch S1 and thus establishes a connection between at least one memory cell 102 and the reference potential 104 or 106 (in Fig. 3 to 5: 104) prevented.

[0054] For example, in the on-state, the gate of the first transistor (i.e., the first switch S1), also referred to as the first gate, can be connected to a positive voltage supply terminal (the positive reference potential 106), e.g., VDD. In the off-state, the first gate can be connected to a ground terminal 104 (the negative reference potential, e.g., VSS), and in the conducting state, the first gate can be connected to a virtual voltage supply terminal 110.

[0055] The first field-effect transistor can be an NFET transistor, and the virtual voltage supply terminal 110 can be a ground terminal.

[0056] To enable switching of the connections of the gate with the positive reference potential 106, the negative reference potential 104 and the virtual voltage supply connection 110, the switch control logic 330 can have further switches, e.g. transistors.

[0057] For example, the switch control logic 330 can have or consist of a gate control circuit. In the exemplary embodiment from Fig. The gate control circuit for the first switch S1 corresponds to the first part 330_1 of the switch control logic 330. The gate control circuit can include a fourth field-effect transistor 550 between the first gate and the positive voltage supply terminal 106. A first switching voltage conb1 can be provided to the gate of the fourth field-effect transistor.

[0058] The gate control circuit can further include a fifth field-effect transistor 552 between the first gate and the ground terminal 104. A second switching voltage coff1 can be supplied to the gate of the fifth field-effect transistor 552.

[0059] The gate control circuit can further include a sixth field-effect transistor TG1 (or a pair of two field-effect transistors TG1) between the first gate and the virtual voltage supply terminal 110. A third switching voltage cdiode1 can be provided at the gate of the sixth field-effect transistor TG1 (or at the gates of the pair of two field-effect transistors TG1). The pair of two field-effect transistors can comprise an NFET transistor and a PFET transistor, in particular a parallel-connected pair of two field-effect transistors.

[0060] In various embodiments, a PFET transistor can be used instead of the NFET transistor for the first switch S1. In this case, the first switch S1 and the switch control logic 330 can be connected between the positive reference potential 106 and the at least one memory cell 102. The negative reference potential 110 (e.g., the ground connection VSS) can then be provided directly as the supply voltage 104.

[0061] In this case (not shown), the gate control circuit can be configured to connect the first gate to a ground terminal in the on state, to connect the first gate to a positive voltage supply terminal in the off state, and to connect the first gate to a virtual voltage supply terminal in the conducting state. The virtual voltage supply terminal can be a positive voltage supply terminal.

[0062] The described design makes it possible to provide a storage cell device 300 with a low-energy mode, in which the first switch S1 contributes to the power supply of the at least one storage cell 102 in both the on and conducting states, and in which components connected in parallel to switch S1, which are ineffective in one of the switching states, can be omitted. Furthermore, the switch control logic 330 is of simple design, robust, and can be dimensioned very small.

[0063] In various embodiments, the memory cell device 300, 300b, 300c can further include a second switch S2 connected between the at least one memory cell 102 and the reference potential 104 or 106.

[0064] The switch control logic 330, 330_2 can further be configured to selectively put the second switch S2 into one of at least three operating states by activating or deactivating a second sub-circuit 330_2T of the switch control logic 330_2: an on state, an off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0065] In other words, the second switch S2 can have functionality comparable to the first switch S1. The design of the second switch S2 can be the same as or similar to that of the first switch S1. For example, the second switch S2 could be a (second) transistor, e.g., a (second) field-effect transistor.

[0066] The switch control logic 330 can have or consist of a second gate control circuit for controlling a gate of the second switch S2. In the exemplary embodiment from Fig. In section 5, the gate control circuit for the second switch S2 corresponds to the second part 330_2 of the switch control logic 330. The gate control circuit can include a seventh field-effect transistor 554, an eighth field-effect transistor 556, and a ninth field-effect transistor TG2 (or a pair of two field-effect transistors TG2), which function similarly to the field-effect transistors 550, 552, and TG1, respectively, of the first gate control circuit. A fourth, fifth, and sixth switching voltage, conb2, boff2, and cdiode2, respectively, can be provided to the respective gates of the seventh, eighth, and ninth field-effect transistors 554, 556, and TG2. The pair of two field-effect transistors TG2 can comprise an NFET transistor and a PFET transistor, and in particular, a pair of two field-effect transistors connected in parallel.

[0067] The first switch S1 and the second switch S2 can be connected in parallel, as shown in Fig. 4 and Fig. 5 shown.

[0068] The memory cell device 300, 300b, 300c may further include additional switches (not shown) connected between the at least one memory cell 102 and the reference potential 104 or 106, which have the same functionality as the first switch S1 and the second switch S2, in particular being able to be switched into one of at least three operating states (a switch-on state, a switch-off state, and a conductive state in which the electrical conductivity is lower than in the switch-on state and higher than in the switch-off state) by means of the switch control logic 330.

[0069] In various embodiments, both the first switch S1 and the second switch S2 can be configured to be independently in one of their three operating states. In other words, both switches S1 and S2 can be in the ON state, both switches S1 and S2 can be in the OFF state, both switches can be in the conductive state, one of the switches can be in the ON state and the other in the OFF state, one of the switches can be in the ON state and the other in the conductive state, or one of the switches can be in the conductive state and the other in the OFF state.

[0070] In the memory cell device 300, the switch control logic 330 can be configured in various embodiments to selectively put the memory cell device 300 into one of at least three power levels by moving the first switch S1 and the second switch S2 into one of their three operating states (on state, off state, conductive state): a fully on state, in which the first switch and the second switch are in the on state, a partial power state, in which at least one of the first switch and the second switch is in the conductive state, and a fully off state, in which the first switch and the second switch are in the off state.

[0071] The fully-on state can be provided for the normal operation of the storage cell device 300.

[0072] The all-off state can be provided for a complete shutdown of the memory cell device 300, i.e. a state in which a loss of the data stored in the at least one memory cell 102 is accepted.

[0073] The partial power state can be used for standby operation, i.e., for example, for a state in which there is no active use of the memory cell device 300, i.e., no normal operation in which, for example, writing to the at least one memory cell 102 and / or reading from the at least one memory cell 102 takes place, but in which it is desirable to retain the data stored in the at least one memory cell 102, e.g., the memory cell array 100.

[0074] In various embodiments, the at least three power levels can also have a partial-on state in which the first switch S1 is in the on state and the second switch S2 is in the off state, or vice versa.

[0075] The partially on state can serve as an intermediate switching state for transitioning from the fully off state or the partial power state to the fully on state, as this can reduce or prevent the occurrence of high peak currents. For example, the individual switches can be switched sequentially from the off state to the on state, thus avoiding high peak currents.

[0076] In various embodiments, the partially-on state and / or the partial-power state may be arranged such that the value of a voltage drop across the at least one memory cell 102 is sufficiently high to ensure continuous data storage.

[0077] All (main) switches S1, S2, ..., i.e., those switches S1, S2, ... which are configured to directly switch the supply voltage of at least one memory cell 102, are configured, in the normal operating mode (active mode) of the memory cell device 300, in which all switches S1, S2, ... are or will be switched on (i.e., fully on), to contribute to the power supply of at least one memory cell 102, e.g., the memory cell array 100. Serial connections of power supply switches, which degrade conductivity, as in the prior art example from Fig. The step shown in 2B (above) can be omitted. Furthermore, chip area can be saved.

[0078] In various embodiments, the memory cell arrangement 300, 300b, 300c can further comprise a third switch S3 connected between the at least one memory cell 102 and the reference potential 104 or 106. The switch control logic 330 can be configured to selectively set the third switch S3 to one of exactly two operating states, namely either an on state or an off state.

[0079] In other words, the third switch S3 can have limited functionality (only on / off) compared to the first switch S1 (and, if present, compared to the second switch S2). The third switch S3 can be connected in parallel to the first switch S1 (and, if applicable, to the second switch S2 and any other switches), as shown in Fig. 4 and Fig. Figure 5 shows the third switch S3 being implemented as a transistor (also referred to as the third transistor), e.g. as a field-effect transistor, e.g. as an NFET as in Figure 5. Fig. 5 shown, or as PFET (not shown).

[0080] A gate of the third switch S3 can be selectively connected to either the positive reference potential 106 or the negative (ground) reference potential 104. For selective connection, i.e., switching between the two connections, a tenth transistor 558 can be provided between the gate and the positive reference potential 106, and an eleventh transistor 560 can be provided between the gate and the negative (ground) reference potential 104. A common seventh switching voltage, conb3, can be provided at the gates of the tenth and eleventh transistors 558 and 560.

[0081] The third switch S3 can be considered the main power supply switch. Since, in normal operating mode, in addition to the main power supply switch S3, the first switch S1 and possibly the second switch S2 and possibly other switches also contribute to the power supply of at least one storage cell, the third switch S3 can be smaller.

[0082] Similar to the memory cell device 300, 300b described above with the first switch S1 and the second switch S2, the switch control logic 330 of the memory cell device 300c can be configured to selectively put the memory cell device 300c into one of at least three power levels by setting the first switch S1 and the second switch S2 into one of their three operating states and the third switch S3 into one of its two operating states: a fully-on state in which the first switch, the second switch and the third switch are in the on state, a partially-power state in which at least one of the first switch and the second switch is in the conducting state, and a fully-off state in which the first switch, the second switch and the third switch are in the off state.

[0083] In the exemplary embodiment from Fig. 5. The off state can be achieved, for example, by connecting the respective gate of the first, second, and third switches S1, S2, and S3, respectively, which are each implemented as NFET transistors, to the negative reference potential 104, e.g., VSS. This can be achieved, for example, as described below.

[0084] In various embodiments, the at least three power levels can also have a partially on state in which at least one of the first switch S1, the second switch S2 and the third switch S3 is in the on state and at least one of the other two switches is in the off state.

[0085] The use of the power levels can correspond analogously to that described above for the memory cell device 300b with the two switches S1, S2.

[0086] The completely off state can be implemented in various ways (such as in Fig. Figure 5 shows that the three switches S1, S2 and S3 are to be switched off for the fully off state. This is achieved by providing a negative (or grounding) reference potential as a virtual reference potential, i.e., cdiode1 or cdiode2, a positive reference potential (conb1, conb2 and conb3 are e.g. VDD) is provided at the gate of the fourth transistor 550, the seventh transistor 554 and the tenth transistor 558, and a positive reference potential (coff1, coff2 are e.g. VDD) is also provided at the gate of the fifth transistor 552 and the eighth transistor 556.

[0087] In various embodiments, the first switch S1 can have a higher electrical conductivity in the conductive state than the second switch S2 in the conductive state. This can be achieved, for example, as a simple technical implementation, by using the first switch S1 as a first field-effect transistor and the second switch S2 as a second field-effect transistor, with the first field-effect transistor having a larger transistor width than the second field-effect transistor.

[0088] In various embodiments, as a further simple technical realization of different conductivities, the first field-effect transistor (i.e. the first switch S1) can alternatively or additionally have a lower threshold voltage than the second field-effect transistor (i.e. the second switch S2).

[0089] This allows for more different configurations / settings for a low-energy mode (e.g., the partial power mode; the partially on mode could also be considered a low-energy mode).

[0090] To illustrate, in Fig. 6 different combinations of operating states for the three switches S1, S2 and S3 of the exemplary embodiment of the Fig. Figure 5 shows the power levels indicated at the bottom, ranging from "Active ON" to "Off" and including three intermediate power levels designated as "Low Energy" (Weak / Medium / Strong), a "Weak ON" and a "Medium ON" (these would correspond to the partially on modes described above).

[0091] As shown by the Fig. As can be seen by way of example in Figure 6, the power level "Medium Low Energy" differs from the power level "High Low Energy," even though in both power levels one of the switches S1 and S2 is in diode mode and the other is switched off. Such differentiation is made possible precisely by the different design of the switches described above, e.g., with regard to their electrical conductivity. In this case, the first switch S1 has a higher conductivity than the second switch S2.

[0092] An operating voltage of 110 or 108, which is provided to the at least one memory cell 102 in low-energy mode, can accordingly be finely adjusted and adapted to the requirements of the at least one memory cell 102, e.g., of the memory array 100, by using several switches S1, S2, ... which may be designed differently.

[0093] In various embodiments, the requirements of at least one memory cell 102 can be determined during a test phase, e.g., the operating voltage required for data retention can be determined, and the conductive state of the first and / or the second switch S1, S2, and / or a combination of the power levels to be implemented can be set up or made so that the determined operating voltage is also ensured in low-energy mode.

[0094] Such flexibility can be advantageous because variations during the manufacturing of the semiconductor device can lead to memory cells 102 or memory arrays 100 with different characteristics. In particular, some memory arrays 100 may require a higher sustained voltage (VDDC-VSSC) (which is provided in low-power mode) than others. For example, one memory array 100 may require 0.6V to ensure the retention of the data stored in it, while another memory array 100 may only require 0.5V.

[0095] Setting the maintenance voltage for all storage arrays 100 according to the storage array 100 that requires the highest voltage would unnecessarily increase the energy consumption for some of the storage arrays 100, because the storage array 100 that actually requires a lower voltage is operated at an unnecessarily high voltage during low-energy mode (e.g., it could actually be operated at 0.5V, but 0.6V is used).

[0096] In various embodiments, a configurable power supply (i.e., from VDDC, VSSC, or both) is provided. The configuration, i.e., the adjustment of the maintenance voltage to the fluctuations of the manufacturing process, can be performed, for example, during production tests.

[0097] The adjustments or tuning can be carried out at the wafer level in various embodiments, i.e., in such a way that all chips on a wafer are provided with the same setting, but each wafer receives its own individual setting.

[0098] In various embodiments, the adjustment or tuning can be carried out at the chip level, i.e., in such a way that all memory arrays of a chip are provided with the same setting, but each chip receives its own setting.

[0099] In various embodiments, the adjustment or tuning can be carried out at the memory level, i.e., in such a way that each memory array of a chip is provided with its own setting.

[0100] In various embodiments, the energy consumption of the storage cell device 300 is reduced.

[0101] Reducing the required chip area and lowering energy consumption leads directly or indirectly (e.g., reduced energy consumption can lead to cost savings in chip packages, power supply devices and / or cooling devices) to a reduction in costs.

[0102] Furthermore, the ability to finely adjust the maintenance voltage after a test can increase the yield in production.

[0103] Fig. Figure 7 shows a flowchart of a method 700 for operating a storage cell device according to various embodiments.

[0104] Method 700 may include providing the memory cell device comprising at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic with a first sub-circuit (at 710).

[0105] Method 700 can further enable the first switch to be moved selectively by activating or deactivating the first sub-circuit into one of at least three operating states: an on state, an off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state (in 720).

[0106] The following is a summary of some examples.

[0107] Exemplary embodiment 1 is a memory cell device. The memory cell device can have at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic configured to selectively put the first switch into one of at least three operating states by activating or deactivating a first sub-circuit of the switch control logic: an on state, an off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0108] Exemplary embodiment 2 is a memory cell device according to exemplary embodiment 1, which further comprises a second switch connected between the at least one memory cell and the reference potential, wherein the switch control logic is further configured to selectively put the second switch into one of at least three operating states by activating or deactivating a second sub-circuit of the switch control logic: on state, off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0109] Exemplary embodiment 3 is a memory cell device according to exemplary embodiment 1 or 2, which further comprises a third switch connected between the at least one memory cell and the reference potential, wherein the switch control logic is further configured to selectively place the third switch in one of exactly two operating states: on state and off state.

[0110] Exemplary embodiment 4 is a storage cell device according to exemplary embodiment 2 or 3, wherein the first switch in the conductive state has a higher electrical conductivity than the second switch in the conductive state.

[0111] Exemplary embodiment 5 is a memory cell device according to one of the exemplary embodiments 1 to 4, wherein the first switch comprises a first field-effect transistor.

[0112] Exemplary embodiment 6 is a memory cell device according to exemplary embodiment 5, wherein the conductive state of the first field-effect transistor is a diode-mode state of the first field-effect transistor.

[0113] Exemplary embodiment 7 is a memory cell device according to one of the exemplary embodiments 2 to 6, wherein the second switch has a second field-effect transistor.

[0114] Exemplary embodiment 8 is a memory cell device according to exemplary embodiment 7, wherein the conductive state of the second field-effect transistor is a diode-mode state of the second field-effect transistor.

[0115] Exemplary embodiment 9 is a memory cell device according to exemplary embodiment 7 or 8, wherein the first field-effect transistor has a larger transistor width than the second field-effect transistor.

[0116] Exemplary embodiment 10 is a memory cell device according to one of the exemplary embodiments 7 to 9, wherein the first field-effect transistor has a lower threshold voltage than the second field-effect transistor.

[0117] Exemplary embodiment 11 is a memory cell device according to one of the exemplary embodiments 5 to 10, wherein the first field-effect transistor has a first gate, wherein the switch control logic has a first gate control circuit which is configured to connect the first gate to a positive voltage supply terminal in the on state, to connect the first gate to a ground terminal in the off state, and to connect the first gate to a virtual voltage supply terminal in the conducting state.

[0118] Exemplary embodiment 12 is a memory cell device according to exemplary embodiment 11, wherein the first field-effect transistor is an NFET transistor, and wherein the virtual voltage supply terminal is a ground terminal.

[0119] Exemplary embodiment 13 is a memory cell device according to one of the exemplary embodiments 5 to 10, wherein the first field-effect transistor has a first gate, wherein the switch control logic has a gate control circuit which is configured to connect the first gate to a ground terminal in the on state, to connect the first gate to a positive voltage supply terminal in the off state, and to connect the first gate to a virtual voltage supply terminal in the conducting state.

[0120] Exemplary embodiment 14 is a memory cell device according to exemplary embodiment 13, wherein the first field-effect transistor is a PFET transistor, and wherein the virtual voltage supply terminal is a positive voltage supply terminal.

[0121] Exemplary embodiment 15 is a memory cell device according to one of the exemplary embodiments 11 to 14, wherein the gate control circuit has a third field-effect transistor between the first gate and the positive voltage supply terminal.

[0122] Exemplary embodiment 16 is a memory cell device according to one of the exemplary embodiments 11 to 15, wherein the gate control circuit has a fourth field-effect transistor between the first gate and the ground terminal.

[0123] Exemplary embodiment 17 is a memory cell device according to one of the exemplary embodiments 11 to 16, wherein the gate control circuit has a fifth field-effect transistor between the first gate and the virtual voltage supply terminal.

[0124] Exemplary embodiment 18 is a storage cell device according to exemplary embodiment 2, wherein the switch control logic is configured to selectively put the storage cell device into one of at least three power levels by moving the first switch and the second switch into one of their three operating states: a fully-on state in which the first switch and the second switch are in the on state, a partial-power state in which at least one of the first switch and the second switch is in the conductive state, and a fully-off state in which the first switch and the second switch are in the off state.

[0125] Exemplary embodiment 19 is a storage cell device according to exemplary embodiment 18, wherein the at least three power stages further have a partial-on state in which the first switch is in the on state and the second switch is in the off state, or vice versa.

[0126] Exemplary embodiment 20 is a storage cell device according to exemplary embodiment 3, wherein the switch control logic is configured to selectively put the storage cell device into one of at least three power levels by setting the first switch and the second switch into one of their three operating states and the third switch into one of their two operating states: a fully-on state in which the first switch, the second switch and the third switch are in the on state, a partially-power state in which at least one of the first switch and the second switch is in the conducting state, and a fully-off state in which the first switch, the second switch and the third switch are in the off state.

[0127] Exemplary embodiment 21 is a storage cell device according to exemplary embodiment 20, wherein the at least three power stages further have a partial-on state in which at least one of the first, the second and the third switch is in the on state and at least one of the other two switches is in the off state.

[0128] Exemplary embodiment 22 is a memory cell device according to one of the exemplary embodiments 18 to 21, wherein the partial power state and / or the partial on state is configured such that the value of a voltage drop across the at least one memory cell is sufficiently high to ensure continuous data storage.

[0129] Exemplary embodiment 23 is a memory cell device according to exemplary embodiments 1 to 22, wherein the memory cell device forms a volatile data storage device.

[0130] Exemplary embodiment 24 is a memory cell device according to one of the exemplary embodiments 1 to 23, wherein the memory cell device forms an SRAM, DRAM, RRAM, MRAM, PC RAM, ROM or Flash data memory.

[0131] Exemplary embodiment 25 is a method for operating a storage cell device comprising at least one storage cell, a first switch connected between the at least one storage cell and a reference potential, and a switch control logic with a first sub-circuit, the method comprising setting the first switch optionally by activating or deactivating the first sub-circuit into one of at least three operating states: an on-state, an off-state, and a conductive state in which the electrical conductivity is lower than in the on-state and higher than in the off-state.

[0132] Exemplary embodiment 26 is a method according to exemplary embodiment 25, wherein the memory cell device further comprises a second switch connected between the at least one memory cell and the reference potential and a second sub-circuit in the switch control logic, the method further comprising setting the second switch optionally by activating or deactivating the second sub-circuit into one of at least three operating states: on state, off state, and a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state.

[0133] Embodiment 27 is a method according to embodiment 25 or 26, wherein the storage cell device further comprises a third switch connected between the at least one storage cell and the reference potential, the method further comprising: setting the third switch selectively into one of exactly two operating states: an on state and an off state.

[0134] Exemplary embodiment 28 is a method according to exemplary embodiment 26, further comprising setting the first switch and the second switch into each of its three operating states in order to selectively set the storage cell device into one of at least three power levels: a fully-on state in which the first switch and the second switch are in the on state, a partial-power state in which at least one of the first switch and the second switch is in the conductive state, and a fully-off state in which the first switch and the second switch are in the off state.

[0135] Embodiment 29 is a method according to embodiment 28, wherein the at least three power stages further have a partial-on state in which the first switch is in the on state and the second switch is in the off state, or vice versa.

[0136] Exemplary embodiment 30 is a method according to exemplary embodiment 27, further comprising setting the first switch and the second switch into one of their three operating states and the third switch into one of their two operating states in order to selectively set the storage cell device into one of at least three power levels: a fully-on state in which the first switch, the second switch and the third switch are in the on state, a partial-power state in which at least one of the first switch and the second switch is in the conductive state, and a fully-off state in which the first switch, the second switch and the third switch are in the off state.

[0137] Embodiment 31 is a method according to embodiment 30, wherein the at least three power stages further have a partial-on state in which at least one of the first, the second and the third switch is in the on state and at least one of the other two switches is in the off state.

[0138] Embodiment 32 is a method according to one of embodiments 28 to 31, further comprising placing the storage cell device in the fully-on state for active operation.

[0139] Embodiment 33 is a method according to one of embodiments 28 to 32, further comprising placing the storage cell device into the partial power state for standby operation.

[0140] Exemplary embodiment 34 is a method according to exemplary embodiment 29 or 31, furthermore, when moving the memory cell device from the completely off state to the completely on state, first moving the memory cell device from the completely off state to the partially on state, and subsequently moving the memory cell device from the partially on state to the completely on state.

Claims

[1] Storage cell arrangement (300), comprising: at least one memory cell (102); one between the at least one memory cell (102) and a reference potential (104 or 106) switched first switch (S1); a switch control logic (330) which is configured to selectively put the first switch (S1) into one of at least three operating states by activating or deactivating a first sub-circuit (330_1T) of the switch control logic (330): • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on-state and higher than in the off-state, further comprising: a second switch (S2) connected between the at least one memory cell (102) and the reference potential (104 or 106); wherein the switch control logic (330) is further configured to selectively place the second switch (S2) into one of at least three operating states by activating or deactivating a second sub-circuit (330_2T) of the switch control logic (330): • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state, wherein the first switch (S1) and the second switch (S2) are connected in parallel. [2] Storage cell arrangement (300) according to claim 1, further comprising: one between the at least one memory cell (102) and the reference potential (104 or 106) switched third switch (S3); wherein the switch control logic (330) is further configured to selectively place the third switch into one of exactly two operating states: • Power-on state; and • Off state. [3] Storage cell device (300) according to claim 2, wherein the first switch (S1) in the conductive state has a higher electrical conductivity than the second switch (S2) in the conductive state. [4] Memory cell device (300) according to any one of claims 1 to 3, wherein the first switch (S1) comprises a first field-effect transistor. [5] Memory cell device (300) according to claim 4, wherein the conducting state of the first field-effect transistor is a diode-mode state of the first field-effect transistor. [6] Memory cell device (300) according to any one of claims 1 to 5, wherein the second switch (S2) has a second field-effect transistor. [7] Memory cell device (300) according to claim 6, wherein the conducting state of the second field-effect transistor is a diode-mode state of the second field-effect transistor. [8] Memory cell device (300) according to claim 6 or 7, wherein the first field-effect transistor has a larger transistor width than the second field-effect transistor. [9] Memory cell device (300) according to any one of claims 6 to 8, wherein the first field-effect transistor has a lower threshold voltage than the second field-effect transistor. [10] Storage cell arrangement (300) according to any one of claims 4 to 9, where the first field-effect transistor has a first gate, wherein the switch control logic (330) has a first gate control circuit which is configured to connect the first gate to a positive voltage supply terminal in the on state, to connect the first gate to a ground terminal in the off state, and to connect the first gate to a virtual voltage supply terminal in the conducting state. [11] Storage cell device (300) according to claim 10, • where the first field-effect transistor is an NFET transistor; and • where the virtual power supply connection is a ground connection. [12] Storage cell arrangement (300) according to any one of claims 4 to 9, • wherein the first field-effect transistor has a first gate, • wherein the switch control logic (330) has a gate control circuit configured to connect the first gate to an earth terminal in the on state, to connect the first gate to a positive voltage supply terminal in the off state, and to connect the first gate to a virtual voltage supply terminal in the conducting state. [13] Storage cell device (300) according to claim 12, • where the first field-effect transistor is a PFET transistor; and • where the virtual power supply connection is a positive power supply connection. [14] Memory cell device (300) according to one of claims 10 to 13, wherein the gate control circuit has a third field-effect transistor between the first gate and the positive voltage supply terminal. [15] Memory cell device (300) according to any one of claims 10 to 14, wherein the gate control circuit has a fourth field-effect transistor between the first gate and the ground terminal. [16] Memory cell device (300) according to any one of claims 10 to 15, wherein the gate control circuit has a fifth field-effect transistor between the first gate and the virtual power supply terminal. [17] Memory cell device (300) according to claim 1, wherein the switch control logic (330) is configured to selectively switch the memory cell device into one of at least three power levels by moving the first switch (S1) and the second switch (S2) into one of their three operating states: • a fully-on state in which the first switch (S1) and the second switch (S2) are in the on state; • a partial power state in which at least one of the first switch (S1) and the second switch (S2) is in the conductive state; and • a completely off state in which the first switch (S1) and the second switch (S2) are in the off state. [18] Storage cell device (300) according to claim 17, wherein the at least three power levels further comprise a partial-on state in which the first switch (S1) is in the on state and the second switch (S2) is in the off state, or vice versa. [19] Memory cell device (300) according to claim 2, wherein the switch control logic (330) is configured to selectively put the memory cell device (300) into one of at least three power levels by setting the first switch (S1) and the second switch into one of its three operating states and the third switch into one of its two operating states: • a fully-on state in which the first switch (S1), the second switch (S2) and the third switch (S3) are in the on state; • a partial power state in which at least one of the first switch (S1) and the second switch (S2) is in the conductive state; and • a completely off state in which the first switch (S1), the second switch (S2) and the third switch (S3) are in the off state. [20] Storage cell device (300) according to claim 19, wherein the at least three power levels further comprise a partial-on state in which at least one of the first, the second and the third switch (S3) is in the on state and at least one of the other two switches is in the off state. [21] Memory cell arrangement (300) according to one of claims 17 to 20, wherein the partial power state and / or the partial on state is configured such that a value of a voltage drop across the at least one memory cell (102) is sufficiently high to ensure continuous data storage. [22] Memory cell arrangement (300) according to any one of claims 1 to 21, wherein the memory cell arrangement (300) forms a volatile data storage device. [23] Memory cell arrangement (300) according to any one of claims 1 to 22, wherein the memory cell arrangement forms an SRAM, DRAM, RRAM, MRAM, PC RAM, ROM or Flash data storage. [24] Method for operating a memory cell device comprising at least one memory cell, a first switch connected between the at least one memory cell and a reference potential and a switch control logic with a first sub-circuit, comprising the method: Moving the first switch into one of at least three operating states, either by activating or deactivating the first sub-circuit: • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state (710, 720), wherein the memory cell device further comprises a second switch connected between the at least one memory cell and the reference potential and a second sub-circuit in the switch control logic, the method further comprising: Moving the second switch into one of at least three operating states, either by activating or deactivating the second sub-circuit: • On state; • Off state; and • a conductive state in which the electrical conductivity is lower than in the on state and higher than in the off state, with the first switch and the second switch connected in parallel. [25] Method for operating a storage cell device according to claim 24, wherein the storage cell device further comprises a third switch connected between the at least one storage cell and the reference potential, the method further comprising: Setting the third switch to one of exactly two operating states: • Power-on state; and • Off state. [26] Method for operating a storage cell device according to claim 24, further comprising: Moving the first switch and the second switch to one of their three operating states each, in order to selectively move the storage cell device to one of at least three power levels: • a fully-on state in which the first switch and the second switch are in the on state; • a partial power state in which at least one of the first switch and the second switch is in the conductive state; and • a completely off state, in which the first switch and the second switch are in the off state. [27] Method for operating a storage cell device according to claim 26, wherein the at least three power levels further comprise: • a partially on state in which the first switch is in the on state and the second switch is in the off state, or vice versa. [28] Method for operating a storage cell device according to claim 25, further comprising: Setting the first switch and the second switch to one of their three operating states each, and the third switch to one of its two operating states, in order to selectively set the memory cell device to one of at least three power levels: • a fully-on state in which the first switch, the second switch and the third switch are in the on state; • a partial power state in which at least one of the first switch and the second switch is in the conductive state; and • a completely off state in which the first switch, the second switch and the third switch are in the off state. [29] Method for operating a storage cell device according to claim 28, wherein the at least three power levels further comprise: • a partially on state in which at least one of the first, second and third switches is in the on state and at least one of the other two switches is in the off state. [30] Method for operating a storage cell device according to any one of claims 26 to 29, further comprising: Putting the memory cell assembly into the fully-on state for active operation. [31] Method for operating a storage cell device according to any one of claims 26 to 30, further comprising: Putting the memory cell device into partial power mode for standby operation. [32] Method for operating a storage cell device according to one of claims 27 or 29, further comprising: When moving the memory cell device from the fully off state to the fully on state, first move the memory cell device from the fully off state to the partially on state, and subsequently move the memory cell device from the partially on state to the fully on state.

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