SEMICONDUCTOR PACKAGE

Abstract

Package that includes: a substrate (120) comprising: an insulation layer (100), first conductor tracks (108) on a first side of the insulation layer (100) and second conductive traces (112) on a second side of the insulating layer (100) opposite the first side of the insulating layer (100); and conductive pins (110) extending through the insulation layer (100) and the vertically interconnecting the first and second conductor tracks (108, 112); a first die (126) disposed within the substrate (120); a redistribution structure (140) over the substrate (120) and the first die (126), wherein the redistribution structure (140) is adjacent to the substrate (120), wherein the redistribution structure (140) and the substrate (120) together form a first package (101); an encapsulated device (180) over the redistribution structure (140), the redistribution structure (140) coupling the first die (126) to the encapsulated device (180); and a ring structure (194) attached to the redistribution structure (140), the ring structure (194) surrounding the encapsulated device (180); wherein the insulation layer has a cavity (118), wherein a portion of the insulation layer (100) is present along a bottom of the cavity (118) and wherein the first die (126) is disposed within the cavity (118).

Description

GENERAL STATE OF THE ART

[0001] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components and thus more functions to be integrated into a given area. Integrated circuits with high functionality require many input / output pads. However, small packages may be desirable for applications where miniaturization is important.

[0002] Integrated fan-out (InFO) package technology is enjoying increasing popularity, particularly when combined with wafer-level packaging (WLP) technology. InFO packages can comprise integrated circuits housed in packages that typically include a redistribution layer (RDL) or a post-passivation interconnect, which is used to fan out wiring for the package's contact pads so that electrical contacts can be made on a larger pitch than the integrated circuit's contact pads. The resulting package structures provide high functional density at relatively low cost and high-performance packages.

[0003] US 2015 / 0 061 139 A1 discloses a method for forming a semiconductor device, in which two overlapping recesses are formed on opposite sides of a dielectric substrate. A die is arranged in each of the recesses, so that the two dies are arranged in a back-to-back arrangement with respect to each other.

[0004] US 2014 / 0 097 532 A1 describes a semiconductor device in which a die is surrounded by a heat dissipation ring structure, with no conductive elements extending between opposite sides of the heat dissipation ring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It should be noted that various features are not to scale, in accordance with standard industry practice. Indeed, the dimensions of various features may have been arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 illustrates a core substrate according to some embodiments. Fig. 2 illustrates formation of openings in the core substrate according to some embodiments. Fig. 3 illustrates formation of conductive traces and conductive pins in the core substrate according to some embodiments. Fig. 4 illustrates formation of a dielectric layer and a protective layer over the core substrate according to some embodiments. Fig. 5 illustrates formation of a cavity in the core substrate according to some embodiments. Fig. 6 illustrates bonding the substrate to a carrier according to some embodiments. Fig. 7A illustrates attachment of a first die within the cavity according to some embodiments. Fig. 7B illustrates a multilayer ceramic capacitor according to some embodiments. Fig. 8 illustrates formation of a fill material surrounding the passive component, according to some embodiments. Fig. 9 to 15 illustrate formation of a front-side redistribution structure over the substrate and the passive device according to some embodiments. Fig. 16 illustrates formation of openings in the front-side redistribution structure according to some embodiments. Fig. 17A illustrates formation of conductive connectors on the front-side redistribution structure according to some embodiments. Fig. 17B and Fig. 17C illustrate first packages formed over a carrier, according to some embodiments. Fig. 18 illustrates a detachment of the carrier according to some embodiments. Fig. 19 illustrates bonding of semiconductor devices housed in a package according to some embodiments. Fig. 20 illustrates attachment of a ring structure according to some embodiments. Fig. 21 illustrates formation of conductive connectors on a backside of the substrate according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for carrying out various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Additionally, reference numerals and / or letters may be repeated throughout the various examples in the present disclosure. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms describing a spatial relationship, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Terms describing a spatial relationship are intended to encompass various orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the terms for spatial relationships used herein may also be interpreted accordingly.

[0008] Various embodiments relate to semiconductor devices housed in a package and methods of forming them. The semiconductor devices housed in the package may be system on integrated substrate (SoIP) packages, system-in-packages (SiPs), or the like. A cavity may be formed in a core substrate, and an electronic component, such as a multilayer ceramic capacitor (MLCC), an integrated passive device (IPD), an integrated voltage regulator (IVR), a static random access memory (SRAM), or the like, may be attached to the core substrate in the cavity.Redistribution layers (RDLs) can be formed over the core substrate and the electronic component, and an electronic device, such as a chip-on-wafer (CoW), an integrated fan-out (InFO) package, a die, or other package, can be attached to the RDLs. Embedding the electronic component in the core substrate shortens the distance between the electronic component and the electronic device, thereby reducing the voltage drop between the electronic component and the electronic device and improving the power integrity and overall performance of the packaged semiconductor device.

[0009] First, with reference to Fig. 1, a substrate 104 is shown comprising an insulating layer 100 with conductive layers 102 on both sides of the insulating layer 100, according to some embodiments. The substrate 104 may be a core substrate. In some embodiments, the substrate 104 is a double-sided copper clad laminate (CCL). The insulating layer 100 may be an organic substrate, a ceramic substrate, a prepreg, an Ajinomoto Build-up Film (ABF), paper, fiberglass, fiberglass mat, other insulating materials, or combinations thereof. The conductive layers 102 may be one or more layers of copper, nickel, aluminum, other conductive materials, or a combination thereof, laminated or formed on opposite sides of the insulating layer 100.

[0010] With reference to Fig. 2, openings 106 are formed in the substrate 104. In some embodiments, the openings 106 are formed by laser drilling. Other processes, such as mechanical drilling, etching, or the like, may also be used. The openings 106 may have a rectangular, circular, or other shape in a top-down view.

[0011] With reference to Fig. 3, the openings 106 (see Fig. 2) to form conductive pins 110, first conductive traces 108, and second conductive traces 112, according to some embodiments. Conductive traces, such as first conductive traces 108 and second conductive traces 112, may be used to form routing lines for redistributing electrical signals or as die connector pads to which die connectors may be attached. Prior to depositing a conductive material within openings 106, a surface preparation process may be performed. The surface preparation process may include cleaning the exposed surfaces of substrate 104 (e.g., surfaces of conductive layers 102 and surfaces of insulation layer 100 within openings 106) with one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralizing alkaline solution, water rinse, etc.) to remove or reduce dirt, oils, and / or native oxide films.A desmearing process may be performed to clean the area near the openings 106, which may be contaminated with the material of the insulating layer 100 that was removed to form the openings 106. Desmearing may be accomplished mechanically (e.g., blasting with a fine abrasive material in a wet aqueous mixture), chemically (e.g., rinsing with a combination of organic solvents, permanganate, etc.), or by a combination of mechanical and chemical desmearing. After cleaning, treatment with a chemical pretreatment agent may be used to facilitate the adsorption of an activating agent used during subsequent electroless plating.In some embodiments, the pretreatment step may be followed by micro-etching the conductive layers 102 to micro-roughen the conductive surfaces of the conductive layers 102 for better bonding between the conductive layers 102 and the later deposited conductive material.

[0012] Forming the conductive pins 110, the first conductive traces 108, and the second conductive traces 112 may include forming a patterned mask layer and selectively depositing conductive materials (e.g., copper, other metals, metal alloys, or the like) in the openings in the patterned mask layer using an electroless metal plating technique. The patterned mask layer may be formed by coating the surface with a photoresist layer, exposing the photoresist layer to an optical pattern, and developing the exposed photoresist layer to form openings in the photoresist layer that define a pattern of the region where conductive material can be selectively deposited.

[0013] After forming the first conductive lines 108 and the second conductive lines 112, the patterned mask layer (e.g., the photoresist) may be stripped away. Portions of the conductive layers 102 that were covered by the patterned mask layer may be removed using a suitable etching process. The removal of the unwanted portions of the conductive layers 102 prevents unwanted electrical short circuits between the conductive features formed in the areas exposed by the patterned mask layer. The conductive pins 110, the first conductive lines 108, and the second conductive lines 112 may be formed on both sides of the substrate 104 in the manner described above. Fig. The cross-sectional view illustrated in Figure 3 shows the state of the substrate 104 after the conductive layers 102 have been etched as previously described.

[0014] As discussed in more detail below, the substrate 104 will act as a base for forming a cavity-containing core substrate 120 (in Fig. 3 not illustrated, but in Fig. 5). In Fig. 3, first conductor tracks 108 are formed on one side of the insulation layer 100, in which a cavity 118 (in Fig. 3 not illustrated, but in Fig. 5) during subsequent processing steps. According to some embodiments, the first conductive traces 108 may be omitted from the region in which the cavity may subsequently be formed, in this example, e.g., the region between the innermost conductive pins 110.

[0015] Although not illustrated in this example, it should be understood that the process of using a metal-clad laminate, forming openings extending through the metal-clad laminate, forming a patterned conductive layer (e.g., using electroless deposition or electroplating or the like), and removing unwanted metal cladding can be repeatedly performed to vertically stack multiple alternating layers of insulating material and conductive traces with conductive pins for vertically connecting adjacent layers of conductive traces.

[0016] With reference to Fig. 4, a dielectric layer 114 and a protective layer 116 are formed over the first conductive lines 108 and the second conductive lines 112, respectively, and the substrate 104. In some embodiments, the dielectric layer 114 is formed from a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithography mask. The dielectric layer 114 may be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof. The dielectric layer 114 is patterned to form openings that expose portions of the first conductive lines 108. Patterning may be performed by exposing the dielectric layer 114 to light and developing the dielectric layer 114 if the dielectric layer 114 is a photosensitive material.The dielectric layer 114 may also be formed from materials that are not photosensitive, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. In embodiments where the dielectric layer 114 is formed from materials that are not photosensitive, the dielectric layer 114 may be patterned by etching with a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask.

[0017] In various embodiments, the protective layer 116 may be a solder resist or the like formed over the second conductive lines 112 to protect portions of the insulating layer 100 from external damage. The protective layer 116 may be patterned to form openings that expose portions of the second conductive lines 112. In embodiments where the protective layer 116 is formed from a photosensitive material, patterning may be performed by exposing the protective layer 116 to light and developing the protective layer 116. In embodiments where the protective layer 116 is formed from materials that are not photosensitive, the protective layer 116 may be patterned by etching with a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask.The openings exposing the second conductive traces 112 may be used as die connector pads to which conductive connectors 198 (in . Fig. 4 not illustrated, but in Fig. 21 shown).

[0018] In Fig. 5, a cavity 118 is formed by removing a portion of the insulating layer 100 according to some embodiments. Removing the portion of the insulating layer 100 does not affect the first conductive traces 108, which are located on the same side of the insulating layer 100 that is recessed by the removal process. As previously described with reference to Fig. 3, the patterned mask used to form the first conductive lines 108 may be designed to preclude the formation of the first conductive lines 108 over a portion of the insulation layer 100 where the cavity 118 is formed. The removal of material to form the cavity 118 may be performed by a machining process (Computer Numeric Control - CNC) in which the material is removed by mechanical drilling. As shown in Fig. 5, the resulting structure is a cavity substrate 120. The insulation layer 100 of the cavity substrate 120 may have a thickness T1 of about 25 µm to about 2000 µm, such as about 250 µm or about 500 µm. The cavity 118 may have a depth of about 10 µm to about 1000 µm, such as 70 µm or about 400 µm. The cavity 118 may have an area of ​​about 1 mm by 1 mm to about 20 mm by 20 mm, such as about 1.5 mm by 1.5 mm or about 5.0 mm by 4.0 mm. In some embodiments, a portion of the insulating layer 100 may remain along the bottom of the cavity 118 and may have a thickness of about 20 µm to about 1600 µm, such as about 30 µm or about 800 µm. Other processes may also be used to form the cavity 118, such as laser drilling, etching, and / or the like.

[0019] In Fig. 6, the cavity substrate 120 is attached to a carrier substrate 122 using a release layer 124 according to some embodiments. As shown in Fig. 6, the cavity substrate 120 may be attached to the carrier substrate 122 using the release layer 124 such that the cavity 118 is opposite the release layer 124. The carrier substrate 122 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The release layer 124 may be a polymer-based material, an epoxy-based thermal release material such as a light-to-heat conversion (LTHC) release coating, or an ultraviolet (UV) adhesive (e.g., an adhesive that loses its adhesive properties when exposed to UV light). The release layer 124 may aid in the removal of the carrier substrate 122 during subsequent processing. The release layer 124 may be removed along with the carrier substrate 122 during subsequent processing.

[0020] In Fig. 7A, according to some embodiments, a first die 126 is placed inside the cavity 118 (in Fig. 6). The first die 126 may be placed in the cavity 118 using a pick-and-place (PnP) tool. The first die 126 may be a passive device, such as a multilayer ceramic chip capacitor (MLCC); an integrated passive device (IPD); an integrated voltage regulator (IVR), the like, or a combination thereof; or an active device, such as a memory die (e.g., a static random-access memory (SRAM) die, a dynamic random-access memory (DRAM) die, a high bandwidth memory (HBM) die, or the like), a logic chip, an analog chip, a microelectromechanical system (MEMS) chip, a radio frequency (RF) chip, the like, or a combination thereof. In some embodiments, the first die 126 is adhered to the insulation layer 100 by an adhesive 128.Although . Fig. 7A illustrates only a first die 126 being placed in the cavity 118, it will be understood that multiple dies or devices may also be placed in the cavity 118 of the cavity substrate 120. For example, in some embodiments, the first die 126 may be multiple devices placed laterally adjacent to one another and / or stacked on top of one another, where the multiple devices may have the same or different sizes. Before being placed on the cavity substrate 120, the first die 126 may be processed according to applicable manufacturing processes to form the corresponding device structure. The first die 126 may include connection terminals 130 (e.g., aluminum pads, copper pads, or the like) to which external connections are made.The first die 126 may have a height of about 30 µm to about 350 µm, a length of about 0.5 mm to about 0.8 mm, and a width of about 0.5 mm to about 0.8 mm.

[0021] The adhesive 128 may be applied to a backside of the first die 126 and may attach the first die 126 to the insulation layer 100. The adhesive 128 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 128 may be applied to the backside of the first die 126 prior to singulation of the first die 126. The first die 126 may be singulated, such as by sawing or dicing, and adhered to the insulation layer 100 by the adhesive 128 using, for example, a PnP tool. In some embodiments, the adhesive 128 may be applied to the cavity substrate 120 prior to placement of the first die 126 in the cavity 118.

[0022] Fig. Figure 7B illustrates an MLCC 220 that can be used as the first die 126. As in Fig. As illustrated in Figure 7B, the MLCC 220 includes electrodes 226 sandwiched between layers of ceramic 224. The MLCC 220 further includes connection terminals 222 for external connection.

[0023] In Fig. 8, a fill material 123 is formed between sidewalls of the first die 126 and the cavity substrate 120 according to some embodiments. The fill material 132 may be formed by a capillary flow process after the first die 126 is attached, or may be formed by a suitable deposition process before the first die 126 is attached. The fill material 132 may be a material such as a molding compound, an epoxy, a filler material, a molding underfill (MUF), a resin, or the like. The fill material 132 may reduce stress between the first die 126 and the cavity substrate 120 and may help secure the first die 126 in the cavity 118. As shown in Fig. 8, upper surfaces of the fill material 132 may be concave; however, in some embodiments, the upper surfaces of the fill material 132 may be convex or planar.

[0024] Fig. 9 to 15 illustrate the formation of a front-side redistribution structure 140 (in Fig. 15) over the connection terminals 130 of the first die 126 and the first conductive traces 108 of the cavity substrate 120, according to some embodiments. The front-side redistribution structure 140 comprises a vertical stack of alternating layers of dielectric and conductive traces. Each layer of conductive traces is separated from vertically adjacent layers of conductive traces by a dielectric layer. The conductive traces extend through underlying dielectric layers to form conductive vias used to interconnect vertically adjacent conductive traces. The front-side redistribution structure 140 and the cavity substrate 120 together form a first package 101 (in Fig. 15 shown).

[0025] In Fig. 9, a dielectric layer 134 is formed over the cavity substrate 120, the fill material 132, and the first die 126. In some embodiments, the dielectric layer 134 is formed from a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like, that can be patterned using a lithography mask. The dielectric layer 134 may be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof. The dielectric layer 134 is patterned to form openings that expose portions of the connection terminals 130 and the first conductive lines 108. Patterning may be performed by exposing the dielectric layer 134 to light if the dielectric layer 134 is a photosensitive material.The dielectric layer 134 may also be formed from materials that are not photosensitive, such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. In embodiments where the dielectric layer 134 is formed from materials that are not photosensitive, the dielectric layer 134 may be patterned by etching with a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask.

[0026] In Fig. 10, a metallization structure 136 is formed on and extending through the dielectric layer 134. As an example of the formation of the metallization structure 136, a seed layer (not separately illustrated) is formed over the dielectric layer 134. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD), CVD, or the like. A photoresist (not separately illustrated) is then formed and patterned over the seed layer.The photoresist may be formed by spin coating or the like, may be exposed to patterned light or another patterned energy source, and may be exposed to a developer to remove exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the metallization pattern 136. The patterning forms openings through the photoresist to expose the seed layer. A conductive material (not separately illustrated) is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating, electroless plating, or the like. The conductive material may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed.The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization structure 136. The metallization structure 136 includes conductive traces formed along the top surface of the dielectric layer 134 and conductive vias through the dielectric layer 134. The vias electrically and physically connect the conductive traces of the metallization structure 136 to the metal structure directly beneath the dielectric layer 134 (e.g., the first conductive traces 108 and the connection terminals 130).

[0027] The method for forming the dielectric layer 134 (referring to Fig. 9) and the conductive traces and vias of the metallization structure 136 (with reference to Fig. 10) is described purely by way of example. It will be understood that the processes for forming the dielectric layer 134 and the metallization structure 136 may be varied based on the design specifications, e.g., the desired minimum dimensions of the structures. For example, in some embodiments, a damascene process (e.g., a single or dual damascene process) may be used. The front-side redistribution structure 140 may be constructed by vertically stacking additional dielectric layers and metallization structures.

[0028] Fig. 11 illustrates additional dielectric layers 138, 144, and 148 formed over a top surface of the dielectric layer 134 and the metallization structure 136. Also in Fig. 11 illustrates the metallization structures 142, 146, and 150. The metallization structures 142, 146, and 150 include conductive traces formed along the upper surfaces of the respective dielectric layers 138, 144, and 148, and conductive vias extending through the dielectric layers 138, 144, and 148. The vias of the metallization structures 142, 146, and 150 electrically and physically connect the conductive traces of the metallization structures 142, 146, and 150 to the corresponding metallization structures directly beneath the respective dielectric layers 138, 144, and 148 (e.g., the respective metallization structures 136, 142, and 146).Processes, techniques, and materials similar to those previously described with reference to dielectric layer 134 and metallization structure 136 may be repeated to form dielectric layers 138, 144, and 148 and metallization structures 142, 146, and 150.

[0029] In Fig. 12, conductive pillars 152 are formed on the metallization structure 150. As an example of the formation of the conductive pillars 152, a seed layer (not separately illustrated) is formed over the dielectric layer 148 and the metallization structure 150. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, CVD, or the like. Then, a photoresist (not separately illustrated) is formed and patterned over the seed layer.The photoresist may be formed by spin coating or the like, may be exposed to patterned light or another patterned energy source, and may be exposed to a developer to remove exposed or unexposed portions of the photoresist. The pattern of the photoresist corresponds to the conductive pillars 152. The patterning forms openings through the photoresist to expose the seed layer. A conductive material (not separately illustrated) is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating, electroless plating, or the like. The conductive material may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed.The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the conductive pillars 152. The conductive pillars 152 are electrically and physically connected to the metallization structure 150.

[0030] Now with reference to Fig. 13, the conductive pillars 152 may be embedded in an insulating layer 154 by, for example, laminating a build-up film such as ABF, or a prepreg, or the like, and using an etch-back or planarization process such as CMP, grinding, or the like to expose upper surfaces of the conductive pillars 152. In some embodiments, the insulating layer 154 may be applied as a liquid molding compound that is molded onto the dielectric layer 148 and the metallization structure 150 and surrounds the conductive pillars 152.

[0031] In Fig. 14, conductive traces 156 are formed over the conductive pillars 152 and the insulation layer 154. The conductive traces 156 may be formed using processes, techniques, and materials similar to those previously described with reference to the formation of the metallization structure 136, as in Fig. 10, wherein a seed layer is deposited, a patterned mask is formed over the seed layer, a plating process is performed to form the metallization structure, the patterned mask is removed, and unused portions of the seed layer are removed.

[0032] In Fig. 15, a dielectric layer 158, conductive traces 160, conductive pillars 162, an insulating layer 164, conductive traces 166, and under-bump metallizations (UBMs) 168 are formed over the conductive traces 156 and the insulating layer 154. The dielectric layer 158 may be formed using processes, techniques, and materials similar to those previously described with reference to forming the dielectric layer 134, as in Fig. 9. The conductive traces 160 and 166 and the conductive pillars 162 may be formed using processes, techniques, and materials similar to those previously described with reference to the formation of the metallization structure 136, as in Fig. 10, wherein a seed layer is deposited, a patterned mask is formed over the seed layer, a plating process is performed to form the metallization structure, the patterned mask is removed, and unused portions of the seed layer are removed. Although this is Fig. 15, conductive traces may be formed that extend through the dielectric layer 158 and electrically connect the conductive traces 160 to the conductive traces 156. The insulating layer 164 may be formed using processes, techniques, and materials similar to those previously described with reference to forming the insulating layer 154, as shown in Fig. 13 illustrates.

[0033] The UBMs 168 may be formed over the insulation layer 164 and the conductive pillars 162. The UBMs 168 include solderable metal surfaces that serve as an interface between subsequently formed solder bumps (e.g., conductive connectors 174 formed in Fig. 17A) and the front redistribution structure 140. As shown in Fig. 15, the UBMs 168 may be electrically and physically connected to the conductive pillars 162. The UBMs 168 may be formed using processes, techniques, and materials similar to those used to form the metallization structure 136 shown in Fig. 10. The dielectric layer 170 may then be formed over the insulation layer 164, the conductive traces 166, and the UBMs 168 using processes, techniques, and materials similar to those previously described with reference to forming the dielectric layer 134, as shown in Fig. 9 illustrates.

[0034] More or fewer dielectric layers, insulation layers, metallization structures, conductive traces, and conductive pillars may be formed in the front-side redistribution structure 140. In some embodiments, the front-side redistribution structure 140 may include from 1 to 10 dielectric layers / insulation layers; however, the front-side redistribution structure 140 may be optional and may not be included in some embodiments. If fewer dielectric layers and metallization structures are to be formed, previously discussed steps and processes may be omitted. If more dielectric layers and metallization structures are to be formed, previously discussed steps and processes may be repeated. Each of the dielectric layers 134, 138, 144, 148, 158 and 170 and each of the insulating layers 154 and 164 may have a thickness of about 5 µm to about 100 µm, such as about 30 µm.

[0035] In the previously described embodiment, two insulation layers 154 and 164 are included in the front-side redistribution structure 140. The insulation layers 154 and 164 may be formed from a molding material having a lower impedance than the dielectric materials used to form the dielectric layers 134, 138, 144, 148, 158, and 170. As such, the insulation layers 154 and 164 may be included in the front-side redistribution structure 140 to control the impedance of the front-side redistribution structure 140 and to tune the impedance of the front-side redistribution structure to a desired value. For example, the impedance of the front-side redistribution structure 140, which includes the insulation layers 154 and 164, may be between about 90 Ω and about 100 Ω, such as about 100 Ω.

[0036] In Fig. 16, the dielectric layer 170 is patterned to form openings 172 that expose portions of the UBMs 168. Patterning may be performed by exposing the dielectric layer 170 to light if the dielectric layer 170 is a photosensitive material. In embodiments where the dielectric layer 170 is formed from materials that are not photosensitive, the dielectric layer 170 may be patterned by etching with a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask.

[0037] In Fig. 17A, conductive interconnects 174 are formed on the UBMs 168. The conductive interconnects 174 may be ball grid array (BGA) interconnects, solder balls, conductive pillars, controlled collapse chip connection (C4) contact bumps, microbumps, contact bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. The conductive interconnects 174 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 174 are formed by initially forming a layer of solder by a process such as evaporation, electroplating, printing, solder delivery, ball placement, or the like over the structure of Fig. 16. After the layer of solder is formed, reflow may be performed to form the solder material into the desired bump shapes. In another embodiment, the conductive interconnects 174 are conductive pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The conductive interconnects 174 may be solder-free and may have substantially vertical sidewalls. In some embodiments, a metal capping layer (not separately illustrated) is formed on top of the conductive pillars. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0038] A plurality of first packages 101 may be formed on a single carrier substrate 122. As shown in Fig. 17B, ​​first packages 101 may have rectangular shapes, the carrier substrate 122 may have a round shape, such as a circular shape, and the carrier substrate 122 may be referred to as a wafer. As in Fig. 17C, first packages 101 may have rectangular shapes, the carrier substrate 122 may have a rectangular shape, and the carrier substrate 122 may be referred to as an array. The first packages 101 may be singulated from one another, such as by sawing, dicing, or the like. The first packages 101 may be singulated before removing the carrier substrate 122. Although in Fig. 17B four first packages 101 are illustrated and in Fig. 17C illustrates nine first packages 101, any number of first packages 101 may be formed on the carrier substrate 122, such as from a single first package 101 to thousands of first packages 101.

[0039] In Fig. 18, according to some embodiments, a carrier substrate stripping process is performed to detach (peel off) the carrier substrate 122 from the protective layer 116 of the cavity substrate 120. In embodiments where the release layer 124 is a photosensitive adhesive, the stripping may be performed by projecting a light, such as a laser light or a UV light, onto the release layer 124 such that the release layer 124 decomposes and the carrier substrate 122 may be removed. A cleaning process may be performed to remove residues of the release layer 124 from the protective layer 116. The stripping of the carrier substrate 122 exposes the protective layer 116 and the openings therein.

[0040] In Fig. 19, packaged semiconductor devices 180 may be bonded to the conductive connectors 174. The packaged semiconductor devices 180 may be disposed over the front-side redistribution structure 140, for example, by a pick-and-place machine (not separately illustrated), according to one embodiment. However, any other alternative method for disposing the packaged semiconductor devices 180 on the front-side redistribution structure 140 may be used.

[0041] In one embodiment, the packaged semiconductor devices 180 may include a processor die 182 (e.g., an xPU), such as a central processing unit (CPU), a micro control unit (MCU), a graphics processing unit (GPU), an application processor (AP), or the like. The packaged semiconductor devices 180 may also include additional dies 184, such as a memory die (e.g., dynamic random-access memory (DRAM) die, a wide input / output (I / O) die, a magnetic random-access memory (MRAM) die, a resistive random-access memory (RRAM) die, a NAND die, a static random-access memory (SRAM) die, or the like), a memory cube (e.g.,a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), or the like), a high data rate transceiver die, an I / O interface die, an Integrated Passive Device (IPD) die, a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a Micro-Electro-Mechanical-System (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front-end die (e.g., an Analog Front-End (AFE) die), a monolithic heterogeneous 3D chiplet stacking die, the like, or a combination thereof. The processor die 182 and the additional dies 184 may be connected via a combination of HMC interconnects, through-silicon vias (TSVs), and micro-bumps and may be embedded in an encapsulation material 186.In some embodiments, the packaged semiconductor devices 180 may be a single chip-on-wafer (CoW) device, a system-on-chip (SoC) device, an integrated fan-out (InFO) device, a single die, or a package comprising one or more dies. External contacts of the packaged semiconductor devices 180 may be deposited on first surfaces of the packaged semiconductor devices 180 opposite to thinned second backside surfaces of the packaged semiconductor devices 180.

[0042] Furthermore, the packaged semiconductor devices 180 may include an integrated fan-out (InFO) structure 188 with external contacts 190. The InFO structure 188 may include a plurality of dielectric layers and redistribution layers (RDLs) for interconnecting the external contacts of the packaged semiconductor devices 180 disposed on a first side of the InFO structure 188 with the external contacts 190 disposed on a second side of the InFO structure 188 opposite the first side of the InFO structure 188.

[0043] In one embodiment, the external contacts 190 may be, for example, conductive pillars, such as copper pillars or copper posts. In some embodiments, the external contacts 190 may be solder bumps, copper bumps, or other suitable external contacts 190 that may be fabricated to provide electrical connection from the packaged semiconductor devices 180 to other external devices through, for example, the conductive connectors 174 and the front-side redistribution structure 140. All such external contacts are intended to be fully encompassed within the scope of the embodiments.

[0044] As in Fig. As further illustrated in Figure 19, in one embodiment, the packaged semiconductor devices 180 may be arranged over the front-side redistribution structure 140 such that the external contacts 190 of the packaged semiconductor devices 180 are aligned and placed in contact with the conductive connectors 174 on the front-side redistribution structure 140. After being arranged, a bonding procedure may be performed to bond the packaged semiconductor devices 180 to the front-side redistribution structure 140. The external contacts may be bonded to the conductive connectors 174 using metal-to-metal bonding, solder bonding, or the like.

[0045] A fill material 192 may be formed in openings between the InFO structure 188 and the front-side redistribution structure 140 and surrounding the conductive connectors 174 and the external contacts 170. The fill material 192 may be formed by a capillary fill process after the packaged semiconductor devices 180 are attached. In another embodiment, the fill material 192 may be provided by a suitable deposition process before the packaged semiconductor devices 180 are attached.

[0046] Fig. 19 illustrates that the packaged semiconductor devices 180 are connected to the first die 126 through the front-side redistribution structure 140, the conductive interconnects 174, and the InFO structure 188. Disposing the first die 126 in the cavity 118 of the cavity substrate 120 enables the reduction of the distance between the first die 126 and the packaged semiconductor devices 180. For example, a distance between the first die 126 and the packaged semiconductor devices 180 may be less than about 0.3 mm or from about 0.1 mm to about 0.5 mm. In contrast, alternative package structures may have a distance between a first die 126 and a packaged semiconductor device 180 of greater than about 10 mm.Reducing this distance reduces the voltage drop between the first die 126 and the packaged semiconductor devices 180, thereby improving the power integrity and performance of the packaged semiconductor device (e.g., the SoIS 200 described below with reference to FIG. Fig. 21), which includes the first die 126 and the semiconductor devices 180 housed in a package.

[0047] In Fig. 20, a ring structure 194 is attached to the front-side redistribution structure 140, surrounding the packaged semiconductor devices 180. The ring structure 194 may be attached to protect the packaged semiconductor devices 180, to enhance the stability of the first package 101, and to dissipate heat from the packaged semiconductor devices 180 and the first package 101. The ring structure 194 may be formed from a material having high thermal conductivity, such as steel, stainless steel, copper, aluminum, combinations thereof, or the like. In some embodiments, the ring structure 194 may be a metal coated with another metal, such as gold. In various embodiments, the ring structure 194 may be a lid covering upper surfaces in the packaged semiconductor devices 180.An adhesive 196 may be used to secure the ring structure 194 to the front redistribution structure 140.

[0048] In Fig. 21, conductive interconnects 198 are formed on the second conductive traces 112 to form a System on Integrated Substrate (SoIS) 200. The conductive interconnects 198 may be BGA interconnects, solder balls, conductive pillars, C4 bumps, microbumps, bumps formed with ENEPIG, or the like. The conductive interconnects 198 may be formed from a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 198 are formed by initially forming a layer of solder by a method such as evaporation, electroplating, printing, solder delivery, ball placement, or the like, over the structure of Fig.20. After the layer of solder is formed, reflow may be performed to form the solder material into the desired bump shapes. In another embodiment, the conductive interconnects 198 are conductive pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The conductive interconnects 198 may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not separately illustrated) is formed on top of the conductive pillars. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0049] Mounting the first die 126 in the cavity 118 of the cavity substrate 120 and then connecting the packaged semiconductor devices 180 connected to the first die 126 by the front-side redistribution structure 140, the conductive interconnects 174, and the InFO structure 188 minimizes the distance between the first die 126 and the packaged semiconductor devices 180. This reduces the voltage drop between the first die 126 and the packaged semiconductor devices 180, thereby improving the power integrity and overall performance of the SoIS 200.

[0050] According to one embodiment, a package comprises: a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, wherein the redistribution structure couples the first die to the encapsulated device. In one embodiment, the first die comprises a multilayer ceramic capacitor (MLCC). In one embodiment, the first die comprises an integrated passive device (IPD). In one embodiment, the first die comprises an integrated voltage regulator (IVR). In one embodiment, the first die comprises a static random access memory (SRAM) die. In one embodiment, a distance between the encapsulated device and the first die is less than 0.3 mm.In one embodiment, the redistribution structure comprises one or more molding compound layers. In one embodiment, each of the one or more molding compound layers has a thickness of 5 µm to 100 µm. In one embodiment, the package further comprises a ring structure attached to the redistribution structure, the ring structure surrounding the encapsulated device. In one embodiment, the package further comprises a fill material surrounding sidewalls of the first die.

[0051] According to another embodiment, a method comprises forming a cavity in a substrate; attaching a first die to the substrate, wherein the first die is disposed within the cavity; forming a redistribution structure over a first side of the substrate and the first die; and attaching a semiconductor device to the redistribution structure, wherein the semiconductor device comprises a second die encapsulated by an encapsulant. In one embodiment, the method further comprises filling the cavity with a fill material after attaching the first die to the substrate. In one embodiment, the first die is attached to the substrate using an adhesive.In one embodiment, forming the redistribution structure comprises forming a via over the first side of the substrate and the first die and forming a molding compound surrounding the via, the molding compound being adjacent to the substrate.

[0052] According to yet another embodiment, a method comprises forming a cavity in a substrate; mounting the substrate to a carrier; attaching a first device to the substrate within the cavity; and coupling a second device to the first device, wherein the second device is encapsulated by an encapsulator, wherein the second device is disposed over the first device in a direction perpendicular to a major surface of the substrate. In one embodiment, the method further comprises depositing a fill material surrounding the first device.In one embodiment, the method further comprises forming a front-side redistribution structure over a front side of the substrate and the first device, the front-side redistribution structure comprising one or more molding compound layers, wherein the second device is coupled to the first device through the front-side redistribution structure. In one embodiment, the carrier is peeled from the substrate prior to coupling the second device to the first device. In one embodiment, the method further comprises forming electrical connectors over a back side of the substrate after peeling the carrier. In one embodiment, the cavity is formed using mechanical drilling.

[0053] The foregoing presents features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that the present disclosure may be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

[1] Package that includes: a substrate (120) comprising: an insulation layer (100), first conductor tracks (108) on a first side of the insulation layer (100) and second conductive traces (112) on a second side of the insulating layer (100) opposite the first side of the insulating layer (100); and conductive pins (110) extending through the insulation layer (100) and the vertically interconnecting the first and second conductor tracks (108, 112); a first die (126) disposed within the substrate (120); a redistribution structure (140) over the substrate (120) and the first die (126), wherein the redistribution structure (140) is adjacent to the substrate (120), wherein the redistribution structure (140) and the substrate (120) together form a first package (101); an encapsulated device (180) over the redistribution structure (140), the redistribution structure (140) coupling the first die (126) to the encapsulated device (180); and a ring structure (194) attached to the redistribution structure (140), the ring structure (194) surrounding the encapsulated device (180); wherein the insulation layer has a cavity (118), wherein a portion of the insulation layer (100) is present along a bottom of the cavity (118) and wherein the first die (126) is disposed within the cavity (118). [2] The package of claim 1, wherein the first die (126) comprises a multilayer ceramic capacitor. [3] The package of claim 1 or 2, wherein the first die (126) comprises an integrated passive component. [4] Package according to one of the preceding claims, wherein the first die (126) comprises an integrated voltage regulator. [5] Package according to one of the preceding claims, wherein the first die (126) comprises a static random access memory die (126). [6] Package according to one of the preceding claims, wherein a distance between the encapsulated device and the first die (126) is less than 0.3 mm. [7] Package according to one of the preceding claims, wherein a distance between the encapsulated device and the first die (126) is from 0.1 mm to 0.5 mm. [8] Package according to one of the preceding claims, wherein the redistribution structure (140) comprises one or more molding compound layers. [9] The package of claim 8, wherein each of the one or more molding compound layers has a thickness of 5 µm to 100 µm. [10] The package of any preceding claim, further comprising a filler material (132) surrounding sidewalls of the first die (126).

Images