Method for producing a fin field-effect transistor component

Abstract

Method (1000) for manufacturing a semiconductor device comprising the following steps: Producing a fin (64, 64A, 64B) projecting beyond a substrate (50); Producing a gate structure (75, 75A-C) over the fin (64, 64A, 64B); Creating a recess (88) in the fin (64, 64A, 64B) and adjacent to the gate structure (75, 75A-C); performing a wet etching process to clean the recess (88); Treating the recess (88) with a plasma process, wherein the plasma process removes portions of the fin (64, 64A, 64B) exposed by the recess (88) at a first etching rate along a first direction and at a second etching rate along a second direction, wherein the first direction runs along a longitudinal direction of the fin (64, 64A, 64B), the second direction runs along a depth direction of the recess (88), and the first etching rate is greater than the second etching rate, and wherein the plasma process is carried out using a gas source comprising hydrogen; and Performing a dry etching process to clean the recess (88) after the plasma process and the wet etching process.

Description

Background of the invention

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated into a given area.

[0002] FinFET (fin field-effect transistor) devices are now widely used in integrated circuits. FinFET devices have a three-dimensional structure with a semiconductor fin protruding from a substrate. A gate structure, configured to control the flow of charge carriers in a conductive channel of the FinFET device, encloses the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure encloses three sides of the semiconductor fin, creating conductive channels on three sides of the semiconductor fin.

[0003] US 2018 / 0 286 676 A1 discloses a method for manufacturing an integrated circuit device and an integrated circuit device manufactured according to the method. US 2016 / 0 020 301 A1 discloses a method for manufacturing a semiconductor device. US 9 202 919 B1 discloses techniques and structures for shaping the source and drain junction profiles of a FinFET. US 8 501 629 B2 discloses a method for etching silicon-containing material. US 8 541 312 B2 discloses a method for suppressing the etch rate for exposed silicon and nitrogen-containing material on patterned heterogeneous structures. Short description of the drawings

[0004] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows a perspective view of a FinFET device according to some embodiments. The Fig. 2 to 8, 9A to 9C, 10, 11, 12A and 12B show various cross-sectional views of a FinFET device at various stages of manufacture according to an embodiment. Fig. 13 shows a flow diagram of a method for manufacturing a semiconductor device according to some embodiments. Detailed description

[0005] The invention is defined by the independent claims, which define a method for manufacturing a semiconductor device. Preferred embodiments of the invention are provided in the dependent claims, the description, and the drawings. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention.For example, in the description below, the fabrication of a first element over or on top of a second element may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] Embodiments of the present invention are discussed in the context of fabricating a FinFET device, particularly in the context of cleaning a recess in the fin of a FinFET device in preparation for forming source / drain regions in the recess. While the disclosed embodiments are discussed using FinFET devices as examples, the disclosed methods may also be used with other types of devices, such as planar devices.

[0008] In some embodiments, a cleaning method for cleaning a surface of a semiconductor material comprises three cleaning steps performed sequentially. In one embodiment, the three cleaning steps are plasma cleaning, wet etching, and dry etching, performed sequentially. In another embodiment, the three cleaning steps are wet etching, plasma cleaning, and dry etching, performed sequentially. Wet etching and dry etching may remove an oxide layer on a surface of the semiconductor material, while plasma cleaning may remove impurities such as carbon, fluorine, chlorine, and oxygen located between the oxide layer and the semiconductor material. In some embodiments, plasma cleaning may be performed by treating the surface of the semiconductor material with hydrogen radicals and atomic hydrogen (e.g., H2 gas).In some embodiments, the three-step cleaning method is used to clean a recess in a fin of a FinFET device in preparation for epitaxial growth of the source / drain regions. In this case, plasma cleaning not only acts as a cleaning process to remove impurities, but also removes portions of the semiconductor material to adjust the profile (e.g., width, depth) of the recess. In some embodiments, adjusting the pressure of the plasma cleaning adjusts a ratio between the lateral etch rate and the vertical etch rate of the plasma cleaning, allowing fine-tuning of the recess profile. This allows fine-tuning of the drain-induced barrier depression (DIBL) and the channel resistance R. ch and the contact resistance R sd of the component can be adjusted (e.g. lowered).

[0009] Fig. 1 shows an example of a FinFET 30 in a perspective view. The FinFET 30 includes a substrate 50 and a fin 64 extending beyond the substrate 50. Isolation regions 62 are formed on opposite sides of the fin 64, with the fin 64 extending beyond the isolation regions 62. A gate dielectric 66 extends along sidewalls and over a top surface of the fin 64, and a gate electrode 68 is disposed over the gate dielectric 66. Source / drain regions 80 are disposed in the fin 64 and on opposite sides of the gate dielectric 66 and the gate electrode 68. Fig. 1 also shows reference cross sections used in later figures. A cross section B-B runs along a longitudinal axis of the gate electrode 68 of the FinFET 30. A cross section A-A is perpendicular to the cross section B-B and runs along a longitudinal axis of the fin 64 and, for example, in a direction of current flow between the source / drain regions 80. A cross section C-C is parallel to the cross section B-B and runs across the source / drain region 80. Later figures refer to these reference cross sections for clarity.

[0010] The Fig. 2 to 8, 9A to 9C, 10, 11, 12A, and 12B are cross-sectional views of a FinFET device 100 at various stages of fabrication according to some embodiments. The FinFET device 100 is similar to the FinFET 30 of Fig. 1, but it has multiple fins and multiple gate structures. Fig. 2 to 5 show sectional views of the FinFET device 100 along the cross section B - B. The Fig. 6 to 8, 9A, 10, 11 and 12A show sectional views of the FinFET device 100 along the cross section A - A. The Fig. 9B and Fig. 9C show exemplary cross-sectional views of the FinFET device 100 along the cross section C - C. Fig. Figure 12B shows a cross-sectional view of the FinFET device 100 along the cross section B-B.

[0011] Fig. 2 shows a cross-sectional view of substrate 50. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is formed on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0012] In Fig. 3, the substrate 50, which is in Fig. 2, for example, using photolithographic and etching techniques. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin film of silicon oxide, formed, for example, using a thermal oxidation process. The pad oxide layer 52 may act as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is made of silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or a combination thereof, and may be formed, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0013] The mask layer can be patterned using photolithographic techniques. Generally, photolithographic techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from later processing steps, such as etching. In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to produce a patterned mask 58, as shown in Fig. 3 is shown.

[0014] The patterned mask 58 is then used to pattern exposed portions of the substrate 50 to create trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, as shown in Fig. 3. In some embodiments, the semiconductor fins 64 are formed by etching trenches in the substrate 50, for example, by reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching process may be anisotropic. In some embodiments, the trenches 61 may be stripes (viewed from above) that are parallel to each other and arranged in close proximity to each other. In some embodiments, the trenches 61 may be contiguous and enclose the semiconductor fins 64. The semiconductor fins 64 may also be referred to as fins 64 hereinafter.

[0015] The fins 64 may be patterned using a suitable method. For example, the fins 64 may be patterned using one or more photolithographic processes, such as double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine photolithographic and self-aligned processes that can create structures having, for example, pitches smaller than those otherwise achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers, or mandrels, can then be used to structure the fins.

[0016] Fig. 4 shows the deposition of an insulating material between adjacent semiconductor fins 64 to create isolation regions 62. The insulating material may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-bake to convert to another material, such as an oxide), or the like, or a combination thereof. Other insulating materials and / or other manufacturing methods may also be used. In the illustrated embodiment, the insulating material is silicon oxide deposited using an FCVD process. After the insulating material is deposited, an annealing process may be performed.Using a planarization process, such as chemical mechanical polishing (CMP), excess insulating material can be removed and top surfaces of the isolation regions 62 and top surfaces of the semiconductor fins 64 can be fabricated that are coplanar (not shown). The patterned mask 58 (see . Fig. 3) can also be removed with the planarization process.

[0017] In some embodiments, the isolation regions 62 include a coating, e.g., an oxide coating (not shown), at the interface between the isolation region 62 and the substrate 50 or the semiconductor fins 64. In some embodiments, the oxide coating is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Likewise, the oxide coating may be used to reduce crystal defects at the interface between the semiconductor fins 64 and the isolation region 62. The oxide coating (e.g., silicon oxide) may be a thermal oxide deposited by thermal oxidation of a surface layer of the substrate 50, but other suitable methods for depositing the oxide coating may also be used.

[0018] Then, the isolation regions 62 are recessed to form shallow trench isolation (STI) regions 62. The isolation regions 62 are recessed such that the tops of the semiconductor fins 64 protrude between adjacent STI regions 62. The tops of the STI regions 62 may have a flat surface (as shown), a convex surface, a concave surface (such as dishing), or a combination thereof. The tops of the STI regions 62 may be made flat, convex, and / or concave using a suitable etch. The isolation regions 62 may be recessed using a suitable etching process, such as one that is selective for the material of the isolation regions 62. For example, a dry etch or a wet etch using dilute hydrofluoric acid (dHF acid) may be performed to recess the isolation regions 62.

[0019] The Fig. 2 to 4 illustrate one embodiment for fabricating fins 64, but fins 64 may also be fabricated using various other methods. For example, an upper portion of substrate 50 may be replaced with a suitable material, such as an epitaxial material suitable for a desired doping type (e.g., n- or p-type) of the semiconductor devices to be fabricated. Subsequently, substrate 50 is patterned with the epitaxial material thereon to fabricate semiconductor fins 64 comprising the epitaxial material.

[0020] As another example, a dielectric layer may be formed over a top surface of a substrate; trenches may be etched through the dielectric layer; homoepitaxial structures may be grown epitaxially in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer and form fins.

[0021] As yet another example, a dielectric layer may be formed over a top surface of a substrate; trenches may be etched through the dielectric layer; heteroepitaxial structures may be grown epitaxially in the trenches using a material different from the substrate; and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer and form fins.

[0022] In embodiments where one or more epitaxial materials or epitaxial structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the grown materials or structures may be doped in situ during growth, so that preceding and subsequent implantations may be omitted, but in situ and implantation doping may also be used together. Furthermore, it may be advantageous to epitaxially grow a material in an NMOS region that is different from the material in a PMOS region. In various embodiments, the fins 64 may comprise silicon germanium (Si x Ge 1-x, where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The materials that can be used to fabricate the III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0023] Fig. 5 illustrates the formation of a dummy gate structure 75 over the semiconductor fins 64. The dummy gate structure 75, in some embodiments, includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fins 64. The dielectric layer may, for example, comprise silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown.

[0024] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer can be deposited over the dielectric layer and then planarized, for example, using CMP. The mask layer can be deposited over the gate layer. The gate layer can be made of polysilicon, for example, but other materials can also be used. The mask layer can be made of silicon nitride or the like, for example.

[0025] After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) have been formed, the mask layer may be patterned using suitable photolithographic and etching techniques to form a mask 70. The pattern of the mask 70 may then be transferred to the gate layer and the dielectric layer using a suitable etching technique to form the gate electrode 68 and the gate dielectric 66, respectively. The gate electrode 68 and the gate dielectric 66 cover respective channel regions of the semiconductor fins 64. The gate electrode 68 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective semiconductor fins 64.

[0026] In the example of Fig. 5 shows that the gate dielectric 66 is formed over the fins 64 (e.g., over tops and sidewalls of the fins 64) and over the STI regions 62. In other embodiments, the gate dielectric 66 may be formed, for example, by thermal oxidation of a material of the fins 64 and may therefore be formed over the fins 64 but not over the STI regions 62.

[0027] The Fig. 6 to 8, 9A, 10, 11, and 12A show cross-sectional views of the further processing of the FinFET device 100 along the cross section A-A (along the longitudinal axis of the fin 64). It should be noted that in the Fig. 6 to 8, 9A and 10, three dummy gate structures 75 (e.g., 75A, 75B and 75C) are formed over the fin 64. However, one skilled in the art will recognize that more or fewer than three dummy gate structures may be formed over the fin 64,

[0028] As in Fig. 6, lightly doped drain (LDD) regions 65 are formed in the fins 64. The LDD regions 65 may be formed using a plasma doping process. The plasma doping process may include forming and patterning masks, such as a photoresist, to cover the regions of the FinFET to be protected from the plasma doping process. In the plasma doping process, n-type or p-type dopants may be implanted into the fins 64 to form the LDD regions 65. For example, p-type dopants, such as boron, may be implanted into the fins 64 to form the LDD regions 65 for a p-type device. As another example, n-type dopants, such as phosphorus, may be implanted into the fins 64 to form the LDD regions 65 for an n-type device. In some embodiments, the LDD regions 65 are adjacent to the channel region of the FinFET device 100.Portions of the LDD regions 65 may extend under the gate electrode 68 and into the channel region of the FinFET device 100. Fig. 6 shows a non-limiting example of the LDD regions 65. Other configurations, shapes, and manufacturing methods for the LDD regions 65 are also possible. For example, the LDD regions 65 may be formed after the formation of gate spacers 87. In some embodiments, the LDD regions 65 are omitted. For simplicity, the LDD regions 65 are not shown in subsequent figures, it being understood that the LDD regions 65 may be formed in the fin 64.

[0029] Let us stay with Fig. 6. After the LDD regions 65 have been formed, gate spacers 87 are formed around the dummy gate structures 75. The gate spacers 87 may include a first gate spacer 72 and a second gate spacer 86. For example, the first gate spacer 72 may be a gate seal spacer formed on opposite sidewalls of the gate electrode 68 and on opposite sidewalls of the gate dielectric 66. The second gate spacer 86 is formed on the first gate spacer 72. The first gate spacer 72 may be made of a nitride, such as silicon nitride, silicon oxynitride, or silicon carbonitride, or silicon carbide, or the like, or a combination thereof, and may be formed, for example, by thermal oxidation, CVD, or other suitable deposition techniques.The second gate spacer 86 may be made of silicon nitride, silicon carbonitride, a combination thereof, or the like, and may be formed using a suitable deposition process.

[0030] In one embodiment, the gate spacer 87 is formed by first conformally depositing a first gate spacer layer over the FinFET device 100 and then conformally depositing a second gate spacer layer over the first gate spacer layer. Subsequently, an anisotropic etch process, such as a dry etch process, is performed to remove a first portion of the second gate spacer layer located on top surfaces of the FinFET device 100 (e.g., on top of the mask 70), while leaving a second portion of the second gate spacer layer located along sidewalls of the gate structures. The second portion of the second gate spacer layer remaining after the anisotropic etch process forms the second gate spacer 86.The anisotropic etching process also removes a portion of the first gate spacer layer located outside the sidewalls of the second gate spacer 86, and the remaining portion of the first gate spacer layer forms the first gate spacer 72.

[0031] The shapes and manufacturing processes for the gate spacer 87 described in Fig. 6 are merely non-limiting examples, and other shapes and manufacturing methods are possible.

[0032] As in Fig. 7, recesses 88 are then formed in the fins 64 adjacent to the dummy gate structures 75, e.g., between adjacent dummy gate structures 75 and / or close to a dummy gate structure 75. The recesses 88 are formed, for example, with an anisotropic etch process using the dummy gate structures 75 and the gate spacers 87 as an etch mask in some embodiments, but another suitable etch process may also be used. The recesses 88 expose sidewalls 64S and bottom surfaces 64L of the fin 64, and thus, the sidewalls 64S and bottom surfaces 64L may also be referred to as surfaces of the fin 64 exposed by the recesses 88. The recess 88 has a depth D measured between a top surface 64U of the fin 64 and the bottom surface 64L (e.g., at the lower part of the recess 88) of the fin 64. Fig. 7 also shows a width W of the recess 88 between sidewalls 64S on opposite sides of the recess 88 (e.g., measured along a direction parallel to the top surface 64U of the fin 64) and a distance A between the sidewall 64S and a corresponding sidewall 68S of the gate electrode 68.

[0033] The etching process for forming the recesses 88 may leave impurities, such as oxygen (O), carbon (C), chlorine (Cl), fluorine (F), or the like, in surface areas of the fin 64 exposed by the recesses 88. The impurities may bond with the material (e.g., Si or SiGe) of the fin 64 at the surfaces (e.g., 64S, 64L) exposed by the recesses 88, forming a thin layer containing the impurities. Furthermore, an oxide layer (e.g., a silicon oxide layer) may form over the thin layer containing the impurities, which may be formed by exposure to ambient oxygen and / or by the preceding etching process. If the oxide layer and the impurities are not removed, they may interfere with the formation of source / drain regions 80 (see Fig. 9A) in the recesses 88 during subsequent processing and reduce the performance of the manufactured component.

[0034] Then in Fig. 8, the recesses 88 are cleaned before forming source / drain regions 80 in the recesses 88. In other words, the surfaces (64S, 64L) of the fin 64 that have been exposed by the recesses 88 are cleaned to remove the oxide layer and the impurities before forming the source / drain regions 80. However, existing cleaning methods (e.g., dry etching, wet etching) used to clean the recesses 88 are designed to remove oxide and may not be effective in removing the impurities. The present invention explains various exemplary cleaning methods for cleaning the recesses 88 to effectively remove the oxide layer and the impurities.

[0035] In one embodiment, a cleaning method for cleaning the recess 88 includes three cleaning steps. Specifically, a wet cleaning process is performed as the first cleaning step. Then, a plasma process (also referred to as a plasma cleaning process or a plasma cleaning step) is performed as the second cleaning step, followed by a dry etching process as the third cleaning step. Details of the wet etching, the plasma process, and the dry etching are discussed below.

[0036] In some embodiments, the wet etch process is performed using a suitable etchant, such as dilute hydrofluoric acid (dHF acid) or a solution comprising deionized water and ozone (DIO3). The wet etch process, in some embodiments, removes oxide on the surface areas of fin 64. While the wet etch process is used to remove oxide, it may also oxidize the surfaces (e.g., 64S, 64L) of fin 64 and form a thin oxide layer over the surfaces of fin 64.

[0037] Then, the plasma process is performed to treat the recesses 88 to remove the contaminants on the surface areas of the fin 64 exposed by the recesses 88. In a typical embodiment, the plasma process is performed using a gas source comprising hydrogen (H2). The gas source also comprises argon (Ar), helium (He), or a mixture of argon and helium. In other words, the gas source may be a mixture of hydrogen and argon, a mixture of hydrogen and helium, or a mixture of hydrogen, argon, and helium. The gas source is activated into a plasma using a plasma generation source, such as a transformer-coupled plasma generator, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, or the like.The argon and / or helium can act as an ignition gas to generate hydrogen ions during the activation process by colliding with the hydrogen gas.

[0038] In some embodiments, the plasma generation source activates portions of the hydrogen gas in the gas source into plasma, while other portions of the hydrogen gas in the gas source remain as atomic hydrogen (e.g., H2 gas). In some embodiments, a filtering mechanism in the plasma generation source is used to filter out electrically charged (e.g., positively or negatively charged) hydrogen ions while allowing hydrogen radicals (also referred to as H* radicals), which are not electrically charged (e.g., electrically neutral), to pass through. The hydrogen radicals, in some embodiments, are released along with the atomic hydrogen (H2 gas) to come into contact with the surfaces (e.g., 64S, 64L) of the fins 64 and are used to treat the recesses 88.

[0039] In some embodiments, the hydrogen radicals are small and can therefore penetrate the oxide layer on the surface areas of the fins 64 to react with the impurities beneath the oxide layer. For example, the hydrogen radicals can break the bonds (e.g., Si-Si, Si-C, Si-O, Si-Cl, Si-F) between the material of the fin 64 (e.g., Si, SiGe, or SiC) and the impurities (e.g., O, C, Cl, F), and the impurities can then react with hydrogen radicals to form volatile products (e.g., H3CSiH3, HF, HCl) that can be removed from a chamber (e.g., a cleaning chamber) containing the FinFET device 100. The hydrogen radicals can form bonds (e.g., Si-H) with the material of the fin 64, thereby advantageously avoiding or reducing the oxidation of the surfaces of the fin 64 in the subsequent etching process (e.g., a dry etch). It should be noted that the hydrogen radicals can also, for example,the Si-Si bond at the surfaces (e.g., 64S, 64L) of the fin 64 can break, thereby increasing the roughness of the surfaces. Since severe roughness can impair the epitaxial growth of the source / drain regions 80 in the recesses 88, the plasma process bonds are controlled to maintain the roughness of the surfaces (e.g., 64S, 64L) of the fins 64 at an acceptable level, so that the epitaxial growth of the source / drain regions 80 can be performed with little or no interference from the roughness of the surface regions in the recesses 88. Details of the plasma treatment conditions are discussed below.

[0040] In some embodiments, the plasma process is performed with a gas source comprising hydrogen and an ignition gas, where the ignition gas may be argon, helium, or a mixture of argon and helium. The plasma process may be performed with a hydrogen flow rate of approximately 10 cm 3 / min up to about 2000 cm 3 / min and a flow rate of the ignition gas (e.g. Ar, He or a mixture of Ar and He) of about 50 cm 3 / min up to about 6000 cm 3 / min. A temperature of the plasma process can be about 100 °C to about 600 °C. A pressure of the plasma process can be about 6.7 Pa (about 0.05 Torr) to about 800 Pa (about 6 Torr), and a duration of the plasma process can be about 10 s to about 100 s. The duration of the plasma process can be adjusted according to its temperature; for example, a shorter duration can be used at a higher temperature, and vice versa.

[0041] Let us stay with Fig. 8, in which the hydrogen radicals react with the material of the fin 64 and parts of the material of the fin 64 are removed. Therefore, the plasma process enlarges the recesses 88. In particular, after the plasma process, a width of the recess 88 increases to W'. As a result, after the plasma process, the distance between the sidewall 64S of the fin 64 and the corresponding sidewall 68S of the gate electrode 68 decreases to A'. By controlling the conditions of the plasma process so that the increase in the depth of the recess 88 is smaller than the increase in the width of the recess 88, the depth of the recess 88 can remain largely unchanged or slightly increase to D' after the plasma process. Details of this will be discussed below.

[0042] In some embodiments, the pressure of the plasma process is adjusted (e.g., increased or decreased) to adjust the etch rates (e.g., the removal rate of the material of the fin 64 by the plasma process) of the plasma process along the horizontal direction (e.g., the direction of the width W' or the direction along the length direction of the fin 64) from Fig. 8 and along the vertical direction (e.g. the direction of the depth D' or the direction perpendicular to the top surface 64U of the fin 64) of Fig. 8. In other words, the plasma process has a first etch rate along the horizontal direction and a second etch rate along the vertical direction, wherein the first etch rate is different from the second etch rate. In the illustrated embodiment, the pressure of the plasma process is controlled such that the first etch rate along the horizontal direction is greater than the second etch rate along the vertical direction. In a typical embodiment, a ratio between the first etch rate and the second etch rate is between 1 and 5. Therefore, the recess 88 is enlarged more in the horizontal direction than in the vertical direction. In the discussion herein, the first etch rate may also be referred to as a lateral etch rate, and the second etch rate may also be referred to as a vertical etch rate.

[0043] In some embodiments, increasing the pressure of the plasma process increases the ratio between the first etch rate and the second etch rate, and decreasing the pressure of the plasma process decreases the ratio between the first etch rate and the second etch rate. Thus, by adjusting the pressure of the plasma process, the profile (e.g., width, depth) of the recess 88 can be easily and precisely adjusted to achieve a targeted profile.

[0044] As feature sizes continue to decrease at modern process nodes, drain-induced barrier depression (DIBL) becomes an even more significant factor affecting the performance of the fabricated device. In some embodiments, the DIBL is determined at least in part by the width of the recesses 88. Depending on the process node used and the design of the FinFET device 100, the width of the recesses 88 should be within a specified range to achieve a target DIBL. If the width of the recesses 88 is too large (e.g., larger than the upper limit of the specified range), the DIBL may become too large, and the channel regions beneath the gate structures may be damaged. If the width of the recesses 88 is too small (e.g., smaller than the lower limit of the specified range), the DIBL may be too small, and the channel resistance (R ch) of the fabricated device may be too high because the source / drain regions 80 may be too far from the channel region, and as a result, dopants (e.g., B from epitaxial source / drain regions comprising SiGeB or P from epitaxial source / drain regions comprising SiP) for the channel region may not diffuse from the source / drain regions to reach the correct positions in the channel region. Furthermore, the volume of the source / drain regions 80 fabricated in the recesses 88 may be too small, resulting in a high channel resistance R sd can lead to.

[0045] With the etching process used to create the recesses 88 (see the above explanations with reference to Fig. 7), however, fine adjustment of the dimensions (e.g., width, height) of the recesses 88 to achieve the desired DIBL is not possible. The plasma process disclosed here (which is used, for example, to remove foreign matter from the recesses 88) offers the further advantage of being able to fine-tune the dimensions of the recesses 88 by controlling the conditions (e.g., pressure) of the plasma process, and thereby provides simple and precise control options for fine-tuning the channel resistance (R ch ) and the DIBL. In other words, the plasma process described above with reference to Fig. 8, cleans the recesses 88 and simultaneously modifies the profile of the recesses 88.

[0046] In the illustrated embodiment, the plasma process has a high etch selectivity between the material (e.g., Si, SiGe, SiC) of fin 64 and an oxide / nitride. In particular, the hydrogen radicals have a high etch rate for, e.g., Si, SiGe, or SiC, but they do not etch (e.g., remove) oxides or nitrides. Thus, the plasma process can be performed to remove the impurities and change the profile of the recesses 88 without attacking other structures of the FinFET device 100, such as the gate spacers 87 and the mask 70.

[0047] After the plasma process is completed, a dry etching process (the third cleaning step) is performed to remove oxide from the surfaces (e.g., 64S, 64L) of the fins 64. The dry etching process is performed using a suitable etching gas, such as a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) or a mixture of ammonia (NH3) and hydrogen fluoride (HF). As discussed above, the hydrogen radicals used in the plasma process (the second cleaning step) terminate (e.g., combine) on the surfaces of the fins 64 to prevent or reduce the formation of oxide by the dry etching process, which is a further advantage of the present invention. In some embodiments, the three cleaning steps (the wet etching process, the plasma process, and the dry etching process) are performed in the same processing chamber (e.g., the cleaning chamber).

[0048] Let us continue to Fig. 8. After the dry etching process, the distance A' between the sidewall 64S of the fin 64 and the corresponding sidewall 68S of the gate electrode 68 is less than or equal to 9 nm (i.e., A' ≤ 9 nm). In a typical embodiment, the distance A' is about 0.1 nm to about 4 nm. The depth D' of the recess 88 is compared to the depth D of the recess 88 of Fig. 7 unchanged or slightly increased (e.g., by less than 2 nm or less than 1 nm). In some embodiments, the depth D' is about 25 nm to about 60 nm.

[0049] As in Fig. 9A, the source / drain regions 80 are then formed in the recesses 88. The source / drain regions 80 are formed by epitaxially growing a material in the recesses 88 using suitable techniques such as metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or the like, or a combination thereof.

[0050] As in Fig. 9A, the epitaxial source / drain regions 80 may have surfaces that are raised relative to respective surfaces of the fins 64 (e.g., protrude beyond the non-recessed portions of the fins 64) and chamfers. In the example of Fig. 9A, a top surface 80U of the source / drain regions 80 extends, for example, with a distance of 3 nm or more above the top surface 64U of the fin 64. The source / drain regions 80 of adjacent fins 64 may merge into a contiguous epitaxial source / drain region 80 (see Fig. 9B). In some embodiments, the source / drain regions 80 for adjacent fins 64 do not merge together and remain separate source / drain regions 80 (see Fig. 9C). In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain regions 80 comprise silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), or the like. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain regions 80 comprise SiGe and a p-type dopant, such as boron or indium.

[0051] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80, and an annealing process may then be performed. The implantation process may include fabricating and patterning masks, such as a photoresist, to cover the regions of the FinFET device 100 that are to be protected from the implantation process. The source / drain regions 80 may have a doping concentration of approximately 1E19 cm -3 up to about 1E21 cm -3 P-type dopants, such as boron or indium, may be implanted into the source / drain region 80 of a p-type transistor. N-type dopants, such as phosphorus or arsenic, may be implanted into the source / drain region 80 of an n-type transistor. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0052] After the source / drain regions 80 have been fabricated, an interfacial concentration of hydrogen (from the hydrogen radicals in the plasma process) in an interfacial region 82 is greater than about 1E18 atoms per cubic centimeter (at / cm 3 ), where the interface region 82 is a region at an interface between the source / drain regions 80 and the fin 64. In addition, the interface concentration of impurities is reduced by the plasma process. For example, the interface concentration of impurities, such as oxygen and carbon, can be reduced to less than 5E19 at / cm 3 be reduced.

[0053] As in Fig. 10, a contact etch stop layer (CESL) 89 is then deposited over the Fig. 9A. The CESL 89 functions as an etch stop layer in a later etch process and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed using a suitable manufacturing method such as CVD, PVD, combinations thereof, or the like.

[0054] A first interlayer dielectric (ILD) 90 is then formed over the CESL 89 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is made of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited using a suitable process such as CVD, PECVD, or FCVD. A planarization process, such as a CMP process, may be performed to remove the mask 70 and the portions of the CESL 89 located above the gate electrode 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0055] Then in Fig. 11, an exemplary gate-last process (sometimes referred to as a replacement gate process) is performed to replace the gate electrode 68 and the gate dielectric 66 with an active gate (which may also be referred to as a replacement gate or a metal gate) and one or more active gate dielectric materials, respectively. Therefore, the gate electrode 68 and the gate dielectric 66 in a gate-last process may also be referred to as a dummy gate electrode and a dummy gate dielectric, respectively. The active gate is a metal gate in some embodiments.

[0056] In Fig. 11, the dummy gate structures 75A, 75B and 75C (see Fig. 10) are replaced by replacement gate structures 97A, 97B, and 97C, respectively. In some embodiments, to form replacement gate structures 97 (e.g., 97A, 97B, and 97C), gate electrode 68 and gate dielectric 66 directly beneath gate electrode 68 are removed in one or more etch steps, creating recesses (not shown) between gate spacers 87. Each recess exposes the channel region of a respective fin 64. During dummy gate removal, gate dielectric 66 may be used as an etch stop layer when gate electrode 68 is etched. After gate electrode 68 is removed, gate dielectric 66 may also be removed.

[0057] A gate dielectric layer 94, a barrier layer 96, a seed layer 98, and a gate electrode 99 are then formed in the recesses for the replacement gate structure 97. The gate dielectric layer 94 is conformally deposited in the recesses, such as on the tops and sidewalls of the fins 64, on sidewalls of the gate spacers 87, and on a top surface of the first ILD 90 (not shown). In some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.The fabrication methods for the gate dielectric layer 94 may include molecular beam epitaxy (MBD), atomic layer deposition (ALD), PECVD, and the like.

[0058] Then, the barrier layer 96 is conformally deposited over the gate dielectric layer 94. The barrier layer 96 may comprise an electrically conductive material, such as titanium nitride, but alternatively, other materials, such as tantalum nitride, titanium, tantalum, or the like, may be used. The barrier layer 96 may be formed using a CVD process, such as PECVD. Alternatively, other methods, such as sputtering, MOCVD, or ALD, may also be used.

[0059] Although they are in Fig. 11, in some embodiments, work function layers, such as a p-type work function layer or an n-type work function layer, may be formed in the recesses above the barrier layer 96 and prior to the formation of the seed layer 98. Example p-type work function metals that may be used in the gate structures for p-type devices are TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may be used in the gate structures for n-type devices are Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.A work function value is associated with the material composition of the work function layer, and therefore, the material for the work function layer is selected to adjust its work function value to achieve a desired threshold voltage Vt in the device to be fabricated. The one or more work function layers may be deposited by CVD, physical vapor deposition (PVD), and / or another suitable process.

[0060] Then, the seed layer 98 is conformally deposited over the barrier layer 96. The seed layer 98 may comprise copper, titanium, tantalum, titanium nitride, tantalum nitride, or the like, or a combination thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers composed of different materials. For example, the seed layer 98 comprises a titanium layer and a copper layer over the titanium layer.

[0061] Then, the gate electrode 99 is deposited over the seed layer 98 to fill the remaining portions of the recesses. The gate electrode 99 may be made of a metal-containing material, such as Cu, Al, W, or the like, or combinations thereof or multilayers thereof, and may be formed, for example, by electroplating, electroless plating, or another suitable method. After the gate electrode 99 is formed, a planarization process, such as CMP, may be performed to remove those excess portions of the gate dielectric layer 94, the barrier layer 96, the work function layer (if formed), the seed layer 98, and the gate electrode 99 that are located above the top surface of the first ILD 90.The resulting remaining portions of the gate dielectric layer 94, the barrier layer 96, the work function layer (if fabricated), the seed layer 98, and the gate electrode 99 form the replacement gate structure 97 of the resulting FinFET device 100.

[0062] Now let’s come to Fig. 12A, in which a second ILD 92 is formed over the first ILD 90. Contact openings are then created through the second ILD 92 to expose the replacement gate structures 97 (e.g., 97A, 97B, and 97C) and the source / drain regions 80. Contacts 102 (e.g., 102A, 102B) are formed in the contact openings.

[0063] In one embodiment, the second ILD 92 is a flowable layer formed by flowable CVD. In some embodiments, the second ILD 92 is made of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited using a suitable process such as CVD or PECVD. The contact openings may be created by photolithography and etching. During the etching process, the CESL 89 is etched through to expose the source / drain regions 80 and the replacement gate structures 97.

[0064] After the contact openings have been created, silicide regions 95 are formed over the source / drain regions 80. In some embodiments, the silicide regions 95 are formed by first depositing a metal that can react with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, over the exposed portions of the epitaxial source / drain regions 80 and subsequently performing a thermal annealing process to form the silicide regions 95. Then, the unreacted portions of the deposited metal are removed, e.g., with an etching process. While the regions 95 are referred to as silicide regions, they may also be germanide regions or silicon germanide regions (i.e., regions comprising silicide and germanide).

[0065] Contacts 102 (e.g., 102A and 102B, which may also be referred to as contact pins) are then formed in the contact openings. In the illustrated embodiment, contacts 102 each include a barrier layer 101, a seed layer 103, and a conductive material 105, and are each electrically connected to the underlying conductive feature (e.g., replacement gate structure 97 or silicide region 95). Contacts 102A, which are electrically connected to replacement gate structure 97, may be referred to as gate contacts, and contacts 102B, which are electrically connected to silicide regions 95, may be referred to as source / drain contacts. The materials and manufacturing methods for the barrier layer 101, the seed layer 103, and the conductive material 105 may be the same or similar to those described above for the barrier layer 96, the seed layer 98, and the conductive material 105, respectively.the gate electrode 99 of the substitute gate structure 97 have been discussed, and therefore details are not repeated here. In . Fig. For illustrative purposes, all contacts 102 are shown in Figure 12A with the same cross-section. This is, of course, merely an example and not limiting. The contacts 102 can be manufactured with different cross-sections.

[0066] Fig. 12B shows the FinFET device 100 of Fig. 12A, but along the cross section B - B. Fig. 12B shows a contact 102 above each of the fins 64A and 64B. The contacts 102 are electrically connected to the replacement gate structure 97. The number and positions of the contacts 102 are illustrative only and are not limiting, and other numbers and positions are possible.

[0067] Modifications of the disclosed embodiments are possible. For example, the order of the above Fig. 8, the first two cleaning steps of the cleaning method for the recess 88, such as the wet cleaning process and the plasma process, may be modified to allow flexibility for integrating the various processing steps into the process flow for the FinFET device 100. In other words, as an alternative embodiment, the cleaning method for cleaning the recess 88 may include three cleaning steps. In particular, a plasma process is performed as the first cleaning step. Then, a wet etching process is performed as the second cleaning step, and subsequently, a dry etching process is performed as the third cleaning step. Details of the plasma process, the wet etching process, and the dry etching process in the alternative embodiment are the same or similar to those described above with reference to Fig. 8, and therefore, they will not be repeated. As another example, although embodiments of the present invention are discussed in connection with cleaning the recesses 88 for the source / drain regions 80, the principle of the present invention may also be used for other surface cleaning processes, such as a cleaning process during the formation of the fins 64, wherein the cleaning process is performed between a first processing step in which upper portions of the fins 64 are removed (e.g., with an etching process) and a second processing step in which an epitaxial material is grown over the remaining lower portions of the fins 64.As yet another example, although embodiments of the present invention are discussed in the context of fabricating a FinFET device, the cleaning method may also be used for other types of devices, such as planar devices. For example, the . Fig. 7 and Fig. 8 can be used as sectional views of a planar component by considering regions designated by reference symbols 64 and 50 as regions of a substrate of the planar component and the dummy gate structures 75 as gate structures of the planar component.

[0068] Fig. 13 shows a flow diagram of a method 1000 for manufacturing a semiconductor device, according to some embodiments. It should be appreciated that the exemplary method described in Fig. 13 is merely one example of numerous possible exemplary methods. A person of ordinary skill in the art will recognize numerous variations, alternatives, and modifications. For example, various steps described in Fig. 13 are added, omitted, replaced, rearranged and repeated.

[0069] In Fig. 13, in a step 1010, a fin is formed that protrudes above a substrate. In a step 1020, a gate structure is formed over the fin. In a step 1030, a recess is created in the fin and adjacent to the gate structure. In a step 1040, a wet etching process is performed to clean the recess. In a step 1050, a plasma process is performed to treat the recess. In a step 1060, a dry etching process is performed to clean the recess after the plasma process and the wet etching process.

[0070] Embodiments may achieve advantages. For example, with the disclosed cleaning methods, impurities and oxide may be effectively removed from the recesses 88, and a clean surface for the subsequent growth of the epitaxial source / drain regions 80 may be achieved. This allows for better epitaxial growth of the source / drain regions 80. In addition, the fabricated source / drain regions 80 have a better quality, thereby reducing the contact resistance R sd is reduced and the source / drain regions 80 can better strain the channel region to increase device performance. Furthermore, the plasma process of the cleaning process not only removes impurities, but it can also be used to fine-tune the profile of the recesses 88. This allows for better control of the DIBL and a lower channel resistance R ch reached.

[0071] In one embodiment, a method of manufacturing a semiconductor device comprises the steps of: forming a fin that protrudes above a substrate; forming a gate structure over the fin; creating a recess in the fin and adjacent to the gate structure; performing a wet etching process to clean the recess; treating the recess with a plasma process; and performing a dry etching process to clean the recess after the plasma process and the wet etching process. In one embodiment, the method further comprises forming an epitaxial source / drain region in the recess.In one embodiment, the gate structure includes a gate electrode and gate spacers arranged along sidewalls of the gate electrode, wherein the plasma process increases a width of the recess such that a distance between a sidewall of the recess and a corresponding sidewall of the gate electrode is reduced. In one embodiment, the plasma process selectively removes a portion of the fin exposed by the recess without attacking the gate spacers of the gate structure. In one embodiment, a depth of the recess is substantially unaltered by the plasma process.In one embodiment, the plasma process removes portions of the fin exposed by the recess at a first etch rate along a first direction and at a second etch rate along a second direction, wherein the first direction runs along a longitudinal direction of the fin, the second direction runs along a depth direction of the recess, and the first etch rate is greater than the second etch rate. In one embodiment, a ratio between the first etch rate and the second etch rate is between 1 and 5. In one embodiment, the method further comprises adjusting a ratio between the first etch rate and the second etch rate by changing a pressure of the plasma process. In one embodiment, the plasma process is performed using a gas source comprising hydrogen.In one embodiment, treating the recess comprises treating the recess with hydrogen radicals and atomic hydrogen. In one embodiment, the plasma process is performed before the wet etching process. In one embodiment, the wet etching process is performed using dilute hydrofluoric acid or a solution comprising deionized water and ozone. In one embodiment, the dry etching process is performed using a mixture of ammonia and nitrogen trifluoride or a mixture of ammonia and hydrogen fluoride.

[0072] In one embodiment, a method of manufacturing a semiconductor device comprises the steps of: forming a gate structure over a substrate; creating a recess in the substrate and adjacent to the gate structure; performing a plasma process to treat the recess; performing a wet etching process to clean the recess; performing a dry etching process to clean the recess; and forming an epitaxial source / drain region in the recess. In one embodiment, the plasma process is performed using a gas source comprising hydrogen. In one embodiment, the plasma process reduces a concentration of impurities in surface areas of the substrate exposed by the recess, wherein the impurities include oxygen, carbon, chlorine, or fluorine.In one embodiment, the plasma process increases a width of the recess more than a depth of the recess.

[0073] In one embodiment, a method of manufacturing a semiconductor device comprises the steps of: forming a gate structure over a semiconductor fin; removing a portion of the semiconductor fin closest to the gate structure to create a recess; treating surface areas of the semiconductor fin exposed by the recess with a plasma process, wherein the plasma process increases dimensions of the recess by removing portions of the semiconductor fin exposed by the recess, wherein a width of the recess, measured along a longitudinal direction of the semiconductor fin, is increased more than a depth of the recess; performing a wet etching process to clean the recess; performing a dry etching process to clean the recess; and epitaxially growing a source / drain region in the recess.In one embodiment, the plasma process is performed using a gas source comprising hydrogen. In one embodiment, the plasma process removes portions of the semiconductor fin along the longitudinal direction of the semiconductor fin at a lateral removal rate and removes portions of the semiconductor fin along a depth direction of the recess at a vertical removal rate, the method further comprising: increasing a pressure of the plasma process to increase a ratio between the lateral removal rate and the vertical removal rate, or decreasing the pressure of the plasma process to decrease the ratio between the lateral removal rate and the vertical removal rate.

Claims

[1] A method (1000) for manufacturing a semiconductor device comprising the following steps: Producing a fin (64, 64A, 64B) projecting beyond a substrate (50); Producing a gate structure (75, 75A-C) over the fin (64, 64A, 64B); Creating a recess (88) in the fin (64, 64A, 64B) and adjacent to the gate structure (75, 75A-C); performing a wet etching process to clean the recess (88); Treating the recess (88) with a plasma process, wherein the plasma process removes parts of the fin (64, 64A, 64B) that have been exposed by the recess (88) at a first etching rate along a first direction and at a second etching rate along a second direction, wherein the first direction runs along a longitudinal direction of the fin (64, 64A, 64B), the second direction runs along a depth direction of the recess (88), and the first etching rate is greater than the second etching rate, and wherein the plasma process is carried out using a gas source comprising hydrogen; and Performing a dry etching process to clean the recess (88) after the plasma process and the wet etching process. [2] The method (1000) of claim 1, further comprising forming an epitaxial source / drain region (80) in the recess (88). [3] The method (1000) of claim 1 or 2, wherein the gate structure (75, 75A-C) comprises a gate electrode (68, 99) and gate spacers (87) arranged along sidewalls of the gate electrode (68, 99), wherein the plasma process increases a width of the recess (88) such that a distance between a sidewall of the recess (88) and a corresponding sidewall of the gate electrode (68, 99) is reduced. [4] The method (1000) of any preceding claim, wherein the plasma process selectively removes a portion of the fin (64, 64A, 64B) exposed by the recess (88) without attacking the gate spacers of the gate structure (75, 75A-C). [5] Method (1000) according to one of the preceding claims, wherein a depth of the recess (88) is substantially unchanged by the plasma process. [6] Method (1000) according to one of the preceding claims, wherein the plasma process comprises an ignition gas of argon, helium or a mixture of argon and helium, preferably at a hydrogen flow rate of 10 cm^3 / min - 2000 cm^3 / min and an ignition gas flow rate of 50 cm^3 / min - 6000 cm^3 / min. [7] The method (1000) according to any one of the preceding claims, wherein a ratio between the first etching rate and the second etching rate is between 1 and 5. [8] The method (1000) of any preceding claim, further comprising adjusting a ratio between the first etching rate and the second etching rate by changing a pressure of the plasma process. [9] Method (1000) according to one of the preceding claims, wherein a temperature of the plasma process is 100 °C to 600 °C, a pressure of the plasma process is 6.7 Pa to 800 Pa, and a duration of the plasma process is 10 s to 100 s. [10] The method (1000) of any preceding claim, wherein treating the recess (88) comprises treating the recess (88) with hydrogen radicals and atomic hydrogen. [11] Method (1000) according to one of the preceding claims, wherein the plasma process is carried out before the wet etching process. [12] The method (1000) of any preceding claim, wherein the wet etching process is performed using dilute hydrofluoric acid or a solution comprising deionized water and ozone. [13] The method (1000) according to any one of the preceding claims, wherein the dry etching process is carried out using a mixture of ammonia and nitrogen trifluoride or a mixture of ammonia and hydrogen fluoride. [14] A method (1000) for manufacturing a semiconductor device comprising the following steps: Forming a gate structure (75, 75A-C) over a substrate (50); Creating a recess (88) in the substrate (50) and adjacent to the gate structure (75, 75A-C); Performing a plasma process to treat the recess (88), wherein the plasma process increases a width of the recess (88) more than a depth of the recess (88), and wherein the plasma process is carried out using a gas source comprising hydrogen; performing a wet etching process to clean the recess (88); performing a dry etching process to clean the recess (88); and Producing an epitaxial source / drain region in the recess (88). [15] Method (1000) according to claim 14, wherein the plasma process comprises an ignition gas of argon, helium or a mixture of argon and helium, preferably at a hydrogen flow rate of 10 cm^3 / min - 2000 cm^3 / min and an ignition gas flow rate of 50 cm^3 / min - 6000 cm^3 / min. [16] The method (1000) of claim 14 or 15, wherein the plasma process reduces a concentration of contaminants in surface areas of the substrate (50) exposed by the recess (88), the contaminants comprising oxygen, carbon, chlorine, or fluorine. [17] Method (1000) according to one of claims 14 to 16, wherein a temperature of the plasma process is 100 °C to 600 °C, a pressure of the plasma process is 6.7 Pa to 800 Pa and a duration of the plasma process is 10 s to 100 s. [18] A method (1000) for manufacturing a semiconductor device comprising the following steps: Forming a gate structure (75, 75A-C) over a semiconductor fin (64, 64A, 64B); Removing a portion of the semiconductor fin (64, 64A, 64B) closest to the gate structure (75, 75A-C) to create a recess (88); Treating surface areas of the semiconductor fin (64, 64A, 64B) that have been exposed by the recess (88) with a plasma process, wherein in the plasma process dimensions of the recess (88) are increased by removing parts of the semiconductor fin (64, 64A, 64B) that have been exposed by the recess (88), wherein a width of the recess (88), measured along a longitudinal direction of the semiconductor fin (64, 64A, 64B), is increased more than a depth of the recess (88), wherein the plasma process is carried out using a gas source that comprises hydrogen; performing a wet etching process to clean the recess (88); performing a dry etching process to clean the recess (88); and epitaxial growth of a source / drain region in the recess (88). [19] Method (1000) according to claim 18, wherein the plasma process comprises an ignition gas of argon, helium or a mixture of argon and helium, preferably at a hydrogen flow rate of 10 cm^3 / min - 2000 cm^3 / min and an ignition gas flow rate of 50 cm^3 / min - 6000 cm^3 / min, wherein a temperature of the plasma process is 100 °C to 600 °C, a pressure of the plasma process is 6.7 Pa to 800 Pa and a duration of the plasma process is 10 s to 100 s. [20] The method (1000) of claim 18 or 19, wherein the plasma process removes portions of the semiconductor fin (64, 64A, 64B) along the longitudinal direction of the semiconductor fin (64, 64A, 64B) at a lateral removal rate and removes portions of the semiconductor fin (64, 64A, 64B) along a depth direction of the recess (88) at a vertical removal rate, the method (1000) further comprising: Increasing a pressure of the plasma process to increase a ratio between the lateral removal rate and the vertical removal rate, or decreasing the pressure of the plasma process to decrease the ratio between the lateral removal rate and the vertical removal rate.

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