IMPLEMENTATION OF NEURAL NETWORKS WITH TERNAR INPUTS AND BINAR WEIGHTS IN NAND STORAGE ARRAYS

Abstract

A non-volatile memory circuit comprising: an array of non-volatile memory cells arranged as NAND chains and configured to store one or more binary weights of a neural network, each weight being stored in a pair of non-volatile memory cells on a common NAND chain; and one or more control circuits connected to the array of non-volatile memory cells, the one or more control circuits being configured for: receiving one or more inputs for a layer of a neural network and converting the one or more inputs into one or more corresponding voltage patterns from a set; applying one or more voltage patterns to the array of non-volatile memory cells to perform in-array multiplication of the one or more inputs by the weights; accumulating the results of the in-array multiplication;and determining a number of the one or more voltage patterns corresponding to a first voltage pattern, and adjusting the accumulated results of the in-array multiplication based on the number of the one or more voltage patterns corresponding to the first voltage pattern.

Description

BACKGROUNDArtificial neural networks are increasingly used in artificial intelligence and machine learning applications. In an artificial neural network, a set of inputs is propagated through one or more intervening or hidden layers to generate an output. The layers connecting the input to the output are connected by sets of weights generated in a training or learning phase by determining a set of mathematical manipulations to convert the input to the output, the layers calculating the probability of each output. Once the weights are fixed, they can be used in the inference phase to determine the output from a series of inputs. Although such neural networks can provide highly accurate results, they are extremely computationally intensive, and the data transfers involved in reading the weights that connect the various layers from memory and transfer them into the processing units of a processing unit can be quite intensive.US 2015 / 0 324 691 A1 discloses a system comprising a plurality of non-volatile memory cells and a card which assigns connections between nodes of a neural network to the memory cells. Memory devices that include non-volatile memory cells and corresponding read and write circuitry may operate with the card. Information stored in the memory cells may represent weights of the connections. One or more neural processors may be present and configured to implement the neural network.U.S. Pat. No. 9,965,208 B1 discloses memory devices with a configurable operating mode. In at least one embodiment, a storage device is configurable in one or more modes of operation. An array of memory cells may be divided into one or more partitions, each partition being associated with only a particular mode of operation. In at least one further embodiment, a memory device is configured to store user data in a portion of a memory array and store data corresponding to a logical function associated with a different mode of operation of the memory device in a different portion of the memory array.US 2017 / 0 054 032 A1 discloses a nonvolatile memory with individually optimized silicide contacts and a method for this. In an integrated circuit memory, the performance is increased by the decrease in electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically limited by considering the integrated circuit manufacturing geometry for each memory cell so that it does not exceed a given aspect ratio. The present implementation enables independent optimization of the thickness of the silicide layer in the memory cell region and the non-memory cell region. Particularly in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slot contact for components in which the upper poly layer is in contact with a lower poly layer (a floating gate poly).The article by COWBARIAUX, Matthieu et al.: "Binary Neural Networks: Training Neural Networks with Weights and Activation Constrained to +1 and -1" presents a method for training binary neural networks (BNNs) - neural networks with binary weights and activations at runtime. During training, the binary weights and activations are used to calculate the parameter gradients. During the forward pass, BNNs drastically reduce memory size and memory accesses and replace most arithmetic operations with bitwise operations, which may result in a significant improvement in energy efficiency. In order to validate the effectiveness of BNNs, two series of experiments are performed with the Pinch? and Theano frameworks. In both cases, BNNs achieved near state-of-the-art results for the MNIST, CIFAR-10, and SVHN records. A GPU kernel for binary matrix multiplication has been written, with which it is possible to train a MNIST BNN seven times faster than with an unoptimized GPU kernel without compromising classification accuracy.The article by BAYAT F. Merrikh et al.: "Sub-1 - ps, Sub-20-nJ Pattern Classification in a Mixed-Signal Circuit Based on Embedded 180 nm Floating-Gate Memory Cell Arrays" presents the pattern classification in a mixed-signal circuit. A prototype mixed signal with 28x28 binary inputs, 10 outputs and a three-layered neuromorphic network ("MLP perceptron") was designed, manufactured and successfully tested. It is based on embedded non-volatile floating gate cell arrays newly developed from a commercial 180 nm NOR flash memory. The arrays allow precise (~11%) individual tuning of all memory cells that have long term analog level storage and low noise. Each array performs a very fast (below μs) and energy efficient analog vector matrix multiplication, which represents the bottleneck for signal propagation in most neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating gate "synaptic cells", 74 analog neurons and the periphery circuit for weight adjustment and I / O operations, have a total area of less than 1 mm 2. Tests with the current MNIST benchmark set (at this stage with a relatively low import accuracy of the weights) have given a classification accuracy of 94.65%, which is close to the 96.2% achieved in the simulation. The classification of a pattern takes less than 1 μs and consumes ~20 nJ of energy - both values are significantly better than digital implementations of the same task. It is estimated that this performance can be further improved by a better neuron design and more advanced memory technology, which would result in a speed advantage of a >10 2 x and an energy efficiency advantage of a >10 4 x over the most modern purely digital (GPU and custom) circuits in the classification of large, complex patterns.BRIEF DESCRIPTION OF THE DRAWINGSLike numbered elements refer to common components in the various figures. FIG. 1 is a block diagram illustrating one embodiment of a memory system connected to the host. FIG. 2 is a block diagram of an embodiment of a front-end processor circuit. In some embodiments, the front-end processor circuit is part of a controller. FIG. 3 is a block diagram of an embodiment of a back-end processor circuit. In some embodiments, the back-end processor circuit is part of a controller. FIG. 4 is a block diagram of one embodiment of a memory package. FIG. 5 is a block diagram of an embodiment of a memory chip. FIG. 6 shows a simple example of an artificial neural network. FIG. 7A is a flow diagram describing an embodiment of a process for training a neural network to generate a set of weights. FIG. 7B is a flowchart describing an embodiment of an inference process using a neural network. FIG. 8 is a schematic illustration of the use of matrix multiplication in a neural network. FIG. 9 is a table illustrating the output of a binary neural network in response to the various input-weight combinations. FIG. 10 shows an embodiment for a unit synapse cell for storing a binary weight in a pair of memory cells connected in series. FIG. 11 shows the distribution of threshold voltages for storing data states in a binary or single level cell memory (SLC). FIGS. 12 and 13 show an embodiment for implementing a binary neural network using a pair of the SLC memory cells connected in series as a unit synapse.Figures 14 and 15 correspond to Figures 12 and 13 which are extended to include a "0" input logic value for implementing a ternary input. FIG. 16 shows the organization of the unit synapses into a NAND array. FIGS. 17 and 18 illustrate an example of the computation of a dot product for the binary neural network algebra and how to implement using a counter-based summing digital circuit for an embodiment of a SLC NAND binary neural network (BNN). FIG. 19 is a flow diagram for an embodiment of dot product computation using a binary neural network in inference. FIGS. 20 and 21 illustrate an example that extends the computation of a dot product for a ternary binary neural network and how it is implemented using a counter-based digital summation circuit for an embodiment of a ternary binary SLC NAND network (TBN). FIG. 22 shows an embodiment of a summation circuit for an SLC NAND array for supporting ternary binary neural networks. Figures 23A and 23B provide two embodiments for the combinational logic circuitry of Figure 22. FIG. 24 is a flow diagram for an embodiment of a dot product calculation using a ternary binary neural network in inference as shown in the tables of FIGS. 20 and 21 and the array architecture 22. FIGS. 25 and 26 illustrate an example of a neural network and its implementation by a NAND array. FIG. 27 illustrates an example of a neural network and its implementation by a NAND array to achieve high parallelism across NAND blocks by exploiting multiple blocks in a single plane. FIG. 28 is a flow diagram for an embodiment of a dot product calculation similar to FIG. 19, but including the multi-block parallelism illustrated in FIG. 27. FIG. 29 shows additional embodiments that can simultaneously infer the inputs of a neural network via multiple levels. FIG. 30 illustrates an embodiment of a planar line for various neural network layers. Figure 31 shows an embodiment in which weights of different layers can be stored in the same block, plane or both.DETAILED DESCRIPTIONTo reduce computational complexity and to loosen neural network storage requirements, binary neural networks (BNNs) have been introduced. In BNNs, the weights and inputs of the neural network are shortened to binary values (-1, +1), and binary arithmetic simplifies multiplication and addition to XNOR and bit count operations. The following disclosure presents techniques for exploiting the structure of a NAND memory for storing the weights of binary neural networks and for performing the multiplication and accumulation operations within the NAND memory.Each binary weight is stored in a unit synapse formed of a pair of series-connected binary memory cells, such as a pair of adjacent memory cells on a NAND string, one of the memory cells being in a programmed state and the other in an erased state. Depending on which memory cell of the unit synapse is in the programmed and which memory cell is in the erased state, the unit synapse will be either in the weight -1 or the +1. The binary input is then applied as a voltage pattern to the corresponding word lines in which one of the word line pairs is at a read voltage (for which only the erased state memory cell is conducting) and the other of the word line pair is at a forward voltage (for which one memory cell is conducting in either state). Depending on which word line of the word line pair is at which value, the input will be either a -1 or a +1. By applying the input to the word line pair, the unit synapse (and the corresponding NAND string) will either conduct or not depending on whether the input and the weight match or not. The result may be determined by a sense amplifier connected to a corresponding bit line. By applying the input / unit synapse pairs along a NAND string and accumulating the results of the sense amplifier, the multiplication and accumulation operations of propagating an input through a layer of a neural network can be performed. Since the word lines of the array span multiple NAND strings, the operation can be performed simultaneously for the binary weights of multiple unit synapses.The degree of parallelism can be increased by the introduction of multi-bit sense amplifiers so that the unit synapse of different memory blocks of the array can be simultaneously sensed. Further increases in parallelism can be obtained by simultaneously scanning at multiple levels and pipelining the output of one level corresponding to one layer of neural network to the input of another level corresponding to the subsequent layer of neural network.The accuracy of a binary weighted neural network can be increased by using a ternary binary network (TBN). In a TBN arrangement, the weight values are binary (-1, +1), but the inputs are now ternary (-1, 0, +1). As in the BNN case, the weights may still be stored in a unit synapse formed of a pair of memory cells connected in series. The 0-input value may be implemented as a voltage pattern in which both word lines of the word line pair have the read voltage (for which only the erased state memory cell is conducting). To account for such 0 input values, a logic circuit may determine when the voltage levels of a word line pair match and adjust the count value accumulated by the sense amplifiers accordingly.FIG. 1 is a block diagram illustrating one embodiment of a memory system 100 connected to the host 120. The storage system 100 may implement the technology proposed herein, wherein the neural network inputs or other data are received from the host 120. Depending on the embodiment, the inputs may be received from the host 120 and then provided to the memory packages 104 to infer the weights previously programmed into the memory fields of the memory packages 104. Many different types of storage systems may be used with the technology proposed herein. Example storage systems include solid state drives ("SSDs"), memory cards, and embedded storage devices; however, other types of storage systems may be used.The memory system 100 of FIG. 1 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM) 106. The controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified ASIC controller may combine both front-end and back-end functions. The ASICs for each of the BEP circuits 112 and the FEP circuit 110 are implemented on the same semiconductor, such that the controller 102 is fabricated as a system on a chip ("SoC"). The FEP circuit 110 and the BEP circuit 112 both include their own processors. In one embodiment, the FEP circuit 110 and the BEP circuit 112 operate as a master-slave configuration, with the FEP circuit 110 being the master and each BEP circuit 112 being a slave. For example, the FEP circuit 110 implements a flash translation layer (FTL) or a media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other nonvolatile memory system). The BEP circuit 112 manages memory operations in the memory packages / chip upon request from the FEP circuit 110. For example, the BEP circuit 112 may perform the read, erase, and program processes. In addition, the BEP circuit 112 may perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control toggle mode interfaces to the memory packets, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packets.In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory chips. Thus, the controller 102 is connected to one or more non-volatile memory chips. In one embodiment, each memory chip in the memory packages 104 uses a NAND flash memory (including a two-dimensional NAND flash memory and / or a three-dimensional NAND flash memory). In other embodiments, the memory package may include other memory types.The controller 102 communicates with the host 120 via an interface 130 that implements NVM Express (NVMe) via PCI Express (PCIe). For cooperation with the memory system 100, the host 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 connected along the bus 128. The host memory 124 is the physical memory of the host and may be a DRAM, SRAM, non-volatile memory, or other type of memory. Host 120 is external and separate from storage system 100. In one embodiment, the storage system 100 is embedded in the host 120.FIG. 2 is a block diagram of an embodiment of the FEP circuit 110. FIG. 2 shows a PCIe interface 150 for communicating with the host 120 and a host processor 152 in communication with this PCIe interface. Host processor 152 may be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. NOCs may span synchronous and asynchronous clock domains or use untimed asynchronous logic. NOC technology applies network theory and methods to on-chip communications and provides significant improvements over conventional bus and crossbar interconnects. NOC improves the scalability of SoCs and the power efficiency of complex SoCs compared to other designs. The wires and the connections of the NOC are shared by many signals. High parallelism is achieved because all connections in the NOC can operate simultaneously on different data packets. Thus, as integrated subsystem complexity grows, NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Connected to and in communication with NOC 154 is memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 is used to operate with and communicate with the DRAM (e.g., DRAM 106). SRAM 160 is a local RAM memory used by memory processor 156. The memory processor 156 is used to operate the FEP circuitry and to perform the various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. In the embodiment of FIG. 2, the SSD controller includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112; thus, there may be more than two PCIe interfaces.The FEP circuit 110 may also include a flash translation layer (FTL) or, more generally, a media management layer (MML) 158 that performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD or other nonvolatile storage system. The media management layer MML 158 may be incorporated as part of the memory management that can handle memory errors and interact with the host. In particular, MML may be a module in FEP circuit 110 and responsible for the internals of the memory management. In particular, the MML 158 may include an algorithm in the firmware of the memory device that translates writes from the host into writes to the memory structure (e.g., 326 of FIG. 5 below) of a chip. MML 158 may be required because: 1) the memory may have limited durability; 2) the memory structure may be written to only in multiples of pages; and / or 3) the memory structure may not be written to unless it is deleted as a block. The MML 158 understands these potential limitations of the memory structure that may not be visible to the host. Accordingly, the MML 158 attempts to translate the writes from the host into writes to the memory structure.FIG. 3 is a block diagram of an embodiment of a BEP circuit 112. FIG. 3 shows a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., in conjunction with one of the PCIe interfaces 164 and 166 of FIG. 2 ). The PCIe interface 200 is in communication with two NOCs, 202 and 204. In one embodiment, the two NOCs may be combined into a large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), a buffer (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engines 226 / 256 are used to perform error correction as is known in the art. The XOR engines 224 / 254 are used to XOR the data so that data can be combined and stored in a manner that can be recovered in the event of a programming error. The data path controller 222 is connected to an interface module to communicate with memory packets over four channels. Thus, the upper NOC 202 is associated with a four channel interface 228 for communication with memory packets and the lower NOC 204 is associated with a four additional channel interface 258 for communication with memory packets. Each interface 228 / 258 includes four toggle mode (TM) interfaces, four buffers, and four schedulers. For each channel, there is a scheduler, buffer and TM interface. The processor may be any standard processor known in the art. The data path controllers 222 / 252 may be a processor, an FPGA, a microprocessor, or other type of controller. XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, XOR engines 224 / 254 and ECC engines 226 / 256 may be implemented in software. The schedulers, buffers and TM interfaces are hardware circuits.FIG. 4 is a block diagram of an embodiment of a memory package 104 that includes a plurality of memory chips 292 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a toggle mode interface 296 for communication with the TM interface of a BEP circuit 112 (see, e.g., FIG. 3 ). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may include one or more memory chips. In one embodiment, each memory package includes eight or 16 memory chips; however, other numbers of memory chips may also be implemented. The technology described herein is not limited to a specific number of memory chips.FIG. 5 is a functional block diagram of an embodiment of a memory chip 300. The components shown in FIG. 5 are electrical circuits. In an embodiment, each memory chip 300 includes a memory structure 326, a control circuit 310, and read / write circuits 328. The memory structure 126 is addressable by word lines via a row decoder 324 and by bit lines via a column decoder 332. The read / write circuits 328 include multiple read blocks 350 including SB 1, SB 2,..., SBp (measurement circuit) and enable a page of memory cells to be read or programmed in parallel. Commands and data are transmitted between the controller and the memory chip 300 via signal lines 318. In one embodiment, memory chip 300 includes a set of input and / or output (I / O) pins connected to lines 318.The control circuit 310 cooperates with the read / write circuits 328 to perform memory operations (e.g., write, read, and others) on the memory structure 326, and includes a state machine 312, an on-chip address decoder 314, and a power control circuit 316. State machine 312 provides chip level control of memory operations. In one embodiment, state machine 312 is programmable by software. In other embodiments, state machine 312 does not use software and is fully implemented in hardware (e.g., electrical circuits). In another embodiment, state machine 312 is replaced with a microcontroller. In one embodiment, control circuit 310 includes buffers, such as registers, ROM fuses, and other memory devices for storing default values such as base voltages and other parameters.The on-chip address decoder 314 provides an address interface between addresses used by a controller 102 to the hardware address used by decoders 324 and 332. The power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 316 may include charge pumps for generating voltages. The read blocks include bit line drivers.For purposes of this document, the term "one or more control circuits" refers to a controller, state machine, microcontroller and / or control circuit 310, or other analog circuits used to control non-volatile memory.In one embodiment, the memory structure 326 includes a three-dimensional array of non-volatile memory cells on which multiple memory stages are formed over a single substrate, such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having an active area disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings of charge trapping material, such as described in U.S. Pat. No. 9,721,662, which is incorporated herein by reference in its entirety.In another embodiment, the memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells using floating gates as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) may also be used.The exact type of memory array architecture or memory cell included in the memory structure 326 is not limited to the examples above. Many different types of memory array architectures or memory technologies may be used to form the memory structure 326. No special non-volatile memory technology is required for the purposes of the novel claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of memory structure 326 include ReRAM memories, magneto-resistive memories (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase change memories (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architectures of the memory structure 126 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.An example of a ReRAM or PCMRAM cross-point memory includes reversible resistance switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge storage element may be used as a state changing element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge storage element may include two solid metal electrodes, a relatively inert (e.g., tungsten) and an electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, so that the programming threshold for the conductive bridge memory cell decreases. Thus, the conductive bridge memory element may have a wide range of program thresholds as a function of temperature.A magneto-resistive memory (MRAM) stores data through magnetic memory elements. The elements are formed of two ferromagnetic plates, each of which can maintain a magnetization separated by a thin insulating layer. One of the two plates is a permanent magnet set to a certain polarity; the magnetization of the other plate may be changed to correspond to that of an external field to store memories. A memory device is constructed of a grid of such memory cells. In one embodiment for programming, each memory cell is sandwiched between a pair of write lines which are at right angles to each other parallel to the cell, one above and one below the cell. When current flows through them, an induction magnetic field is generated.Phase Change Memory (PCM) takes advantage of the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase changes by simply changing the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Thus, the doses of programming are laser pulses. The memory cells may be disabled by preventing the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a square-wave pulse, but involves (continuous or non-continuous) oscillation or surge of sound, current, voltage light or other wave.One skilled in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures according to the spirit and scope of the technology described herein and as known to one skilled in the art.Turning now to the types of data that can be stored on nonvolatile memory devices, a specific example of the type of data of interest in the following discussion is the weight used in deep neural networks. An artificial neural network is formed of one or more intermediate layers between an input layer and an output layer. The neural network finds mathematical manipulation to convert the input to the output, moving through the layers, and calculating the probability of each output. FIG. 6 shows a simple example of an artificial neural network.In FIG. 6, an artificial neural network is shown as a connected group of nodes or artificial neurons represented by the circles and a series of connections from the output of one artificial neuron to the input of another. The example shows three input nodes (I 1, I 2, I 3) and two output nodes (O 1, O 2), with an intermediate layer of four hidden or intermediate nodes (H 1, H 2, H 3, H 4). The nodes, or artificial neurons / synapses, of the artificial neural network are implemented by logical elements from a host or other processing system as a mathematical function that receives one or more inputs and sums them to generate an output. Typically, each input is separately weighted and the sum is passed through the mathematical function of the node to provide the output of the node.In common implementations of artificial neural networks, the signal at a junction between nodes (artificial neurons / synapses) is a real number, and the output of each artificial neuron is calculated by a non-linear function of the sum of its inputs. Nodes and their connections normally have a weight that adjusts during the learning process. The weight increases or decreases the strength of the signal at a connection. Nodes may have a threshold such that the signal is transmitted only when the sum signal crosses this threshold. Typically, the nodes are aggregated into layers. Different layers may perform different types of transformations on their inputs. The signals travel from the first layer (the input layer) to the last layer (the output layer), possibly after the layers have been traversed a number of times. Although FIG. 6 shows only a single intermediate or hidden layer, a complex deep neural network (DNN) may have many such intermediate layers.An artificial neural network is "trained" by providing inputs and then checking and correcting the outputs. For example, a neural network trained to recognize dog trains processes a set of images and calculates the probability that the dog belongs to a particular breed in an image. A user can see the results and select what probabilities the network should indicate (above a certain threshold, etc.) and return the proposed label. As such, any mathematical manipulation is considered a layer, and complex neural networks have many layers. Due to the depth provided by a large number of intermediate or hidden layers, neural networks may model complex non-linear relationships when trained.FIG. 7A is a flow diagram describing an embodiment of a process for training a neural network to generate a set of weights. The training process is often performed in the cloud, thereby enabling additional or more efficient processing of the access. In step 701, the input, such as a set of images, is received at the input node (e.g., I 1, I 2, I 3 in FIG. 6 ). In step 703, the input is forwarded using the current set of weights by the nodes of the hidden intermediate layers (e.g., H 1, H 2, H 3, H 4 in FIG. 6 ). The output of the neural network is then received at the output node (e.g., O 1, O 2 in FIG. 6 ) in step 705. In the dog-breed example of the previous paragraph, the input would be the image data of a number of dogs, and the intermediate layers use the current weight values to calculate the probability that the dog in an image will return a particular breed, with the suggested dog-breed label, in step 705. A user can then check the results in step 707 to select which probabilities the neural network should return and to decide whether the current set of weights will provide a sufficiently accurate label, and if so, training is complete (step 711). If the result is not accurate enough, the neural network adjusts the weights at step 709 based on the probabilities the user has selected and then returns to step 703 to re-execute the input data with the adjusted weights. Once the set of weights of the neural network has been determined, inference may be inferred. This is the process of using the determined weights to generate an output result from data input to the neural network. Once the weights have been determined in step 711, they may be stored in non-volatile memory for later use, with the storage of these weights in non-volatile memory being discussed in more detail below.FIG. 7B is a flowchart describing a process for the inference phase of supervised learning using a neural network to predict the "meaning" of the input data using estimated accuracy. As the case may be, the neural network may be derived both in the cloud and by the processor of an edge device (e.g., smartphone, automobile process, hardware accelerator). In step 721 the input is received, for example the picture of a dog in the example used above. If the previously determined weights are not present in the device on which the neural network application is executed, they are loaded in step 722. For example, on a host processor executing the neural network, the weight could be read from an SSD in which it is stored and loaded into the RAM on the host device. In step 723, the input data is then passed through the layers of the neural network. Step 723 will be similar to step 703 of FIG. 7B, but now using the weights set up at the end of the training process in step 711. After passing the input through the interlayer, the output is then provided in step 725.Neural networks are typically feedforward networks in which data flows from the input layer through the intermediate layers and to the output layer without loop back. First, in the training phase of supervised learning, as shown in FIG. 7A, the neural network constructs a virtual neuron map and assigns random numerical values or "weights" to these connections. The weights and inputs are multiplied and return an output between 0 and 1. If the network does not accurately recognize a particular pattern, an algorithm adjusts the weights. In this way, the algorithm may make certain parameters more influence (by increasing the corresponding weight) or less influence (by decreasing the weight) and adjust the weights accordingly until it determines a set of weights that provides sufficiently correct mathematical manipulation to fully process the data.FIG. 8 is a schematic illustration of the use of matrix multiplication in a neural network. Matrix multiplication or MatMul is a commonly used approach in both the training and inference neural network phases and is used in kernel methods for machine learning. Figure 8 is similar to Figure 6 above, where only a single hidden layer is shown between the input layer and the output layer. The input data is represented as a vector of a length corresponding to the number of input nodes. The weights are represented in a weight matrix, the number of columns corresponding to the number of intermediate nodes in the hidden layer and the number of rows corresponding to the number of input nodes. The output is determined by a matrix multiplication of the input vector and the weight matrix, wherein each element of the output vector is a dot product of the vector of the input data with a column of the weight matrix.A common technique for performing the matrix multiplication is to use a multiplier-accumulator (MAC or MAC unit). This, however, has a number of problems. Referring again to FIG. 7B, in step 722, the inference phase loads the weights of the neural network before performing the matrix multiplications by the propagation in step 723. However, since the amount of data involved may be extremely large, the use of a multiplier-accumulator for the re-tracking has several problems related to loading weights. One of these is high energy dissipation, since large MAC arrays with the required bit width must be used. Another problem is the high power dissipation due to the limited size of the MAC arrays, which results in a high data movement between logic and memory and a much higher power dissipation than is used in the logic computations themselves.To help avoid these limitations, the use of a multiplier accumulator array may be replaced with other memory technologies. For example, matrix multiplication in a memory array may be calculated using memory class memory (SCM) characteristics, e.g., those based on ReRAM, PCM, or MRAM-based memory cells. This allows the neural network inputs to be provided via read commands and the neural weights to be precharged for transceiving. By using in-memory computing, the need for logic to perform matrix multiplication in the MAC array and moving data between the memory and the MAC array may be eliminated.The following contemplates embodiments based on memory arrays using NAND-type architectures, such as flash NAND memories using memory cells having a charge storage region. Flash NAND memories may be implemented using both multi-level cell (MLC) structures and single-level cell (SLC) structures, mainly considering embodiments based on SLC flash memory below. Unlike MAC array logic, the use of SLC flash memory has several advantages, including a much higher range / bit value, a much higher throughput rate, and a significant reduction in power consumption due to minimizing data movement by multiplication within the array. Moreover, the NAND flash structure is highly scalable and supports deep and wide neural networks.One technique that can be used to reduce the computational complexity of the inference process is the use of a binary neural network (BNN) in which a neural network operates with binary weights and activations. A BNN (also called XNOR network) calculates the matrix-vector multiplication with "binary" inputs {-1, 1} and "binary" weights {-1, 1}. FIG. 9 is a table illustrating the output of a binary neural network in response to the various input-weight combinations. As shown in the rightmost column, when input and weight match, output is 1; and when input and weight differ, output is -1. FIGS. 10-13 show an embodiment of the realization of a neural network with binary inputs and binary weights in an SLC NAND array.FIG. 10 shows an embodiment for a unit synapse cell for storing a binary weight in a pair of memory cells FG1 and FG2 connected in series. In this example, each of the memory cells is an SLC cell that stores one of two states and may be part of a larger NAND string. Memory cells FG1 and FG2 may be flash memory cells and are programmed or erased by respectively adding or removing electrons from a charge storage layer or floating gate and are sensed by applying corresponding voltages V1 and V2 to their control gates. If memory cells FG1 and FG2 are part of a larger NAND string that includes additional unit synapse cells or other memory cells, the pair of memory cells on the NAND string may be adjacent or separated by other memory cells that make up the NAND string. In the following discussion, the individual memory cells of a unit synapse cell are shown as adjacent, but other arrangements are possible depending on the embodiment. For example, the upper half of a NAND string could include the first memory cell of each unit byte, while the second memory cell of each unit byte is in the lower half of the NAND string. In each of these arrangements, when a given unit snap is sensed, the other memory cells and select gates on the same NAND string are biased so that both the memory cells of the unselected unit snaps and all other memory cells conduct, along with the select gates, are conducting.FIG. 11 shows the distribution of threshold voltages for storing data states in an SLC memory. In this embodiment, the cleared negative threshold state is assumed to be a "1" state and the positive threshold state is assumed to be a "0" state. FIG. 10 shows a typical distribution of the threshold voltage of the memory cells of a set of memory cells, for example an erase block or an entire array, after the memory cells have been erased (herein assigned to state "1") and the memory cells are programmed to the positive threshold states (herein assigned to state "0"). As further explained with reference to FIGS. 12 and 13, a binary weight has one memory cell of a unit synapse in the "0" state and the other memory cell in the "1" state. More generally, the "1" state need not be a negative threshold state as long as the two states correspond to a lower threshold state, herein defined as the "1" state, and a higher threshold state, herein defined as the "0" state.For sensing the memory cells having the threshold distribution shown in FIG. 11, a first voltage level Vread is used to distinguish between the data states, so that the memory cell, when applied to the control gate of a memory cell, conducts in the "1" state and does not conduct in the "0" state. For example, if the "1" states are a negative threshold voltage state and the "0" states are a positive threshold voltage state, Vread could be taken as 0V. A second sense voltage Vpass is high enough that a memory cell will conduct in each state. For example, Vpass could be several volts. Hereinafter, Vread is defined as an input voltage value "0", and Vpass is defined as an input voltage value "1".In implementations of NAND flash memory, a number of different voltage levels are often used for scan operations in both program verification and read operations for SLC and MLC memories. For example, a program test level for a given data state may be offset from the read voltage level for the same data state. Different levels for passing voltages at different operations and conditions may also be used to place a memory cell in a conductive state regardless of its stored data state. For simplicity of the discussion below, only the single Vread voltage is used to distinguish between data states and only the single Vpass voltage is used when a memory cell or select gate is to be placed in a conductive state for all stored data state values.FIGS. 12 and 13 show an embodiment for implementing a binary neural network using a pair of the SLC memory cells connected in series as a unit synapse. Specifically, FIG. 13 shows an embodiment for the correspondence between the input logic, the weight logic, and the output logic of FIG. 9, and the input voltage patterns, the threshold voltage Vth of the memory cells of the unit synapse, and the output voltage, respectively. Figure 12 is a schematic illustration of the response of a unit synapse to the various cases.In Figs. 12 and 13, a logic input of -1 corresponds to the input voltage pattern of V1=Vpass="1", V2=Vread="0"; and a logic input of +1 corresponds to the input voltage pattern of V1=Vread="0", V2=Vpass="1". A weight logic of -1 corresponds to the state of memory cell FG1 "0" (programmed) and the state of FG2 "1" (erased state); and a weight logic of +1 corresponds to the state of memory cell FG1 "1" and the state of FG2 "0". Output logic of +1 corresponds to the unit snap that conducts current Icell, resulting in an output voltage drop of ΔV across the unit snap; and output logic of -1 corresponds to the unit snap that does not conduct, resulting in little or no output voltage drop across the unit snap.Figure 12 schematically shows the four cases of input weight pairs. In case 1, the input and the weight both coincide with the values of -1. The applied input voltage pattern applies the higher input voltage of Vpass, or "1", to the upper cell having the higher Vth "0" data state and the lower input voltage of Vread, or "0", to the lower cell having the lower value of Vth "1" data state, such that cells are conductive and pass a current of Icell. In case 2, the input voltage pattern is reversed with respect to case 1, with the input logic now at +1, while the weight is at -1. This results in a lower Vpass, or "0", voltage level being applied to the upper cell of higher Vth, which is thus non-conductive (as indicated by the X below the memory cell), and no appreciable current flows through the pair.For cases 3 and 4 at the bottom of Figure 12, the weight value is now +1, with the lower Vth state "1" programmed into the upper cell and the upper Vth state "0" programmed into the lower cell. In case 3, the input voltage pattern -1 is applied to the unit synapse, resulting in the lower cell not conducting when receiving the lower voltage level Vread, or "0". In case 4, the higher Vpass or "1" input is now applied to the lower memory cell, which consequently conducts, and the unit synapse conducts the current Icell.As shown in the embodiment of FIGS. 12 and 13, the use of a pair of series-connected memory cells of FIG. 10 as a unit synapse may be used to implement the binary neural network logic table of FIG. 9. The unit synapses may be integrated into larger NAND strings of multiple such series-connected unit synapses. When a selected unit synapse on a NAND string is sampled, other unit synapses on the same NAND string can be biased using a Vpass voltage, and the NAND string selection gates are also biased.The use of NAND flash memory to store the weight and compute the dot products of inputs and weights in the array can be used in both the training and inference phases. The training phase may continue as in the flow of FIG. 7A, where step 709 would delete the weights as needed and reprogram them to adjust the weights until it is determined in step 707 that they are sufficiently accurate. The present discussion focuses primarily on the inference phase in which the weights were previously determined in a training process and then loaded into NAND memory by programming the unit synapses to the determined binary weight values.One technique for improving the accuracy of a binary weight neural network is to use a 3-value or ternary in a ternary input and binary weight neural network (TBN). In such a TBN network, the logic table of Figure 9 continues to apply to inputs -1 and +1, but is now extended by a third input value of "0" for which the output is now weight independent and "-1" for one of the weight values. Figures 14 and 15 correspond to Figures 12 and 13 which are extended to include a "0" input logic value as cases 5 and 6. Since the weights are still binary, the unit synapse and the allocation of data state and input voltages may be the same as shown in FIGS. 10 and 11.In the table of Fig. 15, the upper four rows for cases 1-4 are the same as for Fig. 13, but extended to include an input logic value "0" for implementing a ternary input. Cases 5 and 6 correspond to logic weight values -1 and +1, respectively, but now with a logic input value of "0". The binary weight values are implemented in the unit synapse as before, but the input logic "0" is implemented by applying the low input voltage of Vread, or "0", to the control gates of both memory cells of the unit synapse. This is schematically illustrated in FIG. 14.Fig. 14 repeats cases 1-4 of Fig. 12 and adds cases 5 and 6. As shown for case 5, when Vread, or "0", is applied to both control gates and the upper memory cell for weight -1 is programmed to the high Vth "0" data state, the unit synapse will not conduct, as represented by the X below the non-conductive memory cell. For case 6, for weight +1, the unit synapse lower memory cell is programmed to the high Vth "0" data state, and the unit synapse will not conduct again as represented by X. This is shown in Figure 15 where both cases 5 and 6 have an output logic of -1, which corresponds to no discharged current and no output voltage drop.FIG. 16 illustrates the incorporation of the unit synapses into a NAND array as in the memory structure 326 of FIG. 5, FIG. 16 illustrates a block of a potentially larger array of multiple blocks, each having a plurality of NAND strings connected between a source line 1615 and a corresponding bit line BLi 1603i. A typical NAND memory array is formed of many such memory blocks. Each NAND string is composed of a number of row memory cells connected in series between a source side selection gate SSLi 1609i through which the NAND string is connected to the source line 1615, and a drain side selection gate DSLi 1607i through which the NAND string is connected to the corresponding bit line BLi 1603i.The memory cells along each NAND string are paired into unit synapses of a pair of memory cells storing a weight W i,j as represented by the unit synapse of FIG. 10. Each of the NAND strings may include one or more unit synapses connected in series, with the embodiment of FIG. 16 showing 32 unit synapses per NAND string. Each unit synapse can store a binary weight and is connected along a pair of word lines WL<j> 1605j and WL'<j> 1605'j that receive a corresponding logic input Input<j> corresponding to the voltages of Fig. 13 for the binary input case and Fig. 15 for the ternary input case. The word line pairs WL<j> 1605j and WL'<j> 1605'j span the columns of the NAND strings of the block. In the embodiment of FIG. 16, the memory cells are adjacent to a unit synapse on the NAND string, but other arrangements may be used such that the memory cells of the synapses are interleaved rather than contiguous; and although the discussion herein focuses on binary weights using two SLC memory cells per synapse, other embodiments may use more memory cells per synapse unit, multi-level memory cells, or both to store neural network weights having more than the two values of the binary example. Although the NAND strings consist of charge storing flash memory cells in the embodiment shown, other memory cells having the same array architecture may also be used.The determination of the output of a unit synapse 1601i,j storing the weight W i,j can be determined by applying an input voltage logic pattern to the corresponding input at the input<j> while the other memory cells and selection gates of the selected NAND string are biased to be ON. Based on the input logic and weight logic, the unit synapse storing 1601i,jweight W i,j will either conduct or not conduct as shown in the table of FIG. 15, which may be determined by the corresponding sense amplifier SAi 1611i. As discussed further below, for each bit line, a corresponding digital summing circuit CSCi 1613i may track on a counter basis how many of the unit synapses pass along the bit line in response to the inputs, sum these values, and the sense amplifiers and summing circuits may be part of the sense blocks 350 of FIG. 5. The same input<j > is applied simultaneously to all unit synapses 1601i, where j stores the weight W i,j for all bit lines BLi 1603i, thereby biasing the selection gates of the corresponding selection gates SSLi 1609i and DSLi 1607i. Thus, the same input can be applied simultaneously to multiple synapses. The various synapses along the NAND strings may be sequentially selected for sensing, and the results along each bit line BLi 1603i are accumulated by CSCi 1613i. In a NAND memory, one page is the unit of read and program, the read page and the programmed page normally being considered the same, such as the entirety of the memory cells connected along a word line or a portion of the memory cells connected along a common word line. For programming, the data of the unit synapses along a single word line would still be programmed word line by word line; however, with respect to a standard NAND memory operation in which the aim is to determine the data content of the individual memory cells, reading of one page of the binary weight unit synapses is performed in word line pairs, so that the read page can be taken corresponding to one word line pair in this case.The arrangement shown in Figure 16 can be used for both binary neural networks (BNNs) where both the weights and the inputs are binary and ternary binary neural networks (TBNs) where the weights are binary but the inputs are ternary. However, referring again to Figure 15, for the case of the ternary input, the output of the sense amplifiers is the same for both cases 2 and 5 and also the same for cases 3 and 6. As the comparison of cases 2 and 5 shows, in a weight logic of -1, both input +1 and input 0 result in the unit synapse not conducting, so that the sense amplifier does not detect a voltage drop. Similarly, as the comparison of cases 3 and 6 shows, with +1 weight logic, both input -1 and input 0 result in the unit synapse not conducting, so that the sense amplifier detects no voltage drop. Consequently, only based on the conduction state of the NAND string, the cases 2 and 5 and the cases 3 and 6 cannot be distinguished.Referring again to FIG. 8, matrix multiplication is a multiple sum product (scalar product) calculation for input weight vector pairs (row column of input matrices) used for re-tracking in a neural network. FIGS. 17 and 18 illustrate an example of calculating a dot product for the binary neural network algebra and how to implement using a counter-based summing digital circuit for an embodiment of an SLC NAND BNN. More specifically, although a binary neural network based on the logic shown in the table of Fig. 8 is based on the weights, inputs and outputs having the values of either +1 or -1, when implemented by a NAND array as shown in Fig. 16, a sense amplifier is registered as either conductive ("1") or non-conductive ("0"). Thus, to accumulate the results for calculating the dot product of the matrix multiplication, the counter-based digital summation circuits CSCi 1613i require conversion of the (+1, -1)-based values to a (1,0) basis, substituting 0 for the -1 values.The table of FIG. 17 considers the dot product of the example of an input vector I bnn of a 8-element binary neural network over the upper row and a weight vector W bnn of a 8-element binary neural network in the second row when all vector elements are quantized to -1 / +1. The third row illustrates the element-by-element product of I bnn and W bnn, equal +1 if the two match, and -1 if they differ. The dot product is then based on summing these bit-by-bit products to produce the dot product P bnn_dec of the two vectors. In the decimal system, the last correct result of the addition of these values is calculated as P bnn_dec= 2.In the upper two lines of the table of Fig. 18, the input vector I bnn and the weight vector W bnn for the same vectors as in Fig. 17 are converted to the 1 / 0 binary base. The third row of Figure 18 shows the corresponding sense amplifier output, which is the bitwise XNOR value of the two vectors, which is 1 if the values match and 0 if the values differ. By accumulating these values from the sense amplifiers SAi 1611i in the respective summing circuits CSCi 1613i to determine their sum, this generates a popcount CNT bnn_out, which corresponds to the values of the number 1. In the example of FIG. 18, CNT is bnn_out= 5, which is different from the value p bnn_dec= 2 of FIG. 17 as a result of a mismatch in the input, and the weight is now a 0 instead of a -1.To correct this and determine p bnn_dec in the binary system, a substitution of the output of the popcount operand CNT bnn_out in eq. 1 to obtain a derived; where S is the size of the vector. In this example, S=8, such that p is bnn_dec= 2*5 - 8 =2 which is exactly P bnn_dec=2 for the dot product of FIG. 17.FIG. 19 is a flow diagram for an embodiment of a dot product calculation using a binary neural network in inference as shown in FIGS. 17 and 18. In step 1901, a first input value is applied to a weight of a first unit synapse to perform multiplication within the array. Referring again to FIG. 16, this corresponds to applying an input value<j> to a corresponding selected unit synapse 1601i, where j stores the weight W i,j on a bit line BLi 1603i, for example, input<0> applied to the lowermost unit synapse on BL0. In step 1903, the corresponding sense amplifier SAi 1611i determines whether or not the NAND string is conducting (1) (0) corresponding to an XNOR of the input and weight values. Step 1905 performs the accumulation, wherein the sampling result is added to a CNT bnn_out- value maintained by the counter CSCi 1613i. In step 1907, it is determined whether there are more input / weight pairs to contribute to the dot product corresponding to another input / weight pair for the NAND (or for other NAND strings on other blocks connected along the bit line) and if so, loops back to step 1901. If all input / weight pairs for CNT bnn_ou of the dot product have been calculated and summed, then flow proceeds to step 1909, to convert the popcount CNT bnn_out- value to dot product p bnn_dec using Eq. 1. (Step 1908 distinguishes between the binary input and ternary input cases, as discussed below). In the example of the tables of FIGS. 17 and 18, the value "S" for Equation 1 would be 8, while for an entire NAND string as shown in FIG. 16, S=32. It should be noted that the NAND array structure of FIG. 16 enables calculation of a dot product according to the flow of FIG. 19 that is performed simultaneously along each bit line.FIGS. 20 and 21 illustrate an example that extends the computation of a dot product for a ternary input binary weight neural network and how this is implemented using a counter-based digital summation circuit for an SLC NAND TBN embodiment. Figure 20 corresponds to Figure 17 of the BNN case, where the input values can now include values 0 as well as -1 and +1. This is illustrated by the example of a ternary input vector I tbn which includes values of -1, 0 and +1. The weights are again a binary input vector W tbn with values of -1 and +1. The output values of the third row are as before for the values -1 and +1 and are +1 if the weight and input match and are -1 if they differ but with an output of 0 for an input of 0 for both weight values. The scalar product P tbn_dec then corresponds to the summation of the output values and yields a result of 1 in this example.Figure 21 assigns these TBN inputs and weights to values 0 and 1. As shown in Figure 18, for both weights and inputs, the +1 value is mapped to 1 and the -1 value to 0. However, the 0 input value is now also mapped to 0. This is shown in lines I bin and W bin in the table in FIG. 21. When I bin and W bin are subjected to XNOR, as seen due to the current at the sense amplifier, this may result in invalid outputs for the 0-I bin- values, as shown in the sixth column, which has a sense amplifier output of 1 in the table of FIG. 21, whereas in the table of FIG. 20 the corresponding output value is 0. This results in a popcount value CNT tbn_dec= 4. Thus, a method is required to adjust the output of the counter-based digital summation circuits CSCi 1613i of FIG. 16 to account for these anomalous results for 0 ternary input values.If the same method is used as for the binary case with Eq. In FIG. 1, this also leads to an incorrect output result: for example, in the case of FIGS. 20 and 21, the equation gives. 1 P bnn_dec= 4*2-8=0, the correct result being 1. However, by discarding the XNOR outputs from the sense amplifiers corresponding to 0 inputs, it is possible to obtain an adjusted correctly derived P tbn_dec using Eq. 2: wherein S tbn= S-Z, S is again the size of the vector and Z is the number of zero inputs. When applied to the example of Figures 20 and 21, this results in the output XNOR (sense amplifier output) for the (ternary) 0 inputs of columns 2, 3 and 6 being discarded, so that Z=3 and S tbn= S - Z= 5. The new CNT tbn_out= 3, since the XNOR value of column 6 is now discarded, since it originates from a (ternary) 0 input. Using the adjusted derived P tbn_dec for TBN can be obtained from Eq. 2: P tbn_dec= 2*3 - 5 = 1.Referring again to FIG. 19, step 1908 determines whether the memory array is operating in a binary input mode (BNN) or a ternary input mode (TBN). (The mode may be established based on the ZID_Enb control signal, as described further below with reference to FIG. 22 ). In binary mode, flow proceeds to step 1909, as described above, and uses Eq. 1. in the ternary input mode, the flow instead proceeds to step 1911 and uses Eq. 2 to convert the popcount CNT tbn_out to P tbn_dec.FIG. 22 shows an embodiment of the summation circuit for an SLC NAND array for supporting ternary binary neural networks. As illustrated in the high level architecture of Figure 22, circuitry is introduced to provide early detection of 0 inputs and then to discard the effects of the 0 inputs shown at the outputs of the gating amplifiers. In particular, FIG. 23 repeats many of the elements of FIG. 16 in a somewhat simplified form, but also includes a zero input detection (ZID) unit 2201 and shows a word line decoder block 2211.The ZID unit 2201 is connected to the word line pairs WL<j>, WL'<j> to detect 0 input data encoded as the two word lines set to Vread. As shown in the table of Figure 15, for ternary inputs -1 and +1, the voltage levels for WL<j > and WL'<j > of a selected unit synapse differ, but are the same for input 0. For unselected unit synapses on the NAND string, both WL<j> and WL'<j> are set to the same voltage level of Vpass. Thus, for a 0 input to the selected unit synapse, the voltage levels on each pair of word lines will match; however, for a -1 or +1 input to the selected unit synapse, one of the word line pairs (that of the selected unit synapse) will not match, while the voltage levels of the other word line pairs (that of all the selected unit synapses) will match. In order to determine whether the voltage levels of the word line pair WL<j>, WL'<j> coincide for the applied input voltage pattern, a NOR logic block 2203j is connected to each of the word line pairs. The output of the NOR logic blocks 2203j is connected to a combinational logic circuit CL 2205 for determining whether all word line pairs match (a 0 input to the selected unit synapse) or whether one of the word line pairs does not match (a -1 or +1 input for the selected unit synapse).Based on these inputs, combinational logic circuit CL 2205 generates a block control signal (BSC) which is supplied to digital summation circuits CSCi 1613i on a counter basis of each of the bit lines. Each CSC unit CSCi 1613i may increase the count value or, when a 0 input is detected, overwrite the output of the sense amplifier in the accumulation process and discard the invalid output of the sense amplifiers SAi 1611i under the control of the BCC signal. The ZID circuit 2201 does not increase the latency of a NAND read command and the ZID logic is not in the critical path of NAND commands. A binary neural network may be implemented in the ternary-binary architecture of FIG. 22 by disabling the ZID circuit 2201 using a ZID_Enb control signal that could be based on a mode register value, for example.FIGS. 23A and 23B provide two embodiments for combinational logic circuitry CL 2205. In both cases, for M word line pairs, the M inputs are the outputs of the M-NOR logic blocks 2203i and the output is the BCC signal. The embodiment of FIG. 23A uses an OR logic reduction tree to reduce the M outputs from the NOR logic blocks 2203i. The embodiment of FIG. 23B uses a tri-state based circuit in which each tri-state element has a "1" at the A input and the output of the corresponding NOR logic blocks 2203i at the B input.FIG. 24 is a flow diagram for an embodiment of a dot product calculation using a ternary binary neural network in inference as shown in the tables of FIGS. 20 and 21 and the array architecture of FIG. 22. Beginning with step 2401 and referring to Figure 22, the memory array receives an input<j > and translates it into a set of voltage values, wherein in a ternary input the voltage pattern of the input may correspond to a -1, 0 or +1 input value; and in step 2403 applies the voltage level to a word line pair WL<j>, WL'<j> 1605j, 1605'j. Since the word lines span the NAND string of the selected block, the process of FIG. 24 can be simultaneously performed for each of the NAND strings for the unit synapses connected along the word line pair WL<j>, WL'<j> 1605j, 1605'j. In addition, in the NAND structure, the other elements of a selected NAND string (SSLi 1609i, DSLi 1607i and the unselected memory cells of the NAND string) are biased to be turned on, such as applying Vpass in step 2405. Although listed as an ordered set of distinct steps in FIG. 24, steps 2403 and 2405 are typically performed simultaneously by word line decoder 2211.In step 2407, NOR logic block 2203j determines whether the voltage pattern of input<j> matches a 0 input corresponding to the voltage level on both word lines of the pair WL<j>, WL'<j> 1605j, 1605'j, matching the Vread voltage in the embodiment of this example. The output of the NOR logic blocks is received at the combinational logic circuit CL 2205, and when the ZID_Enb signal is activated, the BCC signal is generated and supplied to the CSC circuits 1613i. When the circuit is used in the binary input BNN mode, the signal ZID_Enb is not activated and the CSC circuits 1613i may operate as shown in the table of FIG. 13.Step 2409 determines the conductivity of the set of memory cells of the selected unit synapse. As shown in the table of Fig. 15, the conductivity of the NAND string corresponds to the output logic value of the unit synapse in response to the input and can be determined by the sense amplifier SAi 1611i. Based on the conductivity state of the unit synapse and the value of the block counter control signal (BCC), in step 2411, the count value of the corresponding CSCi 1613i is either incremented or not, as described above with reference to Eq. In this manner, the FIG. 2 and the table of FIG. 21 are discussed such that the misderivated contributions to P tbn_dec are omitted, the result of the sense amplifier is overwritten, and the 0 input contributions in the count are ignored.Step 2413 determines whether there are more input weight pairs to add to the dot product, and if so, the flow returns to step 2401. Once the contributions of all input weight pairs to the dot products have been determined, the dot product may be provided in step 2415. The set of dot products determined in step 2415 may then serve as input to a subsequent neural network layer or as output of the inference process.FIGS. 25 and 26 illustrate an example of a neural network and its implementation by a NAND array. In the process described above with reference to FIG. 24, the response to an input of a unit synapse along each bit line is determined based on whether or not the corresponding sense amplifier determines that the unit synapse is conducting. For a given block, the contribution of each of the synapses along a NAND string is sequentially determined by the sense amplifiers.Figure 25 shows an example of three fully connected layers each having four nodes so that the weight matrix between layers is a 4x4 matrix. In FIG. 25, the inputs to the nodes are labeled I l,i,n where I is the layer index, i is the input index, and n is the neuron index. In the example of Fig. 25, three layers are shown, I = (0,1,2), and each has four nodes, n = (0,1,2,3). (The input index is used in some of the following examples for increased parallelism.) The weight matrices W l,n,n, which connect the layers, are then 4x4, the matrix multiplication to form the scalar products from the inputs of one layer to the next being:The inputs of one layer are applied as voltage patterns on the word line pairs to the unit synapses to produce scalar conductance values which are the inputs of the next layer.Figure 26 is a schematic illustration of how these weight matrices are stored in the unit synapses of a NAND array for the in-array calculations of the matrix multiplication. Referring to FIG. 22, the block (referred to herein as block 0) is represented in terms of the weights stored in the unit synapses, rather than the corresponding memory cell pairs. The voltage level input patterns are indicated as a single input, rather than the voltage levels applied to the respective word line pairs. The weight matrix between a pair of layers is then stored in a number of unit synapses along a number of NAND strings, the number of unit synapses per NAND string and the number of NAND strings corresponding to the size of the weight matrix. In this example for 4x4 weight matrices, this corresponds to 4 unit synapses along 4 NAND strings. As shown in Fig. 26, these are 4 adjacent unit synapses on 4 adjacent bit lines, but these may be distributed differently over the block depending on the embodiment.Referring to the diagram of Fig. 25, a weight matrix is stored in transposed form on the NAND array. For example, the weights from the various inputs of the first layer of FIG. 25 are stored in the upper node 2501 of the second layer along the first NAND string connected to BL0; and the weights in the lower node 2503 are stored along the fourth NAND string connected to BL3. To illustrate the match, reference numerals 2501 and 2503 are also used in Figure 26 to illustrate the placement of the corresponding weights in these nodes.To compute the various dot products of the matrix multiplication, the data inputs are provided in a sequence of read instructions. To calculate the output of a single layer, the pages of weights are then read sequentially by the sense amplifiers over four cycles, in this example:Cycle 1: I reaches 0,0,0* W reaches 0,0,0Cycle 2: I reaches 0,0,1* W reaches 0,0,1Cycle 3: Reaches I 0,0,2* W 0,0,2Cycle 4: I reaches 0,0,3* W reaches 0,0,3,wherein each of the cycles corresponds to a loop in the flow of FIG. 24, and different scanning orders may be used in different embodiments. The results of the cycles are sampled by the sense amplifier SA on each of the bit lines and accumulated in the CSCs subtracting the value represented in the PCC signal to discard the influence of zero inputs, in which the latency of the accumulation process is hidden among the simultaneous multiplication operations for the following read cycles. The output P tbn_dec of each bit line will then be the inputs I l+1,i,n of the next layer.FIG. 27 illustrates an example of a neural network and its implementation by a NAND array to achieve high parallelism across NAND blocks by exploiting multiple blocks in a single plane. In the process described above with reference to FIGS. 24 and 26, the response to an input of a unit snap along each bit line is determined based on whether or not the corresponding sense amplifier determines that the unit snap is conducting. FIG. 27 illustrates an embodiment using a multi-bit sense amplifier, such as one that can distinguish between different current levels, thereby allowing multiple blocks in a single plane to be simultaneously sensed.In a standard read operation in which the aim is to determine the data state stored in a memory cell, the determination is made by a sense amplifier based on a current or voltage level along a bit line based on whether or not the selected memory cell is conductive. If multiple cells along a common bit line were sampled simultaneously, with some conducting and others not conducting, it would not be possible to determine which of the individual memories are the conducting cells of the memory cells and establish their corresponding data states. However, for the output of the counter P tbn_dec from the matrix multiplication, only the sum of the number of unit synapses which conduct in response to the inputs is important, but not which of the individual synapses contribute to it. As a result, the response of multiple unit synapses to different blocks may be determined simultaneously in response to a corresponding set of inputs, thereby increasing parallelism when the sense amplifier may determine the number of conductive synapses. By integrating multiple sense amplifiers, the embodiment of Figure 27 allows multiple unit synapses along a common bit line of different blocks to be sampled in parallel.Figure 27 is arranged similar to Figure 26 and is again shown storing the same 4x4 weight matrix connecting the first two layers of Figure 25. Figure 27 differs from Figure 26 in that the weights are now distributed between two different blocks, here denoted block 0 and block 1. However, these may be any two blocks of the same level and the discussion may be extended to more than two blocks to further increase parallelism. As explained above with reference to Figures 25 and 26, the weight matrix is again stored in a transposed form.Fig. 27 also differs in that the block counter control BCC of all sampled blocks must be considered in order to properly offset the CSC counts for 0 input values. The plane counter control (PCC) is a multibit signal indicating the total number of zero inputs present in the L blocks of a plane. Since only one input is assigned to a particular block at a time, at most one zero input per block is fed into the count BTC block logic in each cycle of a sequence of read commands to determine the number of ones from the various blocks. The CSCs subtract the value represented in the PCC signal to change the count and discard the effect of zero inputs that exist in the multiple blocks being accessed in parallel. The multiple blocks sharing a multi-bit sense amplifier and a CSC may then be accessed in parallel to calculate the output of a single layer of neural network.To perform matrix multiplication, data inputs are provided in a sequence of read commands, but to calculate the output of a single layer, multiple blocks are now read in parallel (one page with unit synapses per block). In the example of FIG. 27, for the matrices of FIG. 25 in which two blocks are activated simultaneously, an output of a layer may be calculated within a latency of 2 cycles:Cycle 1: Reaches I 0,0,0* W 0,0,0+ I 0,0,2* W 0,0,2Cycle 2: Reaches I 0,0,1* W 0,0,1+ I 0,0,3* W 0,0,3wherein cycle 2 is accumulated while the output for cycle 1 is calculated so that the accumulation latency is hidden from simultaneous multiplication operations.FIG. 28 is a flow diagram for an embodiment of a dot product calculation similar to FIG. 19, but including the multi-block parallelism illustrated in FIG. 27. Referring now to step 1901, sampling multiple blocks in parallel in step 2801 may apply multiple inputs simultaneously in each loop. In step 2803, the output of the sense amplifier is now a multi-bit value instead of the binary value of step 1903, and corresponds to the number of unit conductive synapses along a bit line. The multibit value is then accumulated in step 2805, steps 2805, 2807, 2808, 2809 and 2811 corresponding to steps 1905, 1907, 1908, 1909, and 1911 of Fig. 19.To further increase parallelism, the number of simultaneously sampled blocks can be increased beyond the two shown in the example of Figure 27 up to the total number of inputs for the layer. The degree of parallelism can be based on considerations including the amount of resultant current that would be drawn and the level of resolution that can be reasonably achieved by the multi-bit sense amplifiers from the available current window.FIG. 29 illustrates additional embodiments that may further increase parallelism using an architecture that may simultaneously infer the inputs of a neural network via multiple levels. The multi-level implementation may be used to scan a single block simultaneously in each level (as in FIG. 26 ) or for multiple blocks simultaneously in each level (as in FIG. 27 ). The example of Figure 29 is again based on the example of the network of Figure 25 and uses two layers and two blocks in each layer, although both the number of layers and that of the blocks may be extended.Figure 29 shows two planes, plane 0 and plane 1, for an embodiment in which two blocks per plane are scanned simultaneously, which planes may be on a common chip or on another chip. For both level 0 and level 1, the weights are stored as in Figure 27 and the other elements are also repeated from Figure 27. If the layers differ, this is the input index for the two layers with the I 0,0,n inputs for layer 0 and the subsequent set of inputs for the layer of I 0,1,n for layer 1.In block-level parallelism, the memory may use multiple blocks of a single level to calculate an output of a single layer, and the read commands may be issued in parallel to access multiple blocks as described with respect to 27 Figure with a page (the unit synapses) accessed per block in a cycle. By adding the level-level parallelism of Figure 29, multiple levels can be used to calculate multiple outputs of a single layer by storing the same weight matrix in both levels and providing data for both levels in parallel. In the embodiment of FIG. 29, using 2 levels of 2 blocks / level in parallel, the two outputs of a single layer may be calculated within a latency of 2 cycles, with the accumulation latency being hidden under multiplication (read command).Parallelism can also be increased by using level pipelining, where the output of one level (corresponding to matrix multiplication between one node set) can be used as the input of another level (corresponding to matrix multiplication between the next node set). Level pipelining may also be combined with block level parallelism, level level parallelism, or both to achieve even greater parallelism levels.FIG. 30 illustrates an embodiment of a planar line for various neural network layers. Referring again to the example of FIG. 25, the first stage in the pipeline stores the weight matrix between layers 0 and 1 and the next stage stores layers 1 and 2 connected to the weight matrix. the example of FIG. 30 applies to two stages and also includes 2-level parallelism and 2-block parallelism, but these are independent aspects, respectively, and similarly more pipeline stages can be implemented, and the degree of parallelism of both stages at block level is higher when additional parallelism is included. The planes may be formed on a single chip or on multiple chips.At the top of FIG. 30, level 0,0 and level 0,1 are arranged as level 0 and level 1 for the embodiment of FIG. 29, and receive inputs I 0,0,n for level 0,0 and I 0,1,n for level 0,1 level 0,0 and level 0,1 calculate the outputs of the 0-layer using parallelism at block and level levels to generate inputs I 1,0,n and I 1,1,n for the next stages in the pipeline of level 1,0 and level 1,1. At the bottom of FIG. 30, level 1,0 and level 1,1 are arranged in level 0,0 and level 0,1 as in the previous pipeline stage, but now store the weight matrix entries W 1,n,n( again stored in transposed form) of the second layer instead of the W 0,n,n- entries of the first layer. Then, by supplying the outputs of the first stage to the second stage and applying the inputs I 1,0,n and I 1,1,n to the matrix entries of layer-1, the outputs of layer-1 are calculated.It should be noted that the weights of different layers may be stored in the same block, level, or both, although this reduces the degree of parallelism, as the matrix multiplication of the different layers would not be performed simultaneously. This is illustrated by the embodiment of Figure 31.Figure 31 shows an embodiment in which weights of different layers can be stored in the same block, plane or, in this case, both. In particular, Fig. 31 shows a plane with the inputs for two layers in a plane with weights for each in the same block. In this example, the weights of layer 1 that were in plane 1,0 of Figure 30 are now in the same blocks as the weights of layer 0 that were in plane 0,0 of Figure 30. Thus, block 0 in FIG. 31 includes the weights for input<0> and input<1> for both layer 0 and layer 1, and block 1 includes the weights for input<2> and input<3> for both layer 0 and layer 1. The inputs I 0,0,n for layer 0 generate the outputs P n of I 1,0,n for layer 0 can then be calculated in a first set of reads as described with respect to FIG. 27. The I 1,0,n serve as input to layer 1, again as described with reference to Figure 27, but with the layer 1 weight matrix values W 1,n,n, to generate the layer 1 outputs in a second set of reads.The above embodiments present methods and architectures for realizing the inference phase of a neural network with ternary inputs and binary weights in a NAND memory structure. By using two memory cells connected in series as a unit synapse, binary weights of neural networks can be encoded and stored in a NAND memory array. Ternary inputs can be used using a simple zero input detection (ZID) circuit, which can adjust the final output of a counter-based digital summing circuit by eliminating errors caused by zero inputs in ternary binary neural networks. These techniques enable in-array implementations of matrix multiplication with improved inference accuracy when TBN is applied to large data sets and complicated deep neural network (DNN) structures.With respect to a standard NAND-based architecture, the described embodiments present some small feature changes for the existing NAND memory architecture to support various levels of computational parallelism. No circuit changes are required for the program and erase operations. A modification is introduced to row, block and / or plane decoders to control read operations to sample weights stored on the two cell unit synapses because they use a doubleword line selection with different voltage control and multiple block selections for multi-block embodiments. To detect 0 inputs, a modified digital summation circuit based on counter is introduced together with a zero input detection circuit. By the introduction of a multibit sense amplifier, parallel computation across blocks and planes can also be used.According to a first set of aspects, a device includes a source line, a bit line, and a plurality of word lines. A NAND string is connected between the source line and the bit line, the NAND string including a plurality of nonvolatile memory cells each connected to a corresponding one of a plurality of word lines. A sense amplifier is connected to the bit line and is configured to determine a conductivity state of the NAND string in response to a set of voltage levels applied simultaneously to the plurality of word lines. A logic circuit is connected to the plurality of word lines and a counter circuit is connected to the sense amplifier and to the logic circuit. The counter circuit is configured to increment a count value in response to the conductivity state determined by the sense amplifier and to change the increment of the count value in response to an output from the logic circuit indicating a pattern of voltage levels applied to the plurality of word lines.In additional aspects, a non-volatile memory circuit includes an array of non-volatile memory cells arranged as NAND strings and configured to store one or more binary weights of a neural network, each weight stored in a pair of non-volatile memory cells on a common NAND string, and one or more control circuits connected to the array of non-volatile memory cells. The one or more control circuits are configured to: receive one or more inputs for a neural network layer and convert the one or more inputs to one or more corresponding voltage patterns from a set; apply the one or more voltage patterns to the array of non-volatile memory cells to thereby perform an in-array multiplication of the one or more inputs with the weights; accumulate the results of the in-array multiplication; and determine a number of the one or more voltage patterns corresponding to a first voltage pattern and adjust the accumulated results of the in-array multiplication based on the number of the one or more voltage patterns corresponding to the first voltage pattern.Further aspects include a method including receiving one or more input values and translating each of the one or more input values into a corresponding voltage pattern, each voltage pattern being one of a plurality of voltage patterns having a set of N voltage values. The one or more voltage patterns are applied to one or more NAND strings connected to a common bit line, wherein no more than one of the voltage patterns is simultaneously applied to a single one of the NAND strings, and the set of N voltage values is applied from each of the voltage patterns to corresponding N memory cells of a NAND string to which the voltage pattern is applied. The method further including: determining the number of the one or more NAND strings connected to the shared bit line that conduct in response to the one or more voltage patterns applied thereto; determining the number of the one or more voltage patterns that match a predetermined one of the plurality of patterns; incrementing a count based on the number of the one or more NAND strings connected to the shared bit line that conduct in response to the one or more voltage patterns applied thereto; and adjusting the count based on the number of the one or more voltage patterns that match a predetermined one of the plurality of patterns;For the purposes of this document, reference in the specification to "one embodiment," "some embodiments," or "another embodiment" may be used to describe various embodiments or the same embodiment.For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other portions). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" when they are directly or indirectly connected to each other so that they can transmit electronic signals to each other.For the purposes of this document, the term "based on" may be read as "based at least in part on.".For the purposes of this document, without additional context, the use of numerical terms such as a "first" object, a "second" object, and a "third" object may not imply a sort of objects, but may instead be used for identification purposes to identify different objects.For the purposes of this document, the term "set" of objects may refer to a "set" of one or more of the objects.The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thus enabling others skilled in the art to best utilize them in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

A non-volatile memory circuit comprising: an array of non-volatile memory cells arranged as NAND strings and configured to store one or more binary weights of a neural network, each weight being stored in a pair of non-volatile memory cells on a common NAND string; and one or more control circuits connected to the array of non-volatile memory cells, the one or more control circuits configured to: receive one or more inputs for a layer of a neural network and convert the one or more inputs into one or more corresponding voltage patterns from a set; apply one or more voltage patterns to the array of non-volatile memory cells to thereby perform an in-array multiplication of the one or more inputs with the weights; accumulate results of the in-array multiplication; and determining a number of the one or more voltage patterns corresponding to a first voltage pattern and adjusting the accumulated results of the in-array multiplication based on the number of the one or more voltage patterns corresponding to the first voltage pattern.The non-volatile memory circuit of claim 1, wherein: the one or more inputs are ternary inputs; and the first voltage pattern corresponds to a 0-ternary input value.The nonvolatile memory circuit of claim 1, wherein: the one or more inputs are a plurality of inputs; and the one or more control circuits are configured to simultaneously apply the corresponding plurality of voltage patterns to a plurality of NAND strings connected to a common bit line, thereby performing simultaneous in-array multiplication of the one or more inputs with the stored weights in the plurality of NAND strings connected to a common bit line.The non-volatile memory circuit of claim 1, wherein: one or more control circuits are configured to simultaneously apply a voltage pattern corresponding to a first input of the one or more inputs to a plurality of NAND strings each connected to another bit line, thereby performing a simultaneous multiplication of the first input within the array with the weights stored on the plurality of NAND strings each connected to another bit line.The non-volatile memory circuit of claim 1, wherein the one or more control circuits are additionally configured to: convert the adjusted accumulated results into a corresponding second set of voltage patterns; apply the second adjusted voltage patterns to the array of non-volatile memory cells to thereby perform a second multiplication within the array of the adjusted accumulated results with the weights and accumulate the results of the second multiplication within the array; and determine a number of the second set of voltage patterns corresponding to a first voltage pattern, and adjust the accumulated results of the second in-array multiplication based on the number of the second voltage pattern corresponding to the first voltage pattern.An apparatus comprising: a source line; a first bit line; a plurality of first word lines; a first NAND string coupled between the source line and the first bit line, the first NAND string including a first plurality of non-volatile memory cells each coupled to a corresponding word line, of a plurality of word lines; a first sense amplifier coupled to the first bit line and configured to determine a conductivity state of the first NAND string in response to a set of voltage levels simultaneously applied to the first plurality of first word lines; a logic circuit coupled to the first plurality of first word lines; and a first counter circuit connected to the first sense amplifier and the logic circuit, the first counter circuit configured to increment a first count value in response to the conductivity state determined by the first sense amplifier and change the increment of the first count value in response to an output from the logic circuit indicating a first pattern of voltage levels applied to the first plurality of first word lines.The apparatus of claim 6, wherein the first plurality of non-volatile memory cells is a first pair of non-volatile memory cells and the first plurality of first word lines is a pair of the first word lines.The apparatus of claim 7, wherein the first pair of non-volatile memory cells includes non-volatile memory cells in a programmed state and memory in an erased state.The apparatus of claim 7, wherein the first pattern of voltage level corresponds to applying the same voltage level to both of the pair of first word lines.The apparatus of claim 6, wherein the logic circuit is enabled in response to a control signal.The apparatus of claim 6, further comprising: a plurality of second word lines; and a second NAND string connected between the source line and the first bit line, the second NAND string including a second plurality of non-volatile memory cells each connected to a corresponding one of the second plurality of second word lines, wherein the first sense amplifier is additionally configured to determine the conductivity state as a combined conductivity state of the first NAND string and the second NAND string as a multi-bit value in response to a set of voltage levels simultaneously applied to the second plurality of second word lines, the logic circuit is additionally connected to the second plurality of second word lines, and the first counter circuit is further configured to change the incrementing of the first counter in response to an output from the logic circuit, indicating a first pattern of voltage levels applied to the second plurality of second word lines.The apparatus of claim 6, further comprising: a second bit line, a second NAND string coupled between the source line and the second bit line, the second NAND string including a first plurality of non-volatile memory cells each coupled to a corresponding one of the first plurality of first word lines, a second sense amplifier coupled to the first bit line and configured to determine a conductivity state of the second NAND string in response to a set of voltage levels simultaneously applied to the first plurality of first word lines; and a second counter circuit coupled to the second sense amplifier and to the logic circuit, the second counter circuit configured to increment a second count value in response to the conductivity state determined by the second sense amplifier and change the increment of the second count value in response to an output from the logic circuit indicating a first pattern of voltage levels applied to the first plurality of first word lines.A method comprising: receiving one or more first input values; translating each of the one or more first input values into a corresponding first voltage pattern, each first voltage pattern being one of a plurality of voltage patterns comprising a set of N voltage values; applying the one or more first voltage patterns to one or more NAND strings connected to a common bit line, wherein no more than one of the first voltage patterns is simultaneously applied to a single one of the NAND strings, and the set of N voltage values of each of the first voltage patterns are applied to corresponding N memory cells of a NAND string to which the first voltage pattern is applied; determining a number of the one or more NAND strings connected to the shared bit line that conduct in response to the one or more first voltage patterns applied thereto; determining a number of the one or more first voltage patterns that match a predetermined one of the plurality of patterns; incrementing a first count based on the number of the one or more NAND strings connected to the shared bit line that conduct in response to the one or more first voltage patterns applied thereto; and adjusting the first count based on the number of the one or more first voltage patterns that match a predetermined one of the plurality of patterns;The method of claim 13, wherein N = 2 and the number of the plurality of input patterns is three.The method of claim 14, wherein the predetermined one of the plurality of voltage patterns corresponds to the two voltage values of the set of voltage values being equal.The method of claim 14, wherein the two memory cells to which each of the first voltage patterns is applied include a first memory cell in an erased state and a second memory cell in a programmed state.The method of claim 13, wherein: the one or more first inputs are a plurality of first inputs; the one or more NAND strings connected to the shared bit line include a first NAND string; applying the first voltage patterns to the NAND strings connected to a shared bit line includes sequentially applying each of the plurality of first voltage patterns to different N memory cells of the first NAND string; and determining the number of NAND strings that conduct in response to the first voltage patterns applied thereto includes determining the number of times the first NAND string conducts in response to sequentially applying the plurality of first voltage patterns thereto.The method of claim 13, wherein: the one or more first inputs are a plurality of first inputs; the one or more NAND strings connected to the shared bit line are a corresponding plurality of NAND strings; applying the first voltage patterns to the NAND strings connected to the shared bit line includes applying each of the plurality of first voltage patterns to the corresponding one of the NAND strings simultaneously; and determining the number of NAND strings that conduct in response to the first voltage patterns applied thereto includes performing a multi-bit sensing operation.The method of claim 13, wherein applying the one or more first voltage patterns to one or more NAND strings connected to a shared bit line further includes: biasing memory cells of the one or more other NAND strings different from the corresponding N memory cells to be in a conductive state.The method of claim 13, further comprising: receiving an enable signal, wherein determining the number of the one or more first voltage patterns that match the predetermined one of the plurality of patterns is performed in response to the enable signal.

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