Method for forming thin SOI substrates and SOI substrate

Abstract

A method of forming an SOI substrate (102), the method comprising: epitaxially forming a device layer (108) on a sacrificial substrate (602), Bonding the sacrificial substrate (602) to a handle substrate (104) such that the device layer (108) is located between the sacrificial substrate (602) and the handle substrate (104), Removing the sacrificial substrate (602), and cyclically thinning the device layer (108) until the device layer (108) has a target thickness, wherein each thinning cycle comprises oxidizing a portion of the device layer (108) and removing an oxide resulting from the oxidation, further comprising: Forming an insulating layer (106, 106s) on the device layer (108), the insulating layer (106, 106s) having a net charge that is negative and being located between the sacrificial and handle substrates (104) during bonding.

Description

State of the art

[0001] Integrated circuits are traditionally formed on bulk semiconductor substrates. In recent years, SOI (semiconductor on insulator) substrates have become popular as an alternative to bulk semiconductor substrates. An SOI substrate comprises a handle substrate, an insulation layer overlying the handle substrate, and a device layer overlying the insulation layer. An SOI substrate results in, among other things, reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance.

[0002] Publication US 2004 / 0 259 328 A1 discloses a manufacturing method for a substrate with a buried insulation layer. Porous silicon layers of varying porosity are grown over a sacrificial substrate, followed by a crystalline silicon layer whose surface is oxidized. A second substrate is bonded to the oxidized surface, and the composite substrate is subsequently cleaved at the interface of the porous silicon layers. The subsequently exposed crystalline silicon layer is etched back by cyclic etching.

[0003] Publication US 2010 / 0 176 495 A1 discloses a manufacturing method for an SOI substrate with two buried oxide layers, between which a conductive layer is arranged. An oxide layer, a conductive layer, and a second oxide layer are applied to a first substrate. A silicon-germanium sacrificial layer, a thin layer of epitaxially grown silicon, and an oxide layer are applied to a second silicon substrate. The second substrate is bombarded with hydrogen ions to form an implanted layer in the silicon-germanium layer, and the substrates are bonded to one another and cleaved in the region of the implanted layer.

[0004] Publication US 2007 / 0 032 040 A1 discloses a method for fabricating a multilayer semiconductor structure. The method comprises depositing a dielectric layer on a substrate and inducing a predetermined breaking point by ion implantation. The substrate is bonded to a second substrate with a high-resistivity layer, and the assembled substrate is subsequently cleaved at the predetermined breaking point to obtain an SOI substrate.

[0005] The publication US 2005 / 0 269 640 A1 discloses a method for producing MOSFIT devices. Short description of the drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1A and Fig. 1B show cross-sectional views of various embodiments of an SOI (semiconductor on an insulator) substrate without implant radiation and / or plasma damage. Fig. Figure 2 shows a cross-sectional view of some more detailed embodiments of the SOI substrate having insulation layers with different charges. Fig. Figure 3 shows a top view of some embodiments of the SOI substrate of Fig. 1A. Fig. Figure 4 shows a top view of some embodiments of a semiconductor structure in which the SOI substrate of Fig. 1A is used. Fig. 5 to 16, 17A, 17B, 18, 19A, 19B and 20 to 22 show a series of cross-sectional views of some embodiments of a method for forming and using an SOI substrate without implant radiation and / or plasma damage. Fig. Figure 23 shows a block diagram of some embodiments of the method of Fig. 5 to 16, 17A, 17B, 18, 19A, 19B and 20 and 22. Fig. 24 shows a block diagram of some embodiments of a method for performing thinning of device layers. Detailed description

[0007] The present disclosure provides many different embodiments, or examples, for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] A thin SOI (semiconductor on insulator) wafer with a device layer thickness between approximately 7 to 14 nanometers and an insulation layer thickness between approximately 12 to 20 nanometers can be used in fully depleted metal-oxide-semiconductor (MOS) devices and other advanced MOS devices. The thin SOI wafer promotes, among other things, lower leakage current and low power consumption for semiconductor devices formed over the device layer. According to one method for forming the thin SOI wafer, a bond wafer is oxidized to form an oxide layer surrounding the bond wafer. Hydrogen ions are implanted into the bond wafer over the oxide layer to form a hydrogen-rich region buried within the bond wafer.The bond wafer is bonded to a handle wafer via the oxide layer, and the bond wafer is cleaved along the hydrogen-rich region to partially remove the oxide layer and the bond wafer from the handle wafer. Chemical mechanical polishing (CMP) is then performed on a portion of the bond wafer remaining on the handle wafer to flatten the bond wafer portion. The handle wafer, the bond wafer portion, and the portion of the oxide layer remaining on the handle wafer together define the thin SOI wafer.

[0009] A challenge with this process is that hydrogen implantation can cause implant radiation and / or plasma damage to the oxide layer portion and the bond wafer portion remaining on the handle wafer. Such damage, in turn, can cause high leakage current and power consumption for semiconductor devices formed on the SOI wafer. One possible solution to this damage is high-temperature annealing. However, it is difficult to completely repair the damage with high-temperature annealing, and high-temperature annealing anyway results in increased costs and process complexity.Another challenge with the process is that hydrogen implantation can cause a positive charge to become trapped in the oxide layer portion remaining on the handle wafer, which can negatively impact the performance of the semiconductor devices on the SOI wafer. For example, the positive charge can shift threshold voltages, on-state resistances, and other parameters of semiconductor devices formed on the SOI wafer. Yet another challenge with the process is the high cost of the implantation, cleaving, and CMP.

[0010] Various embodiments of the present application are directed to a method for forming a thin SOI substrate without implant radiation and / or plasma damage, as well as to the thin SOI substrate resulting from the method. In some embodiments, a first insulating layer is deposited on a handle substrate. A buffer layer is epitaxially formed on a sacrificial substrate, an etch stop layer is epitaxially formed on the buffer layer, a device layer is epitaxially formed on the etch stop layer, and a second insulating layer is deposited on the device layer. The etch stop layer may, for example, comprise undoped silicon germanium, boron-doped silicon germanium, boron-doped elemental silicon, or any combination of the foregoing. The second insulating layer may, for example, have a net charge that is negative or neutral.The sacrificial substrate is bonded to the handle substrate such that the buffer layer, the etch stop layer, the device layer, the first insulation layer, and the second insulation layer are located between the sacrificial and handle substrates. The sacrificial substrate is removed, followed by removal of the buffer layer, which is then followed by removal of the etch stop layer. Removal of the buffer layer may comprise, for example, a tetramethylammonium hydroxide (TMAH) wet etch. Removal of the etch stop layer may comprise, for example, a hydrochloric acid (HCL) wet etch, followed by an in-situ anneal to smooth an exposed area of the device layer. After removal of the etch stop layer, the device layer is cyclically thinned until the device layer has a target thickness. A thinning cycle comprises oxidizing a portion of the device layer and removing an oxide resulting from the oxidation.

[0011] By cyclically thinning the device layer to the target thickness, multiple small thinning processes can be performed instead of one large thinning process. This, in turn, allows greater control over the final thickness of the device layer. For example, the device layer thickness can be precisely reduced to a final thickness less than approximately 20, 14, or 10 nanometers and / or between approximately 7 and 20 nanometers or approximately 7 and 14 nanometers. Such small thicknesses are used with fully depleted MOS devices and other advanced MOS devices.

[0012] By forming the second insulating layer with a net charge that is neutral, the second insulating layer does not affect the performance (e.g., on-state resistance, threshold voltage, etc.) of semiconductor devices formed on the SOI substrate. By forming the second insulating layer with a net charge that is negative, the second insulating layer repels negative charge, thereby preventing or reducing leakage current for the semiconductor devices. The reduced leakage current leads to higher power efficiency and performance for the semiconductor devices.

[0013] By depositing the first and second insulation layers and epitaxially forming the device layer, the first and second insulation layers and the device layer are not subject to implant radiation and / or plasma damage during the formation of the SOI substrate. For example, no hydrogen implantation process is performed to form the device layer and the first and second insulation layers. Since no implant radiation and / or plasma damage is present, leakage current for semiconductor devices formed on the SOI substrate is prevented or reduced. The reduced leakage current leads to higher power efficiency and performance for the semiconductor devices.

[0014] By forming the etch stop layer to be or comprise undoped silicon germanium, boron-doped silicon germanium, boron-doped elemental silicon, or any combination of the foregoing, a TMAH wet etch to remove the buffer layer can be performed, for example, with high selectivity for the buffer layer with respect to the etch stop layer. Consequently, the buffer layer can be removed with minimal damage (e.g., due to overetching) to the etch stop layer. Furthermore, the etch stop layer can have a small total thickness variation (TTV), so that subsequent processing can be very uniform. For example, a subsequent etch to remove the etch stop layer can be very uniform. The more uniform the subsequent processing, the more uniform the final thickness of the device layer and the higher the quality of the device layer.

[0015] By using thermal HCl etching to remove the etch stop layer, the selectivity for the etch stop layer relative to the device layer can be high. Consequently, damage to the device layer (e.g., due to overetching) is minimal, and the TTV of the device layer is small. Furthermore, performing in-situ annealing to smooth the device layer further reduces the surface roughness of the device layer. The small TTV and reduced surface roughness of the device layer, in turn, promote high uniformity between semiconductor devices formed on the device layer and are becoming increasingly important with the continuous reduction in the size of semiconductor devices.

[0016] With reference to Fig. 1A provides a cross-sectional view 100A of some embodiments of an SOI substrate 102. In some embodiments, the SOI substrate 102 has a circular plan view and / or has a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the SOI substrate 102 has a different shape and / or dimensions. Additionally, in some embodiments, the SOI substrate 102 is a semiconductor wafer. The SOI substrate 102 includes a handle substrate 104, an insulation layer 106, and a device layer 108. The handle substrate 104 may be or include, for example, single-crystal silicon, another silicon material, another semiconductor material, or any combination of the foregoing.

[0017] In some embodiments, the handle substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance may be, for example, greater than about 1, 3, 4, or 9 kiloohms / centimeter (kΩ / cm), and / or may be, for example, about 1 to 4 kΩ / cm, about 4 to 9 kΩ / cm, or about 1 to 9 kΩ / cm. The low oxygen concentration may be, for example, less than about 1, 2, or 5 ppma (part per million atoms) and / or may be, for example, between about 0.1 to 2.5 ppma, about 2.5 to 5.0 ppma, or about 0.1 to 5.0 ppma. The low oxygen concentration and the high resistance individually reduce substrate and / or radio frequency (RF) losses. In some embodiments, the handle substrate 104 has a low resistance. The low resistance reduces the cost of the handle substrate 104, but may result in increased substrate and / or RF losses.The low resistance may, for example, be less than approximately 8, 10, or 12 kΩ / cm, and / or may, for example, be between approximately 8 to 12 kΩ / cm, approximately 8 to 10 kΩ / cm, or approximately 10 to 12 kΩ / cm. In some embodiments, the handle substrate 104 is doped with p-type or n-type dopants. The resistance of the handle substrate 104 may be controlled, for example, by a doping concentration of the handle substrate 104. For example, increasing the doping concentration may decrease the resistance, while decreasing the doping concentration may increase the resistance, or vice versa.

[0018] The insulation layer 106 overlies the handle substrate 104 and may be or include, for example, silicon oxide, silicon-rich oxide (SRO), another dielectric, or any combination of the foregoing. As seen below, due to the method by which the SOI substrate 102 is formed, the insulation layer 106 is free from implant radiation and / or plasma damage. Consequently, leakage current is low and performance (e.g., power efficiency, switching speed, etc.) is high for semiconductor devices formed on the SOI substrate 102. Also, due to the method by which the SOI substrate 102 is formed, the insulation layer 106 has a net negative or neutral charge at an interface with the device layer 108. By having a neutral charge at the device layer interface, the insulation layer 106 does not affect performance (e.g.,The insulating layer 106 electrostatically repels negative charge (e.g., on-state resistance, threshold voltage, etc.) of semiconductor devices formed on the SOI substrate 102. By having a negative charge at the device layer interface, the insulating layer 106 electrostatically repels negative charge, thereby preventing or reducing leakage current for semiconductor devices formed on the SOI substrate 102.

[0019] In some embodiments, the insulation layer 106 has a first insulator thickness T fi on the device layer 108, and further comprises a second insulator thickness T si on SOI edge portions 102e of the SOI substrate 102, sidewalls of the SOI substrate 102, a bottom surface of the SOI substrate 102, or any combination of the foregoing. The first insulator thickness T fiis greater than the second insulator thickness Tsi and can be, for example, between approximately 12 to 20 nm, approximately 12 to 16 nm, or approximately 16 to 20 nm. The second insulator thickness T simay, for example, be between approximately 10 and 15 nm, approximately 10 to 12.5 nm, or approximately 12.5 to 15 nm. In some embodiments, the insulation layer 106 completely surrounds the handle substrate 104 and / or has a stepped profile at the SOI edge portions 102e. In some embodiments, the insulation layer 106 has upper surfaces located at the SOI edge portions 102e that are recessed below a top surface of the insulation layer 106 by a vertical recess amount VR. The vertical recess amount VR may, for example, be approximately 2 to 5 nm, approximately 2 to 3.5 nm, or approximately 3.5 to 5 nm. In some embodiments, the sum of the vertical recess amount VR and the second insulator thickness Tsi is equal to or approximately equal to the first insulator thickness T fiIn some embodiments, the insulation layer 106 includes inner sidewalls located at the SOI edge portion 102e, each of which is laterally recessed from outer sidewalls of the insulation layer 106 by a lateral recess amount LR. The lateral recess amount LR may be, for example, approximately 0.8 to 1.2 millimeters, approximately 0.8 to 1.0 millimeters, or approximately 1.0 to 1.2 millimeters.

[0020] The device layer 108 overlies the insulation layer 106 and may be or include, for example, single-crystal silicon, another silicon, another semiconductor material, or any combination of the foregoing. As seen below, due to the method by which the SOI substrate 102 is formed, the device layer 108 is free from implant radiation and / or plasma damage. Consequently, leakage current is low and performance (e.g., power efficiency, switching speed, etc.) is high for semiconductor devices formed on the SOI substrate 102.

[0021] In some embodiments, a thickness T d of the device layer 108 is small (ie, the device layer 108 is thin). For example, the thickness T dof the device layer 108 may be small in that it is less than approximately 10, 14, or 20 nanometers, and / or between approximately 7 to 14 nanometers or approximately 14 to 20 nanometers. In addition, the thickness T d for example, be small in that it is equal to or approximately equal to a depletion region width of a semiconductor device formed on the SOI substrate 102. The semiconductor device may, for example, be a MOS field-effect transistor (MOSFET) or another semiconductor device, and / or the depletion region width may, for example, be the depth to which a depletion region of the semiconductor device extends in the device layer 108. In some embodiments in which the thickness T d of the device layer 108 is small, electrical insulation between semiconductor devices formed on the device layer 108 can be improved. Since the thickness T dof the device layer 108 is small, for example, STI (shallow trench isolation) structures and / or other isolation structures may extend completely through the device layer 108 to the isolation layer 106 to provide complete or nearly complete electrical isolation between adjacent semiconductor devices. Furthermore, in embodiments where the thickness T d of the device layer 108 is small, fully depleted semiconductor devices are formed on the device layer. Fully depleted semiconductor devices generally exhibit higher switching speeds and higher power efficiency than their partially depleted counterparts.

[0022] In some embodiments, a TTV of the device layer 108 is low. The TTV represents the difference between the minimum thickness value for the device layer 108 and the maximum thickness value for the device layer 108. For example, the TTV of the device layer 108 may be low in that it is less than about 20, 10, or 5 nanometers, and / or it may be between about 5 to 20 nanometers, 5 to 12 nanometers, about 12 to 20 nanometers, or about 8 to 12 nanometers. The small TTV promotes uniformity of parameters of semiconductor devices formed on the device layer 108. Such parameters may include, for example, a threshold voltage, an on-state resistance, and so on. As semiconductor devices become smaller and smaller, the small TTV becomes increasingly important.

[0023] With reference to Fig. 1B is a cross-sectional view 100B of some alternative embodiments of the SOI substrate 102 of Fig. 1A, in which a trap-rich layer 110 separates the handle substrate 104 from the insulating layer 106. The trap-rich layer 110 has a high density of charge carrier traps with respect to the handle substrate 104 and / or with respect to the device layer 108. The traps may be, for example, dislocations and / or other defects in a crystal lattice of the trap-rich layer 110. The traps trap mobile charge carriers (e.g., mobile electrons) along a top surface of the handle substrate 104 to reduce the effects of parasitic surface conduction (PSC). The mobile charge carriers may, for example, be attracted to the top surface of the handle substrate 104 by a fixed charge in the insulating layer 106.By reducing PSC effects, the trap-rich layer 110 promotes low substrate and / or RF losses, passive devices with high Q factors, low crosstalk, and high linearity (e.g., low second harmonic).

[0024] In some embodiments, the trap-rich layer 110 is or includes undoped polycrystalline silicon, amorphous silicon, or another suitable semiconductor material having a high density of charge traps. In some embodiments where the trap-rich layer 110 is or includes undoped polycrystalline silicon, the charge traps accumulate at grain boundaries of the undoped polycrystalline silicon, and reducing grain sizes of the undoped polycrystalline silicon increases the density of charge traps in the undoped polycrystalline silicon.

[0025] With reference to Fig. 2 is a cross-sectional view 200 of some more detailed embodiments of the SOI substrate 102 of Fig. 1A, in which the insulating layer 106 includes a first insulating layer 106f and further includes a second insulating layer 106s overlying the first insulating layer 106f. The first insulating layer 106f and the second insulating layer 106s may be or include, for example, silicon oxide, SRO, another dielectric, or any combination of the foregoing.

[0026] In some embodiments, the first and second insulation layers 106f, 106s have different charges. For example, the first insulation layer 106f may have a positive or neutral charge, while the second insulation layer 106s may have a negative charge. As another example, the first insulation layer 106f may have a positive charge, while the second insulation layer 106s may have a neutral charge. In other embodiments, the first and second insulation layers 106f, 106s have the same charges. For example, the first and second insulation layers 106f, 106s may have negative or neutral charges. In some embodiments, the first and second insulation layers 106f, 106s are different materials. In other embodiments, the first and second insulation layers 106f, 106s are the same material. In some embodiments, a first thickness T fi'the first insulation layer 106f between approximately 12 to 20 nm, approximately 12 to 16 nm or approximately 16 to 20 nm, and / or a second thickness T si' of the second insulation layer 106s is between approximately 10 to 15 nm, approximately 10 to 12.5 nm, or approximately 12.5 to 15 nm. In some embodiments, the first thickness T fi' greater than the second thickness T si' .

[0027] Although Fig. 2 more detailed embodiments of the insulation layer 106 using Fig. 1A, it is understood that the more detailed embodiments also Fig. 1B can be used. For example, the insulation layer 106 of Fig. 1B in some embodiments, the first insulation layer 106f and the second insulation layer 106s.

[0028] With reference to Fig. 3 is a top view 300 of some embodiments of the SOI substrate 102 of Fig. 1A. The SOI substrate 102 is circular and includes a plurality of IC dies 302 arranged in a grid across the device layer 108. For ease of illustration, only some of the IC dies 302 are labeled 302. In some embodiments, a diameter D of the SOI substrate 102 is approximately 150, 200, 300, or 450 millimeters. In some embodiments, a sidewall 108sw of the device layer 108 is recessed laterally from a sidewall 106sw of the insulation layer 106 by a lateral recess amount LR. The lateral recess amount LR may be, for example, approximately 0.8 to 1.2 millimeters, approximately 0.8 to 1.0 millimeters, or approximately 1.0 to 1.2 millimeters.

[0029] With reference to Fig. 4, a cross-sectional view 400 of some embodiments of a semiconductor structure is provided in which the SOI substrate 102 of Fig. 1A. The semiconductor structure includes a plurality of semiconductor devices 402 laterally spaced above the device layer 108. The semiconductor devices 402 may be, for example, MOSFETs, other MOS devices, other insulated gate field-effect transistors (IGFETs), other semiconductor devices, or any combination of the foregoing. Furthermore, the semiconductor devices 402 may be, for example, fully depleted or partially depleted semiconductor devices.

[0030] In some embodiments, the semiconductor devices 402 include respective sources / drains 404, respective selectively conductive channels 406, respective gate dielectric layers 408, and respective gate electrodes 410. For ease of illustration, only one of the sources / drains 404 is labeled 404, only one of the selectively conductive channels 406 is labeled 406, only one of the gate dielectric layers 408 is labeled 408, and only one of the gate electrodes 410 is labeled 410. The sources / drains 404 and the selectively conductive channels 406 are located in and / or defined by the device layer 108. The sources / drains 404 are each located at ends of the selectively conductive channels 406, and each of the selectively conductive channels 406 extends from one of the sources / drains 404 to another of the sources / drains 404.The gate dielectric layers 408 each overlie the selectively conductive channels 406, and the gate electrodes 410 each overlie the gate dielectric layers 408. The gate dielectric layers 408 may be or include, for example, silicon oxide and / or another dielectric material, and / or the gate electrodes 410 may be or include, for example, doped polysilicon, a metal, another conductive material, or any combination of the foregoing.

[0031] In some embodiments, the isolation structures 412 electrically separate the semiconductor devices 402. For simplicity of illustration, only some of the isolation structures 412 are labeled 412. The isolation structures 412 may be or include, for example, STI structures, DTI (deep trench isolation) structures, field oxide structures, or some other isolation structures.

[0032] A back-end-of-line (BEOL) interconnect structure 414 covers the SOI substrate 102 and the semiconductor devices 402. The BEOL interconnect structure 414 includes an interconnect dielectric layer 416, a plurality of wires 418, and a plurality of vias 420. For ease of illustration, only some of the wires 418 are labeled 418, and only some of the vias 420 are labeled 420. The interconnect dielectric layer 416 may be or include, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicon glass (USG), another low-κ dielectric, silicon oxide, another dielectric, or any combination of the foregoing. As used herein, a low-ĸ dielectric may, for example, be or have a dielectric with a dielectric constant ĸ less than about 3.9, 3.2, or 1.

[0033] The wires 418 and the vias 420 are alternately stacked in the interconnect dielectric layer 416 and define conductive paths extending to the semiconductor devices 402. The conductive paths may, for example, electrically couple the semiconductor devices 402 to other devices (e.g., other semiconductor devices), contact pads, or other structures. The wires 418 and the vias 420 may, for example, be or include copper, aluminum-copper, aluminum, tungsten, another metal, or any combination of the foregoing. In some embodiments, uppermost wires of the wires 418 are thicker than underlying wires of the wires 418.

[0034] Although Fig. 3 and Fig. 4 with respect to embodiments of the SOI substrate 102 in Fig. 1A, it is understood that embodiments of the SOI substrate 102 in Fig. 1B or Fig. 2 alternatively in Fig. 3 and Fig. 4 can be used. Although Fig. 3 shows a specific number of IC dies 302 and a concrete layout of the IC dies 302, more or fewer IC dies 302 and / or other layouts of the IC dies 302 are possible in other embodiments. Although Fig. 4 shows a concrete layout of the BEOL connection structure 414, other layouts of the BEOL connection structure 414 are possible in other embodiments. Although Fig. 4 shows three semiconductor devices 402 and a concrete layout for the semiconductor devices 402, more or fewer semiconductor devices and / or other layouts for the semiconductor devices 402 are possible.

[0035] With reference to Fig. 5 to 16, 17A, 17B, 18, 19A, 19B, and 20 to 22, a series of cross-sectional views 500 to 1600, 1700A, 1700B, 1800, 1900A, 1900B, and 2000 to 2200 of some embodiments of a method for forming and using an SOI substrate without implant radiation and / or plasma damage are provided. Note that Fig. 17B and Fig. 19B enlarged cross-sectional views 1700B, 1900B within box BX each in Fig. 17A and Fig. 19A. Although the method is described as forming embodiments of the SOI substrate 102 in Fig. 1A and Fig. 2, the method may alternatively be used to form embodiments of the SOI substrate 102 in Fig. 1A or any other SOI substrate. Although Fig. 5 to 16, 17A, 17B, 18, 19A, 19B and 20 to 22 are described in relation to a method, it is also understood that the Fig. 5 to 16, 17A, 17B, 18, 19A, 19B and 20 to 22 are not limited to the method and they can be independent.

[0036] As shown in cross-sectional view 500 of Fig. 5, a handle substrate 104 is provided. In some embodiments, the handle substrate 104 is or includes single-crystal silicon, another silicon material, another semiconductor material, or any combination of the foregoing. In some embodiments, the handle substrate 104 has a circular plan view and / or has a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the handle substrate 104 has a different shape and / or dimensions. Additionally, in some embodiments, the handle substrate 104 is a semiconductor wafer. In some embodiments, the handle substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance and low oxygen concentration individually reduce substrate and / or RF losses.The high resistance may, for example, be greater than about 1, 3, 4, or 9 kΩ / cm, and / or may, for example, be between about 1 to 4 kΩ / cm, about 4 to 9 kΩ / cm, or about 1 to 9 kΩ / cm. The low oxygen concentration may, for example, be less than about 1, 2, or 5 ppma, and / or may, for example, be between about 0.1 to 2.5 ppma, about 2.5 to 5.0 ppma, or about 0.1 to 5.0 ppma. In some embodiments, the handle substrate 104 has a low resistance to reduce substrate costs, since a substrate with a high resistance may, for example, be more expensive than a substrate with a low resistance. The low resistance may be, for example, less than about 8, 10, or 12 kΩ / cm, and / or may be, for example, about 8 to 12 kΩ / cm, about 8 to 10 kΩ / cm, or about 10 to 12 kΩ / cm. In some embodiments, the handle substrate 104 is doped with p-type or n-type dopants.The resistance of the handle substrate 104 can be controlled, for example, by a doping concentration of the handle substrate 104.

[0037] As also shown in the cross-sectional view 500 of Fig. 5, a first insulating layer 106f is formed on the handle substrate 104. In some embodiments, the first insulating layer 106f completely surrounds the handle substrate 104. In other embodiments, the first insulating layer 106f is limited to a top surface of the handle substrate 104. In some embodiments, a thickness T fi'The thickness of the first insulating layer 106f may be between approximately 10 and 15 nm, approximately 10 to 12.5 nm, or approximately 12.5 to 15 nm. The first insulating layer 106f may be or include, for example, silicon oxide, another dielectric, or any combination of the foregoing. A process for forming the first insulating layer 106f may include, for example, depositing the first insulating layer 106f using thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), another deposition process, or any combination of the foregoing.

[0038] In some alternative embodiments, a trap-rich layer (not shown) is formed on the handle substrate 104 before the first insulating layer 106f is formed. In such embodiments, the first insulating layer 106f is formed on the trap-rich layer. Furthermore, in some embodiments, the first insulating layer 106f is formed on sidewalls of the handle substrate 104 and / or is formed to completely surround both the trap-rich layer and the handle substrate 104. An example of the trap-rich layer is represented by element 110 in Fig. 1B shown.

[0039] As shown in cross-sectional view 600 of Fig. 6, a sacrificial substrate 602 is provided. In some embodiments, the sacrificial substrate 602 is or includes single-crystal silicon, another silicon material, another semiconductor material, or any combination of the foregoing. In some embodiments, the sacrificial substrate 602 is doped with p-type or n-type dopants. In some embodiments, the sacrificial substrate 602 has a circular plan view and / or has a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the sacrificial substrate 602 has a different shape and / or dimensions. In some embodiments, the sacrificial substrate 602 is a bulk semiconductor substrate and / or a semiconductor wafer.

[0040] As also shown by the cross-sectional view 600 of Fig. 6, a buffer layer 604 is formed over the sacrificial substrate 602. In some embodiments, the buffer layer 604 is or includes single-crystal silicon, another silicon material, another semiconductor material, or any combination of the foregoing. In some embodiments, the buffer layer 604 is or includes the same semiconductor material as the sacrificial substrate 602, has the same doping type as the sacrificial substrate 602, has a different doping concentration than the sacrificial substrate 602, or any combination of the foregoing. For example, the sacrificial substrate 602 may be or include single-crystal P+-type silicon, while the buffer layer 604 may be or include single-crystal P--type silicon.In some embodiments, the buffer layer 604 has the same doping type, doping concentration, resistivity, or any combination of the foregoing as the handle substrate 104 (see . Fig. 5). In some embodiments, a thickness Tb of the buffer layer 604 is between about 0.8 and 1.8 micrometers, about 0.8 to 1.3 micrometers, or about 1.3 to 1.8 micrometers.

[0041] In some embodiments, a process for forming the buffer layer 604 includes growing the buffer layer 604 on the sacrificial substrate 602 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), another epitaxial process, or any combination of the foregoing. In some embodiments, the sacrificial substrate 602 serves as a seed layer for epitaxy. Alternatively, in some embodiments, the buffer layer 604 is formed by doping an upper portion of the sacrificial substrate 602 such that the upper portion defines the buffer layer 604. For example, assuming that the sacrificial substrate 602 is or comprises P+ silicon, the upper portion of the sacrificial substrate 602 may be doped in an opposite manner with n-type dopants such that the upper portion, and therefore the buffer layer 604, is or comprises P- silicon.

[0042] As also shown in the cross-sectional view 600 of Fig. 6, an etch stop layer 606 and a device layer 108 are formed stacked over the buffer layer 604 such that the device layer 108 overlies the etch stop layer 606. The etch stop layer 606 and the device layer 108 are crystalline materials with different crystal lattices, such that the etch stop layer 606 imparts strain to the device layer 108. For example, the device layer 108 may be or include single-crystal silicon, and the etch stop layer 606 may be or include germanium-silicon-germanium, whereby the etch stop layer 606 may induce tensile strain in the device layer 108.

[0043] In some embodiments, the etch stop layer 606 is or comprises silicon germanium, silicon carbide, silicon, another crystal material, or any combination of the foregoing, and / or is doped with boron, aluminum, another p-type dopant, or a combination of the foregoing. For example, the etch stop layer 606 may be or comprise intrinsic (i.e., undoped) silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon. In some embodiments where the etch stop layer 606 is or comprises silicon germanium, an atomic percentage of germanium in the etch stop layer 606 is about 20 to 60%, about 20 to 40%, about 40 to 60%, or about 22 to 55%. For example, the etch stop layer 606 may be or comprise SixGe1-x, where x is about 0.2 to 0.6, about 0.2 to 0.4, or about 0.4 to 0.6.In some embodiments where the etch stop layer 606 is doped with boron, the doping concentration may be approximately 1×10. 19 up to about 5×10 21 Atoms per cubic centimeter (cm 3 ), approximately 1×10 19 up to about 5×10 20 atoms / cm 3 , approximately 5×10 20 up to about 5×10 21 atoms / cm 3 , or approximately 5×10 19 up to about 3×10 21 atoms / cm 3 In some embodiments, a thickness T es the etch stop layer 606 between approximately 15 and 40 nanometers, approximately 15 to 30 nanometers, or approximately 30 to 40 nanometers.

[0044] If the atomic percentage of germanium of the etch stop layer 606 is too high (e.g., greater than approximately 50%, 60%, or another suitable percentage), or the boron doping concentration in the etch stop layer 606 is too high (e.g., greater than approximately 3 x 10 21 atoms / cm 3, approximately 5×10 20 atoms / cm 3 , or other suitable doping concentration), the device layer 108 may be poorly formed on the etch stop layer 606. For example, the crystal lattice of the device layer 108 may be formed with a high concentration of crystal defects, leading to leakage current in devices subsequently formed on the device layer 108.

[0045] In some embodiments, the device layer 108 is or includes single-crystal silicon, another semiconductor material, or any combination of the foregoing. In some embodiments, the device layer 108 is the same semiconductor material as the handle substrate 104 (see Fig. 5) and / or the sacrificial substrate 602. In some embodiments, the device layer 108 has a resistance that is less than about 8, 15, or 20 Ω / cm and / or between about 8 to 20 Ω / cm, about 8 to 14 Ω / cm, or about 14 to 20 Ω / cm. In some embodiments, the resistance of the device layer 108 is the same as or approximately the same as that of the handle substrate 104 (see Fig. 5). In other embodiments, the resistance of the device layer 108 is low compared to that of the handle substrate 104 (e.g., one, two, or more orders of magnitude lower). In some embodiments, a thickness T d the device layer 108 is less than about 20 or 40 nanometers, and / or is between about 20 to 40 nanometers, or about 30 to 40 nanometers.

[0046] In some embodiments, the etch stop layer 606 and the device layer 108 are formed by epitaxy. For example, the etch stop layer 606 and the device layer 108 may be formed by MBE, VPE, LPE, another epitaxial process, or any combination of the above. In some embodiments, the buffer layer 604 serves as a seed layer for the etch stop layer 606 and / or the etch stop layer 606 serves as a seed layer for the device layer 108. By forming the device layer 108 using the etch stop layer 606 as a seed layer and by forming the etch stop layer 606 using the buffer layer 604 as a seed layer, the crystal quality of the etch stop layer 606 and the device layer 108 is high, and crystal defects are few.Consequently, semiconductor devices formed on device layer 108 have, among other things, high performance and low leakage current.

[0047] As also shown by the cross-sectional view 600 of Fig. 6, dielectric capping layer 608 is formed on device layer 108. In some embodiments, dielectric capping layer 608 is or includes silicon oxide, another dielectric, or any combination of the foregoing. A process for forming dielectric capping layer 608 may include, for example, depositing dielectric capping layer 608 using thermal oxidation, PVD, CVD, another deposition process, or any combination of the foregoing. In some embodiments, dielectric capping layer 608 is disposed on a top surface of device layer 108. In some such embodiments, dielectric capping layer 608 is deposited by plasma-assisted PVD to achieve such a configuration.

[0048] As shown in cross-sectional view 700 of Fig. 7, the dielectric cap layer 608, the device layer 108, the etch stop layer 606, the buffer layer 604 and the sacrificial substrate 602 are patterned to remove edge portions 610 (see Fig. 6). Removing the edge portions 610 prevents defects from forming at the edge portions 610 during subsequent grinding and / or wet etching. The edge defects tend to accumulate at the edge portions 610 and negatively impact the quality of the device layer 108. Furthermore, patterning forms a protrusion 702 at an edge of the sacrificial substrate 602. The protrusion 702 is defined by the sacrificial substrate 602 and includes a pair of protrusion portions, each on opposite sides of the sacrificial substrate 602. In some embodiments, the protrusion 702 has a width W of approximately 0.8 to 1.2 millimeters, approximately 0.8 to 1.0 millimeters, or approximately 1.0 to 1.2 millimeters.

[0049] In some embodiments, patterning is performed by a photolithography / etching process or another patterning process. Furthermore, in some embodiments, patterning includes: forming a mask 704 over the dielectric cap layer 608, performing an etch on the dielectric cap layer 608, the device layer 108, the etch stop layer 606, the buffer layer 604, and the sacrificial substrate 602 with the mask 704 disposed; and removing the mask 704. In some embodiments, the mask 704 is or includes silicon nitride, silicon oxide, another hard mask material, photoresist, another mask material, or any combination of the foregoing. In some embodiments, the mask 704 is formed using a wafer edge exposure (WEE) process tool.For example, a process for forming the mask 704 may include: depositing a photoresist layer on the dielectric cap layer 608; selectively exposing an edge portion of the photoresist layer to radiation using the WEE process tool; and developing the photoresist layer to form the mask 704.

[0050] As shown in cross-sectional view 800 of Fig. 8, the dielectric cap layer 608 (see Fig. 7) is removed. The removal can be performed, for example, by a CMP, an etching process, another removal process, or any combination of the above.

[0051] As also shown in the cross-sectional view 900 of Fig. 9, a second insulation layer 106s is formed on the device layer 108. In some embodiments, the second insulation layer 106s completely surrounds the device layer 108, the etch stop layer 606, the buffer layer 604, and the sacrificial substrate. In other embodiments, the second insulation layer 106s is confined to a top surface of the device layer 108. In some embodiments, the second insulation layer 106s has a net charge that is negative. By having a net negative charge, the second insulation layer 106s can electrostatically repel a negative charge, thereby preventing or reducing leakage current for semiconductor devices subsequently formed on the device layer 108. In other embodiments, the second insulation layer 106s has a net charge that is neutral (i.e., approximately zero).By having a net neutral charge, the second insulation layer 106s does not affect the performance (e.g., on-state resistance, threshold voltage, etc.) of semiconductor devices subsequently formed on the device layer 108. In some embodiments, a thickness T is si' the second insulation layer 106s is between approximately 2 and 5 nm, approximately 2 to 3.5 nm, or approximately 3.5 to 5 nm. In addition, in some embodiments, the thickness T si' the second insulation layer 106s is smaller than that of the first insulation layer 106f (see Fig. 5). A process for forming the second insulating layer 608 may include, for example, depositing the second insulating layer 608 using oxidation, CVD, PVD, another deposition process, or any combination of the foregoing.

[0052] In some embodiments where the second insulating layer 106s has a net charge that is neutral, the second insulating layer 106s is formed by a wet oxidation process. The wet oxidation process may, for example, include contacting the device layer 108 with water (i.e., H2O) at elevated temperatures and elevated pressures. The elevated temperatures may be, for example, about 750 to 1150 degrees Celsius (°C), about 750 to 950 °C, or about 950 to 1150 °C, and / or the elevated pressures may be, for example, about 933 mbar to 1093 mbar (700 to 820 Torr), about 933 mbar to 1013 mbar (700 to 760 Torr), about 1013 mbar to 1093 mbar (760 to 820), or about 1013 mbar (760 Torr). In some embodiments, the wet oxidation process further comprises flowing an oxygen gas (e.g., O2) and / or hydrogen gas (e.g.,H2) over the device layer 108 while exposing the device layer 108 to water at the elevated temperatures and pressures. The flow rate of the oxygen gas may be, for example, about 0.1 to 30.0 standard liters per minute (SLM), about 0.10 to 15 SLM, or about 15 to 30 SLM, and / or the flow rate for the hydrogen gas may be, for example, about 0.05 to 10.0 SLM, about 0.05 to 5.00 SLM, or about 5 to 10 SLM. In some embodiments, the wet oxidation process forms the second insulation layer 106s through the following reaction: Si + 2H2O -> SiO2 + 2H2.

[0053] In some embodiments where the second insulating layer 106s has a net charge that is negative, the second insulating layer 106s is formed by a radical oxidation process. The radical oxidation process may include, for example, flowing an oxygen gas (e.g., O2) and hydrogen gas (e.g., H2) over the device layer 108 while exposing the oxygen and hydrogen gases to high-power microwaves. The flow rate of the oxygen gas may be, for example, about 0.1 to 30.0 SLM, about 0.10 to 15 SLM, or about 15 to 30 SLM, and / or the flow rate for the hydrogen gas may be, for example, about 0.05 to 10.0 SLM, about 0.05 to 5.00 SLM, or about 5 to 10 SLM.The high-power microwaves generate oxygen radicals from the oxygen and hydrogen gases, and the oxygen radicals oxidize the device layer 108 to form the second insulating layer 106s with a net charge that is negative. A ratio of the oxygen gas to the hydrogen gas can be varied, for example, to control the magnitude of the negative charge in the second insulating layer 106s. In some embodiments, the radical oxidation process is performed at temperatures between approximately 25 to 600°C, approximately 25 to 300°C, or approximately 300 to 600°C, and / or is performed at pressures between approximately 0.67 mbar to 267 mbar (0.5 to 200.0 Torr), approximately 0.66 mbar to 133 mbar (0.5 to 100.0 Torr), or approximately 133 mbar to 267 mbar (100 to 200 Torr).

[0054] As shown by the cross-sectional view 1000 of Fig. 10, the structure of Fig. 9 vertically turned and attached to the structure of Fig. 5, so that the buffer layer 604, the etch stop layer 606, the device layer 108, the first insulation layer 106f, and the second insulation layer 106s are located between the handle substrate 104 and the sacrificial substrate 602. The bonding can be performed, for example, using fusion bonding, vacuum bonding, or another bonding process. The fusion bonding can be performed, for example, at a pressure of approximately 1 standard atmosphere (atm), and / or the vacuum bonding can be performed, for example, at a pressure of approximately 0.1 to 30 millibars (mbar).

[0055] In some embodiments, a bond anneal is performed to strengthen the bond. In some embodiments, the bond anneal is performed at a temperature of about 300 to 400°C, about 300 to 350°C, about 350 to 400°C, or about 350°C. In some embodiments, the bond anneal is performed for about 1 to 3 hours, about 1 to 2 hours, about 2 to 3 hours, or about 2 hours.

[0056] As shown in cross-sectional view 1100 of Fig. 11, a first thinning process is performed on the sacrificial substrate 602 to remove an upper portion of the sacrificial substrate 602, thereby reducing a thickness Tss of the sacrificial substrate 602. Furthermore, the first thinning process removes an upper portion of the second insulating layer 106s on the removed portion of the sacrificial substrate 602. In some embodiments, the first thinning process is performed until the sacrificial substrate 602, the buffer layer 604, the etch stop layer 606, and the device layer 108 have a combined thickness Tc between approximately 17 to 25.5 micrometers, approximately 17 to 21 micrometers, or approximately 21 to 25.5 micrometers.

[0057] In some embodiments, the first thinning process is performed by a mechanical grinding process, a CMP, another thinning process, or any combination of the above. For example, the first thinning process may be performed entirely by a mechanical grinding process. As mentioned above, removing the edge portions 610 from Fig. 6, edge defects form at the edge portions 610 during grinding. The edge defects tend to accumulate at the edge portions 610 during grinding.

[0058] As shown in cross-sectional view 1200 of Fig. 12, a first etching of the sacrificial substrate 602 (see Fig. 11). The first etch stops on the device layer 108 and removes the sacrificial substrate 602. In some embodiments, the etch further removes a portion of the second insulation layer 106s on sidewalls of the sacrificial substrate 602, sidewalls of the buffer layer 604, sidewalls of the etch stop layer 606, sidewalls of the device layer 108, or any combination of the foregoing. In some embodiments, after the first etch is complete, the buffer layer 604, the etch stop layer 606, and the device layer 108 have a combined thickness Tc between approximately 0.7 to 1.5 micrometers, approximately 0.7 to 1.1 micrometers, or approximately 1.1 to 1.5 micrometers.

[0059] The first etch may be performed, for example, using a hydrofluoric acid / nitric acid / acetic acid (HNA) etchant, another wet etchant, a dry etchant, or another etchant. The HNA etchant may be, for example, or include a chemical solution comprising hydrofluoric acid, nitric acid, and acetic acid. The first etch comprises a first etch rate for a material of the sacrificial substrate 602, and further comprises a second etch rate for a material of the buffer layer 604 that is less than the first etch rate. In some embodiments, the first etch rate is approximately 90 to 100, 90 to 95, or 95 to 100 times greater than the second etch rate. These embodiments may result, for example, when the first etch is performed using the HNA etchant, the sacrificial substrate 602 is or comprises single-crystal P+ silicon, and the buffer layer 604 is or comprises single-crystal P- silicon.

[0060] As shown in cross-sectional view 1300 of Fig. 13, a second thinning process is performed on the buffer layer 604 to remove an upper portion of the buffer layer 604, thereby reducing a thickness Tb of the buffer layer 604. In some embodiments, the second thinning process is performed until the buffer layer 604, the etch stop layer 606, and the device layer 108 have a combined thickness Tc between approximately 0.4 to 1.0 micrometers, approximately 0.4 to 0.7 micrometers, or approximately 0.7 to 1.0 micrometers. The second thinning process may be performed, for example, by a CMP, another suitable thinning process, or any combination of the foregoing.

[0061] As shown in cross-sectional view 1400 of Fig. 14, a second etching of the buffer layer 604 (see Fig. 13). The second etch stops on the etch stop layer 606 and removes the buffer layer 604. In some embodiments, after the second etch is completed, the etch stop layer 606 and the device layer 108 have a combined thickness Tc between approximately 30 to 60 nanometers, approximately 20 to 45 nanometers, or approximately 45 to 60 nanometers.

[0062] The second etch may be performed, for example, by a TMAH etchant, another suitable wet etchant, a dry etchant, or another suitable etchant. The TMAH etchant may be or include, for example, a chemical or aqueous solution comprising tetramethylammonium hydroxide. The second etch comprises a first etch rate for a material of the buffer layer 604, and further comprises a second etch rate for a material of the etch stop layer 606 that is smaller than the first etch rate. In some embodiments, the ratio of the first etch rate to the second etch rate (i.e., the selectivity) is high. For example, the ratio may be high in that the first etch rate is approximately 12, 30, or 50 times greater than the second etch rate and / or approximately 12 to 100, 30 to 100, 30 to 50, or 50 to 100 times greater than the second etch rate.

[0063] For example, the first etch rate may be approximately 12 times greater or greater than the second etch rate in embodiments where: the second etch is performed using the TMAH etchant; the buffer layer 604 is or comprises single-crystal P- silicon; and the etch stop layer 606 is or comprises undoped silicon germanium having a germanium concentration between approximately 20 to 60 atomic percent or approximately 22 to 25 atomic percent. Furthermore, the first etch rate may be approximately 30 to 100 times greater than the second etch rate in embodiments where: the second etch is performed using the TMAH etchant; the buffer layer 604 is or comprises single-crystal P- silicon; and the etch stop layer 606 is or comprises silicon germanium having a germanium concentration between approximately 20 to 60 atomic percent and a boron doping concentration of approximately 1×10 19 up to 5×10 21 atoms / cm 3 or approximately 5×10 19 up to about 3×10 21atoms / cm 3 is or comprises. Still further, the first etch rate may be, for example, approximately 30 to 100 times greater than the second etch rate in embodiments in which: the second etch is performed using the TMAH etchant; the buffer layer 604 is or comprises single-crystal P--type silicon; and the etch stop layer 606 comprises elemental silicon having a boron doping concentration between approximately 1×10 19 up to 5×10 21 atoms / cm 3 or approximately 5×10 19 ) to approximately 3×10 21 atoms / cm 3 is or has.

[0064] Because the ratio of the first etch rate to the second etch rate is high, the buffer layer 604 can be removed with minimal damage to an upper surface of the etch stop layer 606. Consequently, the etch stop layer 606 has a small TTV, and subsequent processing is very uniform. For example, a subsequent etch to remove the etch stop layer 606 can be very uniform, resulting in less damage (e.g., due to overetching) to an upper surface of the device layer 108. The more uniform the subsequent processing, the more uniform the final thickness of the device layer 108 and the higher the quality of the device layer 108.

[0065] If the germanium concentration in the etch stop layer 606 is too low (e.g., less than approximately 22%, 20%, or another suitable percentage), the ratio of the first etch rate to the second etch rate may be too low, thereby exposing the etch stop layer 606 to damage. If the boron doping concentration in the etch stop layer 606 is too low (e.g., less than approximately 5×10 19 atoms / cm 3 , approximately 1×10 19 atoms / cm 3 or other suitable doping concentration), the ratio of the first etch rate to the second etch rate may be too low, exposing the etch stop layer 606 to damage. The low ratio of the first etch rate to the second etch rate may, in turn, result in a high TTV and subsequent processing that is not uniform.

[0066] As shown by the cross-sectional view 1500 of Fig. 15, a third etching of the etch stop layer 606 (see Fig. 14). The third etch stops on the device layer 108 and removes the etch stop layer 606. In some embodiments, after completion of the third etch, a thickness T d the device layer 108 between about 20 to 35 nanometers, about 30 to 27 nanometers, or about 27 to 35 nanometers.

[0067] The third etch may be performed, for example, using an HCl etchant, another suitable wet etchant, a dry etchant, or another suitable etchant. The HCl etchant may, for example, be or comprise a chemical or aqueous solution comprising hydrofluoric acid. The hydrofluoric acid may, for example, comprise 0.1 to 2.0 weight or volume percent of the chemical or aqueous solution. The HCl etchant may, for example, be applied to the etch stop layer 606 at a temperature of approximately 600 to 900°C, approximately 600 to 750°C, or approximately 750 to 900°C and / or at a pressure of approximately 6.7 mbar to 1013 mbar (5 to 760 Torr), approximately 6.7 mbar to 507 mbar (5 to 380 Torr), or approximately 507 mbar to 1013 mbar (380 to 760 Torr).In addition, the HCl etchant may, for example, be applied to the etch stop layer 606 for approximately 20 to 1500 seconds, approximately 20 to 1200 seconds, or approximately 160 to 1500 seconds, and / or may, for example, be applied while a hydrogen gas (e.g., H2) flows over the etch stop layer 606. The flow rate of the hydrogen gas may, for example, be approximately 1 to 30 SLM, approximately 1 to 15 SLM, or approximately 15 to 30 SLM.

[0068] The third etch comprises a first etch rate for a material of the etch stop layer 606, and further comprises a second etch rate for a material of the device layer 108 that is smaller than the first etch rate. In some embodiments, the first etch rate is substantially greater than the second etch rate, such that the selectivity of the third etch for the etch stop layer 606 with respect to the device layer 108 is high. For example, the first etch rate may be approximately 30 to 60, 30 to 45, 45 to 60, or 60 to 80 times greater than the second etch rate, and / or the first etch rate may be greater than approximately 30, 45, 60, or 80 times the second etch rate, such that the selectivity is high.Such embodiments may result, for example, when the third etch is performed using the HCl etchant, the etch stop layer 606 is or comprises silicon germanium or boron-doped elemental silicon, and the device layer 108 is or comprises single-crystal silicon. In embodiments where the third etch has high selectivity for the etch stop layer 606 with respect to the device layer 108, damage to the device layer (e.g., due to overetching) is minimal, and the TTV of the device layer is small. This results in low leakage current and high power efficiency for semiconductor devices subsequently formed on the device layer 108. Furthermore, uniformity between the semiconductor devices is high.

[0069] In some embodiments, an in-situ anneal is performed to smooth a top surface of the device layer 108. The in-situ anneal is "in-situ" in that the device layer 108 is not moved from the time the third etch is performed to the time the in-situ anneal is performed. By smoothing the top surface of the device layer 108, the TTV of the device layer 108 is low. This, in turn, promotes high uniformity between semiconductor devices on the device layer 108 and becomes increasingly important with the continued reduction in the size of semiconductor devices.

[0070] The in-situ annealing may be performed, for example, by flowing a hydrogen gas (e.g., H2) over the device layer 108 at elevated temperatures. The flow rate of the hydrogen gas may be, for example, approximately 10 to 30 SLM, approximately 10 to 20 SLM, or approximately 20 to 30 SLM, and / or the elevated temperatures may be, for example, approximately 750 to 1100°C, approximately 750 to 925°C, or approximately 925 to 1100°C. The in-situ annealing may, for example, last for approximately 30 to 300 seconds, approximately 30 to 165 seconds, or approximately 165 to 300 seconds, and / or may, for example, be performed at a pressure of approximately 6.7 mbar to 1013 mbar (5 to 760 Torr), approximately 6.7 mbar to 507 mbar (5 to 380 Torr), or approximately 507 mbar to 1013 mbar (380 to 760 Torr).

[0071] As shown in the cross-sectional view 1600 of Fig. 16, the thickness T dof the device layer 108. In some embodiments, the thickness T d of the device layer 108 measured at a single position of the device layer 108. In other embodiments, the thickness T d of the device layer 108 measured at multiple positions across the device layer 108. In some embodiments, the thickness T d of the device layer 108 using an optical device 1602. For example, the optical device 1602 can be used to measure the thickness T d of the device layer 108 by spectral reflectance, ellipsometry, another optical thickness measurement technique, or any combination of the foregoing.

[0072] After the measurement, the difference between the measured thickness of the device layer 108 and the desired final thickness of the device layer 108 is determined. In some embodiments where the thickness Td of the device layer 108 is measured at multiple locations, the multiple measurement results are combined into a single value that is used to determine the difference. The multiple measurements may be combined, for example, by an averaging function, a maximum function, a minimum function, a median function, or another function. The difference between the measured thickness and the desired thickness is then distributed over multiple removal cycles subsequently performed on the device layer 108 to achieve the desired final thickness, such that each of the removal cycles has a target removal amount.For example, assuming a difference between the measured thickness and the desired thickness is 10 nanometers, the 10 nanometers may be distributed across two removal cycles such that a first removal cycle has a target removal amount of 5 nanometers and a second removal cycle has a target removal amount of 5 nanometers. As another example, assuming a difference between the measured thickness and the desired thickness is 10 nanometers, the 10 nanometers may be distributed across two removal cycles such that a first removal cycle has a target removal amount of 7 nanometers and a second removal cycle has a target removal amount of 3 nanometers, or vice versa. In some embodiments, the target removal amount for each removal cycle is the difference between the measured and desired final thickness divided by the total number of removal cycles.In other embodiments, the target removal amount increases for each removal cycle from the first removal cycle to the last removal cycle such that the last removal cycle removes the least amount of device layer 108 compared to the remaining removal cycles.

[0073] As shown by cross-sectional views 1700A, 1700B, 1800 of each Fig. 17A, Fig. 17B and 18, respectively, a first removal cycle is performed to remove a corresponding target removal amount from the device layer 108. It should be noted that Fig. 17B is an enlarged cross-sectional view 1700B taken, for example, within box BX of Fig. 17A can be drawn.

[0074] In Figures 1700A and 1700B, a top surface of the device layer 108 is oxidized. The oxidation partially consumes the device layer 108 to reduce the thickness T dof the device layer 108. In addition, the oxidation forms an oxide layer 1702 on the device layer 108. The dashed line LN in the oxide layer 1702 may, for example, represent a top surface of the device layer 108 before oxidation. In some embodiments, a thickness T o of the oxide layer 1702 approximately twice the thickness reduction T Δd the device layer 108.

[0075] The oxidation may be performed, for example, by exposing the device layer 108 to an aqueous solution. The exposure may last, for example, approximately 6 to 60 seconds, approximately 5 to 30 seconds, or approximately 30 to 60 seconds. The aqueous solution may, for example, comprise ozone (e.g., O3) dissolved in the deionized water. One or more parameters of the oxidation may be varied, for example, to control the oxidation such that the thickness reduction T Δdof the device layer 108 is equal to or approximately equal to the target removal amount. The parameter(s) may include, for example, the duration of exposure, the amount of ozone in the chemical solution, another parameter, or any combination of the foregoing. In some embodiments, the relationship between the parameter(s) and the thickness reduction T Δd determined experimentally so that the parameter(s) can be adjusted to achieve the target distance amount with a high degree of accuracy.

[0076] At Fig. 18, a fourth etching is performed on the oxide layer 1702 (see Fig. 17A and Fig. 17B). The fourth etch stops on the device layer 108 and removes the oxide layer 1702. The fourth etch may be performed, for example, using a hydrofluoric acid (HF) etchant, another suitable wet etchant, a dry etchant, or another suitable etchant. The HF etchant may be, for example, or include a chemical or aqueous solution containing hydrofluoric acid. The hydrofluoric acid may, for example, comprise 0.1 to 1.0 weight or volume percent of the chemical or aqueous solution. The HF etchant may, for example, be applied to the oxide layer 1702 for approximately 10 to 30 seconds, approximately 10 to 20 seconds, or approximately 20 to 30 seconds.

[0077] The fourth etch comprises a first etch rate for a material of the oxide layer 1702, and further comprises a second etch rate for a material of the device layer 108 that is smaller than the first etch rate. In some embodiments, the ratio of the first etch rate to the second etch rate (i.e., the selectivity) is high. For example, the ratio may be high in that the first etch rate is approximately 12, 30, 50, or 100 times greater than the second etch rate. Embodiments in which the ratio of the first etch rate to the second etch rate is high may arise, for example, when the oxide layer 1702 is or comprises silicon oxide and the device layer 108 is or comprises single-crystal silicon. Because the ratio of the first etch rate to the second etch rate is high, the oxide layer 1702 may be removed with minimal damage (e.g., overetching) to an upper surface of the device layer 108.Consequently, the device layer 108 has a low TTV and a hot crystal quality.

[0078] As shown by the cross-sectional views 1900A, 1900B, 2000 of each Fig. 19A, Fig. 19B and 20, the processes at Fig. 17A, Fig. 17B and Fig. 18 is repeated to perform a second removal cycle. The second removal cycle removes a corresponding target removal amount from the device layer 108 and further thins the device layer 108 to the desired final thickness. Fig. 19A and Fig. 19B repeat the operations at Fig. 17A and Fig. 17B, and Fig. 19B is an enlarged cross-sectional view 1900B taken, for example, within box BX of Fig. 19A can be drawn. Fig. 20 repeats the processes at Fig. 18. Together, the device layer 108, the first insulation layer 106f, the second insulation layer 106s, and the handle substrate 104 define an SOI substrate 102.

[0079] In some alternative embodiments, the operations at Fig. 17A, Fig. 17B and Fig. 18 is repeated several times to perform additional removal cycles that thin the device layer 108 to the desired final thickness. In some alternative embodiments, the measurement at Fig. 16 is performed at each removal cycle, and the target removal amounts for remaining removal cycles are updated based on the latest measurements of the device layer 108.

[0080] By cyclically thinning the device layer 108 to the desired final thickness (as in Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19A, Fig. 19B and Fig. 20), several small removal steps can be performed instead of one large removal step. This in turn allows greater control over the final thickness of the device layer 108. For example, the thickness T d The device layer 108 can be precisely reduced to a final thickness that is less than approximately 20 or 10 nanometers and / or between approximately 7 to 20 nanometers, approximately 7 to 13 nanometers, or approximately 13 to 20 nanometers. Such a small thickness is used with fully depleted MOS devices and other advanced MOS devices.

[0081] As also shown by the cross-sectional view 2100 of Fig. 21, a plurality of semiconductor devices 402 are formed on the device layer 108. The semiconductor devices 402 may, for example, be as described with reference to Fig. 4, and / or may be, for example, MOSFETs, other MOS devices, other IGFETs, other suitable semiconductor devices, or any combination of the foregoing. Furthermore, the semiconductor devices 402 may be, for example, fully depleted or partially depleted semiconductor devices.

[0082] In some embodiments, a process for forming semiconductor devices 402 includes depositing a gate dielectric layer and a conductive layer over device layer 108, and then patterning (e.g., by photolithography) the dielectric layer and the conductive layer into gate electrodes 410 and gate dielectric layers 408. For simplicity of illustration, only one of gate electrodes 410 is labeled 410, and only one of gate dielectric layers 408 is labeled 408. Device layer 108 is doped (e.g., by ion implantation or another doping process) to define sources / drains 404 adjacent to sidewalls of gate electrodes 410. For simplicity of illustration, only one of sources / drains 404 is labeled 404.In some embodiments, prior to forming the semiconductor devices 402, isolation structures 412 are formed that extend through the device layer 108 to the second isolation layer 106s.

[0083] As shown in cross-sectional view 2200 of Fig. 22, a BEOL interconnect structure 414 is formed over the device layer 108 and the semiconductor devices 402. The BEOL interconnect structure 414 includes an interconnect dielectric layer, a plurality of wires 418, and a plurality of vias 420. For ease of illustration, only some of the wires 418 are labeled 418, and only some of the vias 420 are labeled 420. The interconnect dielectric layer includes an interlayer dielectric (ILD) layer 416ild, a plurality of interlayer dielectric (IWD) layers 416iwd, and a passivation layer 416p. The IWD layers 416iwd are stacked over the ILD layer 416ild, and the passivation layer 416p is located over the IWD layers 416iwd.The ILD layer 416ild, the IWD layers 416iwd, and the passivation layer 416p may be or include, for example, BPSG, PSG, USG, another low-κ dielectric, silicon oxide, another dielectric, or any combination of the foregoing. The wires 418 and the vias 429 are alternately stacked in the interconnect dielectric layer defined by the ILD layer 416ild, the IWD layers 416iwd, and the passivation layer 416p.

[0084] In some embodiments, a process for forming the BEOL interconnect structure 414 includes forming a bottom layer of the vias 420 using a single damascene process, and then forming a bottom layer of the wires 418 using the single damascene process. Furthermore, in some embodiments, the process includes forming remaining layers of the vias 420 and remaining layers of the wires 418 by repeatedly performing a dual damascene process. In some embodiments, the single damascene process includes depositing a dielectric layer, patterning the dielectric layer with openings for a single layer of conductive features (e.g., a layer of vias or wires), and filling the openings with a conductive material to form the single layer of conductive features.The dielectric layer may, for example, correspond to the ILD layer 416ild or a lower IWD layer of the IWD layers 416iwd. In some embodiments, the dual damascene process includes depositing a dielectric layer, patterning the dielectric layer with openings for two layers of conductive features (e.g., a layer of vias and a layer of wires), and filling the openings with a conductive material to form the two layers of conductive features. The dielectric layer may, for example, correspond to one of the IWD layers 416iwd above the lower IWD layer.

[0085] With reference to Fig. 23 is a block diagram 2300 of some embodiments of the method of Fig. 5 to 16, 17A, 17B, 18, 19A, 19B, and 20 to 22. For example, the method may form a thin SOI substrate having a thickness between approximately 7 to 20 nanometers.

[0086] At 2302, a first insulation layer is formed over a handle substrate. See, for example, Fig. 5.

[0087] At 2304, a buffer layer, an etch stop layer, a device layer, and a dielectric cap layer are formed stacked on a sacrificial substrate. See, for example, Fig. 6. In some embodiments, the buffer layer is or comprises single-crystal P--type silicon, the sacrificial substrate is or comprises single-crystal P+-type silicon, the device layer is or comprises single-crystal silicon, the dielectric layer is or comprises an oxide, or any combination of the foregoing. In some embodiments, the etch stop layer 606 is silicon germanium having a germanium concentration between approximately 20 to 60 atomic percent and a boron doping concentration of approximately 1 × 10 19 up to 5 × 10 21 atoms / cm 3In some embodiments, the etch stop layer 606 is or comprises undoped silicon germanium having a germanium concentration between approximately 20 to 60 atomic percent. In some embodiments, the etch stop layer 606 is elemental silicon having a boron doping concentration of approximately 1 × 10 19 up to 5 × 10 21 atoms / cm 3 or indicates this.

[0088] At 2306, edge portions of the buffer layer, the etch stop layer, the device layer, and the dielectric cap layer are removed. See, for example, Fig. 7.

[0089] At 2308, the dielectric cover layer is removed. See for example Fig. 8.

[0090] At 2310, a second insulation layer is formed on the device layer. See, for example, Fig. 9. In some embodiments, the second insulating layer has a negative charge or a neutral charge. By having a neutral charge, the second insulating layer does not affect the performance (e.g., on-state resistance, threshold voltage, etc.) of semiconductor devices subsequently formed on the device layer. By having a negative charge, the second insulating layer electrostatically repels a negative charge, thereby preventing or reducing leakage current for the semiconductor devices.

[0091] At 2312, the sacrificial substrate is bonded to the handle substrate such that the buffer layer, the etch stop layer, the device layer, the first insulation layer, and the second insulation layer are located between the device and handle substrates. See, for example, Fig. 10.

[0092] At 2314, the sacrificial substrate, buffer layer, and etch stop layer are removed. See, for example, Fig. 11 to 15. The removal of the sacrificial substrate can be performed, for example, by mechanical grinding, an HNA etch, another removal process, or any combination of the above. The removal of the buffer layer can be performed, for example, by a CMP, a TMAH etch, another removal process, or any combination of the above. The removal of the etch stop layer can be performed, for example, by an HCL etch, another removal process, or any combination of the above.

[0093] For example, TMAH etching may have a high selectivity for the buffer layer with respect to the etch stop layer, at least in embodiments where the buffer is or comprises single-crystal silicon and the etch stop layer is or comprises undoped silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon. The high selectivity allows removal of the buffer layer with minimal damage to the etch stop layer, whereby the etch stop layer may have a small TTV and subsequent processing may be very uniform. HCl etching may, for example, have a high selectivity for the etch stop layer with respect to the device layer, at least in embodiments where the device layer is or comprises single-crystal silicon and the etch stop layer is or comprises undoped silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon.The high selectivity allows removal of the etch stop layer with minimal damage to the device layer, resulting in a low TTV, low surface roughness, and high crystal quality. Consequently, semiconductor devices formed on the device layer are more uniform and exhibit better performance (e.g., lower leakage current, high power efficiency, etc.).

[0094] In some embodiments, an annealing process is performed to smooth a top surface of the device layer after the etch stop layer is removed. The annealing process is performed in-situ, so that the device layer is not moved from the removal of the etch stop layer to the annealing process. By smoothing the top surface of the device layer, the TTV and surface roughness of the device layer are further reduced, thereby further improving the uniformity of the subsequently formed semiconductor devices.

[0095] In 2316, the device layer is thinned by cyclic oxidation and removal of a resulting oxide. See, for example, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18, Fig. 19A, Fig. 19B and Fig. 20. By cyclic thinning of the device layer, multiple small removal steps can be performed instead of one large removal step. This, in turn, allows greater control over the final thickness of the device layer.

[0096] At 2318, semiconductor devices are formed on the device layer. See, for example, Fig. 21.

[0097] At 2320, an interconnect structure is formed over the semiconductor devices and the device layer. See, for example, Fig. 22.

[0098] As mentioned with reference to Fig. 5 to 16, 17A, 17B, 18, 19A, 19B and 20 to 22, and further with reference to Fig. 23, the SOI substrate can be formed without causing implant radiation and / or plasma damage to the second insulation layer and the device layer. The implantation is not performed through the second insulation layer and the device layer. Furthermore, the second insulation layer and the device layer cannot be directly exposed to plasma. Since the second insulation layer and the device layer are not subject to implant radiation and / or plasma damage, leakage current and power consumption for semiconductor devices formed on the device layer are low.

[0099] With reference to Fig. 24, a block diagram 2400 of some embodiments of a method for performing device layer thinning is provided. The method may, for example, be performed at 2316 of Fig. 23 to cyclically thin the device layer.

[0100] At 2402, a thickness of a device layer is measured. See, for example, Fig. 16. The thickness can be measured optically, for example.

[0101] At 2404, a top surface of the device layer is oxidized to partially consume the device layer, wherein the oxidation forms an oxide layer and reduces a thickness of the device layer. See, for example, Fig. 17A and Fig. 17B and Fig. 19A and Fig. 19B. The thickness reduction may, for example, be smaller than the difference between the measured thickness of the device layer and the desired final thickness of the device layer. The oxidation may, for example, be performed by exposing the device layer to an aqueous solution in which ozone is dissolved.

[0102] In 2406, the oxide layer is removed. See for example Fig. 18 and Fig. 21. Removal can be performed, for example, by HF etching or other etching.

[0103] At 2408, operations 2404 and 2406 are repeated one or more times until the difference between the measured device layer thickness and the desired final device layer thickness is approximately equal to the total thickness reduction of the device layer from the oxidation at 2404. As mentioned above, by cyclically thinning the device layer to the desired final thickness, multiple smaller thinning processes can be performed instead of one large thinning process. This, in turn, allows greater control over the final device layer thickness.

[0104] Although the block diagrams 2300, 2400 of Fig. 23 and Fig.24 are illustrated and described herein as a series of acts or events, it is understood that the illustrated order of such acts or events is not intended to be limiting. For example, besides those illustrated and / or described herein, some acts may occur in different orders and / or concurrently with other acts or events. Furthermore, acts not illustrated may be required to implement one or more aspects or embodiments of the description, and one or more of the acts illustrated herein may be performed in one or more separate acts and / or phases.

[0105] In some embodiments, the present application provides a method of forming an SOI substrate, the method comprising: epitaxially growing a device layer on a sacrificial substrate; bonding the sacrificial substrate to a handle substrate such that the device layer is located between the sacrificial and handle substrates; removing the sacrificial substrate; and cyclically thinning the device layer with a plurality of thinning cycles until the device layer has a target thickness, wherein each thinning cycle comprises oxidizing a portion of the device layer and removing an oxide resulting from the oxidation, wherein a first thinning cycle of the plurality of thinning cycles removes a greater thickness of the device layer according to a first target removal amount than a second thinning cycle with a second target removal amount performed after the first thinning cycle.The method further comprises adjusting one or more parameters of an oxidation of oxidizing the portion of the device layer such that a thickness reduction of the device layer through the respective thinning cycle is equal to or approximately equal to a target removal amount for the respective thinning cycle. In some embodiments, the method further comprises: measuring a thickness of the device layer; and determining a difference between the measured thickness and the target thickness, wherein the cyclic thinning comprises at least two thinning cycles, and wherein the at least two thinning cycles each partially reduce the difference. In some embodiments, the oxidizing comprises exposing the device layer to a chemical solution in which ozone is dissolved in water, wherein the removal comprises exposing the oxide to a chemical solution comprising hydrofluoric acid.In some embodiments, the method further comprises: epitaxially forming an etch stop layer on the sacrificial substrate, wherein the etch stop layer comprises undoped silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon, and wherein the device layer is formed on the etch stop layer; and removing the etch stop layer between removing the sacrificial substrate and cyclic thinning. In some embodiments, removing the etch stop layer comprises an HCl etch. In some embodiments, the method further comprises forming an insulating layer on the device layer, wherein the insulating layer has a net charge that is neutral and is located between the sacrificial and handle substrates during bonding.In some embodiments, the method further comprises forming an insulating layer on the device layer, wherein the insulating layer has a net charge that is negative and is located between the sacrificial and handle substrates during bonding. In some embodiments, forming the insulating layer comprises oxidation by oxygen radicals.

[0106] In some embodiments, the present application provides another method of forming an SOI substrate, the method comprising: epitaxially forming a buffer layer on a sacrificial substrate; epitaxially forming an etch stop layer over the buffer layer; epitaxially forming a device layer over the etch stop layer; bonding the sacrificial substrate to a handle substrate such that the buffer layer, the etch stop layer, and the device layer are located between the sacrificial and handle substrates; removing the sacrificial substrate, the buffer layer, and the etch stop layer, wherein removing the sacrificial substrate comprises a thinning process and a first etch, wherein the thinning process is selected from a mechanical grinding process and a CMP process, and wherein the first etch comprises a first etch rate for a material of the sacrificial substrate that is greater than a second etch rate for a material of the buffer layer;and performing an anneal to smooth a top surface of the device layer after the etch stop layer is removed. In some embodiments, the etch stop layer comprises silicon germanium, in which germanium has an atomic percentage of approximately 20 to 60. In some embodiments, the etch stop layer is not doped. In some embodiments, the etch stop layer is doped with p-type dopants to a concentration of approximately 1 x 10 19 to 5 x 10 ; 21 atoms per cubic centimeter. In some embodiments, the etch stop layer comprises elemental silicon doped with p-type dopants to a concentration of approximately 1 x 1019 to 5×10 21atoms per cubic centimeter. In some embodiments, removing the buffer layer comprises a TMAH etch. In some embodiments, removing the etch stop layer comprises an HCl etch. In some embodiments, the annealing is performed in situ without first moving the device layer from its position during removal of the etch stop layer.

[0107] In some embodiments, the present application provides an SOI substrate comprising: a handle substrate; a first insulating layer overlying the handle substrate; and a device layer overlying the first insulating layer; and a second insulating layer overlying the handle substrate and the device layer, wherein a portion of the second insulating layer adjacent to the device layer has a net charge that is negative or neutral, wherein a sidewall of the second insulating layer is laterally recessed from a sidewall of the first insulating layer by a lateral recess amount, the lateral recess amount being approximately 0.8 to 1.2 millimeters. In some embodiments, the second insulating layer comprises silicon oxide, and the device layer comprises single-crystal silicon.In some embodiments, the device layer has a thickness of approximately 7 to 14 nanometers. In some embodiments, the device layer has a p-type doping type.

Claims

[1] A method of forming an SOI substrate (102), the method comprising: epitaxially forming a device layer (108) on a sacrificial substrate (602), Bonding the sacrificial substrate (602) to a handle substrate (104) such that the device layer (108) is located between the sacrificial substrate (602) and the handle substrate (104), Removing the sacrificial substrate (602), and cyclically thinning the device layer (108) until the device layer (108) has a target thickness, wherein each thinning cycle comprises oxidizing a portion of the device layer (108) and removing an oxide resulting from the oxidation, further comprising: Forming an insulating layer (106, 106s) on the device layer (108), the insulating layer (106, 106s) having a net charge that is negative and being located between the sacrificial and handle substrates (104) during bonding. [2] The method of claim 1, further comprising: Measuring a thickness of the device layer (108), and Determining a difference between the measured thickness and the target thickness, wherein the multiple thinning cycles each partially reduce the difference. [3] The method of claim 1 or 2, wherein oxidizing comprises exposing the device layer (108) to a chemical solution in which ozone is dissolved in water, and wherein removing comprises exposing the oxide to a chemical solution comprising hydrofluoric acid; and / or wherein the one or more parameters of the oxidation are a duration of exposure and / or an amount of ozone in the aqueous solution; and / or wherein the one or more parameters of the oxidation are adjusted according to an experimentally determined relationship between the parameter and a thickness reduction (TΔd) through the respective thinning cycle, such that a thickness reduction (TΔd) of the device layer (108) through the respective thinning cycle is equal to or approximately equal to a target removal amount for the respective thinning cycle. [4] Method according to one of the preceding claims, further comprising: epitaxially forming an etch stop layer (606) on the sacrificial substrate (602), wherein the etch stop layer (606) comprises undoped silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon, and wherein the device layer (108) is formed on the etch stop layer (606), and Removing the etch stop layer (606) between removing the sacrificial substrate (602) and cyclic thinning. [5] The method of claim 4, wherein removing the etch stop layer (606) comprises a salt gas etch, also called HCl etch gas etch. [6] The method according to any one of claims 1 to 5, wherein forming the insulating layer (106, 106s) comprises oxidation using oxygen radicals. [7] A method of forming an SOI substrate (102), the method comprising: epitaxially forming a buffer layer (604) on a sacrificial substrate (602), epitaxially forming an etch stop layer (606) over the buffer layer (604), epitaxially forming a device layer (108) over the etch stop layer (606), wherein the etch stop layer (606) is doped with p-type dopants to a concentration of approximately 1×10 19 up to 5×10 21 atoms per cubic centimeter, Bonding the sacrificial substrate (602) to a handle substrate (104) such that the buffer layer (604), the etch stop layer (606) and the device layer (108) are located between the sacrificial and the handle substrate (104), Removing the sacrificial substrate (602), the buffer layer (604) and the etch stop layer (606), wherein the removal of the sacrificial substrate (602) comprises a thinning process and a first etching, wherein the thinning process is selected from a mechanical grinding process and a CMP process, and wherein the first etching has a first etch rate for a material of the sacrificial substrate (602) which is greater than a second etch rate for a material of the buffer layer (604), and Performing an anneal to smooth a top surface of the device layer (108) after the etch stop layer (606) has been removed. [8] The method of claim 7, wherein the etch stop layer (606) comprises silicon germanium in which germanium has an atomic percentage of about 20 to 60. [9] The method according to any one of claims 7-9, wherein the sacrificial substrate (602) comprises single-crystalline p + -silicon, and the buffer layer (604) is single-crystalline p- -is or has silicon. [10] A method according to any one of the preceding claims 7 to 9, wherein the etch stop layer (606) comprises elemental silicon doped with p-type dopants to a concentration of approximately 1×10 19 up to 5×10 21 atoms per cubic centimeter. [11] The method of any one of the preceding claims 7 to 10, wherein removing the buffer layer (604) comprises a tetramethylammonium hydroxide etch, also called TMAH etch. [12] Method according to one of the preceding claims 7 to 11, wherein the removal of the etch stop layer (606) comprises a salt gas etch, also called HCl etch gas etch. [13] The method of any one of the preceding claims 7 to 12, wherein the annealing is performed in-situ without first moving the device layer (108) from its position during removal of the etch stop layer (606). [14] SOI substrate, comprising: a handle substrate (104), a first insulation layer (106, 106f) lying over the handle substrate (104), a device layer (108) overlying the first insulation layer (106, 106f), and a second insulating layer (106s) disposed between the handle substrate (104) and the device layer (108), wherein a portion of the second insulating layer (106s) adjacent to the device layer (108) has a net charge that is negative, and wherein a sidewall of the second insulation layer (106s) is laterally recessed from a sidewall (106sw) of the first insulation layer (106, 106f) by a lateral recess amount (LR), the lateral recess amount (LR) being approximately 0.8 to 1.2 millimeters. [15] The SOI substrate of claim 14, wherein the second insulation layer (106s) comprises silicon oxide, and wherein the device layer (108) comprises single-crystal silicon, and / or wherein the device layer (108) has a thickness of approximately 7 to 14 nanometers. [16] SOI substrate according to claim 14 or 15, wherein the first insulating layer (106, 106f) and the second insulating layer (106s) were formed by different manufacturing processes; and / or wherein the first insulation layer (106, 106f) and the second insulation layer (106s) have different charges; and / or wherein the first insulation layer (106, 106f) has a positive or neutral charge. [17] The SOI substrate of any one of the preceding claims 14 to 16, wherein the device layer (108) has a p-doping type.

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