PRE-CLEANING FOR CONTACTS

Abstract

Method comprising: Forming (110) a dielectric layer (230, 235, 245) over a contact region on a substrate (210); Etching (120, 130) the dielectric layer (230, 235, 245) to form a contact opening (300, 400, 500) to expose the contact area; and Pre-cleaning (140) the exposed contact area in a reactor (700) having a conductive frame (715) for supporting the substrate (210) to remove a residual material (600) formed by the etching, the pre-cleaning comprising: - exposing the first contact region to an inductively coupled radio frequency plasma (705), wherein the radio frequency plasma (705) is generated by an inductively coupled radio frequency plasma source; - applying, with a DC power supply unit (710), a bias voltage to the substrate (210); and - applying a magnetic field to the inductively coupled radio-frequency plasma (705) to concentrate ions, wherein applying the magnetic field comprises generating the magnetic field by magnets (725, 730) each having oppositely arranged polarities, and wherein the magnetic field is perpendicular to a top surface of the conductive frame (715), wherein a respective axis passing through the north pole and the south pole of the respective magnets (725, 730) is arranged perpendicular to the top surface of the conductive frame (715).

Description

TECHNICAL BACKGROUND

[0001] Contact formation in semiconductor manufacturing involves several processes, such as one or more photolithography processes, etching processes, wet cleaning, pre-cleaning, and metal deposition. The resistance of the formed contacts may depend on the efficiency of the pre-cleaning process used during contact opening formation. A corresponding method including pre-cleaning of an exposed contact area is known from EP 1 081 751 A2. Forming contact openings is known from EP 1 308 986 A2. Another method and apparatus are known from US 2013 / 0 187 546 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with industry practice, some features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1 is a flow diagram of an exemplary method including a novel pre-cleaning process in accordance with some embodiments. Fig. 2 is a cross-sectional view of a dielectric stack over gate structures and metal contacts in accordance with some embodiments. Fig. 3 is a cross-sectional view of contact openings in a dielectric stack over gate structures in accordance with some embodiments. Fig. 4 and Fig. 5 are cross-sectional views of contact openings in a dielectric stack above gate structures and metal contacts in accordance with some embodiments. Fig. 6 is a cross-sectional view of contact openings with a residual or redeposition layer in accordance with some embodiments. Fig. 7 is a cross-sectional view of a pre-purification reactor in accordance with some embodiments. Fig. 8 is a cross-sectional view of contact openings in a dielectric stack over gate structures and metal contacts after a pre-cleaning process in accordance with some embodiments. Fig. 9 is a cross-sectional view of contact openings in a dielectric stack over gate structures and metal contacts after nucleation layer deposition in accordance with some embodiments. Fig. 10 is a cross-sectional view of contact openings in a dielectric stack over gate structures and metal contacts after metal deposition in accordance with some embodiments. Fig. 11 is a cross-sectional view of metal contacts in a dielectric stack over gate structures and metal contacts after a chemical mechanical planarization process in accordance with some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides various embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed that are between the first and second features such that the first and second features are not in direct contact.

[0004] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0005] The term "nominal" as used herein refers to a desired or target value of a property or parameter for a component or process operation, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​is typically due to slight variations in manufacturing processes or tolerances.

[0006] The term "substantially" as used herein refers to the value of a given quantity, which may vary based on a particular technology node associated with the semiconductor device in question. In some embodiments, based on the particular technology node, the term "substantially" may indicate a value of a given quantity that varies within, for example, ±5% of a target (or intended) value.

[0007] The term "about" as used herein refers to the value of a given quantity, which may vary based on a particular technology node associated with the subject semiconductor device. In some embodiments, based on the particular technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0008] The term “vertical” as used herein means nominally perpendicular to the surface of a substrate.

[0009] Metallization in semiconductor manufacturing involves several processes, which may include one or more of photolithography, etching, wet cleaning, pre-cleaning, and metal deposition. The pre-cleaning process may be used to (i) remove oxides from a bottom surface of a contact opening and (ii) prepare surfaces of the contact opening for subsequent metal deposition. The pre-cleaning process may include chemical etching (e.g., a chemical reaction that dissolves the oxide), physical etching (e.g., ion bombardment / sputtering of the oxide), or a combination thereof. A side effect of the pre-cleaning process may be "redeposition" of oxide material from the sidewalls of the contact opening to the bottom surface of the contact opening and / or reshaping of the profile of the contact opening.In terms of reshaping the contact opening profile, the pre-cleaning process can cause several undesirable effects, including "necking" (e.g., a narrowing of the top opening of the contact opening, known as the "re-entrant profile"), "bowing" (e.g., a widening of the center portion of the contact opening), a widening of a bottom portion of the contact opening, or a combination thereof. Any of the aforementioned contact profile changes can result in metal filling problems (e.g., folds or gaps), contact resistance increases, and / or metal contact breaks, short circuits, and other undesirable interconnect characteristics.

[0010] Embodiments of the present disclosure are directed to a pre-cleaning process that may reduce contact profile modifications and oxide redeposition from the sidewalls of the contact opening. In some embodiments, the pre-cleaning process includes a physical etch, such as an argon ion (Ar +) Sputter pre-cleaning process with improved ion directionality. In some embodiments, a substrate tuning bias, which may be supplied from a stacked DC power supply and combined with an inductively coupled plasma power source, may be used to modulate the direction and energy of the argon ions. Furthermore, magnets or electromagnets (e.g., coils) located on the sidewalls of the pre-cleaning reactor may further improve the directionality of the argon ions. In some embodiments, an extended stage with a wide diameter (e.g., 300 mm to 330 mm) and adjustable height (e.g., 12 mm to 12.5 mm) may be used to improve pre-cleaning uniformity across the substrate. In some embodiments, the tunable bias range may be from about -100 volts to about 100 volts.

[0011] According to some embodiments, Fig. 1 is a flow diagram of an exemplary method 100 including a novel pre-cleaning process that provides (i) improved oxide removal from the bottom surface of the contact opening, (ii) and reduced contact profile variation. Other manufacturing operations may be performed between the various operations of exemplary method 100 and may be omitted solely for the sake of clarity. Embodiments of the present disclosure are not limited to method 100.

[0012] Method 100 begins with operation 110, in which a dielectric stack is formed over gate structures and metal contacts. By way of example and not limitation, Fig. 2 shows a cross-sectional view of a partially fabricated semiconductor structure described in operation 110, where a dielectric stack comprising interlayer dielectric (ILD) 245 and etch stop layer 240 is formed over gate structures 205 and metal contacts 200. According to some embodiments, gate structures 205 and metal contact 200 may be formed at an earlier stage of the manufacturing process. For example, Fig. 2 may be a partially fabricated wafer in the middle of the line (MOL) where metal contacts 200 and gate structures 205 were previously formed over a substrate 210.

[0013] Substrate 210 may be a semiconductor wafer (e.g., a bulk silicon wafer or a silicon-on-insulator wafer). According to some embodiments, substrate 210 may comprise silicon or another elemental semiconductor, such as germanium (Ge). Further, substrate 210 may comprise layers or structures formed in Fig. 2 are not shown solely for clarity. For example, substrate 210 may include any number or type of doped regions (e.g., n-type or p-type wells, channel regions, lightly doped regions, heavily doped regions such as source and drain regions, etc.), epitaxially grown source and drain layers, isolation regions such as shallow trench isolation (STI) regions, etc.

[0014] Gate structures 205 may include at least a gate electrode stack and a gate dielectric - both are in Fig. 2 is not shown for clarity. In some embodiments, the high-k dielectric may be hafnium oxide (HfO2), a hafnium silicate-based material, or any suitable dielectric material with a dielectric constant (k value) greater than 3.9—which is the dielectric constant of stoichiometric silicon oxide (SiO2) and is used as an example reference. The gate electrode stack may include a cap layer over the gate dielectric, one or more metallic layers or a work function metal (WFM) stack, a metal fill layer, any other suitable material, or any combination thereof. The number and type of metallic layers in the gate electrode stack may depend on threshold voltage requirements of a transistor.By way of example and not limitation, exemplary metallic layers in the gate electrode stack may include a tantalum nitride (TaN) bottom layer and one or more titanium nitride (TiN) layers. In some embodiments, the WFM stack may include titanium / aluminum (Ti / Al) bilayers or a titanium-aluminum (Ti-Al) alloy. The WFM stack may tune the work function of the gate electrode and affect the threshold voltage of the resulting transistor. However, the thickness and number of the one or more TiN layers in combination with the WFM stack may adjust the threshold voltage of the transistor. In some embodiments, the metal fill layer may include a TiN barrier layer and a tungsten (W) metal stack.

[0015] Adjacent gate structures 205 are gate spacers 215. Gate spacers 215 may comprise a dielectric material such as SiO2, silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), silicon oxycarbide (SiO x C y ), silicon nitride (Si x N y or SiN), any other suitable material, or any combination thereof. Additionally, gate spacers 215 may be a stack of one or more layers comprising the same or different materials. In some embodiments, gate spacers 215 may be used as alignment masks for the source / drain implants.

[0016] Metal contacts 200 may include a barrier layer 220 and a metal fill 225. In some embodiments, barrier layer 220 may include TiN and metal fill 225 may include cobalt (Co) or W. In some embodiments, metal contacts 200 are formed over epitaxial source / drain layers or regions—which in Fig. 2 are not shown. Furthermore, a silicide (not shown in Fig. 2) may be formed between the epitaxial source / drain region and metal contacts 200. Metal contacts 200 and gate structures 205 are formed in insulation layer 230. Insulation layer 230 may be a single dielectric layer or a stack of dielectrics that electrically isolate the embedded structures, such as metal contacts 200 and gate structures 205. In some embodiments, insulation layer 230 may be SiO2, carbon-doped silicon oxide (SiO xC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), SiN, any other suitable material, or any combination thereof. By way of example and not limitation, if insulation layer 230 comprises a material other than SiN (e.g., silicon oxide), a SiN cap layer (not shown) may be used. Fig. 2) over gate structure 205 and gate spacers 215.

[0017] Interlayer dielectric (ILD) 235 can be formed over insulation layer 230. In the example of Fig. 2, ILD 235 surrounds metal contacts 200 via insulation layer 230. According to some embodiments, ILD 235 may be a single dielectric layer or a stack of dielectrics including SiO2, SiO xC, SiON, SiOCN, SiC, SiCN, SiN, any other suitable material, or any combination thereof. ILD 235 can have a thickness range between about 10 nm and about 20 nm.

[0018] An etch stop layer 240 having a thickness between about 10 nm and about 20 nm may be formed over ILD 235, and ILD 245 may be formed over etch stop layer 240. By way of example and not limitation, etch stop layer 240 may be a SiN layer, and ILD 245 may be a single dielectric layer or a dielectric stack comprising SiO2, SiO x C, SiON, SiOCN, SiC, SiCN, any other suitable material, or a combination thereof. The thickness of ILD 245 can be between about 40 nm and 60 nm.

[0019] In relation to Fig. 1 and Fig. 3, method 100 continues with operation 120 and the formation of first contact openings 300 (hereinafter contact openings 300) in the dielectric stack (e.g., ILD 235 and etch stop layer 240) and insulation layer 230 to expose the underlying gate structures 205. Contact openings 300 may be formed by patterning ILD 245, etch stop layer 240, ILD 235, and insulation layer 230 with photolithography and etch processes. By way of example and not limitation, the formation of contact openings 300 is described below. A film of photoresist (not shown) Fig. 3) may be applied over ILD 245. The photoresist may be patterned (e.g., exposed and developed) according to a desired pattern; for example, a desired pattern may be the formation of openings in the photoresist that are aligned with gate structures 205 and expose respective portions of ILD 245. Unexposed areas of the photoresist may be removed using a wet or dry etching process to leave the desired pattern of developed photoresist on ILD 245. A dry etching process may, for example, be used to remove exposed areas of ILD 245 through the openings in the patterned photoresist. Areas of ILD 245 covered by the developed photoresist may be protected from the etch chemistry of the dry etching process and therefore not etched. The etching process may be anisotropic, such that the sidewalls of contact opening 300 may be substantially vertical, e.g., greater than 80°.By way of example and not limitation, a dry etch chemistry may use a mixture of carbon fluoride gases (CF. x ). In some embodiments, the etch process may also etch part of gate spacers 215 when gate structure 205 is exposed. The dry etch process may include several steps, each of which may require different etch conditions (e.g., etch chemistry, process pressure, temperature, etc.). Once contact openings 300 are formed, the structural photoresist is removed (e.g., ablated with a wet or dry etch process). In some embodiments, an ashing process is substantially performed to chemically remove any polymer (e.g., carbon-based material) formed as a result of the etch process. Further, wet cleaning may be performed to remove particles and residual photoresist from the surface of ILD 245 and contact openings 300.

[0020] In relation to Fig. 1 and Fig. 4, a method 100 proceeds to operation 130 and the formation of second contact openings 400 (hereinafter contact opening 400) in the dielectric stack (e.g., ILD 235 and etch stop layer 240) to expose the underlying metal contacts 200. Forming contact openings 400 may be accomplished in a single process operation similar to the previously described process to form first contact openings 300. For example, a film of photoresist (not shown) may be applied to ILD 245. The photoresist may subsequently be exposed and developed according to a desired pattern; for example, a desired pattern may be the formation of openings in the photoresist that are aligned with metal contacts 200 and expose respective portions of ILD 245. Unexposed areas of the photoresist may be removed using a wet or dry etch process to leave the desired pattern of developed photoresist on ILD 245.For example, a dry etch process may be used to remove exposed areas of ILD 245 through the openings in the patterned photoresist. Areas of ILD 245 covered by the developed photoresist may be protected from the etch chemistry of the dry etch process and therefore not etched. The etch process may be anisotropic, so that the sidewalls of contact opening 400 may be substantially vertical, for example, greater than 80°. By way of example and not limitation, a dry etch chemistry may use a mixture of carbon fluoride gas (CF x ). The resulting second contact openings 400 are in Fig. 4 shown.

[0021] In some embodiments, a “split” contact opening 500 may be formed as shown in Fig. 5. A split contact opening 500 is a contact opening that simultaneously exposes a metal contact 200 and a gate structure 205. By way of example and not limitation, a split contact opening 500 may be formed with a double photolithography step. The double photolithography step may also include two etching processes. For example, during the first etching process, a first photolithography and a first etching may form a first contact opening that exposes a portion of metal contact 200; and a second photolithography and a second etching process may form a second contact opening, which may be slightly shifted compared to the first opening and may expose a portion of gate structure 205. The combination of the first and second contact openings forms the "split" contact opening 500 shown in Fig. 5 is shown.

[0022] During the formation of contact openings 300, 400 and 500, material from ILD 230 and 245 may be redeposited (e.g., resputtered) at the bottom surfaces of the contact openings to form a residual or redeposition layer 600, as shown in Fig. 6. The formation of residual or redeposition layer 600 is an undesirable side effect of the etching process, which can increase contact resistance. Since the sidewalls of contact openings 300, 400, and 500 are primarily formed of ILD 245 and 235, redeposition layer 600 can contain SiO2, SiO x C, SiON, SiOCN, SiC, SiCN, any other suitable material, or any combination thereof. In some embodiments, the thickness of redeposition layer 600 may range from about 0.3 nm to about 1.3 nm. However, the aforementioned thickness of redeposition layer 600 is not limiting.

[0023] In relation to Fig. 5 and Fig. 6, the profile geometry of each contact opening may be different. For example, contact opening 500 has a wide top opening, a large depth reaching the gate structure 205, and a multi-level bottom surface (e.g., one bottom surface on metal contact 200 and another bottom surface on metal gate structure 205). On the other hand, contact opening 400 has a narrow top opening and a shallower depth. Further, contact opening 300 has a narrow opening, a similar depth to contact opening 400, but a smaller bottom surface. In other words, the contact openings in Fig. 5 and Fig. 6 have different aspect ratios. The aspect ratio of a contact opening can be defined as the ratio of its depth to its width (e.g., its top opening width). Consequently, the aspect ratio of contact opening 300 is larger than the aspect ratios of contact openings 400 and 500.

[0024] High aspect ratio contact openings may be more difficult to clean with a pre-cleaning process that uses physical sputtering to remove oxide. For example, it is more difficult for the sputtered ions to reach the bottom of the contact opening and remove redeposition layer 600. This is because with a high aspect ratio contact of at least (for example) about 3:1, the argon ions have a higher probability of impacting the sidewalls of the opening before reaching the bottom surface of the contact opening. This can result in re-sputtering of material from the sidewalls of the opening and contact profile changes, including diffraction, necking (re-entry profile), or a combination thereof. To mitigate the contact profile changes and improve the cleaning efficiency of the pre-cleaning process, the argon ions must impact the substrate at approximately 90° of incidence with respect to the surface of the substrate.

[0025] Additionally, the argon ions accelerated toward substrate 210 must have sufficient kinetic energy to successfully remove (e.g., clean) redeposition layer 600. According to some embodiments, the pre-cleaning process removes other materials—for example, Ti, W, Co, TiN, and titanium aluminum (TiAl)—at a lower etch rate. As previously discussed, such materials may be included in metal contacts 200 and metal gate structures 205. Consequently, the pre-cleaning process forms a depression on metal contacts 200 and gate structures 205.

[0026] In operation 140 of method 100, a pre-cleaning process is used to remove redeposition layer 600. In some embodiments, the pre-cleaning process may remove from about 5 nm to about 45 nm of oxide (e.g., SiO2). According to some embodiments, the pre-cleaning process uses a physical etch (e.g., ion bombardment) to remove redeposition layer 600 from the bottom surfaces of contact vias 300, 400, and 500. By way of example and not limitation, the pre-cleaning process of operation 140 may be performed in a reactor 700 located in Fig. 7. In the pre-cleaning process of operation 140, argon ions are generated from an argon plasma 705 generated by an inductively coupled radio frequency (RF) plasma source (in Fig. 7 not shown). In some embodiments, the inductively coupled plasma source generates a forward power between about 250 watts and about 600 watts. Within this forward power range, the power reflected from the argon plasma can range from 0 to 50 watts. During the pre-cleaning process, the argon gas flow into reactor 700 can range from about 5 sccm to about 10 sccm, and the reactor pressure can range from about 1.33 Pa (0.01 Torr) to about 666.61 Pa (5 Torr). In some embodiments, a stacked direct current (DC) power supply unit (PSU) 710—which can be attached to a radio frequency (RF) generator 720—can be used to modulate a bias voltage that can be applied to substrate 210 (e.g., a substrate bias voltage) through a conductive stage 715.The substrate bias, in turn, can be used to modulate the energy at which the argon ions from the plasma impact the surface of substrate 210—and therefore the amount of sputtering during the pre-cleaning process. Consequently, the stacked DC PSU 710 can be used to tune the amount of sputtering in the pre-cleaning process. In some embodiments, the DC PSU 710 can apply a substrate bias between about -100 volts and about 100 volts (e.g., about -100 volts, about -50 volts, about -20 volts, about 0 volts, about 20 volts, about 50 volts, about 100 volts, etc.) to achieve an optimal sputtering amount. For example, a substrate bias below about -100 volts may increase the amount of sputtering but damage the substrate. On the other hand, a substrate bias above 100 volts may result in an adequate amount of sputtering. Electrical connections to conductive frame 715 are provided, for example, with a through connection 735.Additionally, conductive stage 715 may, for example, be an electrostatic liner comprising a conductive top portion (not shown) comprising Ti and an insulating bottom portion (not shown) comprising quartz. The conductive top portion of conductive stage 715 may be in contact with the backside of substrate 210. In some embodiments, conductive stage 715 has a diameter larger than substrate 210 (e.g., 300 mm). A larger diameter stage may provide improved pre-cleaning uniformity according to some embodiments. For example, the diameter of conductive stage 715 may range from about 300 mm (e.g., approximately equal to the diameter of substrate 210) to about 330 mm. A conductive stage with a diameter greater than about 300 mm does not provide additional uniformity benefits according to some embodiments.Further, extended conductive stage 715 has a height that can range from about 12.0 mm to about 12.5 nm. According to some embodiments, cleaning efficiency for the pre-cleaning process can be tuned by combining the bias voltage applied to argon plasma 705 and the DC bias voltage applied to substrate 210 by stacked DC PSU 710. The aforementioned ranges should not be considered limiting, and other ranges may be used depending on the reactor geometry.

[0027] Pre-cleaning uniformity and etching amounts can be further fine-tuned using cylindrical magnets 725 and 730 attached to opposite side walls of reactor 700. In some embodiments, magnets 725 and 730 can be configured to have opposite polarities, as shown in Fig. 7. The generated magnetic fields, which are perpendicular to conductive stage 715, can focus (collimate, or parallelize) the argon ions from argon plasma 705 over a larger surface area of ​​substrate 210. In some embodiments, side-electron magnets with four sets of coils can be used instead of cylindrical magnets 725 and 730. By way of example and not limitation, the electromagnetic coils can be connected to an RF source, which can provide, for example, about 1.5 kW of power. Modulation of the argon ion energy and alignment can be accomplished by synchronizing the RF signal from the coils, the bias voltage applied to substrate 210, and the bias voltage applied to argon plasma 705.

[0028] The placement of the aforementioned components of reactor 700 may vary depending on the design of reactor 700. Consequently, the illustration of reactor 700 in Fig. 7 is not intended to be limiting. For illustrative purposes, Fig. 7 Selected sections of reactor 700 and other sections (not shown) may be included. For example, gas lines, exhaust lines, electrical connections, heaters, valves, additional plates, match boxes, additional RF generators, additional DC power supplies, isolation transformers, pump stacks, external peripherals and equipment, and other elements may be included.

[0029] The pre-cleaning process conditions discussed previously have a significant effect on the profile of contact openings with different aspect ratios according to some embodiments. For example, if in contact opening 400 of Fig. 8 As the bias applied to substrate 210 (e.g., by stacked DC PSU 710) increases, contact opening 300 may become wider. On the other hand, and for the same substrate bias condition, contact opening 300 may develop a reentrant profile with overhang 810 ranging, for example, from about 12 nm to about 16 nm. Reentrant profiles in contact openings are undesirable because they can result in poor metal fill and high contact resistance. Consequently, for higher substrate bias (e.g., about 100 volts), high aspect ratio contacts (e.g., higher than about 3:1) may develop a reentrant profile, while lower aspect ratio contact openings become larger. Therefore, tuning the bias applied to the substrate may provide a balance between contact profiles in high and low aspect ratio contact openings.

[0030] Further, as previously discussed, the pre-cleaning process may deepen gate structures 205 and metal contacts 200. Deepened gate structures 205 and metal contacts 200 are desirable because they can reduce the resistance of the formed contacts by increasing their bottom surface area. As in Fig. 8, gate structures 205 may be recessed by a recess amount 815, and metal contacts 200 may be recessed by a recess amount 820. By way of example and not limitation, recess amount 815 may range from about 2 nm to about 5 nm, and recess amount 820 may range from about 0.5 nm to about 3 nm. In contact opening 500, a portion of ILD 235 may also be recessed during the pre-cleaning process of operation 140, as shown in Fig. 8 shown.

[0031] The aforementioned recess dimensions 815 and 820 in gate structures 205 and metal contacts 200, respectively, may further result in profile changes for the respective contact openings. For example, the bottom portion, or critical dimensions (CD), of the bottom of the contact openings may become wider. In some embodiments, after the pre-cleaning process of operation 140, the bottom CD for contact openings 300 and 500 may increase between about 5% and about 75%. Accordingly, the bottom CD for contact opening 400 may increase between about 5% and about 75%.

[0032] In relation to Fig. 1, the method 100 continues with operation 150, where contact openings 300, 400, and 500 are filled with a metal. In some embodiments, the filling may be a two-step process comprising a uniform deposition of a nucleation layer followed by a metal fill. According to some embodiments, the nucleation layer and metal fill may comprise W. By way of example and not limitation, Fig. 9 is a cross-sectional view of contact openings 300, 400, and 500 after the uniform deposition of nucleation layer 900. In some embodiments, nucleation layer 900 is deposited after the pre-cleaning process of operation 140 without a "vacuum break" (e.g., in-situ) to prevent or limit oxidation of recessed metal contacts 200 and gate structures 205. By way of example and not limitation, nucleation layer 900 may be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) at a thickness between about 2 nm and about 4 nm. In some embodiments, the substrate temperature during nucleation metal layer deposition may range from about 350°C to about 500°C.Other deposition techniques may be used to form nucleation layer 900, such as plasma-enhanced CVD (PECVD) or plasma-enhanced ALD (PEALD). In some embodiments, the nucleation layer does not fill contact openings 300, 400, and 500.

[0033] The metal filling can be deposited by CVD at a thickness between about 130 nm and about 180 nm. As an example and not a limitation, Fig. 10 the deposition of metal filling 1000 on nucleation layer 900. As in Fig. As shown in Figure 10, metal fill 1000 fills contact openings 300, 400, and 500. For example, and not by way of limitation, metal fill 1000 may not be limited to W, and other metals may be used. In some embodiments, metal fill 1000 is deposited with an overlay that may cover the top surface of ILD 245.

[0034] In some embodiments, a chemical mechanical planarization (CMP) process may be used to polish metal fill 1000, nucleation layer 900, and portions of ILD 245 below overhang 810, as shown in Fig. 11. After the CMP process, the top surfaces of metal fill 1000 and ILD 245 are essentially coplanar. The CMP process completes the formation of the metal contacts over metal contacts 200 and 205.

[0035] In some embodiments, the pre-cleaning process described in method 100 may be applied to contact openings formed over a variety of conductive structures, including, but not limited to, gate structures, contacts, source / drain regions, etc.

[0036] A pre-cleaning process with improved cleaning efficiency is disclosed. According to some embodiments, the pre-cleaning process can mitigate contact profile changes and reduce or prevent oxide redeposition from the sidewalls of a contact opening to the bottom of the contact. In some embodiments, the pre-cleaning process includes sputtering with argon ions with improved ion directionality. A tunable bias from a stacked DC power supply coupled to an inductively coupled plasma energy source can be used to control the direction and energy of the argon ions. Furthermore, a set of magnets or coils located on the sidewalls of the pre-cleaning reactor can further enhance the directionality of the argon ions.In some embodiments, an extended stage with a wide diameter (e.g., 300 mm to 330 mm) and extended height (e.g., between about 12.0 mm and about 12.5 mm) may be used to improve pre-clean uniformity across the wafer. In some embodiments, the tunable bias voltage range provided by the DC power supply unit may be from about -100 volts to about 100 volts.

[0037] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Method comprising: Forming (110) a dielectric layer (230, 235, 245) over a contact region on a substrate (210); Etching (120, 130) the dielectric layer (230, 235, 245) to form a contact opening (300, 400, 500) to expose the contact area; and Pre-cleaning (140) the exposed contact area in a reactor (700) having a conductive frame (715) for supporting the substrate (210) to remove a residual material (600) formed by the etching, the pre-cleaning comprising: - exposing the first contact region to an inductively coupled radio frequency plasma (705), wherein the radio frequency plasma (705) is generated by an inductively coupled radio frequency plasma source; - applying, with a DC power supply unit (710), a bias voltage to the substrate (210); and - applying a magnetic field to the inductively coupled radio-frequency plasma (705) to concentrate ions, wherein applying the magnetic field comprises generating the magnetic field by magnets (725, 730) each having oppositely arranged polarities, and wherein the magnetic field is perpendicular to a top surface of the conductive frame (715), wherein a respective axis passing through the north pole and the south pole of the respective magnets (725, 730) is arranged perpendicular to the top surface of the conductive frame (715). [2] The method of claim 1, wherein the DC power supply unit (710) is electrically coupled to the substrate (210) through an RF generator (720). [3] The method of claim 1 or 2, wherein the bias voltage is from about -100 volts to about 100 volts. [4] The method of any preceding claim, wherein applying the bias voltage comprises applying the bias voltage to the conductive frame (715) having a diameter between about 300 mm and about 330 mm. [5] A method according to any one of the preceding claims, wherein applying the magnetic field comprises generating the magnetic field by electromagnets connected to an RF source. [6] Method according to one of the preceding claims, wherein the residual material (600) is SiO2, SiO x C, SiON, SiOCN, SiC, SiCN or a combination thereof. [7] A method according to any one of the preceding claims, wherein the pre-cleaning comprises deepening the contact region from about 0.5 nm to about 5 nm. [8] A method according to any one of the preceding claims, wherein the inductively coupled radio frequency plasma (705) comprises argon plasma. [9] The method according to claim 8, wherein during pre-cleaning an argon gas stream with a volume flow of 5 sccm to 10 sccm flows into the reactor (700), and the reactor pressure is 1.33 Pa to 666.61 Pa. [10] The method of any preceding claim, wherein applying the bias voltage comprises increasing the bias voltage to narrow a top width of the contact opening (300) when the contact opening (300, 400) has an aspect ratio higher than about 3:

1. [11] The method of claim 10, wherein the top width of the contact opening (300, 400) is from about 12 nm to about 16 nm. [12] The method of any one of the preceding claims 1 to 9, wherein applying the bias voltage comprises increasing the bias voltage to widen a top width of the contact opening (300) when the contact opening has an aspect ratio less than about 3:

1. [13] System (700), comprising: a stage (715) configured to support a substrate (210); a DC power supply unit (710) electrically coupled to the substrate (201) through the frame (715) and configured to apply a bias voltage to the substrate (210); an inductively coupled radio frequency power supply configured to generate a plasma (705); and Magnets (725, 730) each having oppositely arranged polarities and configured to generate a magnetic field that focuses ions in the plasma (705), wherein the generated magnetic field is configured to be perpendicular to an upper surface of the frame (715), wherein a respective axis passing through the north pole and the south pole of the respective magnets (725, 730) is perpendicular to the upper surface of the frame (715). [14] The system (700) of claim 13, wherein a diameter of the frame (715) is from about 300 mm to about 330 mm. [15] The system (700) of claim 13 or 14, wherein the bias voltage is from about -100 volts to about +100 volts. [16] Method according to one of the preceding claims 13 to 15, wherein the DC power supply unit (710) is electrically connected to the frame (715) by a high frequency generator (720). [17] The system (700) of any one of the preceding claims 13 to 16, wherein the magnets (725, 730) comprise cylindrical electron magnets or electron magnet coils electrically connected to a high frequency power source. [18] Method comprising: Forming transistors over a substrate (210), each transistor comprising a gate (205), a source, and a drain; forming metal contacts (200) at the source and drain of each transistor; Depositing a dielectric layer (230, 235, 245) over the transistors and the metal contacts (200); Etching (120) a first opening (300) in the dielectric layer (230, 235, 245) to expose the gate (205) of each transistor; Etching (130) a second opening (400) in the dielectric layer (230, 235, 245) to expose the metal contacts (200), the second opening (400) having a smaller aspect ratio than the first opening (300); and Performing (140) a pre-cleaning in a reactor (700) having a conductive stage (715) for supporting the substrate (210) to remove a residual material (600) formed on the exposed gate (205) of each of the transistors and the metal contacts (200) by the etching (120, 130), wherein performing the pre-cleaning comprises: - forming a plasma (705), wherein the high-frequency plasma is formed by an inductively coupled high-frequency plasma source; - applying a bias voltage to the substrate (210) by a frame (715) electrically connected to a DC power supply unit (710); and - applying a magnetic field to concentrate ions from the plasma (705), wherein applying the magnetic field comprises generating the magnetic field by magnets (725, 730) each having oppositely arranged polarities, and wherein the magnetic field is perpendicular to a top surface of the conductive frame, wherein a respective axis passing through the north pole and the south pole of the respective magnets (725, 730) is arranged perpendicular to the top surface of the conductive frame (715). [19] The method of claim 18, wherein the bias voltage is from about -100 volts to about 100 volts. [20] The method of claim 18 or 19, wherein the plasma (705) comprises argon plasma and the DC power supply unit (710) is electrically connected to the frame (715) by a radio frequency generator (720).

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