Power semiconductor device and method

Abstract

Power semiconductor device (1), comprising: - a semiconductor body (10) having a front surface (10-1) and including a drift region (100) having dopants of a first conductivity type; - an edge termination region (105), wherein the edge termination region (105) is contained in the semiconductor body (10) and comprises: ◯ part of the drift area (100); ◯ a first semiconductor region (103) extending along the front surface (10-1), wherein the first semiconductor region (103) comprises dopants of the first conductivity type and dopants of a second conductivity type complementary to the first conductivity type, wherein an integrated vertical dopant concentration of the dopants of the second conductivity type is higher than an integrated vertical dopant concentration of dopants of the first conductivity type in the first semiconductor region (103), wherein the first semiconductor region (103) forms a continuous pn junction (J) with the drift region (100); wherein a first dose profile (D_1) representing a vertically integrated net dopant concentration of the dopants of the first and second conductivity types in the first doped semiconductor region (103) has a lower degree of ripple along a horizontal direction (X, Y) than a second dose profile (D_2) representing a vertically integrated dopant concentration of the dopants of the second conductivity type in the first doped semiconductor region (102).

Description

TECHNICAL FIELDThis document relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, this document relates to aspects of a power semiconductor device comprising a doped semiconductor region within an edge termination region.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as conversion of electrical energy and driving an electric motor or machine, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications including, but not limited to, switches in power supplies and power converters.A power semiconductor device typically comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device.Further, the power semiconductor device for conducting the load current may comprise one or more power cells, which may be arranged in a so-called active region (or active region) of the power semiconductor device. In the case of a controllable power semiconductor device, for example a transistor, the load current path may be controlled by means of an insulated electrode, commonly also referred to as gate electrode. Upon receiving a corresponding control signal from, for example, a driver unit, the control electrode may, for example, put the power semiconductor device in one of a conductive state and a blocking state. In some cases, the gate electrode may be included in a trench of the power semiconductor switch, wherein the trench may have a stripe configuration or a needle configuration, for example.The power semiconductor device may be laterally bounded by an edge, such as a lateral chip edge. Between the edge and the active area comprising the one or more power cells, an edge termination region may be arranged, which may comprise an edge termination structure. Such an edge termination structure may serve the purpose of influencing the course of an electric field in the semiconductor body in order to ensure a reliable blocking capability of the power semiconductor device, for example. The edge termination structure may include one or more components arranged in the semiconductor body and also one or more components arranged over a surface of the semiconductor body.Some common edge termination structures, such as lateral variation of doping (VLD) structures, comprise one or more doped semiconductor regions having a defined shape. It is generally desirable to provide such doped semiconductor regions at relatively low cost, for example in a manner that allows a relatively fine definition of their shape, but does not require dedicated lithography techniques with a very fine resolution.DE 10 2017 127 848 A1 describes the following: A semiconductor component has an SiC semiconductor body having an active region and an edge termination structure at least partially surrounding the active region. In the SiC semiconductor body, a drift zone of a first conductivity type is formed. The edge termination structure comprises a first doped region of a second conductivity type between a first surface of the SiC semiconductor body and the drift zone. The first doped region at least partially surrounds the active region and is spaced apart from the first surface. The edge termination structure further comprises second doped regions of the second conductivity type between the first surface and the first doped region and third doped regions of the first conductivity type between the second doped regions.DE 10 2009 044 670 A1 describes a semiconductor component having a diode structure which contains a structured emitter which is electrically connected to a first metallization. The patterned emitter includes a first lightly doped semiconductor region of a first conductivity type forming a pn-load junction with a lightly doped second semiconductor region of the diode structure. The patterned emitter includes at least one highly doped first semiconductor island of the first conductivity type at least partially surrounding a highly doped second semiconductor island of the second conductivity type.US 2011 / 0233 714 A1 describes a semiconductor device including a first conductivity type (n-type) drift layer and a second conductivity type VLD region formed on a chip inner peripheral side of a termination structure region formed on a main surface of the n-drift layer and having a higher concentration than the drift layer.SUMMARYAspects described herein relate to a specific design of a doped semiconductor region within an edge termination region of a power semiconductor device, wherein a portion of a first implanted dopant dose of one conductivity type (e.g. p-type) is compensated by a second implanted dopant dose of the complementary conductivity type (e.g. n-type). For example, the second implanted dopants may be diffused to a smaller lateral extent than the first implanted dopants. As a result, a ripple of a vertically integrated net dopant concentration of the doped semiconductor region may be reduced.According to an embodiment, a power semiconductor device comprises: a semiconductor body having a front side surface and comprising a drift region comprising dopants of a first conductivity type; and an edge termination region, wherein the edge termination region is included in the semiconductor body and comprises: a part of the drift region; a first semiconductor region extending along the front side surface, wherein the first semiconductor region comprises dopants of the first conductivity type and dopants of a second conductivity type complementary to the first conductivity type, wherein an integrated vertical dopant concentration of the dopants of the second conductivity type is higher than an integrated vertical dopant concentration of dopants of the first conductivity type in the first semiconductor region. The first semiconductor region forms a continuous pn junction with the drift region. A first dose profile representing a vertically integrated net dopant concentration of the dopants of the first and second conductivity types in the first doped semiconductor region has a lower degree of ripple along a horizontal direction than a second dose profile representing a vertically integrated dopant concentration of the dopants of the second conductivity type in the first doped semiconductor region.According to another embodiment, a method of manufacturing a power semiconductor device is provided. The method comprises: providing a semiconductor body having a front side surface and including a drift region having dopants of a first conductivity type; and forming an edge termination region within the semiconductor body. Forming the edge termination region comprises forming a first doped semiconductor region extending along the front side surface and forming a continuous pn junction with the drift region, wherein forming the first doped semiconductor region comprises the steps of: implanting dopants of a second conductivity type through the front side surface by means of a first masked implantation, wherein a first mask is used for the first masked implantation, wherein the first mask defines first open regions and first masked regions; and implanting dopants of a first conductivity type through the front side surface by means of a second masked implantation, wherein a second mask is used for the second masked implantation, wherein the second mask defines second open regions and second masked regions. The first mask and the second mask are arranged on the semiconductor body such that open regions of the second mask that lie on the first doped semiconductor region during the second implantation step horizontally overlap open regions of the first mask that lie on the first doped semiconductor region during the first masked implantation. Furthermore, the first mask and the second mask are arranged on the semiconductor body such that closed regions of the second mask which lie on the first doped semiconductor region during the second implantation step horizontally overlap closed regions of the first mask which lie on the first doped semiconductor region during the first masked implantation.According to a further embodiment, a method of manufacturing a power semiconductor device comprises: providing a semiconductor body having a front side surface and comprising a drift region comprising dopants of a first conductivity type; and forming an edge termination region within the semiconductor body, wherein forming the edge termination region comprises: forming a first doped semiconductor region extending along the front side surface and forming a continuous pn junction with the drift region; and forming a further doped semiconductor region in the semiconductor body. Forming the first doped semiconductor region and the further doped semiconductor region comprises the following steps: forming a patterned shielding layer on the front side, wherein the patterned shielding layer covers the first doped semiconductor region to be formed, wherein the patterned shielding layer is not present on the further doped semiconductor region to be formed; in a first implantation step, implanting dopants through the patterned shielding layer into the semiconductor body with a first implantation energy; in a further implantation step, implanting dopants into the patterned shielding layer into the semiconductor body with a second implantation energy that is lower than the first implantation energy; by means of the first mask; wherein the first mask is open over the further doped semiconductor region to be formed, and wherein the first mask defines first open regions and first masked regions, wherein in a cross section along a horizontal direction an area ratio of the open regions to the masked regions over the first semiconductor region decreases in a direction facing from an active region of the power semiconductor device to a lateral edge of the semiconductor body.Additional features and advantages will become apparent to those skilled in the art upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrative principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings, there are shown: FIGS. 1A-G each schematically and exemplarily illustrate process steps of a method for manufacturing a power semiconductor device according to one or more embodiments; FIGS. 2A-G each schematically and exemplarily illustrate process steps of a method for manufacturing a power semiconductor device according to one or more embodiments; FIGS. 3A-F are schematic and exemplary process steps of a method for manufacturing a power semiconductor device according to one or more embodiments; FIGS. 4A-E are schematic and exemplary process steps of a method for manufacturing a power semiconductor device according to one or more embodiments; FIGS. 5A-D each schematically and exemplarily illustrate process steps of a method for manufacturing a power semiconductor device according to one or more embodiments; FIG. 6 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; FIG. 7 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; FIG. 8 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; FIG. 9 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; FIG. 10 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; FIGS. 11A-E each schematically and exemplarily illustrate a portion of an implantation mask used in a method according to one or more embodiments; FIGS. 12A-E each schematically and exemplarily illustrate a portion of two different implantation masks used in a method according to one or more embodiments; FIG. 13 schematically and exemplarily illustrates lateral profiles of dopant doses (after diffusion) according to one or more embodiments; FIG. 14 schematically and exemplarily illustrates lateral profiles of net dopant doses (after diffusion) according to one or more embodiments; FIG. 15 schematically and exemplarily illustrates lateral profiles of net dopant doses (after diffusion) according to one or more embodiments; FIG. 16 schematically and exemplarily illustrates lateral profiles of net dopant doses (after diffusion) according to one or more embodiments; FIGS. 17A-C respectively schematically and exemplarily illustrate lateral profiles of dopant doses (after diffusion) according to one or more embodiments; and FIGS. 18A-C each schematically and exemplarily illustrate a portion of an implantation mask used in a method according to one or more embodiments.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology, such as "top," "bottom," "below," "front," "back," "back," "leading," "trailing," "above," etc., may be used with reference to the orientation of the figures just described. Since portions of embodiments may be positioned in multiple different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. Features illustrated or described as part of one embodiment may be used, for example, in or in combination with other embodiments to obtain yet another embodiment. The present invention is intended to include such modifications and variations. The examples are described using a specific terminology, which is not to be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. For clarity, the same elements or manufacturing steps have been denoted by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used herein is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die or a chip. For example, both the first lateral (or horizontal) direction X and the second lateral (or horizontal) direction Y mentioned below and / or shown in the figures may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used herein is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / die / die. For example, the vertical direction Z mentioned below and / or shown in the figures may be a direction perpendicular to both the first lateral direction X and the second lateral direction Y.In this specification, n-doped is generally referred to as "first conductivity type", while p-doped is referred to as "second conductivity type". Alternatively, opposite doping relationships may be used such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.As used herein, the terms "in ohmic contact", "in electrical contact", "in ohmic connection", and "electrically connected" are intended to describe that there is a low ohmic electrical connection or current path between two regions, regions, zones, portions or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a portion or part of a semiconductor device. Further, as used herein, the term "in contact" is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include a further interposer or the like.Moreover, the term "electrical insulation" is used within the scope of its generally valid understanding, unless otherwise stated, and is thus intended to describe that two or more components are arranged separately from one another and that there is no ohmic connection connecting these components. However, components electrically insulated from one another may nevertheless be coupled to one another, for example mechanically coupled and / or capacitively coupled and / or inductively coupled. To name an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, for example by means of an insulation, for example a dielectric.Specific embodiments described herein relate to a power semiconductor device having a single cell, strip cell or cellular (also referred to as "pin" or "column") cell configuration, for example, a power semiconductor device that may be used within a power converter or power supply, without being limited thereto. Thus, in such an embodiment, such a device may be configured to carry a load current to be supplied to a load and / or which is respectively provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, a variation of a monolithically integrated diode cell (for example a monolithically integrated cell of two antiseries-connected diodes), a monolithically integrated transistor cell, for example a monolithically integrated IGBT cell or a MOSFET cell, and / or variations thereof. Such diode / transistor cells may be integrated in a power semiconductor module. A plurality of such power cells may form a cell array disposed with an active region of the power semiconductor device.The term "power semiconductor device" as used herein is intended to describe a semiconductor device on a single chip with high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for a high current, typically in the Ampere range, for example up to several tens or hundred Ampere, and / or high voltages, typically above 15 V, more typically 100 V and above, for example up to at least 400 V or even more, for example up to at least 3 kV or even up to 6 kV or more.For example, the power semiconductor device described below may be a single semiconductor chip having a single cell configuration, a strip cell configuration, or a cell-shaped cell configuration, and may be configured to be employed as a power component in a low, medium, and / or high voltage application.For example, the term "power semiconductor device" as used herein is not directly directed to logic semiconductor devices used for storing data, computing data, and / or other types of semiconductor-based data processing, for example.FIGS. 1A-G each schematically and exemplarily illustrate process steps of a method for manufacturing a power semiconductor device 1 according to one or more embodiments.Initially, a semiconductor body 10 having a front surface 10- 1 is provided (see FIG. 1A ). For example, the semiconductor body 10 may be provided in the form of a wafer having a wafer surface 10- 1 extending in both a first horizontal direction X and a second horizontal direction Y (i.e., in a horizontal plane XY).The semiconductor body 10 includes a drift region 100 of a first conductivity type (e.g., n-type). For example, the drift region may be an intrinsically doped region of the semiconductor body 10. Alternatively, the drift region can be produced by means of an implantation of dopants of the first conductivity type. The drift region may be, for example, an n -- doped region that may be configured to conduct a load current through the (processed) power semiconductor device 1.As a further step, the method may include forming an edge termination region 105 within the semiconductor body 10. For example, in an embodiment according to FIGS. 1A-G, the edge termination region 105 may form at least a part of a variation of lateral doping (VLD) edge termination region. That is, the edge termination region 105 to be formed may have a lateral variation of a net average dopant concentration in a direction facing from an active region to the lateral edge of the semiconductor body 10, such that a higher average dose is present near the active region than at a location near the lateral edge. Thus, in an embodiment, the method may comprise forming such a VLD region or at least a portion thereof.Forming the edge termination region 105 may include forming a first doped semiconductor region 103 in the semiconductor body 10 by means of a first masked implantation of dopants of the second conductivity type (e.g. p-type) through the front side surface 10- 1. For example, as a result of the first masked implantation, first implanted surface regions 1031 may be formed under first open regions (see FIG. 1B ). For example, a first mask 21 (such as a resist mask or a hard mask) may be used for the first masked implant, the first mask defining first open regions and first masked regions (see FIG. 1A ).Regarding the layout of the first mask 21, for example, in a cross section along a horizontal direction X, Y (for example, in a cross section along both the first and second horizontal directions X, Y), an area ratio of the first open regions to the first masked regions over the first semiconductor region 103 may decrease in a direction (for example, on average, i.e., not forcibly monotone) facing from an active region of the power semiconductor device 1 to a lateral edge of the semiconductor body 10 (not illustrated in FIGS. 1A-G). Thus, a lateral variation of the dopant concentration may be achieved, as intended for the VLD edge termination region 105. This can be better understood by considering Figures 18A-D, which are discussed below.Forming the first doped semiconductor region 103 may further comprise at least one diffusion step for diffusing the dopants of the second conductivity type. In the diffusion step, the first implanted surface regions 1031 may be extended and recessed to form the first doped semiconductor region 103, as exemplarily illustrated in FIGS. 1C-D. As a result of the at least one diffusion step, the first doped semiconductor region 103 may, for example, extend seamlessly within the semiconductor body 10 along the front side surface 10- 1 and form a continuous pn-junction J with the drift region 100.The pn-junction J may define a ripple or wave shape, as schematically and exemplarily illustrated in FIG. 1D. For example, in an embodiment, a ripple contour C describing the vertical extension of the dopants of the second conductivity type from the front side 10- 1 into the semiconductor body 10 may have a plurality of local maxima, wherein adjacent local maxima of the ripple contour C may be spaced apart from each other at least by a third horizontal h3span amounting to at least 2 μm (see FIG. 1D ).Forming the first doped semiconductor region 103 may further include implanting dopants of the first conductivity type (e.g. n-type) through the front side surface 10- 1 by means of a second masked implantation step (see FIG. 1E ). As a result of the second masked implantation, second implanted surface regions 1041 may be formed under the second open regions (see FIG. 1F ).For example, a second mask 22 is used for the second masked implant, the second mask defining second open regions and second masked regions. It should be noted that the second mask 22 may be identical to the first mask 21. In other words, a same mask 21, 22 may be used for the first masked implantation and the second masked implantation.More generally, the second implantation may be performed with a pattern related to that of the first implantation. In an embodiment, the first mask 21 and second mask 22 may be arranged on the semiconductor body 10 such that open areas of the second mask 22 overlying the first doped semiconductor region 103 during the second implantation step horizontally overlap with open areas of the first mask 21 overlying the first doped semiconductor region 103 during the first masked implantation. Furthermore, the first mask 21 and second mask 22 may be arranged on the semiconductor body 10 such that closed regions of the second mask 22 overlying the first doped semiconductor region 103 during the second implantation step horizontally overlap with closed regions of the first mask 21 overlying the first doped semiconductor region 103 during the first masked implantation.For example, open areas of the second mask 22 may be entirely within the areas where the open areas of the first mask 21 were previously present. Accordingly, open areas of the second mask 22 may be smaller than open areas of the first mask 21.In an embodiment according to FIGS. 1B-F, the above-mentioned at least one diffusion step may be carried out before the implantation of dopants of the first conductivity type.The dopants of the first conductivity type implanted in the second implantation step may also be diffused to expand and recess the second implanted surface regions 1041 to second doped semiconductor regions 104 (see FIG. 1G ). For example, the dopants of the first conductivity type may be diffused to a smaller lateral extension than the dopants of the second conductivity type, such that the second doped semiconductor regions 104 remain arranged within the first implanted region 103 (e.g. separated from each other), as illustrated in FIG. 1G.The result may be a first doped semiconductor region 103 (comprising the second doped semiconductor regions 104) with a net dose having a more homogeneous distribution than a VLD structure created with a conventional method using the same feature size (i.e. the same size of the first mask opening). This will be explained in further detail below with reference to FIGS. 13 to 17C, which illustrate exemplary lateral dose profiles of the first doped semiconductor region 103 by way of example.For example, in an embodiment, the implanted dopants of the first conductivity type may form regions (within the second doped semiconductor regions 104) where they have a higher concentration than the dopants of the second conductivity type. This may be referred to as local overcompensation. Alternatively, the implanted dopants of the first conductivity type may have a lower concentration elsewhere than the dopants of the second conductivity type, referred to as a partial compensation.FIGS. 2A-G schematically and exemplarily illustrate process steps of a variant of the method described above with reference to FIGS. 1A-G. In this variant, the dopants of the first conductivity type and the dopants of the second conductivity type are implanted by a shielding layer 3, such as an oxide layer, arranged over the front side surface 10- 1 (e.g., directly on the front side surface 10- 1). Thus, FIGS. 2A-G may show, for example, a method for forming a VLD region 103 when a thick oxide 3 is arranged over the edge termination region 105.If the first mask 21 and / or the second mask 22 are resist masks, a thickness of the resist used for the masks 21, 22 may be at least twice the thickness of the thick oxide 3 under the resist, for example.As schematically and exemplarily illustrated in FIGS. 3A-F, the proposed method may further also be incorporated in a more comprehensive process that may require other lithography layers. In particular, in the case where a relatively thick oxide 3 (e.g. an oxide thicker compared to a gate oxide and / or other oxides in other parts on the semiconductor body 10) is above the edge termination region 105 to be formed (cf. FIGS. 2A-G ), a mask 21, 22 used for forming the edge termination region 105 (e.g. the VLD region 103) may also be used for an additional implantation with lower energy masked by the thick oxide 3 but not masked in other parts of the semiconductor body 10 not covered by the thick oxide 3 nor by the masks 21, 22, see FIGS. 3A-F. This may refer to the mask(s) 21, 22 used for the first and / or second implantation. However, it should be noted that, for example, a thin oxide 4 (thinner than the thick oxide 3) may be located in the other parts of the semiconductor body, as illustrated in FIGS. 3A-F. For example, a thickness of such a thin oxide 4 may be smaller than a thickness of the oxide layer 3 by at least a factor of 3. For example, the thickness of the thin oxide 4 may be in the range of 20 nm to 200 nm.Thus, in an embodiment of the proposed method, the dopants of the first conductivity type and / or the dopants of the second conductivity type are implanted through a shielding layer 3, such as an oxide layer arranged over the front side surface 10- 1, wherein the method may further comprise forming, by means of a third implantation of dopants of the first or second conductivity type through the front side surface 10- 1, a third doped semiconductor region 106 extending along the front side surface 10- 1 in a region in which the front side surface 10- 1 is not covered by an oxide layer (such as the oxide layer 3) or in a region in which the front side surface 10- 1 is covered at most by a thin oxide 4, as exemplarily shown in FIGS. 3A-F. According to the embodiment illustrated in FIGS. 3A-F, a further (third) doped semiconductor region 106, for example in the form of a deep p-well, may thus be provided next to a VLD region 10.The shielding layer 3 may for example comprise or consist of an oxide layer with a thickness of at least 400 nm. In an embodiment, the third masked implantation may further be performed at a lower energy than the first masked implantation, such that the dopants of the second type do not penetrate the oxide layer 3 during the third masked implantation. This is exemplarily illustrated in FIG. 3C showing implanted regions 1062 within the shield layer 3 in addition to implanted surface regions 1061 within the semiconductor body 10 where the shield layer 3 is not present. Furthermore, FIGS. 3B-C show first implanted surface regions 1031 and (deeper) implanted regions 1032 in the semiconductor body 10 resulting from the first masked implantation. After diffusion, the implanted surface regions 1061 and the (deeper) implanted regions 1031 may together form the third doped semiconductor region 106, as illustrated in FIG. 3D, for example.In an embodiment, a same mask 21 may be used for the first masked implant and the third masked implant. Alternatively, a same mask 22 may be used for the first masked implant and the third masked implant. In this case, further (fourth) implantation may also be performed with the same (second) mask 22, wherein the fourth implantation may, for example, create an n-well that may function as a channel stopper region (not illustrated).In one embodiment, a method of processing a power semiconductor device according to one or more embodiments may include, for example:providing a semiconductor body 10 having a front side surface 10- 1 and including a drift region 100 having dopants of a first conductivity type;forming an edge termination region 105 within the semiconductor body 10, wherein forming the edge termination region 105 comprises:forming a first doped semiconductor region 103 extending along the front side surface 10- 1 and forming a continuous pn junction J with the drift region 100,forming a further doped semiconductor region 106 in the semiconductor body 10, wherein forming the first doped semiconductor region 103 and the further doped semiconductor region 106 comprises the following steps:forming a patterned shielding layer 3 on the front side 10- 1, wherein the patterned shielding layer 3 covers the first doped semiconductor region 103 to be formed, wherein the patterned shielding layer 3 is not present on the further doped semiconductor region 106 to be formed (however, it should be noted that a thin oxide 4 may be present on the further doped semiconductor region 106 to be formed);in a first implantation step by means of a first mask 21, dopants are implanted through the structured shielding layer 3 into the semiconductor body 10 with a first implantation energy;in a further implantation step, by means of the first mask 21, implanting dopants into the patterned shielding layer 3 into the semiconductor body 10 with a second implantation energy that is lower than the first implantation energy; wherein the first mask 21 is open over the further doped semiconductor region 106 to be formed, and wherein the first mask 21 defines first open regions and first masked regions, wherein in a cross section along a horizontal direction X, Y an area ratio of the open regions to the masked regions over the first semiconductor region 103 (for example on average, i.e. not necessarily monotonically) decreases in a direction pointing from an active region of the power semiconductor device 1 to a lateral edge of the semiconductor body 10.In an embodiment, dopants implanted through the first mask 21 may have an implantation maximum located in the shielding layer 3 over the first doped semiconductor region 103 to be formed in the first step. In an embodiment, dopants implanted through the first mask 21 may further have an implantation maximum located in the first semiconductor region 103 in the second implantation step.Forming the first and the further doped semiconductor region 103, 106 may, for example, further comprise performing at least one diffusion step for diffusing the dopants.FIGS. 4A-E schematically and exemplarily illustrate an embodiment wherein the same mask 21 is used for the first implantation (of dopants of the second conductivity type) and the second implantation (of dopants of the first conductivity type). The mask 21 may be, for example, a resist mask or a hard mask. In the case of a resist mask, a diffusion process cannot be applied between the first implantation and the second implantation. In this case, two elements having different diffusion constants should be used as dopants (for example, boron for the p-type and arsenic for the n-type), see FIGS. 1A-D.For example, in an embodiment, the dopants of the first conductivity type may have a first diffusion constant in the semiconductor body 10, and the dopants of the second conductivity type may have a second diffusion constant in the semiconductor body 10, wherein the second diffusion constant exceeds the first diffusion constant by at least a factor of 3.In an embodiment, a diffusion length of the dopants of the first conductivity type is in a range of 30-70% of a diffusion length of the dopants of the second conductivity type. The diffusion length may be defined using a vertical doping profile. Then, the diffusion length may be defined as the difference of the depth of the position of the maximum of the doping profile and the position at which the profile has reached a concentration with a value of the maximum divided by e (Euler number e=2.718... ).In an embodiment, for example, a maximum structure size of the masks 21, 22 used for forming the first doped semiconductor region 103 is not greater than twice the diffusion length of the p-type dopants, such as not greater than 1.5 times the diffusion length of the p-type dopants.In an embodiment, the number of n-type dopants implanted into the semiconductor body 10 is further in a range of 10%-60% of the number of p-type dopants implanted into the semiconductor body 10 in the first doped semiconductor region 103.FIGS. 5A-D schematically and exemplarily illustrate another embodiment, wherein two masks 21, 22 having different openings are used for the first and second implantations, respectively. Thus, the mask 22 used for the second implantation may be different from the mask 21 used for the first implantation. For example, the second mask 22 may have a smaller opening than the first mask 21, as illustrated. The second open region of the second mask 22 can thus lie completely in the first open region of the first mask 21. In these cases, two elements having similar diffusion constants (such as boron and phosphorus) may be used as dopants implanted in the first and second implantation steps, respectively, and may be diffused through the same anneal step(s). See Figs. 5A-D.Accordingly, in an embodiment, the dopants of the first conductivity type may have a first diffusion constant in the semiconductor body 10 and the dopants of the second conductivity type may have a second diffusion constant in the semiconductor body 10, wherein the second diffusion constant differs from the first diffusion constant by at most a factor in the range of 0.5 to 2. In other words, the respective diffusion constants of the dopants of the first conductivity type and the dopants of the second conductivity type may be similar, as in the case of, for example, boron and phosphorus.As mentioned above, in one embodiment, at the time of at least one of the two implantations, a shielding layer 3 may be present at the location of a mask opening. For example, the shielding layer 3 may comprise or consist of a thick oxide 3, wherein the thick oxide may have a thickness of, for example, at least 400 nm and / or may be at least twice as thick at another location. The implantation can be performed through the thick oxide 3 with an energy high enough to penetrate the oxide layer 3. Other parts of the semiconductor body not covered by the thick oxide 3 may be covered by a thin oxide 4 or may not be covered by an oxide at all.FIGS. 6-10 each schematically and exemplarily show a portion of a vertical cross section of a power semiconductor device 1, such as a diode, an IGBT or a MOSFET, according to one or more embodiments. In any case, the illustrated portion comprises an edge termination region 105 (including a first doped semiconductor region 103 in the form of a VLD structure) which may be formed by a method according to one or more of the embodiments described above. Thus, the above with reference to variants of a method for manufacturing a power semiconductor device 1 may analogously also apply to the embodiments of a power semiconductor device 1 of FIGS. 6-10, and vice versa.According to FIG. 6, the power semiconductor device 1 may include, for example, the first doped semiconductor region 103 in the form of a VLD edge termination region 103, as described above. It should be noted that the second doped semiconductor regions 104 described above are not shown separately in FIG. 6. Where the VLD edge termination region 103 extends along the front side surface 10- 1 of the semiconductor body 10, the front side surface 10- 1 is covered by one or more insulation layers 13, 19.On the left side of FIG. 6, the illustrated cross section of the power semiconductor device 1 shows a part of a deep p-well 106 electrically connected to a front side metallization 11. The front side metallization 11 may form part of a first load terminal structure of the power semiconductor device 1.As shown on the right side of FIG. 6, a channel stopper region 107 may additionally be included in the semiconductor body 10. The channel stopper region 107 may include dopants of the second conductivity type and may be in contact with a channel stopper electrode 121, as illustrated. Alternatively, the channel stopper region 107 may include dopants of the first conductivity type, as illustrated in FIG. 9.With regard to the ripple contour C of the VLD region 103, it should be noted that the illustration in FIG. 6 is not true to scale. In a real embodiment, the ripple structure may be, for example, much finer than that shown only schematically in FIG. 6.The VLD region 103 may have, for example, a higher average dopant dose near an active region of the power semiconductor device 1 (i.e. to the left in FIG. 6 ) than at a location further towards the chip edge (i.e. to the right in FIG. 6 ).FIG. 7 schematically and exemplarily illustrates another variant of a VLD region 103 that may have been produced using the method described above. In this case, the second doped semiconductor regions 104 (which may be primarily n-doped) are explicitly shown within the first doped semiconductor region 103. It should be noted that the compensation implantation may be used only in a part of the VLD region 103. During the second implantation, the front side surface 10- 1 may be completely masked, for example, in an inner part of the VLD region 103, i.e., in the vicinity of an active region of the power semiconductor device 1 (to the left in FIG. 7 ).FIG. 8 schematically and exemplarily illustrates yet another cross section of a power semiconductor device 1 having a VLD region 103 which may have been produced using the method described above (including the second doped semiconductor regions 104), not shown. The mask 22 used for the second (n-type) implantation (e.g. phosphorus or arsenic) may also be used for an n-implant 108 at the outer side of the edge termination, for example, which may serve to prevent an excessively wide extension of the space charge region during a blocking state of the power semiconductor device 1.FIG. 9 schematically and exemplarily illustrates a further cross section of a power semiconductor device 1 having a VLD region 103 which may have been manufactured using the method described above. In this case, the vertical cross-sectional portion shown also includes a back side of the power semiconductor device 1. a back side metallization 12 is arranged, for example, on a back side surface 10- 2 of the semiconductor body 10. The back side metallization 12 may form at least a part of a second load terminal structure of the power semiconductor device 1. Further, a back side emitter region 100- 1 may be arranged at the back side in contact with the back side metallization 12. The backside emitter region 100- 1 may include dopants with a higher concentration than the drift region 100. The power semiconductor device 1 may be or comprise, for example, a power diode, in which case the back side emitter region 100- 1 may be of the first conductivity type (e.g. n-type).FIG. 10 schematically and exemplarily illustrates a further cross section of a power semiconductor device 1 having a VLD region 103 which may have been manufactured using the method described above. In this case, the illustrated portion also includes a peripheral part of an active region 14 of the power semiconductor device 1 (leftward in FIG. 10 ) in addition to an edge region 15. The active region 14 may include an active cell array including a plurality of transistor cells 140. The transistor cells 140 may have, for example, a trench gate configuration, as illustrated. Furthermore, an insulation structure 190 may be provided. The design of such transistor cells 140 is basically well known to those skilled in the art and will therefore not be described further herein.The power semiconductor device may have an IGBT configuration, for example. In this case, the back side emitter region 100- 1 may be of the second conductivity type. The power semiconductor device 1 may alternatively have a MOSFET configuration, for example, in which case the back side emitter region 100- 1 may be of the first conductivity type.Summarizing to FIGS. 9 and 10, it should be noted that the edge termination region 103 (e.g. in the form of a VLD region) may belong to an edge termination structure of a diode (cf. e.g. FIG. 9 ) or an IGBT (cf. e.g. FIG. 10 ) or another high voltage device.FIGS. 11A-E each schematically and exemplarily illustrate a portion of an implantation mask 21, 22 that may be used in the method described above, according to one or more embodiments. The shaded areas represent portions where the mask 21, 22 covers the front surface 10- 1. Conversely, the white regions remain free between the shaded regions, such that dopants can be implanted in the white regions.As illustrated, various shapes may be used to pattern the masks 21, such as squares, boxes, or hexagon. These shapes may correspond to either covered regions (see FIGS. 11A, 11B, 11D ) or regions left exposed for implantation (see FIGS. 11C, Fe).In the examples of FIGS. 11A-C, the open area is 50% / 75% and 25% of the total area, respectively. These numbers can, of course, be changed by selecting different sizes of the structures and / or a different distance.In FIGS. 11A-C, arrows L 1-L 7 indicate the paths through which a respective dopant dose (i.e., a dopant dose vertically integrated with respect to depth below the front surface 10- 1) is shown in FIGS. 13- 16, as will be explained further below.It should be noted that although the mask layouts shown in FIGS. 11A-E are marked with the reference numeral of the first mask 21 by way of example, the second mask 22 may have such shapes.FIGS. 12A-E each schematically and exemplarily illustrate a portion of two different implantation masks 21, 22 used in a method according to one or more embodiments. The shaded regions correspond to, for example, open regions of the second mask 22, i.e., regions in which the dopants of the first conductivity type (e.g., n-type) are implanted in the second implantation step. The unshaded regions mark outer contours of open regions of the first mask 21, i.e. regions in which dopants of the second conductivity type (for example n-type) are implanted in the first masked implantationIt should be noted that the unshaded areas in FIGS. 12A-E may also extend under the shaded areas. In other words, the open areas of the first mask 21 may be larger than the open areas of the second mask 22, the latter being arranged completely within the former. In other words, in one embodiment, the first mask 21 may be open wherever the second mask 22 is open.For example, if the second mask 22 used for the second implantation is different from the first mask 21 used for the first implantation, the second mask 22 may be somewhat related to the first mask 21 by having a substantially similar shape, for example, but with openings smaller by a certain amount compared to the openings of the first mask 21.FIGS. 13-16 each schematically and exemplarily show a plurality of lateral profiles of implantation doses according to one or more embodiments. In any case, vertically integrated dopant doses are shown in the first doped semiconductor region 103 along the various paths (arrows) L 1-L 7 indicated in FIGS. 11A-C.In each of Figs. 13-16, curves C1, C2, C3 belong to a mask pattern of Fig. 11B (masked squares; 75% open area). Curve C1 corresponds to the horizontal path L1 in FIG. 11B (completely within an open area of the mask). Curve C2 corresponds to diagonal path L2 in FIG. 11B (partially within an open area and within a masked area). Curve C 3 corresponds to horizontal path L 3 in FIG. 11B (partially within an open area and within a masked area).Further, in each of Figs. 13-16, the curve C4 belongs to a mask pattern of Fig. 11A (implanted elongated boxes, 50% open area), the curve C4 corresponding to the horizontal path L4 (partially within an open area and within a masked area).The curves C5, C6, C7 belong in each case to a mask pattern as shown in Fig. 11C (open / implanted squares; 25% open area). Curve C7 corresponds to horizontal path L7 in Figure 11C (completely within a masked area). Curve C6 corresponds to diagonal path L6 in Figure 11C (partially within an open area and within a masked area). Curve C 5 corresponds to horizontal path L 5 in FIG. 11C (partially within an open area and within a masked area).FIG. 13 shows the dose profiles C 1-C 7 for the three different mask patterns according to FIGS. 11A-C in the absence of a compensating n-implant, i.e. without the second implantation described above. The doses are shown for mask patterns having a pattern size of 4 μm and assuming a diffusion length of 2.55 μm. Doses are normalized to the value corresponding to 100% open range. It can be seen that the doses deviate greatly from respective intended mean values (corresponding to the above-mentioned 75%, 50% and 25% open mask range).For comparison, Fig. 14 shows the dose profiles C1-C7 resulting from the same pattern size of the respective mask patterns with a compensating n-implant according to the invention, assuming the same diffusion length as above for the p-dopants and assuming a smaller diffusion length for the n-dopants. As a result of the compensating n-implant, the deviations are substantially smaller. For these cases, the difference of p dose and n dose (i.e., the net resulting dose) is shown.FIG. 15 shows the dose profiles C 1-C 7 for these three different mask patterns, again in the absence of a compensating n-implant (as in FIG. 13 ), but this time with a smaller structure size of 3 μm and assuming the same diffusion length as above. It can be seen that with a smaller feature size, the lateral profiles are much more homogeneous.FIG. 16 shows the case of n-implant compensation for comparison (assuming the same structure size as in FIG. 15 and the same diffusion length as in FIG. 14 ). Since the profile is even more homogeneous without compensation (see FIG. 15 ), the dose required for a further homogenization is lower. Here too, a strong improvement with compensation can be seen.FIGS. 17A-C each schematically and exemplarily illustrate lateral profiles of vertical implantation doses in the first doped semiconductor region 103 according to one or more embodiments. In any case, the dotted curve D_ 2 is a dose profile of acceptors that may have been implanted in the first masked implant. The dot-dash curve D_ 3 is a dose profile of donors that may have been implanted in the (compensating) second implantation step. The solid curve D_ 1 is a net dose resultant curve, that is, a difference of the dose curves D_ 2 and D_ 3. The dashed curve D_ 4 is a reference dose profile (resulting from a conventional process without a compensating n-implant). The dose profiles D1-D4 show some ripple (or ripple) in each case and are shown over several periods.The example illustrated in FIG. 17A shows a very great reduction in ripple. As can be clearly seen, the first dose profile D_ 1, which represents the vertically integrated net dopant concentration (i.e. the net dose curve) of the dopants of the first and second conductivity type in the first doped semiconductor region 103, shows a lower degree of ripple along a horizontal direction X, Y (for example the horizontal direction of the above mentioned vertical cross section) than the second dose profile D_ 2, which represents a vertically integrated dopant concentration of the dopants (only) of the second conductivity type in the first doped semiconductor region 103.In an embodiment, a relative ripple amplitude Ar_ 1 of the first dose profile D_ 1 amounts to at most 80% (such as at most 70%) of a relative ripple amplitude Ar_ 2 of the second dose profile D_ 2, wherein the relative ripple amplitude Ar_i (i=1.2) is defined as follows: wherein i=1.2, dmax_i is a dose value at a local maximum of the dose profile D_i, and dmin_i is a dose value at an adjacent local minimum of the dose profile D_i. The relative ripple amplitude can thus be reduced by means of the compensation implantation according to the invention from a value of Ar_2=50% to a value of at most Ar_1=35%, such as a value of Ar_1=30%, or even to a value of Ar_1=10%.Further, in an embodiment, an averaged relative ripple amplitude <Ar_1> of the first dose profile D_ 1 amounts to at most 80% of an averaged relative ripple amplitude <Ar_ 2> of the second dose profile D_ 2, the average being taken over a portion of the first dose profile D_ 1 and a corresponding portion of the second dose profile D_ 2, respectively, the portions in each case comprising at least 2 local maxima and a local minimum arranged therebetween.Further, in an embodiment, an averaged relative ripple amplitude <Ar_1> of the first dose profile D_ 1 amounts to at most 80% of an averaged relative ripple amplitude <Ar_ 2> of the second dose profile D_ 2, the average being taken over a portion of the first dose profile D_ 1 and a corresponding portion of the second dose profile D_ 2, the portions in each case comprising at least 5 local maxima and adjacent local minima.In an embodiment, a relative ripple amplitude Ar_ 2 of the second dose profile D_ 2 amounts to at least 0.5, wherein the relative ripple amplitude is defined as the relative ripple amplitude Ar_ 2 of the second dose profile D_ 2, which is defined as follows: wherein dmax_ 2 is a dose value at a local maximum of the second dose profile D_ 2 and dmin_ 2 is a dose value at an adjacent local minimum of the second dose profile D_ 2.Further, in an embodiment, an averaged relative ripple amplitude <Ar_2> of the second dose profile D_2 amounts to at most 0.5, wherein the average is taken over a portion of the second dose profile D_2, wherein the portion comprises at least 5, such as at least 10, local maxima and adjacent local minima.In the example of FIG. 17A, both the reference dose profile D_ 4 and the second dose profile D_ 2 have a relative ripple amplitude of 50% (Ar_ 2=0.5), while the dose profile according to the invention (curve D_ 1) has a relative ripple amplitude of 10% (Ar_ 1=0.1).FIG. 17B shows an example with only moderate ripple reduction: here, the resulting relative ripple amplitude of the curve D_ 1 is A_ 1=0.3 or 30%.The examples of FIGS. 17A-B relate to the case that the ripple runs in a direction Y in which the average dose does not vary, for example parallel to a chip edge in a linear part of the edge termination structure (for example perpendicular to the two-dimensional sections of FIGS. 6-10 ). In a direction corresponding to the lateral direction X in FIGS. 6-10, for example, the profile decreases toward the chip edge, as schematically shown in FIG. 17C.In an embodiment according to any of the examples of FIGS. 17A-C, adjacent local maxima of the first dose profile D_ 1 may be spaced apart from each other by at least a first horizontal distance h 1 amounting to at least 2 μm. Additionally or alternatively, in an embodiment, adjacent local maxima of the second dose profile D_ 2 may be spaced apart from each other at least by a second horizontal distance h 2 amounting to at least 2 μm.FIGS. 18A-C each schematically and exemplarily illustrate a portion of a VLD-type implantation pattern that may be used in a method according to one or more embodiments. The illustrated closed regions are regions in which doped elements are implanted (i.e., openings of the first mask 21 and / or the second mask 22, for example). In FIGS. 18A-C, for example, the chip edge is located on the right (i.e., positioned further in direction X), and the active region of the power semiconductor device 1 is located on the left. The dopant doses of FIGS. 17A-B may correspond to a path along the second horizontal direction Y, wherein the dopant profile may have been produced according to the pattern shown in FIG. 18A, for example.In Figs. 18B and 18C, respectively, two further examples are illustrated showing a combination of a longitudinal stripe pattern for a middle portion of effective doses and patterns of rectangular openings and mask patterns for the low and high doses.According to the patterns of FIGS. 18A-C, for example, in a cross section along the second horizontal direction Y, an area ratio of the open areas of the first mask 21 to the masked areas of the first mask 21 over the first semiconductor region 103 may decrease (e.g., average, i.e., not forcibly monotone) in a direction facing from an active area of the power semiconductor device 1 to a lateral edge of the semiconductor body 10. In some embodiments, such a decrease may occur along both the first and second horizontal directions X, Y, for example.Above, embodiments related to power semiconductor devices and respective processing methods have been explained.For example, these semiconductor devices are based on silicon (Si). Accordingly, a(s) monocrystalline semiconductor region or layer, for example the semiconductor body 10 and its regions / zones, for example regions etc., may be a(s) monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.It should be appreciated, however, that the semiconductor body 10 and its regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), Aluminum gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP), and binary or ternary II-VI semiconductor materials such as, but not limited to, cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe). The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When combining two different semiconductor materials, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For applications with power semiconductor switches, Si, SiC, GaAs and GaN materials are mainly used at present.Spatial terms such as "below," "below," "lower," "over," "upper," and the like are used to describe the positioning of an element relative to a second element for ease of description. These terms are intended to include various orientations of the respective device in addition to orientations different from those shown in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.As used herein, the terms "have," "include," "include," "comprise," "have," and the like are open ended terms and indicate the presence of the stated elements or features, but do not exclude additional elements or features.

Claims

A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side surface (10-1) and including a drift region (100) having dopants of a first conductivity type; - an edge termination region (105), wherein the edge termination region (105) is included in the semiconductor body (10) and comprises: ◯ a part of the drift region (100); ◯ a first semiconductor region (103) extending along the front side surface (10-1), the first semiconductor region (103) comprising dopants of the first conductivity type and dopants of a second conductivity type complementary to the first conductivity type, wherein an integrated vertical dopant concentration of the dopants of the second conductivity type is higher than an integrated vertical dopant concentration of dopants of the first conductivity type in the first semiconductor region (103), wherein the first semiconductor region (103) forms a continuous pn junction (J) with the drift region (100); wherein a first dose profile (D_ 1) representing a vertically integrated net dopant concentration of the dopants of the first and second conductivity type in the first doped semiconductor region (103) has a lower degree of ripple along a horizontal direction (X, Y) than a second dose profile (D_ 2) representing a vertically integrated dopant concentration of the dopants of the second conductivity type in the first doped semiconductor region (102).The power semiconductor device (1) according to claim 1, wherein a relative ripple amplitude Ar_1 of the first dose profile D_1 amounts to at most 80% of a relative ripple amplitude Ar_2 of the second dose profile D_2, wherein the relative ripple amplitude Ar_i (i = 1.2) is defined as: Ar _ i = ( dmax _ i - dmin _ i ) / ( dmax _ i + dmin _ i ), wherein i = 1.2, dmax is a dose value at a local maximum of the dose profile D_i and dmin_i is a dose value at an adjacent local minimum of the dose profile D_i.Power semiconductor device (1) according to claim 2, wherein an averaged relative ripple amplitude <Ar_1> of the first dose profile D_1 amounts to at most 80% of an averaged relative ripple amplitude <Ar_2> of the second dose profile D_2, the average being taken over a portion of the first dose profile D_1 and a corresponding portion of the second dose profile D_2, the portions in each case comprising at least 2 local maxima and a local minimum arranged therebetween.Power semiconductor device (1) according to claim 2 or 3, wherein an averaged relative ripple amplitude <Ar_1> of the first dose profile D_1 amounts to at most 80% of an averaged relative ripple amplitude <Ar_2> of the second dose profile D_2, the average being taken over a portion of the first dose profile D_1 and a corresponding portion of the second dose profile D_2, the portions in each case comprising at least 5 local maxima and adjacent local minima.The power semiconductor device (1) according to any of the preceding claims, wherein a relative ripple amplitude Ar_2 of the second dose profile D_2 amounts to at least 0.5, wherein the relative ripple amplitude is defined as the relative ripple amplitude Ar_2 of the second dose profile D_2 defined as: Ar _ 2 = ( dmax _ 2 - dmin _ 2) / ( dmax _ 2 + dmin _ 2), wherein dmax_2 is a dose value at a local maximum of the second dose profile D_2 and dmin_2 is a dose value at an adjacent local minimum of the second dose profile D_2.The power semiconductor device (1) according to claim 5, wherein an averaged relative ripple amplitude <Ar_2> of the second dose profile D_2 amounts to at most 0.5, wherein the average is taken over a portion of the second dose profile D_2, wherein the portion comprises at least 5 local maxima and adjacent local minima.The power semiconductor device (1) according to any of the preceding claims, wherein the edge termination region (105) forms at least a part of a lateral doping variation edge termination region.Power semiconductor device (1) according to any of the preceding claims, wherein - adjacent local maxima of the first dose profile (D_1) are spaced apart from each other by at least a first horizontal distance (h1) amounting to at least 2 μm; and / or - adjacent local maxima of the second dose profile (D_2) are spaced apart from each other by at least a second horizontal distance (h2) amounting to at least 2 μm.A method for processing a power semiconductor device (1) comprising: - providing a semiconductor body (10) having a front side surface (10-1) and including a drift region (100) having dopants of a first conductivity type; forming an edge termination region (105) within the semiconductor body (10), wherein forming the edge termination region (105) comprises: ◯ forming a first doped semiconductor region (103) extending along the front side surface (10-1) and forming a continuous pn junction (J) with the drift region (100), wherein forming the first doped semiconductor region (103) comprises the steps of: ▪ implanting dopants of a second conductivity type through the front side surface (10-1) by means of a first masked implantation, wherein a first mask (21) is used for the first masked implantation, wherein the first mask defines first open regions and first masked regions; ▪ implanting dopants of a first conductivity type through the front side surface (10-1) by means of a second masked implantation, wherein a second mask (21, 22) is used for the second masked implantation, wherein the second mask defines second open regions and second masked regions, wherein the first mask (21) and the second mask (22) are arranged on the semiconductor body (10) such that open regions of the second mask (22) which lie on the first doped semiconductor region (103) during the second implantation step horizontally overlap open regions of the first mask (21) which lie on the first doped semiconductor region (103) during the first masked implantation, and wherein the first mask (21) and the second mask (22) are arranged on the semiconductor body (10) such that closed regions of the second mask (22) which lie on the first doped semiconductor region (103) during the second implantation step horizontally overlap closed regions of the first mask (21), which during the first masked implantation are situated on the first doped semiconductor region (103), horizontally overlap.The method of claim 9, wherein in a cross-section along a horizontal direction (X, Y), an area ratio of the open areas of the first mask (21) to the masked areas of the first mask (21) over the first semiconductor region (103) decreases in a direction facing from an active region of the power semiconductor device (1) to a lateral edge of the semiconductor body (10).The method of claim 10, wherein forming the first doped semiconductor region (103) comprises performing at least one diffusion step for diffusing the dopants of the second conductivity type.The method of claim 11, wherein the at least one diffusion step is performed prior to the implantation of dopants of the first conductivity type.The method of any of claims 9 to 11, wherein forming the first doped semiconductor region (103) and the second doped semiconductor regions (104) comprises diffusing the implanted dopants of the first conductivity type and the implanted dopants of the second conductivity type in a same diffusion step.The method according to any of claims 9 to 13, wherein the first semiconductor region (103) is formed such that a first dose profile (D_1) representing a vertically integrated net dopant concentration of the dopants of the first and second conductivity type in the first doped semiconductor region (103) has a lower degree of ripple along a horizontal direction (X, Y) than a second dose profile (D_2) representing a vertically integrated dopant concentration of the dopants of the second conductivity type in the first doped semiconductor region (103).Method according to one of claims 9 to 14, wherein a same mask (21) is used for the first masked implantation and the second masked implantation.The method according to any of claims 9 to 13 or 15, wherein the dopants of the first conductivity type have a first diffusion constant in the semiconductor body (10), and wherein the dopants of the second conductivity type have a second diffusion constant in the semiconductor body (10), wherein the second diffusion constant is different from the first diffusion constant by at most a factor in the range of 0.5 to 2.The method according to any of claims 9 to 15, wherein the dopants of the first conductivity type have a first diffusion constant in the semiconductor body (10), and wherein the dopants of the second conductivity type have a second diffusion constant in the semiconductor body (10), wherein the second diffusion constant exceeds the first diffusion constant by at least a factor of 3.The method according to any of claims 9 to 17, wherein the dopants of the first conductivity type and / or the dopants of the second conductivity type are implanted through a shielding layer (3) arranged over the front side surface (10-1), and wherein the method comprises: - forming, by means of a third implantation of dopants of the first or second conductivity type through the front side surface (10-1), a third doped semiconductor region (106) extending along the front side surface (10-1) in a region where the front side surface (10-1) is not covered by the oxide layer (3).The method of claim 18, wherein a same mask (21) is used for the first masked implantation and the third masked implantation.The method according to claim 18 or 19, wherein the third masked implantation is performed with a lower energy than the first masked implantation, such that the dopants of the second type do not penetrate the oxide layer (3) during the third masked implantation.A method for processing a power semiconductor device (1) comprising: - providing a semiconductor body (10) having a front side surface (10-1) and including a drift region (100) comprising dopants of a first conductivity type; - forming an edge termination region (105) within the semiconductor body (10), wherein forming the edge termination region (105) comprises: - forming a first doped semiconductor region (103) extending along the front side surface (10-1) and forming a continuous pn-junction (J) with the drift region (100); forming a further doped semiconductor region (106) in the semiconductor body (10), wherein forming the first doped semiconductor region (103) and the further doped semiconductor region (106) comprises the following steps: - forming a patterned shielding layer (3) on the front side (10-1), wherein the patterned shielding layer (3) covers the first doped semiconductor region (103) to be formed, wherein the patterned shielding layer (3) is not present on the further doped semiconductor region (106) to be formed; - in a first implantation step, by means of a first mask (21), implanting dopants through the patterned shielding layer (3) into the semiconductor body (10) with a first implantation energy; in a further implantation step, by means of the first mask (21), implanting dopants into the patterned shielding layer (3) into the semiconductor body (10) with a second implantation energy which is lower than the first implantation energy; wherein the first mask (21) is open over the further doped semiconductor region (106) to be formed, and wherein the first mask (21) defines first open regions and first masked regions, wherein in a cross section along a horizontal direction (X, Y) an area ratio of the first open regions to the first masked regions decreases over the first semiconductor region (103) in a direction pointing from an active region of the power semiconductor device (1) to a lateral edge of the semiconductor body (10).

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