Mains switch control circuit, storage device and associated procedure

Abstract

A mains switch control circuit (100) comprising the following: a supply rail (189) configured to supply power to a storage arrangement; a first header switch (164) for coupling the supply rail (189) with a first power supply corresponding to a first power range (102); a second header switch (150) for coupling the supply rail (189) with a second power supply corresponding to a second power range; a control circuit (181) configured to receive a selection signal and a shutdown signal and to output control signals to the first and second header switches (164, 150) to selectively couple the first and second header switches (164, 150) to the first or second power supply in response to the selection signal and the shutdown signal; and wherein the control circuit (181) is configured to output the control signals to the first and second header switches (164, 150) in order to disconnect both the first and second header switches (164, 150) from the first and second power supplies in response to the shutdown signal and independently of the selection signal, wherein the control signals comprise first and second control signals for controlling the first and second header switches (164, 150) respectively, wherein the mains switch control circuit (100) further comprises the following: a first latch circuit configured to receive the selection signal and output the first and second control signals in response to it; and wherein the mains switch control circuit (100) is configured to modify the first or the second control signal output by the first latch circuit in response to the shutdown signal.

Description

BACKGROUND

[0001] Some well-known storage devices, such as a static random-access memory (SRAM) device, feature a mains switch control design. A typical SRAM storage device has an array of memory cells. Each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (typically ground), so that one of two memory nodes can be occupied with the information to be stored, with the complementary information stored in the other memory node. Some SRAM arrays operate the memory logic in a low-voltage range, while the memory array itself operates in the high-voltage range. Furthermore, various techniques can be employed to reduce power consumption. For example, parts of the storage device can be switched off during a sleep or shutdown mode.Problems can occur if switching operations are not carefully controlled. For example, header switches can be overloaded if the power supplies are short-circuited for a certain period, especially after numerous switching cycles. Additionally, a DC leakage between the header switches can lead to a large shutdown leakage in shutdown mode if only the internal header switches are turned off.

[0002] US 2010 / 0254209A1 discloses an integrated circuit structure comprising an active power supply line and a data storage power supply line. A storage macro is connected to both the active power supply and data storage power supply lines. The storage macro includes a memory cell array and a switch. The switch is configured to toggle the connection between the memory cell array being connected to the active power supply line and the memory cell array being connected to the data storage power supply line. The data storage power supply line is located outside the storage macro.

[0003] US 2009 / 0039952A1 discloses a method that includes parsing an integrated circuit design to define cells in automatic power-gating power domains, automatically generating an automatic power-gating power domain netlist from the parsed integrated circuit design, and placing and routing the automatic power-gating power domain netlist to create a layout for the integrated circuit. The parsing process divides a high-level power domain of the integrated circuit into one or more automatic power-gating power domains. The automatic power-gating power domains essentially have zero-cycle on-times, thus enabling transparent operation.Furthermore, the automatic power-gating power domains can be automatically inserted into integrated circuit designs, relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

[0004] US 2017 / 0178719A1 discloses a device comprising first memory cells, second memory cells, a first conductive line, and a second conductive line. The first conductive line is electrically isolated from the second conductive line. The first conductive line receives a first supply voltage for the plurality of first memory cells. The second conductive line receives a second supply voltage, independent of the first supply voltage, for the plurality of second memory cells.

[0005] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read with reference to the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not shown to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1 is a block diagram illustrating an example of a storage device according to some embodiments. Fig. 2 is a circuit diagram that shows an example of a mains switch control circuit of the storage device from Fig. 1 according to some embodiments. Fig. 3 is a time diagram showing waveforms of the circuit. Fig. 4 according to some embodiments. Fig. 4 is a circuit diagram showing a first latch circuit of the mains switch control circuit. Fig. 2 according to some embodiments. Fig. 5 is a circuit diagram showing a second latch circuit of the mains switch control circuit. Fig. 2 according to some embodiments. Fig. 6 is a timing diagram showing waveforms of the circuit. Fig. 7 according to some embodiments. Fig. 7 is a circuit diagram that shows another example of the first latch circuit of the mains switch control circuit from Fig. 2 according to some embodiments. Fig. 8 is a timing diagram showing waveforms of the circuit from Fig. 9 according to some embodiments. Fig. 9 is a circuit diagram that shows another example of the first latch circuit of the mains switch control circuit from Fig. 2 according to some embodiments. Fig. 10 is a circuit diagram that shows another example of the first latch circuit of the mains switch control circuit from Fig. 2 according to some embodiments. Fig. Figure 11 is a flowchart that represents a procedure according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, such that the first and second features cannot be in direct contact with each other. Additionally, the present disclosure may repeat reference numbers and / or letters in different examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like can be used here for the sake of simplicity to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the components used or operated, in addition to the orientation shown in the figures. The setup may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] Electronic devices can selectively draw power from two different external power supplies. A storage device, such as a static random-access memory (SRAM) device, is one example of such an electronic device, but not the only one.

[0010] Fig. Figure 1 shows an exemplary electronic device, such as an SRAM memory device 10 according to some embodiments. As in Fig. As shown in Figure 1, the exemplary SRAM device 10 comprises at least one input / output (IO) area 182, a control circuit 181, a bit cell array 183, a word line driver (WL driver) 184, and a power switch 185. The SRAM device 10 may include other components, which are shown in Figure 1. Fig. 1 are not shown. In exemplary embodiments, the SRAM device 10 can be part of an IC chip (integrated circuit chip).

[0011] The I / O area 182 and the control area 181 both operate with an internal voltage supply VDD (i.e., within an internal voltage range VDD). The bit cell arrangement 183 operates selectively in a first or a second power range, where the first power range corresponds to a first supply voltage VDD and the second power range corresponds to a second supply voltage VDDM. The word line driver area 184 provides driver signals and can be considered to operate in both the first and second power ranges VDD and VDDM.

[0012] The power switch area 185 is arranged along the periphery of the bit cell arrangement 183 to switch between VDD and VDDM. The power switch area 185 includes a power switch control circuit 100. In some embodiments, the power switch control circuit 100 may be contained within the control area 181. The power switch area 185 further includes a main power switch 186, which is distributed across the entire memory macro. In some embodiments, the instances of the main power switch 186 are located along the entire periphery of the bit cell arrangement 183 and include, for example, a first instance 186a, an intermediate instance 186b, and a final instance 186c, as well as instances between 186a and 186b and instances between 186b and 186c.

[0013] Each instance of the main power switch 186 has an internal power rail 189. The internal power rail 189 is connected to the VDD power supply via a PMOS header switch 164 and to the VDDM power supply via a PMOS header switch 150. The VDD header switch 164 responds to a control signal ON_GDB, which is provided by an inverter 188 from a signal ON_GD. The ON_GD signal is used to select VDD. The VDDM header switch 150 responds to a control signal ON_GMB, which is provided by an inverter 187 from a signal ON_GM. The ON_GM signal is used to select VDDM. The ON_GD and ON_GM signals are switch control signals and are supplied to each instance of the main power switch 186.

[0014] In some examples, many transistors are switched on simultaneously when a circuit is powered on. This power-up process is also referred to as circuit wake-up, as the circuit is being awakened for operation, for example, from a shutdown or sleep state. When many transistors are switched on during wake-up, a large amount of current flows through the corresponding current distribution nodes used by the transistors, which can result in a current peak known as the wake-up peak current. Reducing a circuit's wake-up peak current to a design specification increases the circuit's wake-up time. For example, in one approach, a wake-up circuit has a series of wake-up stages. Each wake-up stage has a PMOS switch connected in a chain.A wake-up signal is applied to each PMOS switch in turn, switching on the cascaded PMOS switches one after the other. Switching on each PMOS switch sequentially reduces the wake-up peak current. Noise generated by switching operations during wake-up can interfere with the switching control.

[0015] Fig. Figure 2 shows an example of a mains switch control circuit 100 according to aspects of the disclosure. As in Fig. As shown in Figure 2, devices to the left of the dashed line are located in a first power range 102, while devices to the right of the dashed line are located in a third power range 104. In the illustrated example, the first power range 102 is the VDD range, configured to receive a VDD mains supply voltage, and the third power range 104 is the VMAX2 power range, configured to receive a higher VMAX2 mains supply voltage. In other words, the third power range (i.e., the VMAX2 mains supply voltage) 104 is intended for the operation of the mains switch control circuit 100. The first power range (i.e., the VDD mains supply voltage) 102 and the second power range (i.e., the VDDM mains supply voltage) are intended for the operation of the bit cell arrangement 183.In some embodiments, the VMAX2 mains supply voltage can be higher than the VDDM mains supply voltage. In some embodiments, the VMAX2 mains supply voltage can be equal to the VDDM mains supply voltage. In some embodiments, the VMAX2 mains supply voltage can be lower than the VDDM mains supply voltage. The mains switch control circuit 100 is configured to control the VDD header switch 164 and the VDDM header switch 150 in response to a power-on signal AON_SELSRM_IN, a standby signal VDD_RDYB, and a power-off signal SD. The AON_SELSRM_IN signal is activated to select either the VDD or the VDDM power range, and the SD signal indicates the power-off mode.

[0016] In general, the power switch control circuit 100 is configured to turn off both the VDD header switch 164 and the VDDM header switch 150 when the device 10 is in shutdown mode (i.e., SD = 1). Furthermore, the circuit 100 is configured to turn off both the VDD header switch 164 and the VDDM header switch 150 even if event factors such as noise affect the circuit's control signals. For example, as described above in conjunction with... Fig. As specified in Figure 1, the power switch 186 can be distributed across the entire memory macro, resulting in relatively long control signal lines for controlling the various power switches, such as signal feedback lines. These long signal lines can lead to signal loss and thus to oscillations in some control signals. As discussed in more detail below, some disclosed embodiments can address problems such as these by making the power switch control circuit 100 more robust and less susceptible to various signal fluctuations.

[0017] In general, the mains switch control circuit 100 includes, among other things, two latches. A first, or state, latch 118 facilitates a "make-before-break" function during a functional mode (i.e., non-shutdown state) and also prevents both the VDD and VDDM header switches 164, 150 from being turned on simultaneously when the SD signal passes during wake-up. In the internal VDD section 102, the first shutdown signal SD is converted from the internal VDD section 102 to a higher voltage level, such as the VMAX2 section 104, by a level shifter 112, thereby generating a second shutdown signal SD_VMAX2. The SD_VMAX2 signal is fed to an inverter 114, which generates a second shutdown signal bar SDB_VMAX2. On the other hand, in the internal VDD area 102, the switch-on signal AON_SELSRM_IN from the internal VDD area 102 is converted to a SEL_VMAX2 signal in the VMAX2 area 104 by a level converter 116.

[0018] The output of level converter 116 (i.e., the signal SEL_VMAX2) is fed to a set input 120 of state latch 118. The output of level converter 116 is also fed to inverter 136, and the output signal of inverter 136 is fed to a reset input 122 of state latch 118. The state latch outputs the global VDD and VDDM selection signals ON_GD and ON_GM, respectively. The ON_GM signal, along with the SDB_VMAX2 signal, is fed by a first output 128 of state latch 118 to a NAND gate 138. The output of NAND gate 138 is fed to a plurality of inverters, including inverters 140, 142, 144, and 146, which generate a delayed signal of the output of NAND gate 138 to the VDDM header switches 150. At node 148, a feedback signal ON_GMB is fed back to a first feedback input 124 of the state latch 118. The On_GMB signal at node 148 is also fed to a gate of the VDDM header switch 150.In other words, a delayed signal from the output of NAND gate 138 is fed to the gate of VDDM header switch 150. In this example, VDDM header switch 150 is a PMOS transistor. One source of VDDM header switch 150 is connected to the VDDM power supply, while one drain of VDDM header switch 150 is connected to the internal power rail 189. As mentioned above, in some embodiments, the power switch 186 is distributed across the entire memory macro. Accordingly, multiple VDDM header switches 150 can be distributed across the memory macro, and the inverter-delayed ON_GM control signal can be sequentially fed to the VDDM header switches 150 for their sequential control.

[0019] During the shutdown period, the SD signal, and therefore the SD_VMAX2 signal, is a high level (1), whereas the SDB_VMAX2 signal is a low level (0). Therefore, during the shutdown period, the output of NAND gate 138 is a high level (1), regardless of the value of the outputs of state latch 118. Consequently, the signal fed to the gate of VDDM header switch 150 is a high level (1). Accordingly, VDDM header switch 150 is always off during the shutdown period.

[0020] On the other hand, the ON_GD signal from a second output 130 of the state latch 118, along with the SDB_VMAX2 signal, is fed to a NAND gate 152. The output of the NAND gate 152 is fed to a plurality of inverters, including inverters 154, 156, 158, and 160, which generate delayed signals of the NAND gate 152 output. These delayed signals are used to control the VDD switches (e.g., the VDD header switch 164). As mentioned above, in some embodiments, the power switch 186 is distributed across the entire memory macro. Accordingly, a plurality of the VDD header switches 164 can be distributed across the memory macro, and the ON_GD control signal, delayed by the inverters, can be fed sequentially to the VDD header switches 164 for their sequential control.

[0021] At node 162, an ON_GMB signal is fed back to a second feedback input 126 of the state latch 118. The ON_GDB signal at node 162 is also fed to a gate of the VDD header switch 164. In other words, a delayed signal from the output of the NAND gate 152 is fed to the gate of the VDD header switch(es) 164. In this example, the VDD header switch 164 is a PMOS transistor. One source of the VDD header switch 164 is connected to a power supply VDD, while one drain of the VDD header switch 164 is connected to the internal power rail 189. The internal power rail 189 is used to supply power to the bit cell array 183.

[0022] During the shutdown period, the SD_VMAX2 signal is a high level (1), while the SDB_VMAX2 signal is a low level (0), as mentioned above. Therefore, during the shutdown period, the output of NAND gate 152 is a high level (1), regardless of the value of the second output 130 of state latch 118. Thus, the signal provided to the gate of VDD header switch 164 is a high level (1). Accordingly, VDD header switch 164 is always off during the shutdown period. Consequently, during the shutdown period, the power switch control circuit 100 is configured to turn off both VDDM header switch 150 and VDD header switch 164 in response to the SD signal, regardless of the selection signal AON_SELSRM_IN. By switching off both header switches 150 and 164, the DC current loss between the header switches 150 and 164 can be reduced.By disabling both header switches 150 and 164, as well as other header switches, the overall shutdown loss is reduced. Furthermore, the signals at nodes 162 and 148 are fed back to feedback inputs 126 and 124 to latch the inputs with header switches 164 and 150 and ensure that these header switches remain off during shutdown mode.

[0023] An output latch 166 has four inputs: a first input 168; a second input 170; a third input 172; and a fourth input 174. The ON_GMB signal is fed back from node 148 to the first input 168 of output latch 166. The ON_GDB signal is fed back from node 162 to the second input 170 of output latch 166. A third output 132 of status latch 118 provides the ON_GD signal to the third input 172 of output latch 166. A fourth output 134 of status latch 118 provides the ON_GM signal to the fourth input 174 of output latch 166. An AON_SELSRM_OUT signal is generated by output latch 166 at output 176 of output latch 166. It should be noted that the AON_SELSRM_OUT signal is located in the internal VDD area 102.As discussed in more detail below, the output latch 166 is configured such that during shutdown the states of the ON_GDB and ON_GMB signals are latched to keep the header switches 164, 150 off, while ON_GDB and ON_GMB control the output latch state in a functional mode.

[0024] Fig. Figure 3 illustrates a timeline diagram according to some examples. Timeline diagram 200 is described below with reference to Fig. 4 and Fig. 5 reveals. As can be seen from the timeline diagram. Fig. As can be seen in Figure 3, the signal SD is initially a low level (0). At time t1 201, the signal SD becomes a high level (1), which means that the mains switch control circuit 100 is in the shutdown period. At time t3 203, the signal SD becomes a low level (0), which means that the shutdown period of the mains switch control circuit 100 ends. In one embodiment, the signal AON_SELSRM_IN must not switch during the shutdown period (i.e., from time t1 201 to time t3 203) or a shutdown-wake-up period (i.e., a short period after time t3 203). In the example from Fig. The AON_SELSRAM_IN signal remains a constant low level (0) until time t5 205, which is after the end of the shutdown period. At time t5 205, the AON_SELSRAM_IN signal becomes a high level (1). When the AON_SELSRAM_IN signal is low (0) (e.g., before time t5 205), the ON_GDB signal is assumed to be low (0) (e.g., before time t2 202), whereas the ON_GMB signal is assumed to be high (1) (e.g., before time t6 206). This indicates that VDD is selected and VDDM is deselected because VDDM header switch 150 is off, while VDD header switch 164 is on. If the signal AON_SELSRAM_IN is a high level (1) (e.g., after time t5 205), the signal ON_GDB is assumed to be a high level (1) (e.g., after time t7 207), whereas the signal ON_GMB is assumed to be a low level (0) (e.g., after time t7 207).after time t6 206), which indicates a selection of VDDM and a deselection of VDD because the VDD header switch 164 is off while the VDDM header switch 150 is on.

[0025] As described above, during the shutdown period (i.e., from time t2 202 to time t4 204), both the VDDM header switch 150 and the VDD header switch 164 are turned off due to the SD signal. The AON_SELSRM_OUT signal does not respond to the switching of the SD signal. Instead, the AON_SELSRM_OUT signal responds with a delay to the change in the AON_SELSRM_IN signal at time t8 208. When the ON-GDB signal becomes low (0) at time t4 204, the ON_GMB signal additionally remains high (1) until time t6 206. Therefore, the SD signal dropping to low at time t3 203 does not cause a short circuit between the two areas (i.e., VDD and VDDM). The timing diagram 200 is further illustrated below with reference to Fig. 4 and Fig. 5 revealed.

[0026] Fig. Figure 4 shows an embodiment of the state latch 118 of the mains switch control circuit 100 of Fig. 2. In this embodiment, the state latch 118 of the mains switch control circuit 100 has an AND gate 302, a NOR gate 304, an inverter 306, an AND gate 308, a NOR gate 310 and a NOR gate 312.

[0027] The cross-coupled NOR gate 304 and NOR gate 310 act as an SR latch. Specifically, the output (i.e., the signal SEL_VMAX2) of the level shifter 116 is fed to NOR gate 304 at the set input 120 of the state latch 118. An output of the AND gate 302 is also fed to NOR gate 304. An output of NOR gate 304 is fed to inverter 306. The output of inverter 306 at the first output 128 of the state latch 118 is the signal ON_GM. The ON_GM signal is further fed back to an input of the AND gate 302. The ON_GDB signal at node 162 is fed to the other input (i.e., the second feedback input 126 of the state latch 118) of the AND gate 302.

[0028] On the other hand, the output of inverter 136 is fed to NOR gate 310 at the reset input 122 of state latch 118. An output of AND gate 308 is also fed to NOR gate 310. An output of NOR gate 310, along with a signal VDD-RDYB, is fed to NOR gate 312. The output of NOR gate 312 at the second output 130 of state latch 118 is the signal ON_GD. The ON_GD signal is further fed back to an input of AND gate 308. The ON_GMB signal at node 148 is fed to the other input (i.e., the first feedback input 124 of state latch 118) of AND gate 308.

[0029] A first feedback loop 178 is formed by feeding back the ON_GDB signal from node 162 to AND gate 302 and the ON_GMB signal from node 148 to AND gate 308. Thus, in the first loop 178, the ON_GDB control signal for VDD header 164, generated by the upper leg of state loop 118, is fed back to the lower leg of state loop 118, which generates the ON_GMB control signal for VDDM header 150. Furthermore, in the first loop 178, the ON_GMB control signal for VDDM header 150, generated by the lower leg of state loop 118, is fed back to the upper leg of state loop 118, which generates the ON_GDB control signal for VDD header 164.

[0030] When the power switch control circuit 100 is in a functional mode (i.e., SD = 0), the first loop 178 accordingly performs the aforementioned "make-before-break" function, whereby the power headers 164 and 150 are not simultaneously switched off during functional mode. The AND gates 302 and 308, which generate respective inputs for the cross-coupled NOR gates 304 and 310, prevent the latch from simultaneously outputting high-level signals for the ON-GMB and ON_GDB control signals.

[0031] During the shutdown period, as described above, the ON_GMB signal is constantly a high level (1), whereas the ON_GDB signal is also constantly a high level (1), as in Fig. Figure 3 shows that one input (i.e., the second feedback input 126 of state latch 118) of AND gate 302 is a constant high level (1), so the output of AND gate 302 is the same as the other input of AND gate 302 (i.e., the ON_GM signal). The ON_GM signal, along with the output (i.e., the SEL_VMAX2 signal) of level shifter 116, is fed back to NOR gate 304. Similarly, one input (i.e., the first feedback input 124 of state latch 118) of AND gate 308 is a constant high level (1), so the output of AND gate 308 is the same as the other input of AND gate 308 (i.e., the ON_GD signal). The ON_GD signal is fed back to the NOR gate 310 along with the output of inverter 124. In other words, during the shutdown period, the second loop 314 interrupts the first loop 178, resulting in power noise from the ON_GDB signal and the ON_GMB signal after the shutdown wake-up (i.e., after the shutdown wake-up).an SD transition from a high level to a low level) is prevented.

[0032] Fig. Figure 5 shows an embodiment of the output latch 166 of the mains switch control circuit 100 of Fig. 2. In this embodiment, the output latch 166 of the mains switch control circuit 100 comprises an inverter 402, a NOR gate 404, a NOR gate 406, an inverter 408, a NOR gate 410, a NOR gate 412, and an inverter 414. Specifically, the ON_GDB signal is fed to inverter 402. The output of inverter 402, which is an ON_GD signal, is fed to NOR gate 404 along with the ON_GD signal. The output of NOR gate 404 (i.e., a GDD_PS signal) is fed to a reset input of a flip-flop consisting of NOR gate 406 and NOR gate 412. The ON_GMB signal, on the other hand, is fed to inverter 408. The output of inverter 408, which is a signal ON_GM, is fed to NOR gate 410 along with the ON_GM signal. The output of NOR gate 410 (i.e., a signal GDM_PS) is fed to a set input of the flip-flop, which consists of NOR gate 406 and NOR gate 412.The output of the flip-flop, consisting of NOR gates 406 and 412, is fed to inverter 414. The output of inverter 414 is the signal SON_SELSRM_OUT in the internal VDD area 102.

[0033] During a functional mode, the ON_GDB and ON_GMB signals control the state of output latch 166. In other words, output latch 166 latches the selection signal AON_SELSRM_IN as the signal AON_SELSRM_OUT in response to the ON_GDB and ON_GMB signals. During the shutdown period, as described above, both the ON_GDB and ON_GMB signals are high (1). Thus, both the output of inverter 402 and the output of inverter 408 are low (0). The output of NOR gate 404 is the ON_GDB signal, while the output of NOR gate 410 is the ON_GMB signal. Therefore, output latch 166 maintains its state during the shutdown period. In other words, the state of the AON_SELSRM_OUT signal does not change during the shutdown period, even if the AON_SELSRM_IN signal changes during the shutdown period.

[0034] Another example of the mains switch control circuit 100 from Fig. 2 is shown below in conjunction with the time sequence diagram 500 from Fig. 6 and the circuit diagram from Fig. 7 described. As shown in the timeline diagram. Fig. As can be seen in Figure 6, the signal SD is initially a low level (0). At time t1 501, the signal SD becomes a high level (1), indicating that the power switch control circuit 100 is in its shutdown period. At time t3 503, the signal SD becomes a low level (0), indicating that the shutdown period of the power switch control circuit 100 ends. In one embodiment, the signal AON_SELSRM_IN may toggle during the shutdown period (i.e., from time t1 501 to time t3 503) or during a shutdown-wake-up period (i.e., a short period after time t3 503). For example, the signal AON_SELSRM_IN switches from a low level (0) to a high level (1) at time t11 511, from a high level (1) to a low level (0) at time t12 512, from a high level (0) to a high level (1) at time t13 513, and from a high level (1) to a low level (0) at time t14 514.It should be noted that the AON_SELSRM_IN signal can switch to other structures during the shutdown period or a shutdown / wake-up period. The AON_SELSRAM_IN signal becomes a high level (1) at time t5 505. The final state (a low level) of the AON_SELRAM_IN signal before the shutdown wake-up is the same as the (a low level) state before the start of the shutdown period at time t1 501. If the AON_SELSRAM_IN signal is a low level (0) (e.g., before time t11 511), the ON_GDB signal is assumed to be a low level (0) (e.g., before time t2 502), whereas the ON_GMB signal is assumed to be a high level (1) (e.g., before time t6 506), indicating a selection of VDD and a deselection of VDDM, because the VDDM header switch 150 is off, while the VDD header switch 164 is on. If the signal AON_SELSRAM_IN is a high level (1) (e.g.After time t5 505), the ON_GDB signal is assumed to be a high level (1) (e.g., after time t7 507), whereas the ON_GMB signal is assumed to be a low level (0) (e.g., after time t6 506), indicating a selection of VDDM and a deselection of VDD because the VDD header switch 164 is off, while the VDDM header switch 150 is on.

[0035] As described above, during the shutdown period (i.e., from time t2 502 to time t4 504), both the VDDM header switch 150 and the VDD header switch 164 are turned off due to the SD signal. The AON_SELSRM_OUT signal does not respond to the switching of the SD signal. Instead, the AON_SELSRM_OUT signal responds with a delay at time t8 508 to the change in the AON_SELSRM_IN signal at time t5 505. When the ON-GDB signal becomes low (0) at time t4 504, the ON_GMB signal additionally remains high (1) until time t6 506. Therefore, the SD signal dropping at time t3 503 does not cause a short circuit between the two areas (i.e., VDD and VDDM). The implementation of the timing diagram 500 is described below with reference to Fig. 7 revealed.

[0036] Fig. Figure 7 shows an embodiment of the state latch 118 of the mains switch control circuit 100 of Fig. 2, which are shown in the time sequence diagram 500. Fig. 6 is linked. The state latch 118 of Fig. 7 features the AND gate 302, a NOR gate 304, an inverter 306, an AND gate 308, a NOR gate 310 and a NOR gate 312 similar to the one in Fig. 4. In the embodiment shown. Fig. Furthermore, 7 contains an AND gate 601 and an AND gate 607.

[0037] The cross-coupled NOR gate 304 and NOR gate 310 act as a flip-flop for state latch 118. Specifically, the output (i.e., the signal SEL_VMAX2) of the level shifter 116 is provided to the AND gate 601, along with the signal SDB_VMAX2. The output of AND gate 601 is fed to NOR gate 304 at the set input 120 of state latch 118. An output of AND gate 302 is also fed to NOR gate 304. An output of NOR gate 304 is fed to inverter 306. The output of inverter 306 at the first output 128 of state latch 118 is the signal ON_GM. The signal ON_GM is further fed back to an input of AND gate 302. The ON_GDB signal at node 162 is fed to the other input (i.e., the second feedback input 126 of the state latch 118) of the AND gate 302.

[0038] On the other hand, the output of inverter 136 is fed to NOR gate 310 at the reset input 122 of state latch 118, along with the signal SDB_VMAX2. An output of AND gate 308 is also fed to NOR gate 310. An output of NOR gate 310, along with a signal VDD-RDYB, is fed to NOR gate 312. The output of NOR gate 312 at the second output 130 of state latch 118 is the signal ON_GD. The signal ON_GD is further fed back to an input of AND gate 308. The signal ON_GMB at node 148 is fed to the other input (i.e., the first feedback input 124 of state latch 118) of AND gate 308.

[0039] During a function mode, a first loop 178 can execute the "Makebefore-Break" function. During the shutdown period, as described above, the signal SDB_VMAX2 is constantly a low level (o), whereas the signal ON_GMB and the signal ON_GDB are both constantly a high level (1), as in Fig. Figure 6 shows this. Accordingly, one input (i.e., the second feedback input 126 of state latch 118) of AND gate 302 is a constant high level (1), so the output of AND gate 302 is the same as the other input of AND gate 302 (i.e., the ON_GM signal). The ON_GM signal, along with the output of AND gate 601, is fed back to NOR gate 304. Similarly, one input (i.e., the first feedback input 124 of state latch 118) of AND gate 308 is a constant high level (1), so the output of AND gate 308 is the same as the other input of AND gate 308 (i.e., the ON_GD signal). The ON_GD signal, along with the output of AND gate 607, is fed back to NOR gate 310. In other words, the second loop 314 interrupts the first loop 178 during the shutdown period, thus preventing power noise from the ON_GDB signal and the ON_GMB signal after the shutdown wake-up.

[0040] Since the signal SDB_VMAX2 is a constant low level (0) during the shutdown period, the outputs of AND gate 601 and AND gate 607 are also constantly low levels (0). Therefore, the flip-flop of state latch 118, which features the cross-coupled NOR gate 304 and NOR gate 310, is in a held state. Consequently, the signal AON_SELSRM_IN (i.e., the switching of the signal AON_SELSRM_IN occurs via a gate) can switch during the shutdown period (i.e., from time t1 501 to time t3 503) or a shutdown-wake-up period (i.e., a short period after time t3 503), as shown in Fig. 6 shown.

[0041] Another exemplary operation of the exemplary mains switch control circuit 100 is described below with reference to Fig. 8 and Fig. 9 reveals. As can be seen from the timeline diagram from Fig. As shown in Figure 8, the signal SD is initially a low level (0). At time t1 701, the signal SD becomes a high level (1), indicating that the circuit breaker control circuit 100 is in its shutdown period. At time t4 704, the signal SD becomes a low level (0), indicating that the shutdown period of the circuit breaker control circuit 100 ends. In one embodiment, the signal AON_SELSRM_IN may toggle during the shutdown period (i.e., from time t1 701 to time t4 704) or during a shutdown-wake-up period (i.e., a short period after time t4 704). For example, the signal AON_SELSRM_IN switches from a low level (0) to a high level (1) at time t11 711, from a high level (1) to a low level (0) at time t12 712, from a low level (0) to a high level (0) at time t13 713, and from a high level (1) to a low level (0) at time t14 714.It should be noted that the AON_SELSRM_IN signal can switch to other structures during the shutdown period or a shutdown-wake-up period. The AON_SELSRAM_IN signal becomes a high level (1) at time t3 703. In contrast to the timing diagram 200 from . Fig. 3 and Fig. 500 out Fig. 6 is the final state (a high level) of the signal AON_SELRAM_IN before the shutdown wake-up at time t4 704, unlike the state (a low level) before the start of the shutdown period at time t1 701. The signal AON_SELSRM_IN switches from a low level (0) to logic (1) at time t3 703, before the signal SD switches from a high level (1) to a low level (0) at time t4 704. The signal ON_GMB switches from a high level (1) to a low level (0) at time t6 706, after the signal SD has dropped out at time t4 704.

[0042] If the signal AON_SELSRAM_IN is a low level (0) (e.g., before time t11 711), the signal ON_GDB is assumed to be a low level (0) (e.g., before time t2 702), whereas the signal ON_GMB is assumed to be a high level (1) (e.g., before time t6 506), indicating a selection of VDD and a deselection of VDDM because the VDDM header switch 150 is off, while the VDD header switch 164 is on. If the signal AON_SELSRAM_IN is a high level (1) (e.g., after time t3 703), the signal ON_GDB is assumed to be a high level (1) (e.g., after time t3 703), whereas the signal ON_GMB is assumed to be a low level (0) (e.g., after time t6 706), which indicates a selection of VDDM and a deselection of VDD because the VDD header switch 164 is off, while the VDDM header switch 150 is on.

[0043] As described above, during the shutdown period (i.e., from time t2 702 to time t6 706), both the VDDM header switch 150 and the VDD header switch 164 are turned off due to the SD signal. The AON_SELSRM_OUT signal does not respond to the switching of the SD signal. Instead, the AON_SELSRM_OUT signal responds with a delay to the change in the AON_SELSRM_IN signal. When the ON-GMB signal becomes low (0) at time t6 706, the ON_GDB signal additionally remains high (1). Therefore, the SD signal dropping to low at time t4 703 does not cause a short circuit between the two areas (i.e., VDD and VDDM). The implementation of the timing diagram 700 is described below with reference to Fig. 9 reveals.

[0044] Fig. Figure 9 shows an embodiment of the state latch 118 of the mains switch control circuit 100 of Fig. 2, which are shown in the time sequence diagram 700. Fig. 7 is linked. The same reference symbols are used for identical parts, as in Fig. 1. In this embodiment, the state latch 118 of the mains switch control circuit 100 includes the AND gate 601, the AND gate 802, the NOR gate 304, the inverter 306, the AND gate 607, the AND gate 808, the NOR gate 310, and the NOR gate 312. As discussed below, the AND gates 802 and 808 are the ones described above in conjunction with the Fig. 4 and Fig. 7 discussed AND gates 302, 308 similarly, although AND gates 802, 808 each have three inputs.

[0045] The cross-coupled NOR gate 304 and NOR gate 310 act as a flip-flop for state latch 118. Specifically, the output (i.e., the signal SEL_VMAX2) of the level shifter 116 is fed to NOR gate 304 at the set input 120 of state latch 118. The other two input signals to NOR gate 304 are the output of NAND gate 802 and the output of NAND gate 601. One output of NOR gate 304 is fed to inverter 306. The output of inverter 306 at the first output 128 of state latch 118 is a signal ON_GM. The ON_GM signal is further fed back to the first input of AND gate 802. The ON_GDB signal at node 162 is fed to a second input (i.e., the second feedback input 126 of state latch 118) of the AND gate 802. The SDB_VMAX2 signal is fed back to a third input of the AND gate 802. In other words, the three input signals of the AND gate 802 are the ON_GM signal, the ON_GDB signal, and the SDB_VMAX2 signal.The ON_GDB signal, together with the SD_VMAX2 signal, is fed to the AND gate 601. Feeding the ON_GDB signal back to the AND gate 601 forms part of a third loop 816.

[0046] On the other hand, the output of inverter 136 is fed to NOR gate 310 at the reset input 122 of state latch 118. The other two input signals of NOR gate 310 are the output of NAND gate 808 and the output of NAND gate 607. One output of NOR gate 310, along with the VDD-RDYB signal, is fed to NOR gate 312. The output of NOR gate 312 at the second output 130 of state latch 118 is a signal ON_GD. The ON_GD signal is further fed back to the first input of AND gate 808. The ON_GMB signal at node 148 is fed to a second input (i.e., the second feedback input 124 of state latch 118) of AND gate 808. The SDB_VMAX2 signal is fed back to a third input of the AND gate 808. In other words, the three input signals of the AND gate are the ON_GD signal, the ON_GMB signal, and the SDB_VMAX2 signal. The ON_GMB signal, together with the SD_VMAX2 signal, is fed to the AND gate 607.Feeding the ON_GMB signal back to the AND gate 607 forms another part of the third loop 816.

[0047] During a function mode, a first loop 178 can execute the "Makebefore-Break" function, as described above. During the shutdown period, as described above, the signal SDB_VMAX2 is constantly a low level (o), whereas the signal ON_GMB and the signal ON_GDB are both constantly a high level (1), as in Fig. Figure 8 shows that during the shutdown period, the first loop 178 is interrupted, preventing power noise from the ON_GDB and ON_GMB signals after shutdown wake-up. In a case where the AON-SELSRM_IN state differs from the final AON_SELSRM_IN state (i.e., the AON-SELSRM_IN state changes during the shutdown period), the third loop serves to prevent a makebefore-break action during wake-up, thus preventing unintended activation of the net headers 164 and / or 150. Since the AON-SELSRM_IN signal is allowed to change its state during shutdown, the output latch 166 is also allowed to change the state of the output signal AON-SELSRM_OUT based on the ON_GD and ON_GM signals received at the input of the output latch 166.

[0048] Fig. Figure 10 illustrates another embodiment, which is that of the one from Fig. 4A is similar, except that AND gates 302 and 308 are replaced by AND gates 902 and 908, each having a third input that receives the signal SDB_VMAX2. Since the signal SDB_VMAX2 is low during shutdown, both the first loop 178 and the second loop 314 are switched off during shutdown. Accordingly, in this embodiment, Fig. 10 the ON_GD and ON_GM signals continue to indicate the output latch state, as in the embodiment from Fig. 9 shown.

[0049] Fig. Figure 11 is a flowchart illustrating an example of Method 900 for operating header switches of a storage device such as the one described in Fig.The device shown in Figure 10 represents the following. A power range selection signal with a first voltage level, such as the first power range VDD, is received in step 910, and the selection signal is level-shifted to a higher voltage level, such as the third power range VMAX2, in step 912. In some examples, this is achieved by the level shifter 116. The control signals ON_GD, ON_DM are output in the third power range VMAX2 at the first and second header switches 164 and 150, respectively, to selectively couple a memory arrangement 183 to a first or second power supply, respectively, in response to the selection signal during a service period in step 914. In step 916, the control signals in the third power range VMAX2 are output to the first and second header switches to disconnect the memory arrangement from both the first and second power supplies during a shutdown period.The first and second control signals are latched during the operating period in step 918.

[0050] According to the invention, a power switch control circuit comprises a supply rail configured to supply power to a storage arrangement, a first header switch for coupling the supply rail to a first power supply corresponding to a first power range, a second header switch for coupling the supply rail to a second power supply corresponding to a second power range, and a control circuit configured to receive a selection signal and a shutdown signal and to output control signals to the first and second header switches in order to selectively couple the first and second header switches to the first and second power supplies respectively in response to the selection signal and the shutdown signal.The control circuit is configured to output control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and independently of the selection signal, wherein the control signals comprise first and second control signals, respectively, to control the first and second header switches, and wherein the power switch control circuit further comprises: a first latch circuit configured to receive the selection signal and output the first and second control signals in response to it; and wherein the power switch control circuit is configured to modify the first or second control signal output by the first latch circuit in response to the shutdown signal.

[0051] According to further embodiments of the invention, a storage device comprises a bit cell array configured for operation in a first power range or a second power range, a word line driver coupled to the bit cell array, an input / output circuit coupled to the bit cell array, and a power supply rail coupled to the bit cell array. A first header switch selectively couples the power supply rail to a first power supply corresponding to the first power range. A second header switch selectively couples the power supply rail to a second power supply corresponding to the second power range. A control circuit is configured to receive a select signal and a turn-off signal.The control circuit further includes a first latch circuit configured to output control signals to the first and second header switches to selectively couple both the first and second header switches from the first and second power supplies in response to the select and turn-off signals. A second latch circuit receives the first and second control signals and is configured to latch the select signal in response to the turn-off signal.

[0052] According to further embodiments of the invention, a method includes receiving a shutdown signal at a first power range and converting the shutdown signal to a third power range. Control signals are output at the first and second header switches in the third power range to selectively couple a memory arrangement to the first and second power supplies in response to the selection signal during an operating period. The control signals are output at the first and second header switches in the third power range to disconnect the memory arrangement from both the first and second power supplies during a shutdown period. The first and second control signals are latched during the operating period.

Claims

[1] A mains switch control circuit (100) comprising the following: a supply rail (189) configured to supply power to a storage arrangement; a first header switch (164) for coupling the supply rail (189) with a first power supply corresponding to a first power range (102); a second header switch (150) for coupling the supply rail (189) with a second power supply corresponding to a second power range; a control circuit (181) configured to receive a selection signal and a shutdown signal and to output control signals to the first and second header switches (164, 150) to selectively couple the first and second header switches (164, 150) to the first or second power supply in response to the selection signal and the shutdown signal; and wherein the control circuit (181) is configured to output the control signals to the first and second header switches (164, 150) in order to disconnect both the first and second header switches (164, 150) from the first and second power supplies in response to the shutdown signal and independently of the selection signal, wherein the control signals comprise first and second control signals for controlling the first and second header switches (164, 150) respectively, wherein the mains switch control circuit (100) further comprises the following: a first latch circuit configured to receive the selection signal and output the first and second control signals in response to it; and wherein the mains switch control circuit (100) is configured to modify the first or the second control signal output by the first latch circuit in response to the shutdown signal. [2] Mains switch control circuit (100) according to claim 1, which further comprises a level converter (112, 116) configured to receive the selection signal and the shutdown signal in the first power range (102) and to output the selection signal and the shutdown signal in a third power range (104). [3] Mains switch control circuit (100) according to claim 1 or 2, further comprising: a plurality of the first header switches (164) configured to sequentially couple the supply rail (189) to the first power supply in response to the selection signal; and a plurality of the second header switches (150), each configured to sequentially couple the supply rail (189) to the second power supply in response to the selection signal. [4] Mains switch control circuit (100) according to one of claims 1 to 3, further comprising: a first branch configured to generate the first control signal; a second branch configured to generate the second control signal; and a first feedback loop (178) wherein the first control signal is fed back to a first feedback input of the second branch, and the second control signal is fed back to a first feedback input of the first branch. [5] Mains switch control circuit (100) according to claim 4, further comprising: a second feedback loop, wherein the first control signal is fed back to a second feedback input of the first branch, and the second control signal is fed back to a second feedback input of the second branch. [6] Mains switch control circuit (100) according to claim 5, wherein the first latch circuit comprises: a first NOR gate 304 in the first branch with a first input, a second input and an output, wherein the first input is configured to receive a complementary signal to the selection signal, and wherein the output is configured to output the first control signal; a first AND gate (302) with the first and second feedback inputs of the first branch and an output coupled to the second input of the first NOR gate; a second NOR gate (310) in the second branch with a first input, a second input and an output, wherein the first input is configured to receive the selection signal, and wherein the output is configured to output the second control signal; and a second AND gate (308) with the first and second feedback inputs of the second branch and an output coupled to the second input of the second NOR gate. [7] Mains switch control circuit (100) according to claim 6, further comprising: a first NAND gate (138) with a first input configured to receive a complementary signal to the off signal, a second input configured to receive the first control signal, and an output configured to output the first control signal; a second NAND gate (152) with a first input configured to receive the complementary signal to the shutdown signal, a second input configured to receive the second control signal, and an output configured to output the second control signal. [8] Mains switch control circuit (100) according to any one of claims 1 to 7, wherein the switch-off signal has a first state corresponding to a switch-off mode and a second state corresponding to a function mode, and wherein the mains switch control circuit (100) further comprises: a second latch circuit that receives the first and second control signals from the first latch circuit, wherein the second latch circuit is configured to store the selection signal in response to the shutdown signal in shutdown mode and to store the selection signal in response to the first and second control signals in operating mode. [9] Mains switch control circuit (100) according to claim 6, further comprising: a third AND gate (601) with a first input configured to receive the complementary signal to the selection signal, a second input configured to receive the turn-off signal, and an output coupled to the first input of the first NOR gate 304; a second NOR gate (310) in the second branch with a first input, a second input and an output, wherein the first input is configured to receive the selection signal, and the output is configured to output the second control signal; and a fourth AND gate (607) with a first input configured to receive the selection signal, a second input configured to receive the shutdown signal, and an output coupled to the first input of the second NOR gate (310). [10] Mains switch control circuit (100) according to claim 6, further comprising: a third AND gate (601) with a first input configured to receive a complementary signal to the second control signal, a second input configured to receive the shutdown signal, and an output that is coupled to a third input of the first NOR gate 304; a fourth AND gate (607) with a first input configured to receive a complementary signal to the first control signal, a second input configured to receive the shutdown signal, and an output coupled to a third input of the second NOR gate 310. [11] Mains switch control circuit (100) according to claim 6, wherein the first AND gate 302 has a third input configured to receive the shutdown signal, and the second AND gate 308 has a third input configured to receive the shutdown signal. [12] Storage device (10) comprising the following: a bit cell arrangement (183) configured to operate in a first power range (102) or a second power range; a word line driver coupled to the bit cell arrangement (183); an input / output circuit coupled to the bit cell arrangement (183); a power supply rail (189) coupled to the bit cell arrangement (183); a first header switch (164) for coupling the supply rail (189) with a first power supply corresponding to the first power range (102); a second header switch (150) for coupling the supply rail (189) with a second power supply corresponding to the second power range; a control circuit (181) configured to receive a selection signal and a shutdown signal, the control circuit (181) comprising the following: a first latch circuit configured to output control signals to the first and second header switches (164, 150) to selectively couple the first and second header switches (164, 150) to the first or second power supply in response to the select signal and the turn-off signal; and a second latch circuit that receives the first and second control signals and is configured to store the selection signal in response to the shutdown signal. [13] Storage device (10) according to claim 12, wherein the first latch circuit is configured to output the control signals to the first and second header switches (164, 150) in order to disconnect both the first and second header switches (164, 150) from the first and second power supplies in response to the shutdown signal and independently of the selection signal. [14] Storage device (10) according to claim 12 or 13, wherein the first latch circuit is configured to store the selection signal in response to the shutdown signal and the selection signal. [15] Storage device (10) according to one of claims 12 to 14, which further comprises a level converter (112, 116) configured to receive the selection signal and the shutdown signal in the first power range (102) and to output the selection signal and the shutdown signal in a third power range (104). [16] Storage device (10) according to one of claims 12 to 15, wherein the second latch circuit is configured to output the latched selection signal in the first power range (102). [17] Method comprising the following: Receiving a power range selection signal at a first voltage level; Converting the selection signal to a higher voltage level; Outputting control signals at the higher voltage level to a first and a second header switch (164. 150) to selectively couple a memory arrangement to a first or a second power supply in response to the selection signal during a period of operation; Outputting the control signals at the higher voltage level to the first and second header switches (164, 150) to disconnect the memory arrangement from both the first and second power supplies during a shutdown period; and Latching of the first and second control signals during the operating period. [18] Method according to claim 17, wherein the first and the second control signal are latched during the operating period by a first latch circuit, wherein the method further comprises latching the selection signal at the first voltage level by a second latch circuit. [19] Method according to claim 17 or 18, further comprising varying the latched selection signal in response to fluctuations in the received selection signal during the shutdown mode.

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