Metallization process for a semiconductor wafer

Abstract

Metallisation process for a semiconductor wafer (10) comprising at least the steps: - Providing a semiconductor disk (10) with a top (10.1), a bottom (10.2) and comprising several solar cell stacks (12), - wherein each solar cell stack (12) comprises a Ge substrate (14) forming the underside (10.2) of the semiconductor disk, a Ge subcell (16) and at least two III-V subcells (18, 20) in the aforementioned order, and at least one through-hole (22) extending from the top (10.1) to the bottom (10.2) of the semiconductor disk (10) with a continuous side wall (22.1) and an oval perimeter in cross-section, - selective application of a photoresist layer (30) as a varnish pattern by means of a printing process on the top (10.1) or on the bottom (10.2) or on the top and bottom (10.1, 10.2) of the semiconductor disk (10), - application of a metal layer (32) over a wide area to the top surface (10.1) or bottom surface (10.2) coated with photoresist layer (30) in exposed areas, on the side wall of the passage opening (22) and on the photoresist layer (30), - Detachment of the lacquer pattern with the part of the metal layer (32) located on it from the semiconductor disk (10), - wherein, after the application of the photoresist layer (30) and before the application of the metal layer (32), the photoresist layer (30) is finely structured using a photolithographic process.

Description

[0001] The invention relates to a metallization method for a semiconductor wafer.

[0002] Various processes are known for metallizing semiconductor wafers. The desired metal structure is created, for example, using a resist mask made of positive or negative resist, with the metal being applied over a large area, e.g., by physical vapor deposition. Alternatively, printing processes are used, such as screen printing or dispensing heads, which directly apply only the desired metal structure.

[0003] To reduce shading of the front side of a solar cell, it is possible to connect the front side to the back side using a through-hole contact. Such solar cells are also called metal wrap-through (MWT) solar cells.

[0004] In addition to different manufacturing processes for the through-contact opening, different metallization processes are also known, in particular to achieve reliable metallization in the area of ​​the through-contact opening.

[0005] From “The Metal Wrap Through Solar Cell - Development and Characterization”, F. Clement, Dissertation, February 2009, a manufacturing process for a MWT simple solar cell made of multicrystalline silicon is known, in which the through contact openings are created by means of a UV laser or an IR laser in an mc Si substrate layer.

[0006] Only then is an emitter layer created by phosphorus diffusion along the top surface, the side surfaces of the via opening, and the bottom of the solar cell. The via opening is filled with a conductive via paste, e.g., a silver paste, using screen printing.

[0007] From “III-V multi-junction metal-wrap-through (MWT) concentrator solar cells,” E. Oliva et al., Proceedings, 32 nd European PV Solar Energy Conference and Exhibition, Munich, 2016, pp. 1367-1371, an inverted-growth GaInP / AlGaAs solar cell structure with vias is known. The solar cell structure with the pn junctions is grown epitaxially, and only then are the vias created by dry etching. One side surface of the via is then coated with an insulating layer, and the via is then electroplated with copper.

[0008] From US 9 680 035 B1, a solar cell stack comprising a plurality of III-V sub-cells on a GaAs substrate with a back-contacted front side is known, wherein in a first variant a hole extending through the solar cell stack and the thinned substrate and in a second variant a hole extending from the top side of the solar cell through the sub-cells into a not yet thinned substrate layer is produced by means of a wet-chemical etching process.

[0009] The etching process is based on the fact that the etching rates do not differ significantly, at least for the different III-V materials used in the solar cell stack. In the second variant, the hole is first opened by thinning the substrate layer downwards. Passivation and metallization of the front side and the hole are performed before thinning the substrate layer.

[0010] Further methods for producing through-hole connections in solar cells are known from US 2008 / 0 185 038 A1, DE 10 2010 060 303 A1, US 6 235 982 B1 and US 2014 / 0 199 806 A1.

[0011] Against this background, the object of the invention is to provide a device that further develops the state of the art.

[0012] The object is achieved by a method having the features of patent claim 1. Advantageous embodiments of the invention are the subject of subclaims.

[0013] According to the subject matter of the invention, a metallization method for a semiconductor wafer is provided, comprising at least the steps: - Providing a semiconductor wafer having a top side, a bottom side and comprising a plurality of solar cell stacks, each solar cell stack comprising a Ge substrate forming the bottom side of the semiconductor wafer, a Ge sub-cell and at least two III-V sub-cells in the order mentioned, as well as at least one through-opening extending from the top side to the bottom side of the semiconductor wafer with a continuous side wall and a circumference which is oval in cross section, - regional application of a resist layer as a resist pattern by means of a printing process on the top side or on the underside of the semiconductor wafer or on both the top side and the underside of the semiconductor wafer, - application of a metal layer to exposed areas of the surface of the semiconductor wafer coated with the photoresist layer and to the resist layer, - Detaching the resist pattern with the part of the metal layer thereon from the semiconductor wafer, wherein after the application of the photoresist layer and before the application of the metal layer, the photoresist layer is finely structured by means of a photolithographic process.

[0014] It is understood that the individual sub-cells of the solar cell stacks each have a pn junction and that the layers following the substrate are epitaxially produced on top of one another and / or connected to one another by means of a wafer bonding process.

[0015] Furthermore, it is understood that a Ge subcell comprises germanium or consists of germanium, whereby a layer consisting of germanium may also contain, in addition to the germanium, further substances, in particular dopants, but also impurities.

[0016] The same applies to the III-V subcells, which contain one or more materials from the III and V main groups or consist of such materials.

[0017] Using the printing process, the resist layer is applied particularly easily, quickly, reliably, precisely, and reproducibly. In particular, the process enables the reliable occlusion of vias, for example.

[0018] An advantage of the method is therefore that, by means of a surface application of the metallization, a reliable metallization of the through openings, i.e. in particular the side surfaces of the through opening, as well as a surface of the semiconductor wafer, i.e. the top side and / or the bottom side, is possible in one step.

[0019] The metallization process is therefore particularly cost-effective and reliable.

[0020] The more coherent the paint pattern is, i.e. the fewer individual, unconnected sections the paint pattern consists of, the easier and faster the removal process is.

[0021] After the photoresist layer has been applied and before the metal layer has been applied, the photoresist layer is finely structured using a photolithographic process.

[0022] In other words, after coarse structuring, i.e., the application of the photoresist layer in certain areas using a printing process, a second structuring, i.e., fine structuring, is performed using a photolithographic process before the metal layer is applied. This allows even fine structures in a range of a few µm to be produced reliably and reproducibly. It goes without saying that the resist is a photostructurable resist.

[0023] In one embodiment, the photoresist layer is formed as a negative resist layer or as a positive resist layer, wherein the resist pattern is formed in each case as an inverse of a conductor track plan.

[0024] In another embodiment, the resist layer omits the through-holes. This ensures reliable coating of the side surfaces of the through-holes during subsequent metallization.

[0025] According to another embodiment, the semiconductor wafer provided has separating trenches, wherein the resist layer is applied to a surface of the separating trenches.

[0026] In a further development, the printing process is an inkjet process. It has been shown that a varnish pattern can be produced particularly reliably and precisely using an inkjet process.

[0027] In another embodiment, the through openings of the provided semiconductor wafer have a first diameter of at most 1 mm and at least 300 µm or at least 400 µm or at least 450 µm at an edge adjacent to the top side of the semiconductor wafer.

[0028] At an edge adjacent to the underside of the semiconductor wafer, a second diameter of not more than 500 µm and of at least 50 µm or at least 100 µm.

[0029] Preferably, the semiconductor wafer provided has a total thickness of at most 300 µm and of at least 90 µm or of at least 150 µm or of at least 200 µm.

[0030] According to a further embodiment, the resist pattern has at least one auxiliary section extending to an edge of the semiconductor wafer, wherein the removal of the resist layer is started with the auxiliary section.

[0031] In a further embodiment, the resist pattern on the underside of the semiconductor wafer and / or on the top side of the semiconductor wafer is formed contiguously at least in the region of each individual solar cell stack or across several solar cell stacks or across the entire underside of the semiconductor wafer.

[0032] According to another embodiment, the semiconductor wafer provided has a dielectric insulation layer covering the side wall of the through-opening as well as a region of the top side of the semiconductor wafer adjacent to the through-opening and a region of the bottom side of the semiconductor wafer adjacent to the through-opening.

[0033] In a further embodiment, the method is performed first on the underside and then on the top side of the semiconductor wafer. Thus, the underside of the semiconductor wafer is metallized first according to the method.

[0034] Only after the process, ie the processes of coating, metal application and stripping of the coating layer, has been completely carried out for the underside, the process is applied to the top side of the same semiconductor wafer.

[0035] Alternatively, the metallization of the top side is produced using process steps that differ from the process.

[0036] Alternatively, the process is always carried out alternately for the top and bottom of the semiconductor wafer, ie each process step is carried out first for the top then for the bottom or vice versa, before the next process step follows accordingly.

[0037] Alternatively, the process is first applied completely to the top side of the semiconductor wafer and then to the underside of the semiconductor wafer.

[0038] The invention will be explained in more detail below with reference to the drawings. Similar parts are labeled with identical designations. The illustrated embodiments are highly schematic, ie the distances and the lateral and vertical extensions are not to scale and, unless otherwise stated, do not have any deducible geometric relationships to one another. Fig. 1 a plan view of a semiconductor wafer, Fig. 2 a rear view of a solar cell stack back metallized according to the metallization process, Fig. 3 shows a sequence according to a first embodiment of the metallization method according to the invention, Fig. 4 shows a cross-section of a through-hole of a semiconductor wafer after the application of the photoresist layer on the top and bottom sides, Fig. 5 a cross-section of a through-hole of a semiconductor wafer after stripping the photoresist layer from the top and bottom sides, Fig. 6 a cross-section of a through-hole of a semiconductor wafer after application of the photoresist layer on the underside, Fig. 7 a cross-section of a through-hole of a semiconductor wafer after removal of the photoresist layer from the underside.

[0039] The images of the Fig. 1 and Fig. 2 show a top view and a rear side section of a semiconductor wafer 10 with a photoresist layer 30 applied according to the method.

[0040] The semiconductor wafer 10 has a top side 10.1, a bottom side 10.2 and a plurality of solar cell stacks 12, wherein each solar cell stack 12 has a Ge substrate 14 forming the bottom side 10.1, a Ge subcell 16, a first III-V subcell 18 and a second III-V subcell 20 forming the top side 10.1.

[0041] Each solar cell stack 12 also has two through openings 22 extending from the top side 10.1 to the bottom side 10.2.

[0042] On the upper side 10.1 of the semiconductor wafer 10, in this case on the second III-V subcell 20, a photoresist layer 30 is applied as a resist pattern, wherein the resist pattern leaves out an area around the through-openings 22 as well as several linear areas for contact fingers and a busbar connecting the through-openings 22 and the contact fingers per solar cell stack 12.

[0043] In this case, the photoresist layer 30 extends to the edges of each solar cell stack and is connected across all solar cell stacks 12 of the semiconductor wafer 10.

[0044] The photoresist layer 30, i.e. the resist pattern, also extends flatly up to an edge of the semiconductor wafer 10, so that the entire photoresist layer 30 can be removed again in a continuous manner from the upper side 10.1 of the semiconductor wafer 10 across the individual solar cell stacks.

[0045] On the back side 10.2 of the semiconductor wafer, i.e., the Ge substrate 14, the resist pattern of the photoresist layer 30 has a region surrounding the through-holes for each solar cell stack, as well as connecting bridges extending to the edge of the individual solar cell stack. In other words, the through-holes are left out.

[0046] The connecting webs of adjacent solar cell stacks are connected to each other so that the resist pattern has a coherent structure at least along each row of solar cell stacks and can therefore be removed again in a coherent manner.

[0047] In a further development not shown, the connecting webs at the end of a row of solar cell stacks are connected to an auxiliary section extending to the edge of the semiconductor wafer, so that they can be detached more easily from the edge.

[0048] In the illustration of the Fig. Figure 3 illustrates a sequence of a metallization process for a semiconductor wafer 10 according to a first embodiment of the invention. The individual process steps are applied to both the top and bottom sides of the semiconductor wafer.

[0049] The semiconductor wafer 10 with a total layer thickness H1 is provided.

[0050] A photoresist layer 30 is applied as a resist pattern to the top side 10.1 and the bottom side 10.2 of the semiconductor wafer 10 using a printing process. The photoresist layer 30 is thus applied only in certain regions.

[0051] Subsequently, a metal layer 32 is applied to the top side 10.1 and the bottom side 10.2 of the semiconductor wafer 10.

[0052] The metal layer 32 thus covers both the photoresist layer 30 and the exposed regions of the top side 10.1 and the bottom side 10.2 of the semiconductor wafer 10 that are not covered by the photoresist layer 30.

[0053] In a subsequent process step, the photoresist layer 30 is removed together with the portion of the metal layer 32 located on the photoresist layer 30. A residual structure of the metal layer 32 remains on the top side 10.1 and the bottom side 10.2 of the semiconductor wafer 10, wherein the residual structure is a negative of the resist pattern.

[0054] Alternatively, and not explicitly shown here, the method steps are applied only to the top side or only to the bottom side, while the other surface of the semiconductor wafer remains unchanged. According to another alternative embodiment, also not shown here, the method is first carried out completely on one of the surfaces of the semiconductor wafer, i.e., the bottom side or the top side, while the other surface remains unchanged. The method is then applied to the still unchanged surface.

[0055] In the illustration of the Fig. 4 shows a cross section of a through-hole 22 of a semiconductor wafer 10 after the application of the photoresist layer 30. In the following, only the differences to the illustration of the Fig. 3 explained.

[0056] The through-opening 22 has a continuous side wall 22.1 and a circumference which is oval in cross-section, a first diameter D1 at the top side 10.1 of the semiconductor wafer 10 and a second diameter D2 at the bottom side 10.2 of the semiconductor wafer 10.

[0057] The side wall 22.1 of the through-opening 22 as well as a region of the top side 10.1 adjacent to the through-opening 22 and a region of the bottom side 10.1 of the semiconductor wafer 10 adjacent to the through-opening 22 are coated with a dielectric insulation layer 24.

[0058] The photoresist layer 30 on the top side 10.1 has a distance A1 to an edge of the through-opening 22 and on the bottom side 10.2 a distance A2 to an edge of the through-opening 22.

[0059] Here, the distance A1 is so large that the photoresist layer 30 on the top side 10.1 of the semiconductor wafer 10 is spaced from the dielectric insulation layer 24. In other words: the through holes are left out of the photoresist layer 30 during application.

[0060] The distance A2 is smaller than the distance A1 and is selected such that the photoresist layer 30 on the underside 10.1 of the semiconductor wafer 10 also extends over an edge region of the dielectric insulation layer 24.

[0061] In the illustration of the Fig. Figure 5 shows a cross section of a through-hole 22 of a semiconductor wafer 10 after the application of the metal layer 32 and after the removal of the photoresist layer 30, i.e. the resist pattern. Only the differences to the illustration of the Fig. 4 explained.

[0062] The metal layer 32 remaining after the removal of the resist pattern extends over the side wall 22.1 of the through-opening 22 as well as over a part of the dielectric insulation layer 24 on the underside 10.2 of the semiconductor wafer 10. The metal layer 32 is thus spaced from the exposed, non-insulated surface of the underside 10.2 of the semiconductor wafer.

[0063] On the top side 10.2, the metal layer 32 extends over the dielectric insulation layer 24 to an exposed region of the top side 10.1 of the semiconductor wafer adjacent to the dielectric insulation layer 24. The metal layer 32 is thus firmly bonded to both the dielectric insulation layer 24 and an exposed surface region of the semiconductor wafer, here the second III-V subcell 20.

[0064] In the illustrations of the Fig. 6 and Fig. 7 shows a further embodiment of the method according to the invention, in which only the differences to the Fig. 3 to 6 are explained.

[0065] The process is applied to the underside 10.1 of the semiconductor wafer. Fig. 6 shows a cross section of one of the through openings 22 of the semiconductor wafer 10 after the application of the photoresist layer 30 on the underside, while the upper side 10.2 remains unchanged, i.e. in particular without the photoresist layer 30.

[0066] In the illustration of the Fig. Figure 7 shows a cross-section of the through-opening 22 of the semiconductor wafer 10 after the application of the metal layer 32 to the underside 10.2 and the removal of the photoresist layer 30 from the underside 10.2, i.e., the resist pattern. The remaining metal layer 32 covers a portion of the underside 10.2, in particular a region formed by the insulation layer 24 around the through-opening 22 and a region of the sidewall 22.1 of the through-opening adjacent to the underside 10.2. The top side 10.1 of the semiconductor wafer and a region of the sidewall 22.1 of the through-opening 22 adjacent to the top side 10.1 are not covered by the metal layer 32.

Claims

[1] Metallization method for a semiconductor wafer (10) comprising at least the steps: - Providing a semiconductor wafer (10) having a top side (10.1), a bottom side (10.2) and comprising a plurality of solar cell stacks (12), - wherein each solar cell stack (12) comprises a Ge substrate (14) forming the underside (10.2) of the semiconductor wafer, a Ge sub-cell (16) and at least two III-V sub-cells (18, 20) in the order mentioned, as well as at least one through-opening (22) extending from the top side (10.1) to the underside (10.2) of the semiconductor wafer (10) with a continuous side wall (22.1) and a circumference which is oval in cross-section, - applying a photoresist layer (30) as a resist pattern by means of a printing process on the top side (10.1) or on the underside (10.2) or on the top and underside (10.1, 10.2) of the semiconductor wafer (10), - applying a metal layer (32) over the entire surface of the top side (10.1) or bottom side (10.2) coated with a photoresist layer (30) in exposed areas, on the side wall of the through-opening (22) and on the photoresist layer (30), - detaching the resist pattern with the part of the metal layer (32) located thereon from the semiconductor wafer (10), - wherein after the application of the photoresist layer (30) and before the application of the metal layer (32), the photoresist layer (30) is finely structured by means of a photolithographic process. [2] Method according to claim 1, characterized by that the photoresist layer (30) is formed as a negative resist layer or as a positive resist layer, wherein the resist pattern is formed in each case as an inverse of a conductor track plan. [3] Method according to claim 1 or 2, characterized by that the lacquer layer leaves out the through openings (22). [4] Method according to one of the preceding claims, characterized by that the printing process is an inkjet process. [5] Method according to one of the preceding claims, characterized by that the through openings (22) of the provided semiconductor wafer - have a first diameter (D1) of at most 1 mm and at least 300 µm or at least 400 µm or at least 450 µm at an edge adjacent to the upper side (10.1) of the semiconductor wafer (10) and - have a second diameter (D2) of at most 500 µm and of at least 50 µm or at least 100 µm at an edge adjacent to the underside (10.2) of the semiconductor wafer (10), wherein - the provided semiconductor wafer (10) has a total thickness (H1) of at most 300 µm and of at least 90 µm or of at least 150 µm or of at least 200 µm. [6] Method according to one of the preceding claims, characterized bythat the resist pattern has at least one auxiliary section extending to an edge of the semiconductor wafer, wherein the removal of the resist layer (30) is started with the auxiliary section. [7] Method according to one of the preceding claims, characterized by that the resist pattern on the underside (10.2) and / or the upper side (10.1) of the semiconductor wafer (10) is formed in a continuous manner at least in the region of each individual solar cell stack (12) or across several solar cell stacks (12) or across the entire underside (10.2) and / or upper side (10.1) of the semiconductor wafer (10). [8] Method according to one of the preceding claims, characterized bythat the provided semiconductor wafer (10) has a dielectric insulation layer (24) covering the side wall (22.1) of the through-opening (22) as well as a region of the top side (10.1) of the semiconductor wafer (10) adjacent to the through-opening (22) and a region of the bottom side (10.2) of the semiconductor wafer (10) adjacent to the through-opening (22). [9] Method according to one of the preceding claims, characterized by that the process is carried out first for the underside (10.2) and then for the top side (10.1) of the semiconductor wafer (10).

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