Method for manufacturing a membrane component

Abstract

Method for manufacturing a membrane component (190) with a membrane (M1), the method comprising: Providing a semiconductor disk (100) with a first layer (116), a second layer (118) and a third layer (126); Applying (12) a first masking layer (112) to the first layer (116), wherein the first masking layer (112) defines a first selectively machined surface (114) for defining a geometry of the membrane (M1); Forming (13) a first depression (120) by anisotropic etching (13) of the first layer (116); Removal of the first masking layer (112); Introducing (14) a material (122) into the first depression (120); Applying (15) a membrane layer (124) to the first layer (116) containing the introduced material (122); Applying a second masking layer, defining a second selectively editable area, to the third layer (126); Forming a second depression by anisotropic etching of the third layer (126) and the second layer (118) up to the first layer (116); Removing the second masking layer; and isotropic etching (18) of the first layer (116), wherein the isotropic etching is limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M1) is exposed; wherein the process further comprises polishing the first layer (116) with the introduced material (122) prior to applying (15) the membrane layer (124).

Description

[0001] The invention relates to a method for manufacturing a membrane component with a membrane made of a thin layer (< 1 µm) (or thin-film membrane). The membrane component can be used in microelectromechanical systems (MEMS).

[0002] Commonly known methods for producing microstructures from a semiconductor wafer (e.g., silicon wafer), such as thin-layer membranes, include wet chemical etching of silicon (or silicon dioxide - SiO2) with potassium hydroxide (KOH) and deep reactive ion etching (DRIE).

[0003] In the wet chemical etching of silicon using an alkali such as KOH, the etching reaction becomes anisotropic due to the different activation energies of the Si atoms in the various crystal planes. KOH etching of silicon wafers allows for the creation of pyramids with a square base and {111} planes as lateral faces on (100)-oriented wafers, and rectangular trenches with {111} planes as flanks on (110)-oriented wafers. Other shapes cannot be achieved using this method. In principle, precise lateral dimensions can be obtained with KOH etching due to the {111} plane acting as a natural etch stop in the silicon. However, the etching of (100)-oriented wafers, in particular, necessitates large chip dimensions due to the exclusively pyramidal etchable structure.

[0004] Reactive ion etching (DRIE), an advancement of reactive ion etching, is a highly anisotropic dry etching process for fabricating microstructures in silicon. This process can achieve feature depths of several hundred micrometers perpendicular to the wafer surface. Appropriate masking, such as that produced by photolithography, allows for the shaping of the desired structures, including circular, rectangular, or other geometries with nearly perpendicular sidewalls. Due to process variations during DRIE, the sidewalls typically exhibit a lateral angle of approximately ±2.0°. This results in a loss of the initial lithographic accuracy of the masking and the dimensional accuracy of the resulting structure.

[0005] Various methods for producing thin-film membranes are known from the prior art.

[0006] FR 2 859 281 B1 discloses a MEMS pressure sensor with a structure designed to limit excessive deformation of the diaphragm contained within the pressure sensor, thereby preventing damage to the diaphragm. The diaphragm itself is produced using standard methods, as described above (KOH etching or reactive ionic deep etching).

[0007] EP 2 132 547 B1 also discloses a MEMS pressure sensor and a method for manufacturing this pressure sensor, which, due to a rigid center on the back side of the thin-film membrane, can compensate for measurement errors when measuring low pressures. In the manufacturing process, starting from a BESOI wafer (Bonded and Etchback Silicon on Insulator), the substrate is etched on the back side, with the buried oxide layer acting as an etch stop. The resulting recess for exposing the membrane has a conically tapered inner surface. To create the rigid center, the oxide layer that previously served as the etch stop is only partially removed. A groove surrounding the area of ​​the oxide layer exposed by the recess is provided in an outer edge.

[0008] WO 2016 130123 A1 describes the fabrication of a micromechanical device with a membrane that features improved cavity structures to reduce the membrane's size. The fabrication process begins with the epitaxial layer of a silicon-on-insulator wafer (SOI wafer) being etched (reactive ionic deep etching) to create protrusions corresponding to the (reinforcing) structures of the membrane to be fabricated. The etched epitaxial layer is then bonded to an etched layer of another substrate. The etched side of this second substrate has a substantially square-shaped depression (reactive ionic deep etching) which, together with the depressions of the SOI wafer, forms the cavity beneath the membrane. Finally, the substrate layer of the SOI wafer is removed, and the back side of the second substrate is etched, allowing the cavity beneath the membrane to be connected to the surrounding environment.

[0009] EP 3 557 212 A1 discloses a capacitive MEMS pressure sensor with increased temperature resistance and its manufacture. The pressure sensor is particularly suitable for measuring air pressure during aircraft maneuvers and comprises a carrier plate with a central hole to which a membrane is attached. The (silicon) membrane is formed on both sides of a silicon wafer by etching depressions into the top and bottom surfaces of the wafer. The lateral surfaces have a conical shape that tapers towards the center of the wafer. An insulating frame is attached to the membrane, and a plate with an electrode is mounted on this frame. A cavity is enclosed between the insulating frame, the plate with the electrode, and the membrane. The membrane and the plate with the electrode form a capacitive sensor that changes its output when the membrane is deflected relative to the electrode.

[0010] US 7,487,681 B1 discloses a pressure sensor with a cross-shaped back opening that provides variable sensitivity. In the fabrication of the pressure sensor's diaphragm, the diaphragm is first structured and its back surface is exposed using DRIE (digital dermabrasion). Subsequently, another layer (also on the back surface) is bonded to the fabricated structure (wafer bonding). A through-hole is etched (DRIE) into this additional layer (frame), creating a continuous cavity beneath the diaphragm.

[0011] US 2010 / 0 006 840 A1 discloses a method for manufacturing a membrane component with a membrane, there Fig. 1A to 1F and 4A to 4E with associated description. The aforementioned method comprises... providing a semiconductor wafer (there Fig. 1A and Fig. 4D) with a first layer 1 (reference numeral from there), a second layer 2 and a third layer 11; application of a first masking layer to the first layer (there paragraph

[063] , where it can be assumed that the person skilled in the art is aware of the use of a mask, since a DRIE typically uses such a mask. The first masking layer defines a first selectively machined surface for defining a geometry of the membrane (the mask defines grooves 4 which define a membrane geometry, there Fig. 4E); a first depression is created by anisotropic etching of the first layer, there Fig. 1B to 1C formed with paragraph

[063] ; the first masking layer is removed (as is standard in etching processes); a material is introduced into the first well (there Fig. 1D); the application of a membrane layer 9 onto the first layer 1 with the introduced material (there Fig. 1F); the application of a second masking layer, defining a second selectively editable area, to the third layer 11 (there Fig. 4A with paragraph

[0075] : DRIE includes the use of a masking layer; the formation of a second well 12 by anisotropic etching of the third layer 11 and the second layer 2 up to the first layer (there 1 in Fig. 4A); the removal of the second masking layer (is a standard in etching processes); and the isotropic etching of the first layer, wherein the isotropic etching is limited by the membrane layer and by the introduced material, so that the membrane is exposed (there paragraph

[0078] with Fig. 4D and Fig. 4E).

[0012] One object of the invention is to provide a method for manufacturing a membrane component, with which a membrane component can be manufactured with a membrane having high-precision membrane dimensions and freely selectable membrane geometry.

[0013] The problem is solved by a method according to claim 1, and by a method according to claim 14.

[0014] The claimed method for manufacturing the membrane device comprises providing a semiconductor wafer with a first layer, a second layer, and a third layer, and applying a first masking layer to the first layer. The first masking layer defines a first selectively machinable area for specifying a geometry of the membrane. The method further comprises forming a first well by anisotropic etching of the first layer, removing the first masking layer, introducing material into the first well, applying a second masking layer, which defines a second selectively machinable area, to the third layer, forming a second well by anisotropic etching of the third layer and the second layer up to the first layer, removing the second masking layer, and isotropic etching of the first layer.Isotropic etching is limited by the membrane layer and the introduced material, thus exposing the membrane. The process includes polishing the first layer with the introduced material before applying the membrane layer.

[0015] The membrane component can be an unfinished semiconductor device (as a precursor or semi-finished product) or a component to be integrated into a semiconductor device. For example, in further processing steps, the membrane component can be transformed into a finished semiconductor device or further processed and then used as a component in a device such as a MEMS pressure sensor.

[0016] A (layered) material can have a (surface) surface (e.g., the surface of a silicon layer). A region of this surface can be a selectively machinable area. This selectively machinable area can be processed within a single process step, while the remaining surface area remains unmachined. For example, a masking layer (as an etching mask) with at least one cutout can be applied to a layer of a semiconductor wafer. An area covered by the masking layer cannot be machined. An area of ​​the layer uncovered or exposed by the cutout of the masking layer can be the selectively machinable area. This selectively machinable area can be machined by chemical ablation, such as anisotropic etching.The removal of material from the selectively machinable surface can be carried out in such a way that a depression is created in the material which has a basic shape that corresponds to the selectively machinable surface.

[0017] The membrane layer can be applied over a surface area. The membrane layer can enclose the membrane.

[0018] The membrane within the membrane layer can be exposed on both sides; in particular, the membrane is capable of vibration or can deform in a direction perpendicular to a plane spanned by a surface of the membrane.

[0019] The membrane layer, with the exception of the membrane itself, can be attached to a surface or frame and may not be vibrating.

[0020] The membrane can be permeable, in particular the membrane can be permeable to air and / or water.

[0021] The first selectively machinable area can be formed by at least one recess in the first masking layer; in particular, the selectively machinable area can be a surface of a material lying beneath the masking layer that is not covered by the masking layer.

[0022] The first masking layer can serve as an etching mask. The selectively machinable area can define a geometry (or base area) that is to be etched to a depth of the material beneath the masking layer.

[0023] The first selectively machinable surface can, for example, have the geometry of a circular ring. An area enclosed by the circular ring can define the membrane geometry of the membrane to be produced.

[0024] The first selectively editable surface can be a rectangular ring, a polygonal ring, or a non-circular ring.

[0025] The first selectively machinable surface can enclose an area that defines the membrane geometry of the membrane to be produced.

[0026] The first and / or second masking layer can comprise a photoresist, silicon dioxide or silicon nitride.

[0027] The first and / or second masking layer may include a positive varnish.

[0028] The definition of the recess in the first masking layer to define the first selectively processable area can be achieved using lithographic methods. The same can apply to the second selectively processable area.

[0029] The first and / or second masking layer may include hard masks. The hard masks may be structured using lithographic processes.

[0030] Anisotropic etching can include anisotropic reactive ion etching, in particular reactive ion deep etching.

[0031] The anisotropic etching of the first well can include a Deep Trench Isolation (DTI) process (trench etching).

[0032] The first depression can have a base area that corresponds to the first selectively workable surface.

[0033] The first depression can extend into the second layer.

[0034] The first depression can extend down to the second layer; in particular, a surface of the second layer can be exposed through the depression.

[0035] The first and / or second masking layer can be removed by stripping or plasma ashing. Stripping can involve removal with an organic solvent, sodium hydroxide, or a remover (alkaline or neutral liquids).

[0036] The introduction of the material into the first well can be carried out within the DTI process using chemical vapor deposition.

[0037] The membrane layer can include aluminum nitride; in particular, the membrane layer can consist of aluminum nitride.

[0038] The membrane layer can be a thin film. The membrane layer can be applied to the first layer, for example, by sputtering (reactive sputtering).

[0039] Isotropic etching can include wet chemical etching processes.

[0040] The process can further comprise, after removal of the second masking layer, the application of a fourth layer to the third layer, to the first layer and to at least one side wall of the second well formed by the anisotropic etching of the third and the second layer, as well as the anisotropic etching of a region of the fourth layer, wherein the region of the fourth layer contacts the first layer, up to the first layer.

[0041] The fourth layer can be applied to all side walls of the second depression created by the anisotropic etching of the third and second layers.

[0042] The fourth layer can serve as sidewall passivation or protect at least one sidewall(s) during subsequent process steps.

[0043] The fourth layer can include an oxide layer; in particular, the fourth layer can be an oxide layer.

[0044] During anisotropic etching of the fourth layer area, at least one side wall may not be affected; in particular, no removal or as little removal as possible should occur from at least one side wall.

[0045] The anisotropic etching of the fourth layer can extend down to the first layer, in particular exposing a surface of the first layer.

[0046] The polishing process in question can be a chemical-mechanical polishing process.

[0047] The first layer may comprise a different material than the second layer, in particular, it may consist of a different material altogether.

[0048] The first layer can comprise a silicon layer; in particular, the first layer can be a silicon layer.

[0049] The second layer can include an oxide layer; in particular, the second layer can be an oxide layer.

[0050] The semiconductor wafer can comprise a silicon-on-insulator (SOI) wafer. The SOI wafer can consist of three layers: a support substrate layer (handle layer), an oxide layer (BOX layer), and a device layer.

[0051] The support substrate layer of the SOI wafer can have a thickness between 200 µm and 2000 µm.

[0052] The oxide layer of the SOI wafer can have a thickness between 0.05 µm and 10.00 µm.

[0053] The device layer of the SOI wafer can have a thickness between 0.10 µm and 200.00 µm.

[0054] The first layer can have a first layer thickness that is smaller than a fourth thickness resulting from the summation of a second layer thickness of the second layer and a third layer thickness of the third layer; in particular, the ratio of the first layer thickness to the fourth thickness can be between 1:10 and 1:200, preferably between 1:50 and 1:150, more preferably 1:100.

[0055] The first layer thickness can be smaller than the third layer thickness, in particular the ratio of the first layer thickness to the third layer thickness can be between 1:8 and 1:200, preferably between 1:50 and 1:150.

[0056] The first layer can be particularly thick so that a deviation caused by anisotropic etching is smaller than a predetermined tolerance of the membrane geometry.

[0057] The fourth layer may include a passivation layer.

[0058] The first and / or second masking layer may comprise a photoresist; in particular, the first and / or second masking layer may be produced by photolithography.

[0059] The material introduced and the second layer can consist of the same material.

[0060] The membrane can have a circular, rectangular, polygonal or non-circular basic shape.

[0061] The membrane may have at least one recess, in particular the membrane may be perforated.

[0062] Isotropic etching can be performed through at least one recess in the membrane.

[0063] Another claimed method for manufacturing a membrane device comprises providing a semiconductor wafer. The semiconductor wafer comprises a first layer, a second layer, and a third layer. The method further comprises applying a first masking layer to the first layer. The first masking layer defines a selectively machinable area for specifying a geometry of the membrane.Furthermore, the process comprises anisotropic etching of the first layer and the second layer up to the third layer, removal of the first masking layer, at least partial modification of the third layer such that a layer modification extends to a depth of the third layer, removal of the first layer, removal of the second layer so that the third layer with the layer modification remains, application of a membrane layer to the third layer with the layer modification, application of a second masking layer, defining a second selectively machinable area, to the third layer, anisotropic etching of the third layer up to the layer modification, and isotropic etching of the layer modification. The isotropic etching of the layer modification is limited by the membrane layer and by the third layer, so that the membrane is exposed.

[0064] The membrane component can be a precursor to a finished component.

[0065] The process for manufacturing the membrane component can be followed by further process steps. These further process steps can take place on or at the membrane component.

[0066] The membrane component can be integrated particularly into MEM systems.

[0067] The membrane layer can be applied over a flat area. The membrane layer can enclose the membrane. The membrane can, in particular, be uncovered by solid material (exposed on both sides). In particular, the membrane is capable of vibration or deformation and can deform in a direction perpendicular to a plane spanned by a surface of the membrane.

[0068] The membrane layer, with the exception of the membrane itself, can be attached to another material, which can serve as a support material or frame.

[0069] The first selectively editable area can be formed by at least one cutout in the first masking layer.

[0070] The first selectively editable surface can have a circular, rectangular, polygonal, or non-circular shape.

[0071] The first and / or second masking layer can comprise a photoresist, silicon dioxide or silicon nitride.

[0072] The definition of the first cutout in the first masking layer to define the first selectively processable area and / or the definition of a (second) cutout in the second masking layer to define the second selectively processable area can be done using lithographic methods.

[0073] The process may include a LOCOS process (Local Oxidation of Silicon).

[0074] Modifying the third layer can involve thermal oxidation.

[0075] Removing the first layer may involve wet chemical etching.

[0076] Removing the second layer may also include removing material that has grown at least partially through thermal oxidation; in particular, additionally grown material from thermal oxidation may be completely removed.

[0077] The semiconductor disk can comprise a silicon wafer.

[0078] The depth of the layer modification in the third layer (or the thickness of the layer modification) can be less than the thickness of the third layer; in particular, the ratio of the depth of the layer modification to the thickness of the third layer can be between 1:5 and 1:150, preferably 1:100.

[0079] The membrane may have at least one recess, in particular be perforated.

[0080] Isotropic etching can be performed through at least one recess in the membrane.

[0081] The first and / or second masking layer may include photoresist; in particular, the first and / or second masking layer may be produced by photolithography.

[0082] Embodiments of the invention are illustrated by means of examples, but not in a way that transfers or implies limitations from the figures into the claims. Identical reference numerals in the figures denote identical elements. Fig. Figure 1 shows schematic representations 11, 12, ..., 15 of a prestructuring of an SOI wafer 100 in different stages of the prestructuring of the SOI wafer 100 and an application of a continuous membrane layer 124, each shown in cut view, for the production of a membrane component 190; Fig. Figure 2 shows schematic representations 15, 17, 18 of the membrane component fabrication from the prestructured SOL wafer with a continuously applied membrane layer 124 in different stages of fabrication, each shown in a cutaway view; Fig. Figure 3 shows schematic representations 15', 17', 18' of the membrane component fabrication of a pre-structured SOI wafer with an intermittently applied membrane layer 124' in various stages of fabrication, each shown in a cutaway view; Fig. Figure 4 shows schematic representations 41, 42, ..., 46 of a prestructuring of a silicon wafer by means of local oxidation in different stages of the prestructuring of the silicon wafer and a deposition of a continuous membrane layer 224 for the fabrication of a membrane device 290, each shown in cutaway view; Fig. Figure 5 shows schematic representations 46, 47, 48 of a membrane component fabrication of the silicon wafer prestructured by local oxidation with a continuously applied membrane layer 224 in different stages of the membrane component fabrication, each shown in a cutaway view; Fig. Figure 6 shows schematic representations 46', 47', 48' of a membrane fabrication of a silicon wafer prestructured by local oxidation with an interrupted membrane layer 224' in different stages of fabrication, each shown in a cutaway view; Fig. Figure 7 shows schematic representations of membrane geometries from a top view; Fig. Figure 8 shows a schematic representation of the membrane component 190 in a cut view and a detailed excerpt of the membrane component; Fig. Figure 9 shows a schematic representation of the membrane component 290 in a cut view and a detail excerpt of the membrane component.

[0083] Fig. Figure 1 shows a prestructuring of an SOI wafer 100 in various stages of prestructuring the SOI wafer 100 and an application of a continuous membrane layer 124, each shown in cut view, for the production of a membrane component 190.

[0084] Section 11 shows the semiconductor wafer 100 as it can be provided to a process for manufacturing the membrane device 190. The semiconductor wafer comprises three layers: a first layer 116, a second layer 118, and a third layer 126.

[0085] The first layer 116 has a first layer thickness d1, the second layer 118 a layer thickness d2, and the third layer 126 a layer thickness d3. A fourth thickness d4 results from the sum of the layer thicknesses d2 and d3.

[0086] The semiconductor wafer 100 can be an SOI wafer. Accordingly, the first layer 116 can be a (thin) silicon layer, the second layer 118 a (thin) oxide layer (BOX), and the third layer 126 a silicon substrate layer.

[0087] Section 12 shows the semiconductor disk 100 with an additionally applied masking layer 112. The masking layer 112 has a recess.

[0088] The recess may preferably have a ring-shaped base form.

[0089] The example shown depicts a ring-shaped recess. The depicted depressions are connected to each other as sections of the recess.

[0090] The first masking layer 112 can be produced using photolithographic methods and serve as an etching mask.

[0091] The masking layer 112 can include a photoresist. The photoresist can be applied by rotary coating.

[0092] The cutout in the masking layer 112 can be removed, for example, by means of development or exposure (positive varnish).

[0093] The cutout in the first masking layer 112 exposes a first selectively machinable surface 114 on the first layer 116. A surface of the first layer 116, with the exception of surface 114, is covered by the masking layer 112.

[0094] Section 13 shows the semiconductor disk 100 after anisotropic etching (in a z-direction) of the first layer 116.

[0095] Anisotropic etching of the first layer can include trench etching by reactive ionic deep etching.

[0096] The anisotropic etching can proceed section by section through the entire thickness of the first layer 116 (in the z-direction) and at least partially through the second layer 118. Preferably, the anisotropic etching can be stopped when a surface of the second layer 118 is exposed, without leaving any residue of the first layer 116 on the exposed surface of the second layer 118. The first depression 120 shown can thus be formed by the anisotropic etching.

[0097] The recess 120 has a basic shape that corresponds (essentially) to the first selectively editable surface 114.

[0098] Section 14 shows the semiconductor disk 100 without the masking layer 112 and with a material 122 placed in the recess 120.

[0099] The first masking layer 112 can be removed, for example, if the masking layer includes a photoresist, by means of remover (e.g. acetone, 1-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO) etc.), stripping or ashing (O2 ashing).

[0100] The introduced material 122 and the second layer 118 can both comprise an oxide material (oxide layer material).

[0101] The introduced material 122 can be introduced into the second layer 118 by means of trench isolation (thermal oxidation and filling of the trench with CVD oxide).

[0102] After the introduction of material 122, a polishing step (chemical-mechanical polishing) can follow.

[0103] Section 15 shows the semiconductor disk 100 with the additionally applied membrane layer 124.

[0104] The membrane layer 124 can be applied over a flat surface.

[0105] The membrane layer may include aluminium nitride (AlN), in particular the membrane layer may consist of aluminium nitride.

[0106] The membrane layer can be applied using physical deposition processes (PVD), sputtering, or metal-organic chemical vapor deposition (MOCVD).

[0107] Fig. Figure 2 shows the completion of the membrane component from the pre-structured SOI wafer with a continuous membrane layer 124 applied in various stages of production, each shown in a cutaway view.

[0108] Cut 15 from Fig. Figure 1 is shown again for a simplified understanding of the manufacturing process and forms the starting point for the following process steps.

[0109] Section 16 shows the pre-structured semiconductor disk 100 with a fourth layer 152, which is applied section by section to the first layer 116, to the third layer 126 and side walls of a depression in the third layer 126 and the second layer 118.

[0110] The depression in the third layer 126 and the second layer 118 can be produced by anisotropic etching of the third layer 126 and the second layer 118. The anisotropic etching of the third and second layers can be performed selectively; in particular, the geometry of the depression can be determined by prior masking or the application of a second masking layer with a recess that defines a second selectively machinable surface to the third layer 126.

[0111] The anisotropic etching can stop at the first layer 116. In particular, the anisotropic etching of the third layer 126 can be stopped when a surface of the first layer is (completely) exposed without any residue of the second layer 118 remaining on the first layer 116. Subsequently, the fourth layer 152 can be applied.

[0112] The fourth layer 152 can comprise an oxide layer; in particular, the fourth layer 152 can be an oxide layer.

[0113] The fourth layer 152 can include a passivation layer; in particular, the fourth layer 152 can be a passivation layer.

[0114] A cavity 146 is formed (enclosed) by side walls of the fourth layer 152.

[0115] Cavity 146 can have a circular base.

[0116] Section 17 shows the semiconductor wafer 100 after a further anisotropic etching step (in the z-direction) of the fourth layer 152, resulting in the cavity 142 (as a depression of the cavity 148). Only the area of ​​the fourth layer 152 that contacted the first layer 118 is etched (removed), thus exposing a surface of the first layer 116.

[0117] Section 18 shows the semiconductor disk 100 (or the membrane component 190) with the first layer 116 partially removed.

[0118] A section of the first layer 116, enclosed by the membrane layer 124 and the introduced material 122, can be removed by means of an isotropic etching step. The isotropic etching can be stopped by the membrane layer 124 and by the introduced material 122, so that a depression 142 is formed, which extends below the membrane layer 124 and to a side wall 144 (side walls) of the introduced material, thus exposing the membrane layer 124 on both sides.

[0119] The section of membrane layer 124 exposed on both sides forms a membrane M1.

[0120] Fig. Figure 3 shows the fabrication of a membrane component 190' from a pre-structured SOI wafer with an interrupted membrane layer 124' at various stages of fabrication, each shown in a cutaway view.

[0121] Sections 15' to 18' correspond in their representation essentially to section views 15 to 18 from Fig. 2, with the difference that the membrane layer 124' has a recess 150.

[0122] The membrane M1' can have a variety of recesses, in particular be perforated.

[0123] Isotropic etching of the semiconductor disk 100 to remove part of the first layer 116, as shown in 18', can be carried out through the recess 150 (front side).

[0124] Fig. Figure 4 shows a prestructuring of the semiconductor disk 200 by means of layer modification (local oxidation) in different stages of the prestructuring of the semiconductor disk 200 and an application of a continuous membrane layer 224, each shown in cut view, for the production of a membrane device 290.

[0125] Section 41 shows the semiconductor wafer 200. The semiconductor wafer 200 comprises a first layer 216, a second layer 218, and a third (support) layer 226 (silicon wafer). The third layer 226 has a layer thickness d8.

[0126] The first layer 216 can comprise a silicon layer, in particular the first layer 216 can be a silicon nitride layer.

[0127] The second layer 218 can comprise an oxide layer, in particular the second layer 218 can be a silicon dioxide layer.

[0128] Section 42 shows the semiconductor wafer 200 with a first masking layer 212. The first masking layer has a recess. The recess in the first masking layer 212 defines a first selectively machinable area 214 on the first layer 216.

[0129] The first masking layer 212 can be produced using photolithographic processes and serve as an etching mask. The masking layer 212 can comprise a photoresist.

[0130] The first selectively machinable surface 214 can in particular define a geometry of a membrane M2 yet to be produced.

[0131] Section 43 shows the semiconductor disk 200 with masking layer 212 removed and first and second layers 216,218 partially removed.

[0132] The partial or selective removal of the first and second layers 216, 218 can be carried out by means of reactive ion (deep) etching.

[0133] The anisotropic etching can proceed through the entire first layer 216 (in the z-direction) and the second layer 218. In particular, the anisotropic etching can be stopped when a surface of the third layer 226 is exposed without any residue of the second layer 218 remaining on the exposed surface of the third layer 226.

[0134] The partial removal of the first and second layers 216,218 creates the depression 220.

[0135] Section 44 shows the semiconductor disk 200 with a layer modification 222.

[0136] Layer modification 222 can be produced by local thermal oxidation of silicon.

[0137] Oxidation can also include the growth of SiO2 on silicon.

[0138] Layer modification 222 extends to a depth d7 of the third layer 226.

[0139] The depth d7 can be smaller than the layer thickness d8 of the third layer 226. The depth d7 of the layer modification 222 can be significantly smaller than the layer thickness d8 of the third layer 226; preferably, the ratio of the depth d7 to the layer thickness d8 is between 1:5 and 1:150, more preferably 1:100.

[0140] Section 45 shows the semiconductor disk 200 with the first and second layers 216,218 completely removed. The third layer 226 with embedded layer modification 222 remains.

[0141] The first layer 216 can be removed by wet chemical etching.

[0142] The first and / or the second layer 216,218 can be removed by polishing, in particular by chemical-mechanical polishing.

[0143] Polishing can be carried out up to the third layer. In particular, polishing can be stopped when no residues of the second layer 218 remain on the third layer 226.

[0144] Section 46 shows the semiconductor disk with an applied membrane layer 224.

[0145] The membrane layer can be applied over a flat area.

[0146] The membrane layer can be applied using sputtering.

[0147] The membrane layer can be a thin film. In particular, the membrane can be smaller than 1.0 µm.

[0148] The membrane layer may include aluminium nitride (AlN), in particular the membrane layer may consist of AlN.

[0149] Fig. Figure 5 shows the fabrication of the membrane component from the silicon wafer pre-structured by local layer modification with a continuous membrane layer 224 at various stages of the membrane component fabrication, each shown in a sectional view. For better understanding, section 46 is shown in Fig. 5 shown again.

[0150] Section 47 shows the semiconductor disk 200 with the third layer 226 partially removed.

[0151] Partial removal of the third layer can include prior masking of the third layer 226 with a second masking layer that defines a second selectively editable area on the third layer 226.

[0152] The second masking layer can be produced using photolithographic processes. The masking layer can include a photoresist.

[0153] The second selectively editable area can result from at least one cutout in the second masking layer.

[0154] The second selectively editable surface can define the geometry of a recess to be produced.

[0155] The partial removal of the third layer can be achieved by means of anisotropic etching (reactive ionic deep etching), resulting in a depression 248 in the third layer 226.

[0156] The anisotropic etching can stop at layer modification 222. In particular, the anisotropic etching can stop when a surface of the layer modification is exposed without any residue of the third layer 226 remaining on layer modification 222.

[0157] A basic form of the recess 248 can (essentially) correspond to the second selectively editable surface defined by the second masking layer.

[0158] Section 47 shows the semiconductor disk 200 (or membrane component 290) with layer modification 222 removed, so that part of the membrane layer 224 is exposed on both sides. The area of ​​the membrane layer 224 exposed on both sides forms the membrane M2.

[0159] The removal of layer modification 222 can be achieved by means of an isotropic etching step.

[0160] The isotropic etching can stop particularly at the membrane layer 224 and the third layer 226, so that a depression 242 is formed which extends to below the membrane layer 224 and exposes a side wall 244 (side walls) of the third layer 226.

[0161] Fig. Figure 6 shows the fabrication of a membrane component 290' from a silicon wafer pre-structured by local oxidation with an interrupted membrane layer 224' in various stages of fabrication, each shown in a cutaway view.

[0162] Sections 46' to 48' correspond in their representation essentially to section representations 46 to 48, with the difference that the membrane layer 224' has a recess 250.

[0163] The membrane layer 224' can have a variety of recesses, in particular be perforated.

[0164] The layer modification 222 can be removed by isotropic etching through the recess 250 (front side).

[0165] Fig. Figure 7 shows various membrane geometries of membrane components 390, 490, 590, 690 in top view. The dark gray areas each correspond to a membrane layer 324, 424, 524, 624. For better visualization of the geometries, the structural edges actually located beneath the membrane layers 324, 424, 524, 624 have been omitted as dashed lines. Instead, a sectional view AA of one of the components shown in Figure 7 is provided. Fig. 7 membrane components (membrane component 390) are shown.

[0166] Sectional view AA shows the membrane component 390 in a cutaway view. The membrane component comprises a membrane layer 324 with a membrane, a material 344 enclosed by a first layer with an exposed side wall 344, and a cavity 342.

[0167] In the top view, it can be seen that cavity 342 has a round basic shape.

[0168] Cavity 342 can have a different basic shape; for example, the cavity can have a rectangular, polygonal, or non-circular basic shape.

[0169] The introduced material 324 has a circular basic shape.

[0170] The introduced material 322 can define a geometry of a membrane in the membrane layer 324, since the introduced material 322 (and the membrane layer 322 itself) in a step to expose the membrane (cf. Fig. 2 and Fig. 3, section 18 or 18') can stop an isotropic etching process.

[0171] The depicted membrane components 390, 490, 590, 690 are identical to each other except for the geometries of the membrane.

[0172] Here, 442, 542, and 642, which are equivalent to 342, denote a (circular) cavity of the respective membrane component, and 422, 522, and 622, which are equivalent to 322, denote material enclosed by a first layer of the respective membrane component. The enclosed material 422, 522, 622, which are equivalent to 322, has an exposed side wall 444, 544, 644.

[0173] The membrane component 490 has a membrane with a hexagonal base shape.

[0174] The membrane component 590 has a membrane with a rectangular base shape. In particular, the corners of the membrane can be rounded or scalloped.

[0175] The membrane component 690 has a membrane with a sawtooth or star-shaped basic form.

[0176] The coordinates of a plane spanned by a surface of the membrane component 390,490,590,690 can be uniquely defined by an xy coordinate system.

[0177] Fig. Figure 8 shows the membrane component 190 in a cutaway view with a detail excerpt of the membrane component 190.

[0178] The detail excerpt shows a section of the introduced material 122, the first layer 116, the membrane layer 124 and the membrane M1.

[0179] An angle α1 is enclosed between the membrane layer 124 or the membrane M1 and an (exposed) side wall 144 of the enclosed material 144.

[0180] The angle α1 can be essentially 90.0°. The angle α1 can be between 88.0° and 92.0°, in particular between 89.0° and 91.0°.

[0181] The angle α1 can result from process-related deviations. Due to the angle α1, a deviation d can occur at a depth (in the z-direction starting from the membrane layer) of the semiconductor disk 100. 10 in a geometry of the introduced material 122 to the selectively machinable surface 114 previously defined by the first masking layer 112.

[0182] The deviation d 10 can be smaller than 20.0 µm, preferably smaller than 10.0 µm, even more preferably smaller than 1.0 µm.

[0183] Fig. Figure 9 shows the membrane component 290 in a cutaway view with a detail excerpt of the membrane component 290.

[0184] Cavity 242 comprises a first section 260 and a second section 264. The first section 260 has a first lateral dimension S A1 The second section 264 has a second lateral dimension S A2 on.

[0185] The first and / or the second lateral dimension S A1 ,S A2 Each can describe the diameter of a circle.

[0186] The second lateral dimension S A2 may differ from the first lateral dimension S A1 be, in particular the second lateral dimension S A2 50% smaller than the first lateral dimension S A1 preferably 30%, even more preferably 10%.

[0187] The detailed excerpt shows, section by section, the third layer 226, the membrane layer 224 and the membrane M2.

[0188] An angle α3 is enclosed between the membrane layer 224 or the membrane M2 and the side wall 244 of the third layer 226.

[0189] The angle α3 can be essentially 90.0°. The angle α3 can be between 88.0° and 92.0°, in particular between 89.0° and 91.0°.

[0190] The angle α3 can also result from process-related deviations. The angle α3 results in a (geometric) deviation d at a depth (in the z-direction starting from the membrane layer 224) of the semiconductor disk 200. 11 (compared to a lateral dimension that was determined by the selectively machinable area).

[0191] The deviation d 11 can be smaller than 20.0 µm, preferably smaller than 10.0 µm, even more preferably smaller than 1.0 µm.

Claims

[1] A method for producing a membrane component (190) with a membrane (M1), the method comprising: Providing a semiconductor wafer (100) having a first layer (116), a second layer (118) and a third layer (126); Applying (12) a first masking layer (112) to the first layer (116), wherein the first masking layer (112) defines a first selectively processable surface (114) for defining a geometry of the membrane (M1); Forming (13) a first recess (120) by anisotropic etching (13) of the first layer (116); Removing the first masking layer (112); introducing (14) a material (122) into the first recess (120); Applying (15) a membrane layer (124) to the first layer (116) with the introduced material (122); Applying a second masking layer defining a second selectively processable area to the third layer (126); Forming a second recess by anisotropic etching of the third layer (126) and the second layer (118) down to the first layer (116); Removing the second masking layer; and isotropic etching (18) of the first layer (116), wherein the isotropic etching is limited by the membrane layer (124) and by the introduced material (122) so that the membrane (M1) is exposed; wherein the method further comprises polishing the first layer (116) with the introduced material (122) prior to applying (15) the membrane layer (124). [2] The method of claim 1, wherein the method further comprises: after removing the second masking layer, applying (16) a fourth layer (152) to the third layer (126), to the first layer (116) and to at least one side wall of the second recess created by the anisotropic etching of the third (126) and the second layer (118); and anisotropic etching (17) of a region of the fourth layer (152), the region of the fourth layer (152) contacting the first layer (116), up to the first layer (116). [3] The method according to claim 1 or 2, wherein the polishing is a chemical-mechanical polishing. [4] The method of any one of claims 1 to 3, wherein the first layer (116) comprises a different material than the second layer (118). [5] The method of any one of claims 1 to 4, wherein the first layer (116) comprises a silicon layer and the second layer (118) comprises an oxide layer. [6] The method according to any one of claims 1 to 5, wherein the semiconductor wafer (100) comprises a silicon-on-insulator wafer. [7] Method according to one of claims 1 to 6, wherein the first layer (118) has a first layer thickness (d1) which is smaller than a fourth thickness (d4) which results from the summation of a second layer thickness (d2) of the second layer (118) and a third layer thickness (d3) of the third layer (126), in particular a ratio of the first layer thickness (d1) to the fourth thickness (d4) is between 1:10 and 1:200, preferably between 1:50 and 1:150, more preferably 1:

100. [8] The method of any one of claims 2 to 7, wherein the fourth layer (152) comprises a passivation layer. [9] Method according to one of claims 1 to 8, wherein the first and / or the second masking layer comprise a photoresist, in particular the first and / or the second masking layer are produced by means of photolithography. [10] Method according to one of claims 1 to 9, wherein the introduced material (122) and the second layer (118) comprise a same material. [11] Method according to one of claims 1 to 10, wherein the membrane (M1) has a circular, a rectangular, a polygonal or a non-circular basic shape. [12] Method according to one of claims 1 to 11, wherein the membrane (M1) has at least one recess (150), in particular is perforated. [13] Method according to claim 12, wherein the isotropic etching is carried out through the at least one recess (150) of the membrane (M1). [14] A method for producing a membrane component (190) with a membrane (M2), the method comprising: Providing a semiconductor wafer (200) having a first layer (216), a second layer (218) and a third layer (226); Applying (42) a first masking layer (212) to the first layer (216), wherein the first masking layer (212) defines a first selectively processable surface (214) for defining a geometry of the membrane (M2); anisotropic etching of the first layer (216) and the second layer (218) up to the third layer (226); Removing (43) the first masking layer (212); at least partially modifying (44) the third layer (226) such that a layer modification (222) extends into a depth (d7) of the third layer (226); Removing (45) the first layer (216); Removing (45) the second layer (218); Applying (46) a membrane layer (224) to the third layer (226) with the layer modification (222); Applying a second masking layer defining a second selectively processable area to the third layer (226); anisotropic etching (47) of the third layer (226) up to the layer modification (222); isotropic etching (48) of the layer modification (222), wherein the isotropic etching is limited by the membrane layer (224) and by the third layer (226) so that the membrane (M2) is exposed. [15] The method of claim 14, wherein removing (45) the first and / or second layer (216,218) comprises chemical-mechanical polishing. [16] The method of claim 14 or 15, wherein the semiconductor wafer (200) comprises a silicon wafer. [17] The method of any one of claims 14 to 16, wherein removing the first layer (216) comprises wet chemical etching. [18] Method according to one of claims 14 to 17, wherein the depth (d7) of the layer modification (222) is smaller than a layer thickness (d8) of the third layer (226), in particular a ratio of the depth (d7) of the layer modification (222) to the layer thickness (d8) of the third layer is between 1:5 and 1:150, preferably 1:

100. [19] Method according to one of claims 14 to 18, wherein the membrane (M2) has at least one recess (250), in particular is perforated. [20] Method according to claim 19, wherein the isotropic etching is carried out through the at least one recess (250) of the membrane (M2). [21] Method according to one of claims 14 to 20, wherein the first and / or the second masking layer comprise photoresist, in particular the first and / or the second masking layer are produced by means of photolithography.

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