DOUBLE DOUBT SOURCE / DRAIN REGIONS AND THEIR MANUFACTURING PROCESSES

Abstract

Procedure comprehensive: Forming a source / drain region (82) in a semiconductor fin (52); after forming the source / drain region (82), implanting (26) first impurities into the source / drain region (82); after implanting (26) the first impurities, implanting (30) second impurities into the source / drain region (82), wherein the first impurities have a lower enthalpy of formation than the second impurities; and after implanting (30) the second impurities, annealing the source / drain region (82), the first impurities contain arsenic, the second impurities contain phosphorus, and wherein the implantation of the second impurities into the source / drain region (82) includes the implantation of phosphorus dimer into the source / drain region (82).

Description

GENERAL STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements on top of them.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area.

[0003] For the state of the art, reference is made to the publications US 2018 / 0 337 234 A1, US 2018 / 0 108 654 A1, US 2019 / 0 006 363 A1, US 2018 / 0 076 326 A1 and US 2020 / 0 013 878 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. Figure 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16, Fig. 17, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 23A and Fig. Figure 23B shows cross-sectional and top views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. Figure 15D illustrates impurity concentrations in a device according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations explained.

[0006] Furthermore, spatially related terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for a more convenient description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the drawings. These spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0007] Several embodiments involve implanting two different types of dopants into a source / drain region to improve transition abruptness (e.g., reduced leakage current) and reduce source / drain contact resistance. In one embodiment, first dopants are implanted into a source / drain region, followed by the implantation of second dopants. The first dopants are a different element than the second dopants, and the first dopants may have a lower enthalpy of formation than the second dopants. The first dopant contains arsenic, and the second dopant may contain phosphorus or the like. In specific embodiments, the arsenic is implanted into the source / drain region followed by phosphorus dimer implantation (P2 implantation).Due to their lower enthalpy of formation, the first dopants are more strongly attracted to gaps in the source / drain region and form more stable bonds with them. For example, the first dopants can be used to reduce the diffusion of the second dopants and thus decrease their binding to the gaps. By reducing the diffusion of the second dopant, a higher concentration of the second dopant can be achieved in a contact area of ​​the source / drain region, thereby reducing the source / drain contact resistance. Furthermore, the use of two different elements as dopants allows for a transition with improved abruptness and lower diffusion, thus providing improved short-channel control (e.g., to address the effects of drain-induced barrier lowering (DIBL) in advanced process nodes).Different embodiments can provide one or more of the following non-restrictive advantages: improved transition abruptness, reduced diffusion of the second dopant, and reduced source / drain contact resistance.

[0008] Fig. Figure 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulation regions 56 are arranged in the substrate 50, and the fin 52 projects above and between adjacent insulation regions 56. Although the insulation regions 56 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein can refer to the semiconductor substrate only or to a semiconductor substrate including insulation regions. Additionally, the fin 52 and / or the substrate 50 can comprise a single material or multiple materials, although the fin 52 is illustrated as a single continuous material, like the substrate 50.In this context, fin 52 refers to the section that extends between the adjacent isolation regions 56.

[0009] A gate dielectric layer 92 is located along side walls and over an upper surface of the fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Fig. Figure 1 further illustrates reference cross-sections used in the following drawings. Cross-section AA is located along a longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA and is located along a longitudinal axis of the fin 52 and in a direction of, for example, current flow between the source / drain regions 82 of the FinFET. Cross-section CC is parallel to cross-section AA and extends through a source / drain region of the FinFET. For clarity, the following drawings refer to these reference cross-sections.

[0010] Some embodiments described herein are explained in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Likewise, some embodiments consider aspects used in planar devices, such as planar FETs, nanostructured field-effect transistors (NSFETs) (e.g., nanolayer, nanowire, gate-all-around, or the like), or similar devices.

[0011] The Fig. Figures 2 to 23B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. Figures 2 to 7 illustrate the reference cross-section AA, which is in Fig. Figure 1 illustrates this, with the exception of multiple fins / FinFETs. Fig. 8A, Fig. 9A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A and Fig. 23A are illustrated along the reference cross-section AA, which is in Fig. 1 is illustrated, and Fig. 8B, Fig. 9B, Fig. 10, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16, Fig. 17, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B and Fig. 23B are illustrated along a similar cross-section BB, which is in Fig. Figure 1 illustrates this, with the exception of multiple fins / FinFETs. Fig. 12B, Fig. 12C, Fig. 15B and Fig. 15C are illustrated along the reference cross-section CC, which is in Fig. 1 is illustrated, with the exception of multiple fins / FinFETs.

[0012] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, can also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a composite semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0013] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. The p-region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-region 50N can be physically separated from the p-region 50P (as illustrated by the divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P.

[0014] In Fig. 3. Fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 in the substrate 50 can be formed by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic.

[0015] The fins can be structured by any suitable method. For example, the fins 52 can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, which enables the creation of structures that, for example, have slopes smaller than what can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins. In some embodiments, the mask (or another layer) can remain on the fins 52.

[0016] In Fig. 4 An insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be produced by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. An annealing process can be performed after the insulating material has been formed.In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a lining (not shown) can first be formed along a surface of the substrate 50 and the fins 52. Then, a filler material, such as those described previously, can be formed over the lining.

[0017] In Fig. 5. A removal process is applied to the insulation material 54 to remove excess insulation material 54 above the fins 52. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the fins 52 so that the upper surfaces of the fins 52 and the insulation material 54 are at the same level after the planarization process is complete. In some embodiments where a mask remains on the fins 52, the planarization process may expose or remove the mask so that, respectively, the upper surfaces of the mask or the fins 52 and the insulation material 54 are at the same level after the planarization process is complete.

[0018] In Fig. In Figure 6, the insulation material 54 is recessed to form shallow trench isolation regions (STI regions) 56. The insulation material 54 is recessed such that the upper portions of the fins 52 project between adjacent STI regions 56 in the n-region 50N and the p-region 50P. Furthermore, the upper surfaces of the STI regions 56 can have a flat surface, as illustrated, a convex surface, a concave surface (such as molding), or a combination thereof. The upper surfaces of the STI regions 56 can be formed as flat, convex, and / or concave by suitable etching. The STI regions 56 can be spared using an acceptable etching process, such as an etching process that is selective with respect to the material of the insulating material 54 (i.e., etching the insulating material 54 at a faster rate than the fin material 52).For example, oxide removal can be carried out using, for example, dilute hydrofluoric acid (dHF).

[0019] Regarding Fig. The process described in sections 2 to 6 is only one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins 52. For example, the fins 52 can be formed in Fig. In embodiments, the fins 52 can be recessed, and a material different from the fins 52 can be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 comprise the recessed material as well as the epitaxially grown material arranged over the recessed material. In yet another embodiment, a dielectric layer can be formed over an upper surface of the substrate 50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 52.In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which may eliminate the need for prior and subsequent implantations, although in situ and implantation doping can be used together.

[0020] Furthermore, it can be advantageous to epitaxially grow a material in the n-region 50N (e.g., an NMOS region) that differs from the material in the p-region 50P (e.g., a PMOS region). In various embodiments, upper sections of the fins 52 can be made of silicon germanium (Si₂). x Ge 1-x, where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming the III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0021] Furthermore, in Fig. Six suitable wells (not shown) are formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-region 50N and an N-well may be formed in the p-region 50P. In some embodiments, a P-well or an N-well is formed in both the n-region 50N and the p-region 50P.

[0022] In embodiments with different well types, the various implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist and / or other masks (not shown). For example, a photoresist can be formed over the fins 52 and the STI regions 56 in the n-region 50N. The photoresist is patterned to expose the p-region 50P of the substrate 50. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, n-impurity implantation is performed in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-impurities from being implanted into the n-region 50N. The n-impurities are arsenic, present in the region at a concentration of 10 18 cm -3 or less, such as between approximately 1016 cm -3 and approximately 10 18 cm -3 , can be implanted. After implantation, the photoresist is removed, for example by an acceptable ashing process.

[0023] Following the implantation of the p-region 50P, a photoresist is formed over the fins 52 and the STI regions 56 in the p-region 50P. The photoresist is patterned to expose the n-region 50N of the substrate 50. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, a p-impurity implantation can be performed in the n-region 50N, and the photoresist can act as a mask to essentially prevent p-impurities from being implanted into the p-region 50P. The p-impurities can be boron, boron fluoride, indium, or the like, present in the region at a concentration of 1018 cm-3 or less, such as between approximately 10 16 cm -3 and approximately 10 18 cm -3 , are implanted. After implantation, the photoresist can be removed, for example by an acceptable ashing process.

[0024] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair the implantation damage and activate the implanted p- and / or n-impurities. In some embodiments, the grown epitaxial fin materials can be doped in situ during growth, which may eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0025] In Fig. 7. A dummy dielectric layer 60 is formed on the fins 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized, for example, by a CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 62 can be made from other materials with high etch selectivity from etching insulating regions, such as the STI regions 56 and / or the dummy dielectric layer 60. The mask layer 64 can have one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the n-region 50N and the p-region 50P. Note that, for illustrative purposes, the dummy dielectric layer 60 is shown covering only the fins 52.In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI regions 56, extending over the STI regions and between the dummy gate layer 62 and the STI regions 56.

[0026] The Fig. Figures 8A to 16B illustrate various additional steps in the manufacture of embodiment devices. Fig. Figures 8A to 16B illustrate features in each of the n-region 50N and the p-region 50P. For example, the structures that are in Fig. Figures 8A to 16B illustrate the principles that apply to both the n-region 50N and the p-region 50P. Any differences (if any) between the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0027] In Fig. 8A and Fig. 8B can be used for mask layer 64 (see Fig. 7) can be structured using acceptable photolithography and etching techniques to form masks 74. The structure of the masks 74 can then be transferred to the dummy gate layer 62. In some embodiments (not illustrated), the structure of the masks 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The structure of the masks 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective epitaxial fins 52.

[0028] Furthermore, in Fig. 8A and Fig. 8B Gate sealing spacers 80 may be formed on exposed surfaces of the dummy gates 72, the masks 74, and / or the fins 52. The gate sealing spacers 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacers 80 may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0029] After forming the gate seal spacers 80, implantations for lightly doped source / drain regions (LDD regions) (not explicitly illustrated) can be performed. In embodiments with different device types, similar to those previously described in Fig. Following the implantation procedure described in section 6, a mask, such as a photoresist, can be formed over the n-region 50N while the p-region 50P is exposed, and impurities of a suitable type (e.g., p-type) can be implanted into the exposed fins 52 in the p-region 50P. The mask can then be removed. The n-impurities can be any of the previously described n-impurities, and the p-impurities can be any of the previously described p-impurities. The lightly doped source / drain regions can have a contamination concentration of approximately 10 15 cm -3 up to about 10 19 cm -3exhibiting [unclear]. Tempering can be used to repair implantation damage and activate the implanted impurities.

[0030] In Fig. 9A and Fig. 9B, gate spacers 86 are formed on the gate gasket spacers 80 along the side walls of the dummy gates 72 and the masks 74. The gate spacers 86 can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

[0031] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be employed (e.g., the gate seal spacers 80 may not be etched before the formation of the gate spacers 86, resulting in "L-shaped" gate seal spacers, spacers may be formed and removed, and / or the like). Furthermore, the n- and p-devices may be formed using different structures and steps. For example, LDD regions for n-devices may be formed before the formation of the gate seal spacers 80, while the LDD regions for p-devices may be formed after the formation of the gate seal spacers 80.

[0032] In Fig. Epitaxial source / drain regions 82 are formed in the fins 52 at points 10 to 15. These regions are arranged such that each dummy gate 72 is positioned between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and through the fins 52. In other embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by a suitable lateral distance, preventing the epitaxial source / drain regions 82 from short-circuiting subsequently formed gates of the resulting FinFETs. A material of the epitaxial source / drain regions 82 can be selected to exert a load in the respective channel regions 58, thereby improving performance.

[0033] The epitaxial source / drain regions 82 in the n-region 50N can be formed separately and differ from the epitaxial source / drain regions 82 in the p-region 50P. For example, illustrate Fig. 10, Fig. 11, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A Cross-sectional views along line BB from Fig. 1 of the formation of the epitaxial source / drain regions 82 in the n-region 50N. The steps that are in Fig. The operations described in sections 10 to 15A can be performed while the p-region 50P (not explicitly illustrated) is masked. Fig. The source / drain regions of the fins 52 in the n-region 50N are structured to form recesses 20 in the fins 52. For example, the recesses 20 in the fins 52 can be located on opposite sides of the dummy gates 72 (see, e.g., Fig. 19B) are formed, such as between adjacent dummy gates 72. The structuring of the recesses 20 can be achieved, for example, by a combination of photolithography and etching. In some embodiments, the fins 52 can be etched over, so that the recesses 20 extend directly beneath the gate spacers 86.

[0034] In Fig. 11 Optional epitaxial regions 22 are grown in the recesses 20. The epitaxial regions 22 can only partially fill the recesses 20. For example, the epitaxial regions 22 can be grown to cover the sides and bottom surfaces of the recesses 20. The epitaxial regions 22 can be grown by any acceptable process and can be made of any acceptable material, such as that suitable for n-FinFETs. For example, if the fin 52 is silicon, the epitaxial regions 22 can be made of silicon, silicon carbide, silicon phosphide, or the like. In some embodiments, a material of the epitaxial regions 22 in the n-region 50N can be selected to exert a tensile stress on the channel regions 58. In some embodiments, the epitaxial regions 22 have a thickness T1 in a range of approximately 3 nm to approximately 7 nm.

[0035] The epitaxial regions 22 and / or the fins 52 can be implanted with dopants during epitaxy using an in-situ doping process. For example, initial n-impurities can flow into the deposition chamber while the epitaxial regions 22 are being grown. The first n-impurities implanted in the epitaxial regions 22 are arsenic. The epitaxial regions 22 can accommodate an impurity concentration in the range of approximately 5 × 10⁻⁶ 19 cm -3 up to approximately 2×10 20 cm -3In other embodiments, the epitaxial regions 22 may have a different impurity concentration. The impurity concentration in the epitaxial regions 22 may be constant or varied throughout the entire epitaxial regions 22. For example, the epitaxial regions 22 may have a gradient impurity concentration that increases in a direction away from the sidewalls of the fins 52 on which the epitaxial regions 22 are grown.

[0036] In Fig. 12A The epitaxial growth process can further fill remaining sections of the recesses 20 with the epitaxial regions 24a and 24b. The growth of the epitaxial regions 24a and 24b can be performed in situ (e.g., in the same chamber) as the epitaxial regions 22 and using the same process. Furthermore, the epitaxial regions 24a and 24b can be made of the same material as the epitaxial regions 22, such as silicon, silicon carbide, silicon phosphide, or the like. In some embodiments, a material of the epitaxial regions 24a and 24b in the n-region 50N can be selected to exert the same type of load (e.g., tensile stress) on the channel regions 58 as the epitaxial regions 22. In some embodiments, the epitaxial regions 24a and 24b have a combined thickness T2 in a range of approximately 50 nm to approximately 70 nm.The thickness T2 can be measured from a top surface of the epitaxial regions 24b to a bottom point of the epitaxial regions 24a.

[0037] The epitaxial regions 24a, epitaxial regions 24b, and / or the fins 52 can be implanted with dopants during epitaxy using an in-situ doping process. For example, second n-impurities can flow into the deposition chamber while the epitaxial regions 22 are being grown. The second n-impurities implanted in the epitaxial regions 24a and 24b are arsenic. In some embodiments, the second n-impurities can be a different element than the first n-impurities implanted in the epitaxial regions 22. For example, in one specific embodiment, the epitaxial regions 22 can be implanted with arsenic, and the epitaxial regions 24a and 24b can be implanted with phosphorus. Other combinations of n-impurities can be used in other embodiments.

[0038] Furthermore, the concentration of the second n-impurities in the epitaxial regions 24a and 24b can differ. For example, the concentration of the second n-impurities in epitaxial regions 24b can be higher than the concentration of the second n-impurities in epitaxial regions 24a. This can be achieved, for example, by changing the flow rate and / or concentration of a dopant gas flowing into the process chamber during epitaxy. In some embodiments, the epitaxial regions 24a exhibit an impurity concentration in the range of approximately 5 × 10⁻⁶. 20 cm -3 up to about 10 21 cm -3 and the epitaxial regions 24b exhibit a contamination concentration in the range of approximately 10 21 cm -3 up to approximately 3×10 21 cm -3In other embodiments, the epitaxial regions 24a and / or 24b may have different impurity concentrations. The impurity concentration in the epitaxial regions 24a and / or 24b may be constant or varied throughout the respective epitaxial regions 24a / 24b. For example, the epitaxial regions 24a / 24b may each have a gradient impurity concentration that increases in one direction towards an upper surface of the fins 52.

[0039] Thus, epitaxial source / drain regions 82 are formed. These epitaxial source / drain regions 82 contain epitaxial regions 22, 24a, and 24b. Epitaxial region 22 contains first impurities (arsenic), and epitaxial regions 24a and 24b contain second impurities (e.g., phosphorus or the like). The epitaxial regions 22 can coat the sides and undersides of epitaxial regions 24a / 24b. Alternatively, one or more of the epitaxial regions 22, 24a, or 24b can be omitted from the epitaxial source / drain regions 82.

[0040] The epitaxial source / drain regions 82 may have surfaces raised from the respective surfaces of the fins 52 and may exhibit facets. As a result of the epitaxial processes used to form the epitaxial source / drain regions 82, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward across the side walls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to be joined together, as by Fig. Figure 12B illustrates this. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxy process is complete, as shown by Fig. 12C is illustrated. In the Fig. 12B and Fig. In the embodiments illustrated in Figure 12C, gate spacers 86 are formed that cover a section of the sidewalls of the fins 52 extending above the STI regions 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacers 86 can be modified to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 56.

[0041] The Fig. Figures 13A to 14B illustrate additional implantation steps that are formed on the epitaxial source / drain regions 82 after the epitaxial source / drain regions 82 have been fully grown in some embodiments. Fig. 13A and Fig. In procedure 13B, a first implantation 26 is performed on the epitaxial source / drain regions 82. The first implantation 26 can be performed in situ with the formation of the epitaxial source / drain regions 82 or can be performed ex situ with respect to the formation of the epitaxial source / drain regions 82.

[0042] In some embodiments, the first implantation 26 implants third n-impurities into the epitaxial source / drain regions 82. The third impurities can be selected to have a relatively low enthalpy of formation and may be arsenic, antimony, carbon, or the like. As will be explained in more detail below, due to their relatively low enthalpy of formation, the third impurities are more strongly attracted to gaps (V) in the epitaxial source / drain regions 82 and can form inactive clusters with the gaps. For example, in embodiments where the third impurity is arsenic, As4V can be formed as a relatively stable complex (e.g., deactivated to form an inactive cluster).Accordingly, the third impurities help to reduce the diffusion of fourth impurities, which are subsequently implanted into the epitaxial source / drain regions 82. For example, vacancies in the silicon lattice exhibit a stronger attraction with respect to the third impurities (e.g., arsenic) than with respect to the fourth impurities (e.g., phosphorus). Consequently, the diffusion of the fourth impurity can be slowed when the vacancies are consumed by forming stable complexes with the third impurity. As a result, the source / drain contact resistance can be reduced. Furthermore, the implantation of the third impurities can provide improved transition abruptness and reduced diffusion compared to a transition formed by implanting only the fourth impurities, as described below.The third impurities implanted in the first implantation 26 may be the same or different from the first impurities in the epitaxial regions 22.

[0043] The first implantation 26 uses arsenic as a dopant gas. Other carrier gases (e.g., nitrogen, argon, helium, or the like) may also be present. The first implantation 26 can be performed with an implantation energy in the range of approximately 2 keV to approximately 20 keV, such as approximately 4 keV. An implantation dose of the first implantation 26 can be in the range of approximately 5 × 10 14 cm -3 up to about 10 22 cm -3The implantation angle of the first implantation 26 can be in a range of approximately 3° to approximately 15°, and the rotation angle of the first implantation 26 can be in a range of 0° to 360°. For example, the implantation angle can refer to the angle at which the third impurities are implanted from above into the epitaxial source / drain regions 82 with respect to a major surface of the substrate. Furthermore, a rotation angle can refer to the rotation of the wafer 10 around the process chamber during the first implantation 26. For example, with reference to Fig. Figure 13B illustrates a top view of a process chamber 200. The first implantation 26 can be performed in the process chamber 200. The process chamber 200 has a plate 202 which supports the wafer 10 during the first implantation 26. The plate can also be connected to a motor which rotates the wafer 10 according to a rotation angle of the first implantation 26, as indicated by arrow 28. The wafer 10 can be rotated any number of times. For example, in some embodiments, the wafer 10 is not rotated for the entire duration of the first implantation 26. In other embodiments, the wafer 10 is rotated twice by 90°. In still other embodiments, the wafer 10 is rotated four times by 45°. The rotation angle and the number of times the wafer is rotated can influence a post-temper implantation profile of the completed structure (see, for example, Figure 13B). Fig. 15A to 17). Accordingly, 26 different implantation profiles can be achieved by adjusting the rotation angle and rotation times during the initial implantation. Although Fig. Figure 13B illustrates a process chamber 200 with a specific configuration that processes a single wafer 10; other configurations are also possible and a different number of wafers can be processed simultaneously in the process chamber 200.

[0044] In Fig. 14A and Fig. In 14B, a second implantation 30 is next performed on the epitaxial source / drain regions 82. The second implantation 30 can be performed in-situ or ex-situ with respect to the first implantation 26. In some embodiments, no annealing processes are performed between the first implantation 26 and the second implantation 30.

[0045] In some embodiments, the second implantation 30 implants fourth impurities into the epitaxial source / drain regions 82. The fourth impurities can be selected to have a relatively high enthalpy of formation compared to the third impurities implanted in the first implantation 26. For example, the fourth impurities may be phosphorus (e.g., phosphorus dimer (P2)) or the like. In some specific embodiments, the first implantation 26 implants arsenic and the second implantation 30 implants phosphorus dimer. Due to the relatively high enthalpy of formation of the fourth impurities compared to the third impurities, the fourth impurities are less attracted to gaps (V) in the epitaxial source / drain regions 82. For example, the third impurities may form stable complexes with the gaps, thereby reducing the deactivation (e.g.,through the formation of complexes of the fourth impurities and the gaps) and the diffusion of the fourth impurities. Consequently, the contact resistance can be reduced due to a higher concentration of the fourth impurities in a contact area of ​​the epitaxial source / drain regions 82 (e.g., the upper portions of the epitaxial source / drain regions 82). Furthermore, the incorporation of third impurities can provide improved transition abruptness and reduced diffusion compared to a transition formed by implanting only the fourth impurities.

[0046] The second implantation 30 can use phosphorus (e.g., phosphorus dimer (P₂)) or the like as a dopant gas. Other carrier gases (e.g., nitrogen, argon, helium, or the like) may also be present. The second implantation 30 can be performed with an implantation energy in the range of approximately 2 keV to approximately 20 keV. An implantation dose of the second implantation 30 can be at least approximately 4 × 10⁻⁶ 15 cm -3 amount to, for example, in a range of approximately 10 18 cm -3 up to about 10 22 cm -3It has been observed that by implanting the fourth impurities at a high dose (e.g., in the previous region), the source / drain contact resistance can be reduced by providing increased dopants in a contact area of ​​the epitaxial source / drain regions 82. The implantation angle of the second implantation 30 can be in a range of approximately 3° to approximately 15°, and the rotation angle of the second implantation 30 can be in a range of 0° to 360°. For example, the implantation angle can refer to the angle at which the fourth impurities are implanted from above into the epitaxial source / drain regions 82 with respect to a major surface of the substrate. Furthermore, a rotation angle can refer to the rotation of the wafer 10 around the process chamber during the second implantation 30. For example, with reference to Fig. Figure 14B illustrates a top view of the process chamber 200. The second implantation 30 can be performed in the same process chamber 200 as the first implantation 26. Alternatively, the second implantation 30 can be performed in a different process chamber 200. The wafer 10 is rotated on the plate 202 according to a rotation angle of the second implantation 30, as indicated by arrow 32. The wafer 10 can be rotated any number of times. For example, in some embodiments, the wafer 10 is not rotated during the entire duration of the second implantation 30. In other embodiments, the wafer 10 is rotated twice by 90° during the second implantation 30. In still other embodiments, the wafer 10 is rotated four times by 45° during the second implantation 30. The rotation angle and the number of times the wafer is rotated can influence a post-tempering implantation profile of the completed structure (see e.g.B. . Fig. 15A to 17). Accordingly, by adjusting the rotation angle and rotation times during the first implantation, 26 and / or the second implantation, 30 different implantation profiles can be achieved. Although Fig. Figure 14B illustrates a process chamber 200 with a specific configuration that processes a single wafer 10; other configurations are also possible and a different number of wafers can be processed simultaneously in the process chamber 200.

[0047] Subsequently, an annealing process can be performed to activate the third and fourth dopants. For example, in some embodiments, the annealing process may include microsecond annealing (µSSA) followed by laser spike annealing (LSA). In some embodiments, the transition profile of the fourth dopants (e.g., phosphorus) may be the same after the annealing process (e.g., after µSSA / LSA) as before. Accordingly, the implantation of an element with a lower enthalpy of formation may help to reduce diffusion during the annealing process. The µSSA may be performed at a temperature in the range of approximately 1050°C to approximately 1150°C, and the LSA may be performed at a temperature in the range of approximately 1100°C to approximately 1250°C. Other annealing processes may be used in other embodiments.

[0048] The Fig. 15A, Fig. 15B and Fig. Figure 15C illustrates the resulting structure after the tempering process according to some embodiments. Fig. 15A illustrates the structure along line BB of Fig. 1; Fig. 15B illustrates the structure along line CC of Fig. 1 for joined epitaxial source / drain regions 82; and Fig. 15C illustrates the structure along line CC of Fig. 1 for non-joined epitaxial source / drain regions 82. As illustrated, the doped regions 34 and 36 are formed on a top side of the epitaxial source / drain regions 82 and the fins 52. The doped regions 34 contain the third impurities, which have the relatively low enthalpy of formation, and the doped regions 36 contain the fourth impurities, which have the relatively high enthalpy of formation. In the embodiments of the Fig. 15A, Fig. 15B and Fig. 15C The sides and undersides of the doped regions 36 can be covered by the doped regions 34. For example, the doped regions 34 can separate the doped regions 36 from the fins 52 and the lower portions of the epitaxial source / drain regions 82. Furthermore, the doped regions 34 and 36 can contain additional impurities, such as the first and / or second impurities implanted in the epitaxial source / drain regions 82 (e.g., implanted in situ with respect to the epitaxial regions 22, 24A, and 24B). The original boundaries for the epitaxial regions 22, 24A, and 24B are illustrated twice for reference.

[0049] The doped regions 34 provide a steeper transition to improved short-channel control (e.g., improved DIBL with a channel length less than, say, 10 nm, and reduced leakage current). For example, experimental data show that the turn-off current was reduced by at least 20% in embodiment transistors where both the third and fourth impurities were implanted, compared to transistors where only the fourth impurities were implanted. Furthermore, the implantation of the third impurities reduces the diffusion of the fourth impurities, and a concentration of the fourth impurities in the doped regions 36 can be increased. Consequently, the contact resistance can be reduced. For example, experimental data show that the source resistance (RS) can be reduced. s) by at least 20% by implanting impurities with relatively low enthalpy of formation (e.g., the third impurities in the doped regions 34) before implanting the impurities with relatively high enthalpy of formation (e.g., the fourth impurities in the doped regions 36). For example, the additional arsenic implantation can reduce the R s improve by 20% or more compared to a structure without this acetylsalicylic acid (ASA) implantation.

[0050] The doped regions 36 can be designated as regions 36A, 36B, and 36C, and the dopant concentration of the fourth impurities in regions 36A, 36B, and 36C can differ. For example, the concentration of the fourth impurities in region 36B can be higher than in region 36A, and the concentration of the fourth impurities in region 36C can be higher than in region 36B. The concentration of the fourth impurities in each of regions 36A, 36B, and 36C can be varied or constant. For example, doped region 36 can exhibit a gradient concentration of the fourth impurities that increases in one direction toward an upper surface of the epitaxial source / drain regions 82 (as indicated by arrow 38). Likewise, the concentration of the third impurities in region 34 can be constant or varied.For example, the doped region 34 may have a gradient concentration of the third impurities that increases in the direction of arrow 38.

[0051] Fig. Figure 15D illustrates a graph 250 of the impurity concentration in the epitaxial source / drain region 82 in an embodiment, such as along a central line of an epitaxial source / drain region 82. Line 252 represents a concentration of the fourth impurity (e.g., phosphorus dimer), while line 254 represents a concentration of the third impurity (e.g., arsenic). As illustrated, a post-temper concentration of the fourth impurity (e.g., phosphorus dimer) greater than 10 22 cm -3in a contact area (e.g., the doped regions 36C) of the epitaxial source / drain regions 82. It has been observed that providing a doped region with this concentration advantageously reduces the source / drain contact resistance. Other impurity concentration profiles are also possible in other embodiments.

[0052] As previously explained, a profile of the doped regions 34 and 36 can be set by changing the process parameters (e.g. the rotation angle) of the implantation processes 26 and 30. Fig. Figure 15A illustrates a profile achieved by not rotating the wafer 10 around the process chamber during the first implantation process 26 and the second implantation process 30. Fig. Figure 16 illustrates an alternative embodiment where the wafer 10 is rotated twice by 90° during each of the first implantation process 26 and the second implantation process 30. Fig. 16 indicate identical reference symbols for identical elements, which are used using the same processes as in Fig. 15A are formed. As by Fig. As illustrated in Figure 16, the doped regions 34 can be arranged on the side of the doped regions 36, and the doped regions 34 can extend further below the gate spacers 86 / dummy gates 72. The doped regions 36 can extend further into the epitaxial source / drain regions 82 than the doped regions 34. Fig. Figure 17 illustrates an alternative embodiment where the first implantation 26 comprises rotating the wafer 10 four times by 90° and the second implantation 30 does not include rotating the wafer 10. Fig. 17 indicate identical reference symbols for identical elements, which are used using the same processes as in Fig. 15A are formed. As by Fig. As illustrated in Figure 17, the doped regions 34 can be arranged on the side of the doped regions 36, and the doped regions 34 can extend further under the gate spacers 86 / dummy gates 72. The doped regions 34 can also extend under the gate spacers 86 / dummy gates 72, and the doped regions 36 can extend further into the epitaxial source / drain regions 82 than the doped regions 34. In each of the embodiments of Fig. 16 and Fig. 17. The doped regions 34A and 34B are present, and the impurity concentration of the third impurities can be higher in region 34A than in region 34B. The impurity concentration in each of regions 34A and / or 34B can be constant or variable. Other configurations of the doped regions 34 and 36 are also possible.

[0053] The epitaxial source / drain regions 82 in the p-region 50P can be formed by masking the n-region 50N and etching the source / drain regions of the fins 52 in the p-region 50P to create recesses in the fins 52. The epitaxial source / drain regions 82 in the p-region 50P are then grown epitaxially within these recesses. The epitaxial source / drain regions 82 can consist of any acceptable material, such as that suitable for p-FinFETs. For example, the epitaxial source / drain regions 82 in the p-region 50P can consist of materials that exert compression in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like, if the fin 52 is silicon. The epitaxial source / drain regions 82 in the p-region 50P may have surfaces raised from respective surfaces of the fins 52 and may have facets.

[0054] In Fig. 18A and Fig. 18B is a first interlayer dielectric (ILD) 88 deposited over the structure that is in Fig. 10A and Fig. Figure 10B illustrates this. The first ILD 88 can be formed from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is arranged between the first ILD 88 and the epitaxial source / drain regions 82, the masks 74, and the gate spacers 86. The CESL 87 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride or the like, which has a lower etch rate than the material of the overlying first ILD 88.

[0055] In Fig. 19A and Fig. 19B A planarization process, such as a CMP, can be performed to level the top surface of the first ILD 88 with the top surfaces of the dummy gates 72 or the masks 74. The planarization process can also remove the masks 74 on the dummy gates 72 and sections of the gate seal spacers 80 and the gate spacers 86 along the side walls of the masks 74. After the planarization process, the top surfaces of the dummy gates 72, the gate seal spacers 80, the gate spacers 86, and the first ILD 88 are at the same height. Accordingly, the top surfaces of the dummy gates 72 are exposed by the first ILD 88. In some embodiments, the masks 74 can remain, in which case the planarization process levels the upper surface of the first ILD 88 with the upper surfaces of the masks 74.

[0056] In Fig. 20A and Fig. In 20B, the dummy gates 72 and the masks 74, if present, are removed in one etching step(s), forming recesses 90. Sections of the dummy dielectric layer 60 in the recesses 90 may also be removed. In some embodiments, only the dummy gates 72 are removed, leaving the dummy dielectric layer 60 exposed through the recesses 90. In some embodiments, the dummy dielectric layer 60 is removed from the recesses 90 in a first region of a die (e.g., a core logic region) and remains in the recesses 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 72 are removed by an anisotropic dry etching process.For example, the etching process can be a dry etching process using a reactive gas that selectively etches the dummy gates 72, without etching or with minimal etching of the first ILD 88 or the gate spacers 86. Each recess 90 exposes and / or lies above a channel region 58 of a respective fin 52. Each channel region 58 is located between adjacent pairs of the epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gates 72 are etched. The dummy dielectric layer 60 can then optionally be removed after the dummy gates 72 have been removed.

[0057] In Fig. 21A and Fig. 21B are gate dielectric layers 92 and gate electrodes 94 for replacement gates. Fig. Figure 14C illustrates a detailed view of Region 89 of Fig. 14B. The gate dielectric layers 92 comprise one or more layers deposited in the recesses 90, such as on the upper surfaces and side walls of the fins 52 and on side walls of the gate sealing spacers 80 / gate spacers 86. The gate dielectric layers 92 may also be formed on the upper surface of the first ILD 88. In some embodiments, the gate dielectric layers 92 comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments the gate dielectric layers 92 have a silicon oxide interface formed by thermal or chemical oxidation and from an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and combinations thereof.The gate dielectric layers 92 can have a dielectric layer exhibiting a k-value greater than approximately 7.0. The formation methods for the gate dielectric layers 92 can include molecular beam deposition (MBD), ALD, PECVD, and the like. In some embodiments, where portions of the dummy gate dielectric 60 remain in the recesses 90, the gate dielectric layers 92 have a material of the dummy gate dielectric 60 (e.g., SiO2).

[0058] The gate electrodes 94 are deposited over the gate dielectric layers 92 and fill the remaining sections of the recesses 90. The gate electrodes 94 can comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, the gate electrode 94 can have any number of lining layers 94A, any number of work function tuning layers 94B, and a filler material 94C, as shown by Fig. 21C illustrates, although a single-layer gate electrode 94 in Fig. Figure 21B illustrates this. After filling the recesses 90, a planarization process, such as CMP, can be performed to remove the excess portions of the gate dielectric layers 92 and the gate electrode material 94, with the excess portions located above the top surface of the ILD 88. The remaining portions of gate electrode material 94 and the gate dielectric layers 92 thus form substitute gates of the resulting FinFETs. The gate electrodes 94 and the gate dielectric layers 92 can be collectively referred to as the “gate stack.” The gate and the gate stack can extend along sidewalls of a channel region 58 of the fins 52.

[0059] The formation of the gate dielectric layers 92 in the n-region 50N and the p-region 50P can be carried out simultaneously, so that the gate dielectric layers 92 in each region are formed from the same materials, and the formation of the gate electrodes 94 can be carried out simultaneously, so that the gate electrodes 94 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 92 in each region can be formed by different processes, so that the gate dielectric layers 92 can be made of different materials, and / or the gate electrodes 94 in each region can be formed by different processes, so that the gate electrodes 94 can be made of different materials. Different masking steps can be used to mask and expose suitable regions when different processes are used.

[0060] In Fig. 22A and Fig. 22B, a gate mask 96 is formed over the gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94) and can be arranged between opposing sections of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack, such that a recess is formed directly over the gate stack and between opposing sections of the gate spacers 86. A gate mask 96, comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess sections of the dielectric material extending over the first ILD 88.

[0061] As in Fig. 22A and Fig. As illustrated in Figure 22B, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 108 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable process, such as CVD and PECVD. The gate contacts 110 formed thereafter ( Fig. 16A and Fig. 16B) pass through the second ILD 108 and the gate mask 96 to touch the upper surface of the recessed gate electrode 94.

[0062] In Fig. 23A and Fig.In Figure 23B, the gate contacts 110 and the source / drain contacts 112 are formed by the second ILD 108 and the first ILD 88, respectively, according to some embodiments. The openings for the source / drain contacts 112 are formed by the first and second ILDs 88 and 108, and the openings for the gate contact 110 are formed by the second ILD 108 and the gate mask 96. The openings can be formed using acceptable photolithography and etching techniques. A lining (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The lining can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.A planarization process, such as CMP, can be performed to remove excess material from a surface of the ILD 108. The remaining lining and conductive material form the source / drain contacts 112 and the gate contacts 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contacts 110 are physically and electrically coupled to the gate electrodes 106. As a result of the first implantation process 26 and the second implantation process 30, the concentration of the fourth impurities (e.g., phosphorus dimer or the like) can be increased in an area where the source / drain contacts 112 are connected to the epitaxial source / drain regions 82.Consequently, the contact resistance of the source / drain contacts 112 can be advantageously reduced. The source / drain contacts 112 and the gate contacts 110 can be formed in different processes or in the same process. Although they are shown to be formed in the same cross-sections, it should be noted that each of the source / drain contacts 112 and gate contacts 110 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0063] The disclosed FinFET embodiments could also be applied to nanostructured devices, such as nanostructured field-effect transistors (NSFETs) (e.g., nanolayer, nanowire, gate-all-around, or the like). In one NSFET embodiment, the fins are replaced by nanostructures formed by structuring a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a similar manner to the embodiments described previously. After the dummy gate stacks are removed, the sacrificial layers can be partially or completely removed from the channel regions.The replacement gate structures are formed in a similar manner to the embodiments described above. These structures can partially or completely fill openings left by the removal of the sacrificial layers and can partially or completely surround the channel layers in the channel regions of the NSFET devices. The ILDs and the contacts with the replacement gate structures and the source / drain regions can be formed in a similar manner to the embodiments described above. A nanostructure device can be formed as disclosed in US patent application no. 2016 / 0365414, which is incorporated into this application by reference.

[0064] Several embodiments involve implanting two different types of dopants into a source / drain region to improve transition abruptness (e.g., for reduced leakage current) and source / drain contact resistance. In one embodiment, first dopants are implanted into a source / drain region, followed by the implantation of second dopants. The first dopants may have a lower enthalpy of formation than the second dopants. For example, the first dopants may be arsenic, and the second dopants may be phosphorus or the like. In specific embodiments, the arsenic is implanted into the source / drain region followed by phosphorus dimer implantation (P2 implantation). Due to their lower enthalpy of formation, the first dopants are more strongly attracted to gaps in the source / drain region and form more stable bonds with them.For example, the first dopants can be used to reduce the diffusion of the second dopants and decrease their binding to the gaps. By reducing the diffusion of the second dopant, a higher concentration of the second dopant can be achieved in a contact area of ​​the source / drain region, thereby reducing the source / drain contact resistance. Furthermore, the use of two different elements as dopants allows for a transition with improved abruptness and lower diffusion, resulting in improved short-channel control (e.g., to address the effects of drain-induced barrier lowering (DIBL) at advanced process nodes), reduced leakage, and improved equipment performance.Different embodiments may offer one or more of the following non-restrictive advantages: improved transition abruptness, reduced diffusion of the second dopants, and reduced source / drain contact resistance.

[0065] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Procedure comprising: Forming a source / drain region (82) in a semiconductor fin (52); after forming the source / drain region (82), implanting (26) first impurities into the source / drain region (82); after implanting (26) the first impurities, implanting (30) second impurities into the source / drain region (82), wherein the first impurities have a lower enthalpy of formation than the second impurities; and after implanting (30) the second impurities, annealing the source / drain region (82), the first impurities contain arsenic, wherein the second impurities contain phosphorus, and wherein implanting the second impurities into the source / drain region (82) comprises implanting phosphorus dimer into the source / drain region (82). [2] The method of claim 1, wherein forming the source / drain region (82) comprises: Etching a recess (20) into the semiconductor fin (52); epitaxially growing a first epitaxial region (22) in the recess (20); In-situ doping the first epitaxial region (22) with third impurities during epitaxial growth of the first epitaxial region (22); epitaxially growing a second epitaxial region (24) in the recess (20) and above the first epitaxial region (22); and In-situ doping the second epitaxial region (24) with fourth impurities during epitaxial growth of the second epitaxial region (24), wherein the third impurities are a different element than the fourth impurities. [3] The method of claim 2, wherein the third impurities are a same element as the first impurities. [4] A method according to any preceding claim, wherein annealing the source / drain region (82) comprises: Performing a microsecond anneal, hereinafter referred to as µSSA, on the source / drain region (82); and after performing the µSSA, performing a laser tip anneal, hereinafter referred to as LSA, on the source / drain region (82). [5] Procedure comprising: etching a recess (20) in a semiconductor fin; epitaxially growing a source / drain region (82) in the recess (20); after epitaxial growth of the source / drain region (82), implanting (26) the source / drain region (82) with arsenic; after implanting (26) the source / drain region (82) with arsenic, implanting (30) the source / drain region (82) with phosphorus dimer; and after implanting (30) the source / drain region (82) with phosphorus dimer, activating the arsenic and the phosphorus dimer by an annealing process. [6] The method of claim 5, wherein implanting the source / drain region (82) with phosphorus dimer comprises using an implantation dose in a range of 10 18 cm -3 up to 10 22 cm -3 includes. [7] The method of claim 5 or 6, wherein no annealing process is performed between implanting (26) the source / drain region (82) with arsenic and implanting (30) the source / drain region with phosphorus dimer. [8] The method of any one of claims 5 to 7, wherein implanting (26) the source / drain region (82) with arsenic comprises rotating a wafer (10) having the semiconductor fin (52) twice by 90°. [9] The method of any one of claims 5 to 7, wherein implanting (26) the source / drain region (82) with arsenic comprises rotating a wafer (10) having the semiconductor fin (52) four times by 45°. [10] The method of any one of claims 5 to 9, wherein implanting (26) the source / drain region (82) with arsenic comprises not rotating a wafer (10) comprising the semiconductor during an entire duration of implanting (26) the source / drain region with arsenic. [11] Device comprising: a semiconductor substrate (50); a gate stack (94) on a top surface of the semiconductor substrate (50); a source / drain region (82) adjacent to the gate stack (94), the source / drain region (82) having a first epitaxial region (24) having first impurities; a first doped region (34) having second impurities in the first epitaxial region (24); and a second doped region (36) comprising third impurities in the first epitaxial region, the second impurities having a lower enthalpy of formation than the third impurities, the first doped region (34) surrounding sides of the second doped region (36), the second impurities comprising arsenic, the source / drain region (82) further comprising a second epitaxial region (22) surrounding the first epitaxial region (24), the second epitaxial region (22) comprising fourth impurities, and the fourth impurities being a different element than the first impurities. [12] The device of claim 11, wherein the second doped region (36) extends deeper than the first doped region (34). [13] The device of claim 11 or 12, wherein the first doped region (34) covers a bottom surface of the second doped region (36). [14] The device of any one of claims 11 to 13, wherein the third impurities comprise phosphorus. [15] The device of any one of claims 11 to 14, wherein a concentration of the third impurities increases in a direction (38) toward a top surface of the source / drain region (82). [16] The device of any one of claims 11 to 15, further comprising a source / drain contact (112) extending into the second doped region (36), wherein a concentration of the third impurities at the source / drain contact (112) is at least 10 23 cm -3 amounts.

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