Composite pin drivers

Abstract

A combined stage circuit (202) for a pin driver system, wherein the combined stage circuit (202) responds to respective input signals from at least one first driver (208) and a second driver (216), and the combined stage circuit (202) is configured to provide an output voltage signal (206) of an output gain stage at a combined stage output node (306), wherein the combined stage circuit (202) has the following features: a voltage input node (302) configured to receive an input voltage signal from the first driver (208); a current input node (304) configured to receive an input current signal from the second driver (216); a first amplification circuit (308) configured to receive the input voltage signal at the voltage input node (302) and, based on the input voltage signal, to provide a first part of the output voltage signal (206) at the compound stage output node (306); and a transimpedance circuit (310) configured to receive the input current signal at the current input node (304) and, based on the input current signal, to provide a second part of the output voltage signal (206) at the compound stage output node; wherein the first and second part of the output voltage signal (206) are combined at the compound stage output node (306) to provide the output voltage signal (206).

Description

BACKGROUND

[0001] A test system for electronic devices may include a pin driver circuit that provides a voltage test pulse to a device under test (DUT). In response, the test system may be configured to measure a response from the DUT to determine, for example, whether the DUT conforms to one or more specified operating parameters. A test system may optionally include multiple driver circuits, such as a Class AB driver circuit and a Class A driver circuit, to provide circuit test signals with different amplitude or timing characteristics. In one example, the test system is configured to measure a response from a DUT using an active load and a comparator circuit to sample the transitions at a DUT pin.

[0002] A system for testing digital integrated circuits (ICs) may include a driver circuit designed to provide multiple voltage levels (e.g., Vhigh, Vlow, and Vterm) to a device under test (DUT). The DUT may possess bidirectional (I / O) capability, meaning it can both send and receive a stimulus. The Vhigh and Vlow levels of the driver circuit serve to excite a DUT while it is in its "input" state, while Vterm acts as a termination signal for the DUT in its "output" state. The process of switching between Vhigh, Vlow, and Vterm may be implemented as a collection of three switches, with one terminal of each switch connected to either Vhigh, Vlow, or Vterm, and the other terminal connected to a common 50-ohm resistor, which is then connected to the DUT node.In this way, the transitions between the three levels can be achieved by opening and closing the corresponding switches, for example by only one switch being closed at any given time.

[0003] A key feature of ATE test systems is their ability to deliver precisely timed Vhigh, Vlow, and Vterm signals or transitions to the DUT. Providing essentially constant propagation delays and a predictable signal edge arrangement, independent of variables such as temperature, frequency, duty cycle, pulse width, or test vector history, which can impair the effectiveness of a test system, can be crucial.

[0004] DE 10 2017 104 553 A1 concerns a test system that provides a high-fidelity output signal. A transition driver circuit can selectively activate multiple parallel current paths based on a desired voltage transition. The transition driver circuit can include: a first switch designed to switch a first current path between the output node and a first current source / sink, and a second switch designed to switch a second current path between the output node and the first current source / sink.The transition driver circuit can include a control circuit designed to receive information about a desired voltage transition and, depending on the magnitude of the desired voltage transition, selectively turn on the first and / or second switch to activate the first and / or second current path to provide respective portions of the output signal from the first current source / sink to the output node of the test system.

[0005] US 7,755,377 B2 relates to a driver circuit that has a first operating mode and a second operating mode and outputs a signal according to an input signal. The driver circuit comprises a first driver section that, in the first operating mode, generates and outputs the signal according to the input signal and is deactivated in the second operating mode; a high-precision driver section that is deactivated in the first operating mode and, in the second operating mode, outputs a source voltage at a predetermined voltage; and a second driver section that, in the first operating mode, receives the output signal from the first driver section and outputs the received signal, and, in the second operating mode, receives the source voltage from the high-precision driver section, generates the output signal according to the input signal, and outputs the signal thus generated. BRIEF SUMMARY

[0006] The inventor of the present invention recognized, among other things, that a problem to be solved concerns the provision of a test signal generator system that is relatively small, inexpensive to manufacture, consumes less power than conventional systems, or provides higher accuracy performance compared to conventional systems. The problem may, for example, involve providing a test signal generator with improved pulse edge alignment accuracy or improved bandwidth characteristics.

[0007] In one example, a solution to this and other problems might involve a driver system with a compound stage. The compound stage can accommodate a wide range of voltage and current input and output signals and can support high-bandwidth signals with improved accuracy. For instance, the compound stage might have a first input capable of receiving voltage signals and a second input capable of receiving current signals, providing a compound output signal based on a combination of the received voltage and current signals. In another example, a test system incorporating the compound stage could exhibit performance characteristics similar to those of a Class AB driver and bandwidth characteristics similar to those of a Class A driver.

[0008] In one example, the compound stage provides a high-impedance environment, meaning that the devices used in a front-end switching or driver circuit can be many times smaller than those used in a conventional Class A switching circuit. Because the switching operations can be performed within the high-impedance environment of the compound stage, the front-end switching current signals can still be many times smaller than the current signals used in a conventional Class A switching circuit.

[0009] In one example, the composite stage can also help isolate the front-end driver or switching stages from a device under test (DUT). With this improved isolation compared to conventional driver arrangements, parasitic loading effects can be reduced, potentially improving bandwidth. Consequently, smaller or less capacitance-releasing devices can be used, or even omitted altogether.

[0010] This abstract is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide a complete or exclusive explanation of the invention. The detailed description is included to provide further information about the present patent application. Brief description of the multiple views of the drawings

[0011] In order to easily identify the discussion of a particular element or action, the most significant number(s) in a reference sign refer to the number of the character in which that element is first introduced. Fig. Figure 1 generally illustrates an example of a test system topology that has multiple driver circuits. Fig. Figure 2 generally illustrates an example of a test system topology that includes a compound stage and multiple driver circuits. Fig. Figure 3 illustrates in general an example of a block diagram of a combined stage for a test system. Fig. Figure 4 generally illustrates an example of a schematic graphical representation of a section of a composite stage for a test system. Fig. Figure 5 generally illustrates an example of a procedure that may involve the use of a composite stage in a test system to provide a test signal to a DUT. DETAILED DESCRIPTION

[0012] A pin driver circuit of a test system can provide a voltage pulse stimulus to a device under test (DUT) at a specified time, optionally measuring a response from the DUT. The test system can be configured to provide output signal pulses with high accuracy over a relatively wide range of output signal magnitudes to accommodate various types of DUTs. In some examples, a test system incorporates a physically large current switching stage to enable large voltage sweeps. However, such a large current switching stage can be a hindrance to generating small voltage sweeps because the interference signals, such as those resulting from parasitic effects, associated with a physically large switching stage can degrade the accuracy of the test signal shape and the bandwidth of the test signal.

[0013] The test systems and procedures described herein provide, among other things, a pin driver architecture that can improve pulse edge alignment accuracy and signal bandwidth at high or low power operating levels. In one example, the systems described herein may include a compound stage to receive and combine signals from several different driver circuits before the signals are provided to a device under test (DUT). In one example, the compound stage may include a voltage signal amplifier circuit, configured, for example, to receive and process signals from a Class AB driver stage, and a transimpedance circuit, configured, for example, to receive and process signals from a Class A driver stage. Additionally, the driver stages, or multiple instances of one or more types of driver stages, may optionally be used in conjunction with the compound stage discussed herein.

[0014] In one example, multiple drivers or driver stages can be used to provide a test system that is trainable to test various semiconductor devices with varying voltage and speed requirements. Furthermore, multiple drivers can be used to enhance or enable multi-level testing, or "multiplexing," for physical layer testing. During physical layer testing, the multiple drivers can be switched simultaneously to provide different stimuli or drive signals to a device under test (DUT).

[0015] For example, a class AB driver might be configured to deliver a wide range of different voltage magnitude signals and to consume a minimal amount of power. The class AB driver might exhibit moderate bandwidth and timing accuracy. The class AB driver might incorporate or utilize diode bridges, differential transistor pairs, or other switching elements. For example, a class AB driver might be configured for moderate-speed testing of circuits in a system on a chip or other circuits or devices.

[0016] In one example, a Class A driver might be configured to deliver relatively small current signals and be designed for high bandwidth and timing accuracy. In another example, a Class A driver might be configured to switch larger current signals, for example, directly at an output node of the driver or at the input of the device under test (DUT). In another example, a Class A driver might be configured for high-speed testing of memory circuits or other components. In yet another example, a Class A driver might reduce the overall bandwidth of a test system due to its parasitic load on the DUT, for example, due to large constituent devices used to switch large current signals on the DUT.In one example, some test systems may incorporate capacity cancellation elements to counteract the stress effects of the Class A driver; however, such elements can be physically large and contribute to increased part size and die costs. In another example, a compound stage, as discussed here, can be used with a smaller Class A driver to reduce or eliminate the need for such cancellation elements.

[0017] Fig. Figure 1 generally illustrates a first example 100 of a test system topology that includes multiple driver circuits. The first example 100 includes a first driver AB 108, which may be a class AB driver circuit, and a first driver A 116, which may be a class A driver circuit. The first example 100 may further include an output element, such as a first resistor 104, which may be configured to provide a specified output or load impedance. In one example, the first example 100 may include a first load circuit 122, such as a comparator circuit, an active load, or another load device. In one example, the test system is configured to provide a first output current 106, i_OUT, at a DUT pin 102.

[0018] In one example, the first driver AB 108 can be configured to generate a voltage stimulus signal by selecting between parallel-connected diode bridges, each bridge being driven by a unique, dedicated DC voltage level. In the first example, 100 according to Fig. The DC voltages Vih 110 and Vil 112 control the diode bridges of the first driver AB 108. A voltage buffering stage can follow the switching stage, providing power amplification, for example, to generate large currents to power a 50-ohm DUT environment.

[0019] Unlike the first driver AB 108, the first driver A 116 can be configured to generate transitions at DUT pin 102 using a relatively large current switching stage that can be directly coupled to DUT pin 102. A current switching stage in the first driver A 116 can alternately switch current into and out of DUT pin 102 in response to a control signal Hub 120, which can be, for example, a voltage control signal. The first driver A 116 can, for example, provide high-speed operation because it can be relieved of the Class AB voltage buffering stage with its associated bandwidth limitations and other performance constraints.

[0020] In one example, the first driver A116 can be configured to provide a signal with a relatively low amplitude at DUT pin 102. For example, the first driver A116 can provide a signal with approximately a 2-volt range. The first driver AB108 can be configured to provide a signal with a relatively high amplitude at DUT pin 102, for example, -1.5 to +7 volts. The first driver A116 generally operates at a higher switching speed or bandwidth than the first driver AB108. In another example, the first driver AB108 can be configured to absorb the switching currents from the first driver A116. That is, the first driver AB108 can act as a buffer into which the first driver A116 can supply current, such as through the first resistor 104.

[0021] One or both of the first driver AB 108 and the first driver A 116 can be selected to meet different DUT testing requirements that a single driver would not otherwise be able to fulfill. For example, while both driver circuits can provide DUT waveforms, the first driver AB 108 can be configured to provide large-amplitude, low-bandwidth stimulus signals, while the first driver A 116 can be configured to provide low-amplitude, high-bandwidth stimulus signals.

[0022] In one example, the first driver AB 108 and the first driver A 116 do not share an enable pin. Instead, each driver circuit has independent enable control via pins EnAB 114 and EnA 118. This independent enable control allows the first driver AB 108 to act as a low-speed, high-voltage stimulus source and as a static, non-transmitting buffer to absorb the switching currents from the first driver A 116.

[0023] Fig. Figure 2 generally illustrates a second example 200 of a test system topology that includes a compound stage 202 and several driver circuits. The second example 200 may include a second driver AB 208 and a second driver A 216. In one example, the second driver AB 208 may be the same or a similar device as the first driver AB 108, and the second driver A 216 may be the same or a similar device as the first driver A 116 from the example above. Fig. Be 1.

[0024] In one example, the second driver A 216 can be a physically smaller device than the first driver A 116. The second driver A 216 can, for example, be at least one, and optionally several, orders of magnitude smaller than the first driver A 116. The second driver A 216 can be configured to provide signals that have similar timing characteristics to the first driver A 116, but different amplitude characteristics. In another example, the second driver A 216 can be less expensive to manufacture than the first driver A 116 because it can occupy less die area or incorporate or use components with less stringent power requirements.

[0025] The second example 200 may further include the first resistor 104, the DUT pin 102 and the first load circuit 122, which may be, for example, the same as or similar to the elements discussed above. Fig. as described in section 1. That is, the second driver AB 208 and the second driver A 216 of the second example 200 can be used interchangeably with the drivers from the example after. Fig. 1 can be used to provide signals to a DUT via DUT pin 102, or the second driver AB 208 and the second driver A 216 can be used with the same first resistor 104 or the same first load circuit 122 as in the example after Fig. 1 must be completed.

[0026] The second example 200 can further comprise a compound stage 202 and a first amplifier circuit 204. The compound stage 202 can be configured to receive test signals from the second driver AB 208 and the second driver A 216 and, in response, provide the signals to the DUT pin 102 via the first amplifier circuit 204. The first amplifier circuit 204 can be configured to buffer or amplify the signals from the compound stage 202 for delivery to the DUT pin 102. In one example, the compound stage 202 can simultaneously or sequentially receive signals from the second driver AB 208 or the second driver A 216 and respond to these signals.

[0027] The combined stage 202 can provide an environment with a relatively high input impedance for the signals received by the second driver AB 208 or the second driver A 216. Accordingly, the switching signals provided by one or both of the second driver AB 208 or the second driver A 216 can be relatively smaller than the signals provided, for example, by the first driver AB 108 or the first driver A 116 in the first example 100. Fig. 1. The switching current signals from the second driver A 216 can be, for example, one or more orders of magnitude smaller than the signals from the first driver A 116. The compound stage 202 can receive the smaller signals, convert them into voltage signals, and then supply the signals to the DUT pin 102 via the first amplifier circuit 204. With the second driver A 216 being isolated from the DUT pin 102 by the compound stage 202 and the first amplifier circuit 204, the parasitic load on the second driver A 216 can be reduced or eliminated, thus allowing the cancellation component or other attenuating circuit arrangement to be omitted from the signal path.

[0028] Fig. Figure 3 illustrates a general example of a block diagram of the compound stage 202. The compound stage 202 can include, among other things, a compound stage gain circuit 308 and a transimpedance circuit 310. The compound stage gain circuit 308 can be configured to receive a first input signal from a voltage input node 302, while the transimpedance circuit 310 can be configured to receive a second input signal from a current input node 304. That is, the compound stage 202 can be configured to receive a voltage input signal at the voltage input node 302, and the compound stage 202 can be configured to receive a current input signal at the current input node 304.

[0029] In one example, the compound stage amplification circuit 308 can include a buffer circuit or amplifier circuit configured to receive one or more signals from the second driver AB 208 using the voltage input node 302. In response to the signals at the voltage input node 302, the compound stage amplification circuit 308 can provide a first part of an output signal at a summing node 312. In another example, the compound stage amplification circuit 308 can include a pass-through voltage buffer that provides a signal which is substantially the same in amplitude, duration, frequency, phase, or some other characteristic as a signal received by the second driver AB 208 at the voltage input node 302.

[0030] In one example, the transimpedance circuit 310 can include a circuit configured to receive one or more signals from the second driver A 216 using the current input node 304. In response to the current signals received at the current input node 304, the transimpedance circuit 310 can provide a second part of an output signal at the summing node 312. That is, the transimpedance circuit 310 can receive the current signals and, in response, provide corresponding voltage signals. In one example, the transimpedance circuit 310 can be configured to receive a current signal at the current input node 304 and then provide a voltage signal with an amplitude, duration, frequency, phase, or other signal property that corresponds to or depends on the characteristics of the received current signal.

[0031] In one example, the summing node 312 receives the first part of the output signal from the compound stage amplifier circuit 308, receiving the second part of the output signal from the transimpedance circuit 310. The summing node 312 may have a node or circuit configured to combine or summe the signal parts to provide an output signal that is a superposition of the first and second parts of the output signal. Other signals may be similarly superimposed or combined at the summing node 312. The compound stage 202 may provide an output signal from the summing node 312 to, for example, the compound stage output node 306 of the first amplifier circuit 204. The first amplifier circuit 204 may, for example,a superposition signal, which has the first and second part of the voltage output signal, is received from the compound stage output node 306 and in response provides a test signal at the first resistor 104 or at the DUT pin 102.

[0032] Fig. Figure 4 generally illustrates an example of a schematic graphical representation of the interconnection stage 202. In one example, the schematic graphical representation of the interconnection stage 202 can show the components from the block diagram example. Fig. 3 exhibit or represent, which can be used in the compound stage amplification circuit 308 or the transimpedance circuit 310.

[0033] In the example according to Fig. Figure 4 shows that the compound stage 202 includes a compound stage amplifier circuit 402 configured to receive voltage signals from the voltage input node 302. In response to the signals at the voltage input node 302, the compound stage amplifier circuit 402 can provide corresponding voltage signals to a feedback network 406 coupled between the compound stage amplifier circuit 402 and the compound stage output node 306. In one example, the compound stage amplifier circuit 402 and / or the feedback network 406 can be configured to provide a signal at the compound stage output node 306 that can be a substantially 1:1 representation of a signal received at the voltage input node 302. The various components of the feedback network 406 are illustrated as an example, but other configurations or components can be used, for example, to...to improve a bandwidth characteristic of network stage 202 in a similar way.

[0034] In the example according to Fig. The compound stage 202 has a transimpedance resistor 404. The transimpedance resistor 404 can be coupled to the current input node 304 and configured to receive the current input signals from, for example, the second driver A 216. In one example, the transimpedance resistor 404 can have a fixed resistance, such as 1 kΩ. In another example, the transimpedance resistor 404 can have a variable or selectable resistance, which can be determined, for example, based on a magnitude or other property of the signals received by the current input node 304. The transimpedance resistor 404 can be used to receive the current input signals and convert them into voltage signals, which can be combined with other voltage signals from the compound stage amplifier circuit 402 or the voltage input node 302, for example.The signals can be combined using the feedback network 406 or using another circuit configured to combine them. For example, the feedback network 406 can be configured to reduce an apparent input impedance curve of the compound stage 202 at the current input node 304, so that it is, for example, smaller than an impedance curve of the transimpedance resistor 404.

[0035] Fig. Figure 5 generally illustrates an example of a Method 500 that may involve the use of a compound stage in a test system to provide a test signal to a DUT. In one example, the Method 500 may use the compound stage 202 from the examples in [reference to be added]. Fig. 2, Fig. 3 or Fig.4 exhibit or use. The compound stage in the example of method 500 can be configured to receive appropriate voltage and current stimulus signals, convert the current stimulus signal into a voltage, and combine the voltage signals to provide a voltage output signal to a DUT.

[0036] In block 502, procedure 500 may include providing a control signal to a voltage driver. Block 502 may include or use a timing controller or other control circuitry to output control signals to a voltage driver, such as the second driver AB 208. In an example, block 502 may include using the timing controller to provide signals Vih 110 and Vil 112 to the second driver AB 208 at different and non-overlapping times. In response to the control signal provided in block 502, procedure 500 may proceed in block 504 and use a voltage driver to provide a voltage test signal to a compound stage. Block 504 may include, for example, using the second driver AB 208 to provide one or more voltage test signals to the compound stage 202.

[0037] In block 506, procedure 500 may include providing a control signal to a current driver. Block 506 may include or use the same or a different timing controller or other control circuitry to output control signals to the current driver, such as the second driver A 216. In one example, block 506 may include using the timing controller to provide the control signal Hub 120 to the second driver A 216. In response to the control signal provided in block 506, procedure 500 may proceed in block 508 and use a current driver to provide a current test signal to the compound stage. Block 508 may include, for example, using the second driver A 216 to provide one or more current test signals to the compound stage 202.In one example, the control signals provided in block 502 and block 506 can be provided essentially simultaneously, so that the voltage test signals provided in block 504 and the current test signals provided in block 508 can be provided essentially sequentially or essentially simultaneously. In other words, the voltage test signals can be provided to the compound stage at different times or at the same times as the current test signals are provided to the compound stage.

[0038] In block 510, the interconnect stage can receive one or more voltage test signals from block 504, and the interconnect stage can receive one or more current test signals from block 508. The various voltage and current signals can have different non-overlapping arrival times and durations, or the signals can overlap or be received simultaneously. The one or more voltage test signals can be received at voltage input node 302 of interconnect stage 202, and the one or more current test signals can be received at current input node 304 of interconnect stage 202.

[0039] Blocks 512 and 514 can be executed essentially simultaneously, or sequentially, or at different times. In block 512, the procedure 500 can include buffering a voltage test signal received at the compound stage in block 510 and, in response, providing a first voltage signal component of a compound stage output signal. The buffering of the voltage test signal in block 512 can include the use of one or more of the compound stage amplification circuit 308, the compound stage amplifier circuit 402, or the feedback network 406 of the compound stage 202.

[0040] In block 514, the method 500 may involve processing a current test signal received at the compound stage in block 510 and, in response, providing a second voltage signal component of the compound stage output signal. The processing of the current test signal in block 514 may involve the use of a transimpedance device or circuit, such as the transimpedance circuit 310 or the transimpedance resistor 404 of the compound stage 202.

[0041] In block 516, method 500 can include combining the first and second voltage signal parts from block 512 and block 514 to provide a compound stage output signal. For example, the first and second voltage signal parts can be summed or superimposed at summing node 312 to provide the compound stage output signal. In block 518, the compound stage output signal can be buffered or amplified, for example, using the first amplifier circuit 204, and provided to a device under test (DUT), such as DUT pin 102.

[0042] In one example, a problem to be solved involves providing a test signal generator system that is relatively small, inexpensive to manufacture, consumes less power than conventional systems, or provides higher accuracy performance compared to conventional systems, as previously mentioned. The problem might, for example, involve providing a test signal generator with improved pulse edge alignment accuracy or improved bandwidth characteristics. Various aspects of the present disclosure may assist in providing a solution to this and other problems associated with test systems.

[0043] In one example, aspect 1 may include or use an object (such as a device, system, apparatus, method, means of performing actions, or a device-readable medium containing instructions which, when executed by the device, can cause the device to perform actions, or a manufactured article) which may, for example, include or use a compound stage circuit for a pin driver system, wherein the compound stage circuit responds to the input signals of at least one first driver and one second driver, and the compound stage circuit is configured to provide an output voltage signal of an output gain stage at a compound stage output node.In aspect 1, the compound stage circuit can include a voltage input node configured to receive an input voltage signal from the first driver, a current input node configured to receive an input current signal from the second driver, a first gain circuit configured to receive the input voltage signal at the voltage input node and to provide a first part of the output voltage signal at the compound stage output node based on the input voltage signal, and a transimpedance circuit configured to receive the input current signal at the current input node and to provide a second part of the output voltage signal at the compound stage output node based on the input current signal.In aspect 1, the first and second parts of the output voltage signal can be superimposed at the compound stage output node to provide the output voltage signal.

[0044] An aspect 2 may include or utilize the subject of aspect 1, or may optionally be combined with the subject of aspect 1 to optionally include the transimpedance circuit which has a resistor connected in series between the current input node and the compound stage output node.

[0045] An aspect 3 may include or utilize the subject of aspect 2, or may optionally be combined with the subject of aspect 2 to optionally include the first amplification circuit, which has a feedback network designed to reduce an apparent input impedance of the current input node such that it is smaller than an impedance indicator shaft of the resistor.

[0046] An aspect 4 may include or utilize the subject of any or any combination of aspects 1 to 3, or may optionally be combined with the subject of any or any combination of aspects 1 to 3 to optionally include or utilize the output gain stage configured to provide a test signal to a device under test (DUT) via an output resistance, wherein the test signal is based on the output voltage signal at the compound stage output node.

[0047] An aspect 5 may include or utilize the subject of any or any combination of aspects 1 to 4, or may optionally be combined with the subject of any or any combination of aspects 1 to 4 to optionally include or utilize the first amplification circuit which includes a feedback network designed to improve a bandwidth characteristic of the compound stage circuit.

[0048] An aspect 6 may include or utilize the subject of aspect 5, or may optionally be combined with the subject of aspect 5 to optionally include the first amplification circuit configured to provide the first part of the output voltage signal of substantially the same magnitude and phase as the input voltage signal from the first driver.

[0049] An aspect 7 may include or use the subject of any or any combination of aspects 1 to 6, or may optionally be combined with the subject of any or any combination of aspects 1 to 6 to optionally include or use the first driver, which includes a class AB driver trained to provide voltage test signals at a first speed, and the second driver, which includes a class A driver trained to provide current test signals at a second speed less than the first speed.

[0050] An Aspect 8 may include or utilize the subject of any or any combination of Aspects 1 to 7, or may optionally be combined with the subject of any or any combination of Aspects 1 to 7 to optionally include the voltage input node configured to receive the input voltage signal from the first driver in response to first control signals from a control circuit, wherein the current input node is configured to receive the input current signal from the second driver in response to second control signals from the control circuit. In Aspect 8, the control circuit may activate the first and second control signals simultaneously.

[0051] An aspect 9 may feature or utilize the subject of any or any combination of aspects 1 to 8, or may optionally be combined with the subject of any or any combination of aspects 1 to 8 to optionally feature the first and second parts of the output voltage signal, which are superimposed or combined at the compound stage output node using a summing circuit.

[0052] An aspect 10 may include or utilize the subject of any or any combination of aspects 1 to 9, or may optionally be combined with the subject of any or any combination of aspects 1 to 9 to optionally include the first amplification circuit coupled to the transimpedance circuit at the compound stage output node.

[0053] An Aspect 11 may include or use an item (such as a device, system, apparatus, method, means of performing actions or a device-readable medium containing instructions which, when executed by the device, can cause the device to perform actions, or a manufactured article) which may, for example, include or use a driver circuit for providing a test signal to a device under test (DUT).In aspect 11, the driver circuit includes a voltage buffer circuit configured to provide a first voltage output signal at an intermediate output node in response to an input voltage signal from a first driver stage, a transimpedance circuit configured to provide a second voltage output signal at the intermediate output node in response to an input current signal from another second driver stage, and an amplifier circuit configured to receive a combination signal from the intermediate output node, which has a superposition of the first and second voltage output signals, and to provide an output signal to the DUT in response to the combination signal.

[0054] An aspect 12 may include or use the subject of aspect 11, or may optionally be combined with the subject of aspect 11 to optionally include or use the first driver stage to provide the input voltage signal, and to include or use the second driver stage to provide the input current signal.

[0055] An aspect 13 may include or use the subject of aspect 12, or may optionally be combined with the subject of aspect 12 to optionally include the first driver stage configured to provide the input voltage signal with two or more discrete and non-zero signal levels, and the second driver stage to provide the input current signal with two or more discrete and non-zero signal levels.

[0056] An aspect 14 may include or use the subject of one or any combination of aspects 12 or 13, or may optionally be combined with the subject of one or any combination of aspects 12 or 13 to optionally include or use a control circuit designed to provide signal magnitude and signal timing instructions to each of the first and second driver stages.

[0057] An Aspect 15 may incorporate or utilize the subject of any or any combination of Aspects 12 to 14, or may optionally be combined with the subject of any or any combination of Aspects 12 to 14 to optionally incorporate or utilize the first driver stage to provide a signal with a relatively low velocity than the input voltage signal. In Aspect 15, the second driver stage may be configured to provide a signal with a relatively high velocity than the input current signal.

[0058] An Aspect 16 may include or use an item (such as a device, system, apparatus, method, means of performing actions or a device-readable medium containing instructions which, when executed by the device, can cause the device to perform actions, or a manufactured article) which may, for example, include or use a method for providing a digital test signal to a device under test (DUT).In aspect 16, the method may include providing a voltage test signal at a voltage input node, providing a current test signal at a current input node, buffering the voltage test signal to provide a first voltage signal part of a compound output signal, processing the current test signal to provide a second voltage signal part of the compound output signal, wherein the compound output signal has a combination of the first and second voltage signal parts, and buffering the compound output signal to provide the digital test signal to the DUT.

[0059] An aspect 17 may include or use the subject of aspect 16, or may optionally be combined with the subject of aspect 16 to optionally include the processing of the current test signal, including the use of a transimpedance circuit to receive the current test signal and, in response, to provide the first voltage signal part of the compound output signal.

[0060] An aspect 18 may include or utilize the subject of one or any combination of aspects 16 or 17, or may optionally be combined with the subject of one or any combination of aspects 16 or 17 to optionally include buffering of the compound output signal using an amplifier circuit.

[0061] An aspect 19 may include or use the subject matter of any or any combination of aspects 16 to 18, or may optionally be combined with the subject matter of any or any combination of aspects 16 to 18 to optionally include the provision of the voltage test signal using a first driver circuit belonging to a first class of signal drivers, and the provision of the current test signal using a second driver circuit belonging to another second class of signal drivers.

[0062] An aspect 20 may include or utilize the subject matter of any or any combination of aspects 16 to 19, or may optionally be combined with the subject matter of any or any combination of aspects 16 to 19 to optionally include the provision of timing and / or magnitude control signals for the first and second driver circuits and, in response, the use of the first and second driver circuits to provide the voltage test signal and the current test signal, respectively.

[0063] The process examples described here may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions capable of forming an electronic device to execute the processes described in the examples above. An implementation of such processes may include code such as microcode, assembly language code, high-level language code, or the like. Such code may contain computer-readable instructions for executing various processes. The code may form parts of computer program products. Furthermore, in an example, the code may be stored in a tangible manner on one or more volatile, non-transient, or non-volatile tangible computer-readable media, such as during execution or at other times.Examples of these tangible, computer-readable media include hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, read / write memory (RAMs), read-only memory (ROMs), and the like.

[0064] According to one aspect, a test system can use a first and various second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, for example, via an amplification circuit. The compound stage can include a buffer circuit configured to provide a first part of the voltage output signal based on a first output signal from the first driver stage, and a transimpedance circuit configured to provide a second part of the voltage output signal based on a second output signal from the second driver stage. In one example, the amplification circuit can receive a superposition signal containing the first and second parts of the voltage output signal and, in response, provide a test signal to the DUT.

Claims

[1] A combined step-down circuit (202) for a pin driver system, wherein the combined step-down circuit (202) responds to respective input signals from at least one first driver (208) and a second driver (216), and the combined step-down circuit (202) is configured to provide an output voltage signal (206) of an output gain stage at a combined step output node (306), wherein the combined step-down circuit (202) comprises the following: a voltage input node (302) configured to receive an input voltage signal from the first driver (208); a current input node (304) configured to receive an input current signal from the second driver (216); a first amplification circuit (308) configured to receive the input voltage signal at the voltage input node (302) and, based on the input voltage signal, to provide a first part of the output voltage signal (206) at the compound stage output node (306); and a transimpedance circuit (310) configured to receive the input current signal at the current input node (304) and, based on the input current signal, to provide a second part of the output voltage signal (206) at the compound stage output node; wherein the first and second part of the output voltage signal (206) are combined at the compound stage output node (306) to provide the output voltage signal (206). [2] Compound step-down circuit (202) according to claim 1, wherein the transimpedance circuit (310) has a resistance or a resistance value that is connected in series between the current input nodes (304) and the compound step output nodes. [3] Combined stage circuit (202) according to claim 2, wherein the first amplification circuit (308) has a feedback network configured to provide an apparent input impedance of the current input node (304) that is smaller than an impedance indicator shaft of the resistance or resistance value. [4] A combination stage (202) according to a preceding claim, further comprising the output amplification stage configured to provide a test signal to a test object (122) via an output resistor, wherein the test signal is based on the output voltage signal (206) at the combination stage output node. [5] Combined step-up circuit (202) according to claim 1, wherein the first amplification circuit (308) has a feedback network configured to produce a bandwidth property of the combined step-up circuit (202). [6] Combined stage circuit (202) according to a preceding claim, wherein the first amplification circuit (308) is configured to provide the first part of the output voltage signal (206) with magnitude and phase characteristics that correspond to those of the input voltage signal from the first driver (208). [7] Combined step-down circuit (202) according to a preceding claim, wherein the first driver comprises a class AB driver configured to provide voltage test signals at a first speed, and wherein the second driver comprises a class A driver configured to provide current test signals at a second speed which is lower than the first speed. [8] Combined step-down circuit (202) according to a preceding claim, wherein the voltage input node (302) is configured to receive the input voltage signal from the first driver (208) in response to first control signals from a control circuit, and wherein the current input node (304) is configured to receive the input current signal from the second driver (216) in response to second control signals from the control circuit, wherein the control circuit activates the first and the second control signals at least partially simultaneously. [9] Combined stage circuit (202) according to a preceding claim, wherein the first and second part of the output voltage signal (206) are superimposed at the combined stage output node using a summing circuit. [10] Combined stage circuit (202) according to a preceding claim, wherein the first amplification circuit (308) is coupled to the transimpedance circuit (310) at the combined stage output node. [11] Driver circuit (202, 204) for providing a test signal to a test object (122), wherein the driver circuit (202, 204) comprises the following: a voltage buffer circuit (308) configured to provide a first voltage output signal at an intermediate output node (306) in response to an input voltage signal from a first driver stage (208); a transimpedance circuit (310) configured to provide a second voltage output signal at the intermediate output node (306) in response to an input current signal from a second driver stage (216); and an amplifier circuit (204) configured to receive a combination signal from the intermediate output node (306) which has a superposition of the first and the second voltage output signals, and to provide an output signal to the test object (122) in response to the combination signal. [12] Driver circuit (202, 204) according to claim 11, further comprising the first driver stage (208) configured to provide the input voltage signal and the second driver stage configured to provide the input current signal. [13] Driver circuit (202, 204) according to claim 11 or 12, wherein the first driver stage (208) is configured to provide the input voltage signal with two or more discrete and non-zero signal levels, and wherein the second driver stage (216) is configured to provide the input current signal with two or more discrete, non-zero signal levels. [14] Driver circuit (202, 204) according to one of claims 11 to 13, which further comprises a control circuit configured to provide a signal size instruction and a signal time specification instruction to each of the first and second driver stages (208, 216). [15] Driver circuit (202, 204) according to one of claims 11 to 14, wherein the first driver stage (208) is configured to provide a first signal at a relatively lower speed than the input voltage signal, and wherein the second driver stage (216) is configured to provide a second signal at a relatively higher speed than the input current signal. [16] Method (500) for providing a digital test signal to a test object (122), wherein the method (500) comprises the following: Providing (504) a voltage test signal to a voltage input node (302); Providing (508) a current test signal to a current input node (304); Buffering (512) the voltage test signal to provide an initial voltage signal part of a compound output signal; Processing (514) the current test signal to provide a second voltage signal part of the compound output signal, wherein the compound output signal comprises a combination of the first and the second voltage signal part; and Buffering (518) of the compound output signal to provide the digital test signal to the test object (122). [17] Method (500) according to claim 16, wherein the processing (514) of the current test signal comprises the use of a transimpedance circuit (310) to receive the current test signal and in response provide the second voltage signal part of the compound output signal. [18] Method (500) according to claim 16 or 17, wherein the buffering (518) of the compound output signal comprises amplifying the compound output signal. [19] Method (500) according to any one of claims 16 to 18, wherein providing (504) the voltage test signal comprises the use of a first class AB driver circuit and wherein providing the current test signal comprises the use of a second class A driver circuit. [20] Method (500) according to claim 19, further comprising providing a time control signal and / or a quantity control signal to the first or second driver circuit and, in response, using the first and second driver circuit to provide the voltage test signal or the current test signal.

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