Storage devices and methods for operating them

Abstract

Storage device comprising the following features: a plurality of memory cells (12); a plurality of rating elements (14), wherein each rating element (14) is connectable to a memory cell (12) of the storage device; a connecting unit (16) configured to connect the plurality of memory cells (12) to a first assignment of rating elements (14) in a first state and to connect the same plurality of memory cells (12) to at least a second assignment of rating elements (14) in a second state; wherein in the second state at least one memory cell (12) of the plurality of memory cells is connected to a different rating element (14); a rating unit (18) configured to control the connecting unit (16) from the first state to the second state;wherein the evaluation unit (18) is configured to evaluate the majority of memory cells (12) in the first state in order to obtain a first evaluation result (441); and to evaluate the majority of memory elements (12) in the second state in order to obtain a second evaluation result (442).

Description

[0001] The present disclosure relates to storage devices, methods for operating them, and computer programs that implement such methods. In particular, the present disclosure relates to a read amplifier reordering for rereading a memory.

[0002] Storage devices can have multiple memory cells. Memory cells can be evaluated by evaluation elements. Examples of memory cells include transistors, resistive cells, and the like. Such cells can be written to or programmed and can be read.

[0003] Reading a memory cell can involve an evaluation of a physical parameter of the cell, e.g., a voltage or potential detectable at the cell, a current flowing through a cell, and / or an electrical resistance that can be measured.

[0004] There is a need for reliably operating storage devices.

[0005] According to an example, a storage device comprises: a plurality of memory cells, a plurality of rating elements, each rating element being connectable to a memory cell of the storage device, and a connection unit configured to connect the plurality of memory cells to a first assignment of rating elements in a first state and to connect the same plurality of memory cells to at least a second assignment of rating elements in a second state. In the second state, at least one memory cell of the plurality of memory cells is connected to a different rating element. The storage device further comprises a rating unit configured to control the connection unit from the first state to the second state.The evaluation unit is designed to evaluate the majority of memory cells in the first state to obtain a first evaluation result, and to evaluate the majority of memory cells in the second state to obtain a second evaluation result.

[0006] According to an example, a storage device comprises a plurality of memory cells and a plurality of evaluation elements, each evaluation element being connectable to a memory cell of the storage device. The storage device includes a connection unit configured to connect the plurality of memory cells to a first assignment of evaluation elements in a first state and to connect the same plurality of memory cells to a second assignment of evaluation elements in a second state. In the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element. The device further includes an evaluation unit configured to control the connection unit from the first state to the second state.The device further comprises a memory in which error information is stored, indicating that a read operation using a specific pair consisting of a memory cell from the plurality of memory cells and an evaluation unit is prone to errors in the first state. The evaluation unit is configured to read the error information from the memory and to derive an evaluation result for the plurality of memory cells based on a read operation using the second state, based on the error information.

[0007] According to an example, a storage device comprises: a memory cell, a plurality of rating elements, each rating element being connectable to the memory cell of the storage device, a connecting unit configured to connect the memory cell to a first rating element in a first state and to connect the memory cell to a second rating element in a second state, and a rating unit configured to obtain a first rating result of the memory cell in the first state and to obtain a second rating result of the memory cell in a second state. The rating unit is configured to determine a deviation between the first rating result and the second rating result and to store deviation information in a memory of the storage device.

[0008] Other examples include methods for operating a storage device and a computer program.

[0009] Further examples are defined in the dependent claims.

[0010] The following examples describe the figures shown in the accompanying illustrations. Fig. 1a a schematic block diagram of a storage device according to an example and in a first state; Fig. 1b a schematic block diagram of the storage device Fig. 1a in a second state; Fig. 2a a schematic block diagram of a storage device according to another example and in a first state thereof; Fig. 2b a schematic block diagram of the storage device Fig. 2a in a second state; Fig. 3 a schematic block diagram of a storage device according to an example with a reorder logic and an inverse reorder logic; Fig. 4. A schematic block diagram of a storage device according to an example with a memory for reading and / or writing error information; Fig. 5a a schematic representation of a possible distribution of a set of memory cells on the ordinate of a graph, with a parameter to be recorded on the abscissa, in an ideal state; Fig. 5b a schematic representation of the distribution from Fig. 5a in a disturbed state; Fig. 6a a schematic block diagram for obtaining an initial evaluation result in a first state of an example of a storage device; Fig. 6b an example of a second state of education from Fig. 6a; Fig. 7 a schematic flowchart of a procedure according to an example; Fig. 8 a schematic flowchart of a procedure according to another example and Fig. 9 A schematic flowchart of a procedure according to an example for deriving deviation information.

[0011] Identical or equivalent elements, or elements with the same or equivalent functionality, are designated with the same or equivalent reference numbers in the following description, even if they appear in different figures.

[0012] In the following description, a number of details are given for a more thorough explanation of embodiments of the present disclosure. However, it is evident to the person skilled in the art that embodiments of the present disclosure can be implemented without these specific details. In other cases, known structures and devices are not shown in detail, but rather in the form of block diagrams, in order to avoid obscuring embodiments of the present disclosure. Furthermore, features of the different embodiments described below can be combined with one another, unless expressly stated otherwise.

[0013] The examples described here concern storage devices that have memory cells which can be programmed and / or read. In particular, examples include, but are not limited to, non-volatile memory such as EEPROM (electrically erasable programmable read-only memory), RRAM (resistive random access memory), PCRAM (phase change random access memory), FeRAM (ferroelectric random access memory), MRAM (magnetoresistive random access memory), CBRAM (conductive bridging random access memory).Examples include an evaluation of programmable memory cells, which is also applicable without restriction to volatile memory such as SRAM (static random access memory) and / or DRAM (dynamic random access memory).

[0014] The examples described here relate to improving the reliability of storage devices, especially semiconductor storage devices, by providing a robust read operation.

[0015] Examples include evaluation elements that can evaluate such memory cells. An evaluation element can be seen as an element that provides a result for a measured value with respect to the memory cell it evaluates, e.g., an analog value. Such a value could be, for example, a current value, a voltage value, and / or a resistance value.

[0016] A result of the evaluation unit can be further evaluated, e.g., quantified, so that it has a specific meaning. For example, the value obtained from the evaluation unit can be viewed as a logical 0 or logical 1, whereby the assignment of evaluation values ​​to logical meanings is possible without restriction.

[0017] Fig. Figure 1a shows a schematic block diagram of a storage device 10 according to an example. The storage device 10 has a plurality of memory cells 121 and 122, where the number of memory cells can be greater than 2, e.g. at least 3, at least 5, at least 10, at least 100 or even several thousand.

[0018] The storage device 10 further comprises a plurality of evaluation elements 141 and 142, wherein the number of evaluation elements can be greater than 2, e.g., at least 3, at least 5, at least 8, at least 16, at least 32, or any other number. In some examples, the number of implemented evaluation elements is less than the number of memory cells to be evaluated by the evaluation elements 14. For example, the evaluation elements, or a subset thereof, can be associated with memory cells to be read during one operation and with different memory cells for different read operations. Each evaluation element 141 and / or 142 is connectable to one memory cell 121 and / or 122 of the memory cells.

[0019] The storage device 10 has a connecting unit 16. As in connection with Fig. As described in Figure 1b, the connecting unit 16 is configured to connect the memory cells 121 and 122 with a first assignment of evaluation elements 141 and 142 in a first state and to connect the same plurality of memory cells 121 and 122 with a second assignment of the evaluation elements 141 and 142 in a second state. This means that in the second state, which is, for example, in Fig. As illustrated in Figure 1b, at least one memory cell 121 and / or 122 is associated with a different evaluation element from the majority of memory cells. Although Fig. 1a and Fig. 1b. If examples of implementation show a switching or change between two assignments, they are not limited to this, but allow two or a higher number of assignments.

[0020] The storage device 10 has an evaluation unit 18 which is configured to remove the connecting unit 16 from the first state. Fig. 1a into the second state from Fig. 1b to control. The evaluation unit 18 is configured to evaluate the majority of memory cells 121 and 122 in the first state to obtain a first evaluation result, i.e., a read result, and to evaluate the majority of memory cells in the second state to obtain a second evaluation result. This means that the evaluation unit 18 can read the same memory cells using different assignments of evaluation elements 14.

[0021] Fig. Figure 1b shows a schematic block diagram of the storage device 10 in the second state, in which the assignment or connection between memory cells 121 and 122 provided by the linking unit 16 with respect to the evaluation elements 141 and 142 is changed. In the first state from Fig. 1a Memory cell 121 is evaluated by evaluation element 141, and memory cell 122 is evaluated by evaluation element 142, as indicated by the solid lines. Similarly, the solid lines in Fig. 1b indicates that in the second state, memory cell 121 is evaluated by evaluation element 142, and memory cell 122 is evaluated by evaluation element 141. Such a changed assignment can alter the order or sequence of the contents of memory cells 121 and 122 at evaluation unit 18. However, since evaluation unit 18 can control link unit 16, evaluation unit 18 can take this knowledge into account and can rearrange the received bits to maintain or regenerate a sequence of bits.

[0022] Examples are based on the idea of ​​changing assignments between rating elements and memory cells. This can be done in different ways, for example through pairwise changes, ring-based changes (e.g., by connecting each rating element to the next memory cell along a specific direction), or through other solutions.

[0023] This means that the evaluation unit 18 can yield two comparable results with reference to the same memory cells 121 and 122. This can prevent errors in memory cells that might occur when an inaccurately programmed or defined memory cell is read by an inaccurate evaluation unit. Such an error can be avoided by changing the evaluation unit used with the memory cell, as will be described in more detail later.

[0024] In the first and second states, each of the majority of memory cells can be associated with an evaluation unit. It is possible, but not necessary, for each of memory cells 121 and 122 to be associated with a different evaluation unit. For example, evaluation unit 18 can have access to information indicating that some of the memory cells and / or evaluation units are considered error-prone or weak, so that errors occurring when reading these memory cells or using such an evaluation unit can be handled by reconnecting the respective memory cell or evaluation unit, optionally but not necessarily, to reconnect other elements. Error-prone can be understood as having a higher probability of failure compared to a reference state, e.g., higher in the first state than in the second state, or vice versa.

[0025] The evaluation results obtained in the first state and the second state can each be a bit sequence, i.e., a first bit sequence in the first state and a second bit sequence in the second state. The evaluation unit 18 can be configured to assign a value read from a memory cell to the same bit position in the first bit sequence and in the second bit sequence, which can be described as inverse reordering, counteracting the reordering from the first state to the second state. For example, the values ​​of the memory cells can each be assigned to the same, unchanged bit positions.For example, when changing from the first state with an unchanged assignment (which in this example allows memory cell 121 to be assigned the assignment element 141) to the second state, in which the same memory cell 121 is assigned a different assignment element 142, the reordering can be adjusted accordingly. This allows the reordering to be used in both states or only in those states where there is a deviation from a reference state, such as the first state, with regard to the assignment.

[0026] Fig. Figure 2a shows a schematic block diagram of a storage device 20 according to an example and in a first state thereof. Fig. Figure 2b shows a schematic block diagram of the storage device 20 in a second state.

[0027] Compared to storage device 10, storage device 20 can be adapted to use at least one different evaluation element 143, which is unused in the first state. For example, memory cell 121 can be evaluated using evaluation element 141, and memory cell 122 can be evaluated using evaluation element 142. In the second state, memory cell 121 can be evaluated using evaluation element 142. Optionally, evaluation element 141 can be used to evaluate memory cell 121. For example, in the second state, an evaluation element 143 can be connected to memory cell 122.

[0028] This means that, compared to the first state, at least one memory cell 121 or 122 in the second state is associated with a different evaluation element. This different evaluation element may be unused in the first state or it may be used for a different memory cell in the first state.

[0029] Fig. Figure 3 shows a schematic block diagram of a storage device 30 according to an example. The storage device 30 has a plurality of memory cells 121 to 12. M on, whereby a memory field or an arrangement of 12 memory cells is provided.

[0030] The connection unit 16 can implement a reordering logic. The connection unit 16 can have circuits that receive a set of essentially analog signals from the memory cells 121 and 122 in order to feed each of these values ​​in different states of the storage device 30 to different evaluation elements. The evaluation elements can convert the set of analog values ​​into a set of essentially digital values, i.e., a result of the evaluation elements 141 to 14. N ...convert. This means, according to an example, that an evaluation element can have a read amplifier or other element for providing a digital value based on an analog value derived from the memory cell. A sequence of these output values ​​can be controlled by the control signals generated by the evaluation unit 18.

[0031] The evaluation unit 22 may have or implement an inverse reorder logic 22. The inverse reorder logic 22 may be implemented at least partially in software and / or at least partially in hardware, including a purely software implementation and a purely hardware implementation. The inverse reorder logic can rearrange the sequence of bits read from the memory field 12 to undo the changed order that was modified by the reorder logic of the linking unit 16.This means that the inverse reordering of the evaluation unit can be inverse to a reordering logic implemented by the linking unit 16, and can be configured to change an assignment of the evaluation element to a bit position from the first state to the second state inversely to the reordering logic, in order to keep a bit position of a single memory cell, a plurality of memory cells, or all memory cells constant or unchanged in the first bit sequence and in the second bit sequence. This can make it possible to obtain an identical sequence of bits from the evaluated memory cells when the assignment of evaluation elements changes. The evaluation unit 18 can be configured to provide the first bit sequence and the second bit sequence with the same or identical order of bits, i.e., the representation of values ​​of memory cells in the bit sequences can remain unchanged.

[0032] The evaluation unit 18 can include an error detection unit 24, so examples are provided according to which the evaluation unit is configured to determine bit errors in the received result. This means that information about stored bits in the memory field 12 can be fed to the evaluation unit 18. For example, the use of error detection codes or error correction codes can make it possible to detect the occurrence of bit errors in the readout of the evaluated memory cells, i.e., in the sequence of bits. An error correction code can have the ability to detect a certain initial set of bit errors and possibly to correct a certain, usually smaller, second set of bit errors.

[0033] Storage devices, as exemplified, can be configured to always read the majority of memory cells, i.e., the target data, using the first and second states. However, to save time and / or energy, for example, devices can be implemented to perform a read operation in the second state when necessary, e.g., when the error detection logic 24 determines that a number of bit errors in the first evaluation result, i.e., the first state, exceeds a number of errors according to a predefined threshold, e.g., a number of correctable errors. For example, the number of bit errors may exceed the number that can be corrected but remain within a number that is still detectable by the error detection unit 24 and by storing information in the memory cells using an error correction code.

[0034] The storage device 30 can, for example, include a control unit 26 as part of the evaluation unit 18. The control unit 26 can implement state logic and can receive a result regarding the errors that have occurred from the error detection unit 24. The control unit 26 can further be connected to the linking unit 16 and the inverse reorder logic 22 to control the storage device 30 from the first state to the second state. After the storage device 30 has been set to the second state, the memory cells can be read again. For example, the evaluation unit 18 can be configured to determine that a second number of bit errors occurring in the second evaluation result in the second state is at most the number of errors that are correctable, i.e., within the capability of the error correction code.The evaluation unit 18 can be configured to use the second, correctable evaluation result as the result of a read operation from the storage device. This can include correcting bit errors.

[0035] In such a scenario, two selection operations are performed to provide a final result, e.g., by using the second evaluation result.

[0036] However, examples are not limited to such a scenario. According to one example, a storage device such as storage device 10, 20 and / or 30 can be configured to perform at least one third read operation using a third allocation of evaluation units and memory cells, which differs from the first allocation in the first state and the second allocation in the second state.

[0037] The evaluation unit can be configured to determine a combined evaluation result as a majority decision, for example, by comparing the first and second results for coincidence. According to examples, the evaluation unit 18 can control the memory device for at least a third assignment to obtain at least a third evaluation result from the majority of memory cells in such a third state. With such a third result (or a higher number), the decision-making process can be improved by allowing, for example, a 2:1 decision or the like within the majority decision. Alternatively, such a majority decision can be performed group by group for groups of memory cells, with each group of memory cells containing at least one memory cell, thus including a decision for individual cells.By obtaining three or more results regarding a single memory cell, a group of the same, or the sentence to be read, different criteria can be implemented in the evaluation result to decide which result should be used as a basis and / or how these results should be interpreted.

[0038] Examples are not limited to selecting either the first or second result (or a higher number or iteration) or to making a majority decision. For instance, if the evaluation unit has knowledge of which evaluation element and / or memory cell might be faulty, an overall or combined result can also be obtained by combining different evaluation results from different readouts, e.g., by combining bit values ​​considered to be error-free or by excluding faulty bits.

[0039] According to one example, an extension for n data reads, i.e., n states with different read amplifier assignments, can enable a bitwise majority decision to be performed on the n read results, the derivation of which is, for example, sequential. With respect to undecided bits, which can occur for a number of n = 2*k read operations, such bits can be marked as (delete) for processing in suitable ECC; that is, the bit position can be marked for the ECC. Such information can be stored together with error information 32 and can, for example, indicate that a bit error exists at a specific bit position. Writing the error information 32 can thus enable a learning system that can, for example, allow error-prone combinations of read operations to be excluded.Alternatively or additionally, and as a possibility for any value of n, all unstable bits can be marked as deletions.

[0040] Alternatively or additionally, a storage device, such as storage device 10, 20, and / or 30, can be implemented to reread the memory cells with different assignments of evaluation units until a result is obtained that has at most a correctable number of errors. This means the evaluation unit can be configured to repeat a read operation using different assignments or evaluation elements of memory cells until a correctable read result is obtained or until a termination criterion occurs, such as a predefined maximum number of read operations, a timeout, a control command, or the like.

[0041] In other words, the memory array essentially provides analog values ​​that represent data when read. The evaluation elements, e.g., read amplifiers, can include or represent any circuitry that accepts one or more essentially analog values ​​from a memory and converts them into one or more digital data bits. For example, exactly one analog value is converted into one digital bit. This can allow one bit of information to be stored per memory cell. However, one or more memory cells can be implemented as a multi-level memory, where one analog value is converted into more than one digital bit. Alternatively, or additionally and optionally, a plurality of memory cells of the storage device 10, 20, and / or 30 can be implemented to form a multi-cell memory where more than one analog value is converted into one digital bit.

[0042] The error detection logic of error detection unit 24 can be understood as circuits that determine whether the data is correct or not by checking certain properties of a set of data bits. This can be a simple parity check logic that verifies whether the parity of a set of data bits has the expected value, i.e., whether the number of zeros or ones in the set is even or odd, as expected. Alternatively or additionally, the error detection logic can be logic that checks whether a checksum (e.g., a CRC sum; CRC = cyclic redundancy check) for the set of data bits has the expected value. Alternatively or additionally, the error detection logic can implement EDC logic (EDC = error detection code) that checks the conformity of the set of data bits with a specific code.Alternatively or additionally, this can be an ECC logic (ECC = error correction code) that checks the set of data bits according to a specific code and corrects it (if necessary and possible), but also detects when a correction is not possible or meaningful. These examples also include a combination of two or more of these possibilities. If a data inconsistency is generated by evaluation unit 18, the error detection logic can initiate a reread. The maximum number of rereads can be limited to a predefined number. The error detection logic can be implemented in hardware and / or software.

[0043] The state logic or control unit 26 can also be implemented in hardware and / or software. It can implement logic that continuously controls the reordering logic or linking unit 16 and the inverse reordering logic 22 such that their data reordering balances out overall. At least two different orders exist or are implemented; that is, there are at least two states in which the state logic can be. According to examples, several different states exist; that is, at least three, at least four, at least five, at least six, or even more. The initial read operation for some data is performed either with a predefined initial state or only with the current state, that is, the last used state. The state of the state logic, i.e.,The implemented reordering is changed, for example, when the error detection logic detects a data inconsistency and a reread is initiated. This state change can be deterministic (e.g., through the use of a counter or any other deterministic finite state machine) or random.

[0044] The inverse reorder logic can also be implemented in hardware and / or software. It can include circuitry or a control element such as a processor, a field-programmable gate array (FPGA), a microcontroller, or the like, which accepts a set of digital signals and outputs the received values ​​on a set of digital signals, the order of which is controlled by the control signals generated by the state logic. This means the inverse reorder logic can reorder the digital bits based on the order provided by the link unit 16. The inverse reorder logic can undo the reordering performed by the reorder logic, so that the overall allocation of data bits can remain unchanged.

[0045] As described, some parts of the described logic, e.g., the state logic and the inverse reordering logic, can be implemented at least partially in software.

[0046] Fig. Figure 4 shows a schematic block diagram of a storage device 40 according to an example. The storage device 40 may have at least some parts of the same design and / or the same elements as the storage device 30. The evaluation unit 18 of the storage device 40 may be configured to read error information from a memory 28, to which the evaluation unit 18 has access, indicating that a specific pair from a memory cell 12 i of the majority of memory cells and a rating element 14 jis prone to errors, i.e., likely to cause errors. The evaluation unit 18 can be trained to obtain the second evaluation result based on the first evaluation result, which is based on the specific pair indicated by the error information, and / or can be trained to avoid the specific pair when evaluating the majority of memory cells.

[0047] This means that if it is detected that the evaluated bit sequence has errors, and if the error information 32 indicates that an error-prone pair of memory cell and evaluation unit was used to obtain the evaluation result, the evaluation unit 18 can make the decision to perform a reread.

[0048] This can be considered a posteriori analysis, even though the obtained bit sequence is of low quality. For example, the evaluation unit can also be trained to evaluate the error information 32 a priori. If, for instance, the error information 32 indicates that the upcoming read operation, e.g., in the current state, will use an error-prone combination of memory cell and evaluation unit, the evaluation unit 18 can decide to change the state. This can make it possible to obtain an initial result of a first read operation in a different state, thus avoiding the use of the specific pair and preventing a read operation that is expected to result in errors.

[0049] The error information 32 can, for example, be stored in the memory 28 during manufacturing. Alternatively or additionally, the error information 32 can be generated or provided by the evaluation unit configured to store the error information 32. The error information 32 can, for example, relate to stuck bits or memory cells that are stuck on a specific logical value, to error-prone bits or memory cells, and / or to error-prone combinations of memory cells and evaluation units. For example, the evaluation unit 18 can evaluate the read operations while monitoring which cell was evaluated by which evaluation unit and can derive the error information 32 from this.

[0050] Examples from the present disclosure enable the design of storage devices for determining the result of a read operation from a plurality of memory cells without the use of an error correction code, e.g., using a code capable only of detecting errors, i.e., an error detection code such as a code that uses parity bits. For example, if a final result, e.g., by majority vote, is judged by a combination of several read operations and / or taking into account error information, storage devices can be provided that can perform read operations with acceptable reliability, thereby making the use of an error correction code optional, thus saving resources, computational complexity, memory cells, evaluation units, or the like.

[0051] According to an example, using the error information, which indicates that a read operation using a specific pair of a memory cell from the plurality of memory cells and an evaluation unit in the first state is error-prone, to obtain an evaluation result of the plurality of memory cells based on a read operation using the second state based on the error information, i.e., optionally avoiding reading in the first state, can be implemented as an alternative to obtaining both results.

[0052] Fig. Figure 5a shows a schematic representation of a possible distribution of a set M of memory cells on the ordinate of a graph, with a parameter P to be captured, for example a current I, a voltage V, or a resistance R, on the abscissa. While, for example, the number of cells is the same for cells programmed to logical 0 and cells programmed to logical 1, a first distribution 341 and a second distribution 342 show a desired configuration of a memory device according to which a maximum number of programmed cells are spaced apart within the device's specification. However, due to defects in the manufacturing of memory cells, some memory cells programmed to one value, e.g., a logical 0, exhibit an analog value higher than the typical value, whereas memory cells of distribution 342 programmed to the respective other value, e.g.,to a logical 1, cells may have a comparatively low value of the analog parameter. Within the design of the memory device, a window 36 may exist between distributions 341 and 342. The window 36, which may also be called a gap, may have a comparatively small width, e.g., at most 30%, at most 20%, or at most 10% of a base value of the memory cell, e.g., 30%, 20%, or 10% of 30 µA.

[0053] Within window 36, e.g. at its midpoint or at its mean, a discrimination threshold 38 can be established. R a rating element 14 must be specified. This means that even if a memory cell has a minimum value of distribution 342, it can be evaluated as a programmed logical 1. Alternatively, even if the cell has a maximum value within distribution 341, it can be evaluated using the discrimination threshold 38. Rcan be judged as being programmed to a logical 0.

[0054] Fig. Figure 5b shows a schematic representation of the distribution from Fig. 5a, which is extended to a possible non-ideal behavior of a plurality of evaluation elements, e.g., the evaluation elements 14 of the storage devices 10, 20, and / or 30. These evaluation elements may exhibit a distribution within their real discrimination thresholds, which may lead to the effect that some of the discrimination thresholds implemented by the storage device lie within the distribution 341 or 342 of programmed memory cells. For example, with respect to a discrimination threshold 381, which is relative to the parameter P and relative to the ideal reference discrimination threshold 38 RIf the threshold is lower, memory cells of distribution 341 that have a higher value than the discrimination threshold 381 may be misinterpreted, e.g., within an error range 421. The same applies to an error range 422, which may be obtained through discrimination thresholds that are lower than the reference discrimination threshold 38. R are higher, so that memory cells programmed to a logical 1 can be interpreted as 0 if they are evaluated by an evaluation element with a high or even excessively high discrimination threshold, such as for discrimination threshold 38. N illustrated.

[0055] Memory cells within error ranges 421 and 422 can form a so-called "bad pair" with a rating element that itself exhibits a high deviation from a design value. Such pairs can be avoided or modified by the examples described here.

[0056] In other words, when reading a non-volatile memory, an analog property of a memory cell (e.g., its resistance) can be evaluated by a read amplifier. The different cells of a memory array can (inherently or, for example, due to data storage problems) have different analog properties, so that the properties of all cells in combination form property distributions 341 and 342, as shown in Fig. 5a shown. A reading amplifier can determine whether the analog property for a cell is above or below a discrimination threshold 38, and can accordingly assign logical values, e.g. 0 and 1, as also shown in Fig. 5a shown. A set of actually implemented read amplifiers may exhibit some random and chip-related variations in the exact values ​​of the discrimination thresholds, as shown in Fig. 5b shown. The actual values ​​can be adjusted, for example, by the target differentiation threshold of 38. RThe discrimination threshold may be normally distributed. However, since the discrimination threshold of some reading amplifiers can overlap with distributions 341 or 342, this can lead to reading errors that might not occur with ideal reading amplifiers.

[0057] These read errors can be detected using special codes for the stored data, such as error detection codes and / or error correction codes. Some codes can detect and correct incorrect bits in a set of data bits up to a certain number. However, if too many read errors occur simultaneously, correction with the code may no longer be feasible, even though the errors are still detected. In the event that uncorrectable errors are detected, a retry or reread can be initiated in the hope that random fluctuations in the read process might lead to correct, or at least correctable, data in the resulting second state. Since the actual cause of the read error is not addressed, such a solution can, at best, have a limited success rate.

[0058] The root cause of the read error may lie in the faulty implementation of the read amplifiers, caused, for example, by fluctuations during manufacturing, i.e., at least partially by differing discrimination thresholds. A read amplifier with a particularly pronounced threshold shift may fail to correctly read marginal cells that provide an analog value of the parameter close to the read window, e.g., read amplifiers 141 and 14. N , which pass through thresholds 381 and 38 respectively Nare shown. It can be expected that only a small number of read amplifiers will coincide with a small number of marginal cells involved in this error. This allows examples to be based on the principle that reordering or reassigning the read amplifiers offers a high probability that the read error will not be present in the obtained second state. In the event that a read error has been detected for some initially read data, initiating a reread can help. With a new assignment of the read amplifiers, at least some or even all of the read amplifiers can be used to evaluate the properties of a cell that differs from the initial read. With a considerable probability, the coincidences described above can be avoided, and the data can be read correctly, or at least in a correctable manner, upon rereading.If necessary, multiple rereads with different assignments of the read amplifiers can be triggered until the data is read correctly. A relatively small logic can be used to implement such examples.

[0059] Fig. Figure 6a shows a schematic block diagram for obtaining a first evaluation result 441, e.g., in a first state of a storage device 10, 20, and / or 30. For example, four memory cells 121, 122, 123, and 124 are evaluated using four evaluation elements 141, 142, 143, and 144. For better understanding of the example, information A, B, C, and D is stored in memory cells 121–124, where each letter represents part of a bit, a bit, or a set of bits. As illustrated in connection with the evaluation unit 18, in the first state, information A is evaluated by evaluation element 141, where evaluation elements 141–144 are numbered with Arabic numerals for clarity. This means that information A is evaluated by evaluation unit 1, information B by evaluation unit 2, information C by evaluation unit 3, and information D by evaluation unit 4.This can be interpreted at assessment unit 18 as a sequence of information A, B, C and D.

[0060] Fig. 6b shows an example of a second state of education from Fig. 6a, in which the evaluations of memory cells 121 and 122 on the one hand, and 123 and 124 on the other, were exchanged pairwise. This means that information A is evaluated with the evaluation element 142, while information B is evaluated with the evaluation element 141. This change in the order or sequence of the information can be obtained by using the evaluation unit 18, e.g., inverse reordering logic, to reorder the obtained information, so that the sequence A, B, C, and D is still obtained in the second state 442. However, if a pair 121 / 141, 122 / 142, 123 / 143, and / or 124 / 144 is faulty, there is a chance that the evaluation result 442 in the second state will not have such a fault, will have faults in other places, and / or will have a smaller number of faults. Examples are also valid without restriction in the opposite direction, i.e., when changing from the illustrated second state Fig. 6b into the first state from Fig. 6a. Examples also allow for a change in the connection between a memory cell and a rating element that differs from a pairwise exchange, e.g. as a ring-based change, e.g. by connecting each rating element to the next memory cell along a specific direction, adding and / or removing a rating unit from the assignment, or in other ways.

[0061] Fig. Figure 7 shows a schematic flowchart of a method 700 according to an example. Method 700 can be used, for example, to operate the devices 10, 20, and / or 30. In 710, the plurality of memory cells are connected with a first assignment of evaluation elements in a first state. In 720, the same plurality of memory cells are connected with a second assignment of evaluation elements in a second state such that in the second state, at least one memory cell from the plurality of memory cells is connected with a different evaluation element. In 730, the plurality of memory cells are evaluated in the first state to obtain a first evaluation result, and in the second state, the plurality of memory elements are evaluated to obtain a second evaluation result.730 can be subdivided and, for example, partially executed in conjunction with 710, resulting in the first state, and partially executed together with 720, resulting in the second state.

[0062] Fig. Figure 8 shows a schematic flowchart of a procedure 800 according to an example, which can be used, for instance, to operate the storage device 10, 20, and / or 30. In 810, the plurality of memory cells are connected with a first assignment of evaluation elements and in a first state. 810 can correspond to 710. In 820, the same plurality of memory cells, as described in connection with 720, can be connected with a second assignment of evaluation elements and in a second state such that in the second state, at least one memory cell from the plurality of memory cells is connected with a different evaluation element. In 830, error information is read from a memory, the error information indicating that a read operation using a specific pair of a memory cell from the plurality of memory cells and an evaluation unit in the first state is error-prone.An evaluation result for the majority of memory cells is based on a read operation using the second state based on the error information.

[0063] Examples are based on a reordering or reassignment of evaluation elements or read enhancers if a read error is detected for some data. A subsequent reread of the same data can be performed with a different assignment of read enhancers to the data bits, which can improve the probability of reading correct or at least correctable data, or data with a smaller number of errors.

[0064] Instead or additionally, to improve the reliability of a memory, the area of ​​the read amplifiers can be reduced, accepting a resulting lower accuracy of the discrimination threshold, which can be compensated for by the described reread scheme. This means that at least some of the avoidable errors can be invested in lower accuracy of the evaluation elements. Alternatively or additionally, the power consumption of the read amplifiers can be reduced, again accepting a resulting lower accuracy of the discrimination thresholds, which can also be compensated for by the described reread scheme.

[0065] As one example illustrates, an application of the examples described here is the testing and identification of read amplifiers. An entire distribution of a set of cells can be read with multiple read amplifiers, with their differing thresholds becoming directly apparent. This can be useful or even crucial when the read amplifiers are used to shape the distributions during programming. In such cases, the absolute cell distribution can be modulated by and / or normalized to variations in the read amplifiers, which, for example, affects programming load or storage. The read amplifier variation can then be detected by reading the same cells with different read amplifiers, as illustrated by the examples described here.

[0066] The examples described here relate to the use of deviations between evaluation units to avoid or reduce reading errors. However, the teaching of the present disclosure is not limited to this. Examples also relate to the determination of a deviation, for example, in connection with Fig. As described in 5b, between the valuation units in the sense of balancing them.

[0067] Fig. Figure 9 shows a schematic flowchart of an example procedure 900 according to an example. In 910, a memory cell is connected to a first evaluation element in a first state, and a first evaluation result of the memory cell is obtained, e.g., by reading the memory cell. In 920, the same memory cell is connected to a second, different evaluation element in a second state. A second evaluation result of the memory cell is obtained, e.g., by performing another read. In 930, a deviation between the first evaluation result and the second evaluation result is determined in order to obtain deviation information. The deviation information can relate to digital information, but can, in particular, relate to a deviation in the readout result of the analog value.For example, different analog values ​​can be used to determine the deviation information, with the different analog values ​​being obtained in the first state and the second state. At 940, the deviation information can be stored in a memory. The deviation information can, for example, be stored as deviation information 33 in memory 28, which is located, for example, in . Fig. Figure 4 illustrates this. This deviation information may provide a type of correction value that can be taken into account when performing further operations.

[0068] A storage device, such as storage device 10, 20, 30, and / or 40, may store deviation information, such as deviation information 33, or it may otherwise have access to it. The deviation information may indicate a deviation between the behavior of evaluation units, such as a value that represents an offset with respect to a reference value, such as threshold 38. R caused. The storage device, e.g., the evaluation unit, may be configured to correct the first evaluation result and / or the second evaluation result using the deviation information, e.g., by applying it as a correction value and / or correction factor.

[0069] Method 900 can be performed, for example, by the storage device itself, but also by a calibration device of any kind. A storage device according to the examples thus comprises at least one storage cell, e.g., a reference cell, and a plurality of evaluation elements, each evaluation element being connectable to the storage cell of the storage device. The storage device has a connection unit configured to connect the storage cell to a first evaluation element in a first state and to connect the storage cell to a second evaluation element in a second state. The storage device further comprises an evaluation unit configured to obtain a first evaluation result of the storage cell in the first state and to obtain a second evaluation result of the storage cell in a second state.The evaluation unit is configured to determine deviation information between the first evaluation result and the second evaluation result and to store this deviation information in a memory of the storage device. For example, and with reference to storage devices 10, 20, 30, and / or 40, a reference memory array can be connected to the connection unit 16, which can also be part of the test device. However, the evaluation elements 14 can be part of a storage device to be calibrated later. According to an example, storage device 10, 20, 30, and / or 40 can use its own memory cells, i.e., the memory array 12, for internal determination. For example, each evaluation unit adapted to be connected to a specific memory cell during later operation, e.g.,The different states are evaluated or taken into account with reference to the deviation information, the respective information being stored in a memory such as memory 28. This means that a storage device according to the examples can have an evaluation unit configured to determine deviation information for the same memory cell based on different evaluation results obtained with different evaluation elements 14, and / or can be configured to read such deviation information from a memory, the deviation information indicating a deviation between the behavior of evaluation units in order to enable a correction of the first evaluation result and / or the second evaluation result using the deviation information.

[0070] Although Method 900 is described in connection with a single memory cell, it can also be performed in parallel for multiple memory cells. Method 900 can be used to label at least some or even all of the memory cells of a memory array, or at least some or all of the rating elements.

[0071] It is noted that actions of procedures 700, 800 and 900 can be combined in any way, i.e., that procedures 800 and / or 900 can be carried out at least partially together with procedure 700 or vice versa, and / or that procedure 900 can be carried out at least partially together with procedure 800 or vice versa.

[0072] Although some aspects related to a device have been described, it is clear that these aspects also constitute a description of the corresponding process, where a block or device corresponds to a process step or a feature of a process step. Similarly, aspects described in connection with a process step also constitute a description of a corresponding block, element, or feature of a corresponding device.

[0073] Depending on specific implementation requirements, examples of the present disclosure may be implemented in hardware or in software. The implementation may be carried out using a digital storage medium, such as a floppy disk, DVD, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, on which electronically readable control signals are stored that interact (or can interact) with a programmable computer system to perform the respective procedure.

[0074] Some examples according to the present disclosure include a data carrier having electronically readable control signals capable of interacting with a programmable computer system to perform one of the methods described herein.

[0075] In general, examples of the present disclosure can be implemented as a computer program product with program code, wherein the program code is effective in performing one of the methods when the computer program product runs on a computer. The program code can, for example, also be stored on a machine-readable medium.

[0076] Other examples include the computer program for performing one of the procedures described herein, which is stored on a machine-readable medium.

[0077] In other words, an example of the procedure is a computer program that includes program code for performing one of the procedures described herein when the computer program is run on a computer.

[0078] Another example of a process is therefore a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the processes described herein is recorded.

[0079] Another example of a procedure is a data stream or a sequence of signals that represents the computer program for carrying out one of the procedures described herein. The data stream or sequence of signals can be configured, for example, to be transferred via a data communication connection, such as the internet.

[0080] Another example includes a processing device, such as a computer or a programmable logic device, configured or adapted to perform one of the procedures described herein.

[0081] Another example includes a computer on which the computer program for performing one of the procedures described herein is installed.

[0082] In some examples, a programmable logic device (for example, a field-programmable gate array) can be used to perform some or all of the functionalities of the procedures described herein. In some examples, a field-programmable gate array can interact with a microprocessor to perform one of the procedures described herein. Generally, the procedures are preferably performed by any hardware device.

[0083] The examples described above are merely illustrative of the principles of this disclosure. It is understood that modifications and variations of the arrangements and details described herein will be obvious to other people skilled in the art. Therefore, it is intended that any limitation is limited only by the scope of protection of the following claims and not by the specific details presented herein by way of description and explanation of the exemplary embodiments.

Claims

[1] Storage device having the following features: a plurality of memory cells (12); a plurality of evaluation elements (14), each evaluation element (14) being connectable to a memory cell (12) of the memory device; a connection unit (16) configured to connect the plurality of memory cells (12) to a first assignment of evaluation elements (14) in a first state and to connect the same plurality of memory cells (12) to at least a second assignment of evaluation elements (14) in a second state; wherein, in the second state, at least one memory cell (12) of the plurality of memory cells is connected to a different evaluation element (14); an evaluation unit (18) configured to control the connection unit (16) from the first state to the second state; wherein the evaluation unit (18) is configured to evaluate the plurality of memory cells (12) in the first state to obtain a first evaluation result (441); and to evaluate the plurality of memory elements (12) in the second state to obtain a second evaluation result (442). [2] The memory device of claim 1, wherein in the first state and in the second state, each of the plurality of memory elements (12) is connected to an evaluation element (14). [3] Memory device according to claim 1 or 2, wherein the first evaluation result (441) represents a first bit sequence and wherein the second evaluation result (442) represents a second bit sequence, wherein the evaluation unit (18) is designed to provide the first bit sequence and the second bit sequence with an identical order of bits. [4] The memory device of claim 3, wherein the connection unit (16) comprises reordering logic to implement the first assignment and the second assignment; wherein the evaluation unit (18) comprises inverse reordering logic (22) that is inverse to the reordering logic and is configured to change an assignment of an evaluation element (14) to a bit position from the first state to the second state inverse to the reordering logic in order to keep a bit position of a value read from a memory cell (12) unchanged in the first bit sequence and in the second bit sequence. [5] The memory device according to any one of claims 1 to 4, wherein the evaluation unit is configured to determine that a first number of bit errors in the first evaluation result (441) exceeds a number of errors correctable with an error correction code used to store information in the plurality of memory cells (12); and to determine that a second number of bit errors in the second evaluation result is at most the number of errors correctable with the error correction code, and to use the second evaluation result (442) as a result of a read operation of the memory device. [6] The memory device according to any one of claims 1 to 4, wherein the memory device unit is configured to determine a result of a read operation of the plurality of memory cells (12) using an error detection code. [7] The memory device according to any one of the preceding claims, wherein the evaluation unit (18) is configured to determine that a first number of bit errors in the first evaluation result (441) exceeds a predefined threshold; and to control the connection unit (16) to the second state based on the number of bit errors. [8] Memory device according to one of the preceding claims, wherein the evaluation unit (18) is designed to obtain at least a third evaluation result of the plurality of memory cells (12) by means of a third assignment of evaluation elements (14) to the plurality of memory cells (12) in a third state; or a combined evaluation result as a majority decision common to the plurality of memory cells; or to determine group by group for groups of memory cells, each group of memory cells having at least one memory cell. [9] Memory device according to one of the preceding claims, wherein the evaluation unit (18) is designed to repeat a read operation using different assignments of evaluation elements (14) to memory cells (12) until a correct or correctable read result is obtained or until a termination criterion occurs. [10] A memory device according to any one of the preceding claims, wherein the evaluation unit (18) is configured to store error information (32) indicating that a specific pair of a memory cell (12) and an evaluation element (14) is susceptible to errors in a memory accessible to the memory (28) device. [11] Memory device according to one of the preceding claims, wherein the evaluation unit (18) is designed to read from a memory (28) error information (32) indicating that a specific pair of a memory cell (12) of the plurality of memory cells and an evaluation element (14) is susceptible to errors, and to obtain the second evaluation result (442) based on the first evaluation result (441) based on the specific pair, and / or to avoid the specific pair when evaluating the plurality of memory cells (12). [12] Memory device according to one of the preceding claims, wherein at least one evaluation element (14) comprises a sense amplifier. [13] A memory device according to any one of the preceding claims, wherein the plurality of memory cells (12) is implemented to provide one bit of information per memory cell; as a multi-level memory or as a multi-cell memory. [14] The memory device according to any one of the preceding claims, wherein the evaluation unit is configured to determine a deviation between at least one evaluation result of a first evaluation element (141) of the first evaluation result (441) and a second evaluation element (142) of the second evaluation result used for a same memory cell (121); to determine deviation information (33) indicating a deviation between the evaluation of the memory cell (121) using the different evaluation elements; and to store the deviation information (33) in a memory (28) of the memory device. [15] Storage device according to one of the preceding claims, wherein the storage device is configured to read deviation information (33) from a memory (28), the deviation information indicating a deviation between a behavior of evaluation elements (14), and to correct the first evaluation result (441) or the second evaluation result (442) using the deviation information (33). [16] A storage device comprising: a plurality of memory cells (12); a plurality of evaluation elements (14), each evaluation element (14) being connectable to a memory cell (12) of the memory device; a connection unit (16) configured to connect the plurality of memory cells (12) to a first assignment of evaluation elements (14) in a first state and to connect the same plurality of memory cells (12) to a second assignment of evaluation elements (14) in a second state; wherein, in the second state, at least one memory cell (12) of the plurality of memory cells is connected to a different evaluation element (14); an evaluation unit (18) configured to control the connection unit (16) from the first state to the second state; a memory (28) storing error information (32) indicating that a read operation using a specific pair of a memory cell (12) of the plurality of memory cells and an evaluation element (14) is error-prone in the first state; wherein the evaluation unit (18) is designed to read the error information (32) from the memory (28) and to obtain an evaluation result of the plurality of memory cells on the basis of a read operation using the second state on the basis of the error information (32). [17] A storage device comprising: a memory cell (12); a plurality of evaluation elements (14), each evaluation element being connectable to the memory cell (12) of the memory device; a connection unit (16) configured to connect the memory cell (12) to a first evaluation element (141) in a first state and to connect the memory cell to a second evaluation element (142) in a second state; an evaluation unit (18) configured to obtain a first evaluation result of the memory cell (12) in the first state and to obtain a second evaluation result of the memory cell (12) in a second state; wherein the evaluation unit (18) is designed to determine a deviation between the first evaluation result and the second evaluation result and to store deviation information (33) in a memory (28) of the storage device. [18] A method (700) for operating a memory device having a plurality of memory cells and a plurality of evaluation elements, each evaluation element being connectable to a memory cell of the memory device; the method comprising the following steps: Connecting (710) the plurality of memory cells to a first assignment of evaluation elements in a first state; Connecting (720) the same plurality of memory cells to a second assignment of the evaluation elements in a second state; such that in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element; Evaluating (730) the plurality of memory cells in the first state to obtain a first evaluation result; and evaluating the plurality of memory elements in the second state to obtain a second evaluation result. [19] A method (800) for operating a memory device having a plurality of memory cells and a plurality of evaluation elements, each evaluation element being connectable to a memory cell of the memory device; the method comprising the following steps: Connecting (810) the plurality of memory cells to a first assignment of evaluation elements in a first state; Connecting (820) the same plurality of memory cells to a second assignment of the evaluation elements in a second state; such that in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element; Reading (830) from a memory error information indicating that a read operation using a specific pair of a memory cell of the plurality of memory cells and an evaluation element in the first state is error-prone, to obtain an evaluation result of the plurality of memory cells based on a read operation using the second state based on the error information. [20] A method (900) for operating a memory device having a memory cell and a plurality of evaluation elements, each evaluation element being connectable to the memory cell of the memory device; the method comprising the following steps: Connecting (910) a memory cell to a first evaluation element in a first state and obtaining a first evaluation result of the memory cell; Connecting (920) the memory cell to a second evaluation element in a second state and obtaining a second evaluation result of the memory cell; Determining (930) a deviation between the first evaluation result and the second evaluation result to obtain deviation information; Storing (940) the deviation information in a memory. [21] A computer-readable digital storage medium having stored thereon a computer program comprising program code for performing a method according to claims 18 to 20 when run on a computer.