Differential clock / key level correction with hybrid current injectors and taper current digital-to-analog converter

Abstract

Differential clock duty cycle (DCC) circuit (100), comprising: a hybrid current injector (102) with current sources (128) for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node (106) and subtracted from a clock signal of an opposite polarity at a second correction node (108), and wherein several of the current sources (128) in the hybrid current injector (102) are controlled by a first section of an n-bit digital-to-analog converter (DAW) code to generate the correction current; and a current-to-digital-to-analog converter, DAW, (110) for receiving a second, distinct section of the n-bit DAW code and for outputting a corresponding reference current to the current sources (128) in the hybrid current injector (102), wherein the current sources (128) generate the correction current in response to the reference current output by the current DAW (110) for the second section of the n-bit DAW code.

Description

background

[0001] The present invention relates to clock signals and in particular a differential clock duty cycle correction circuit with hybrid current injectors and a taper current digital-to-analog converter (DAW).

[0002] Clock signals are typically used in all electronic devices and integrated circuits capable of storing information (memory). Clock signals can be generated using various types of oscillators and supporting circuitry. A clock signal continuously alternates between two levels (e.g., logic high and logic low). The clock signal has a duty cycle, which is determined by the duration of the logic high level and the duration of the logic low level.

[0003] The duty cycle of a clock signal is generally expressed as a percentage. For example, a clock signal with an 80% high and 20% low structure has a duty cycle of 80%. In some applications, a clock signal with a 50% duty cycle may be required. For instance, circuits that rely on both clock edges may not function correctly if a clock signal deviates significantly from a 50% duty cycle. In such circuits, it is common to employ a duty cycle correction (DCC) loop to compensate for duty cycle distortion (DCD) caused by variations in the manufacturing process, operating temperature, supply voltage, and noise.

[0004] A duty cycle adjuster is known from US patent 6,967,514 B2. This duty cycle adjuster comprises a clock generator configured to produce a clock signal and having a duty cycle correction input; a duty cycle detector configured to generate an incremental error measurement when a duty cycle error is present in the clock signal, wherein the duty cycle detector includes a charge pump with a first and a second capacitor and a switch between the first and second capacitors; an analog-to-digital converter configured to generate the incremental error measurement when a voltage difference between the first and second capacitors exceeds a threshold, and wherein the switch minimizes the voltage difference in response to a reset signal; and a duty cycle error accumulator connected to the duty cycle detector.wherein the duty cycle error accumulator is configured to generate a duty cycle correction signal in response to the incremental error measurement, which represents an accumulated error measurement, and wherein the duty cycle error accumulator delivers the duty cycle correction signal to the duty cycle correction input. Summary

[0005] A first aspect of the invention relates to a differential clock duty cycle (DCC) circuit comprising: a hybrid current injector with current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein several of the current sources in the hybrid current injector are controlled by a first section of an n-bit DAW code to generate the correction current; and a current DAW to receive a second, different section of the n-bit DAW code and output a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAW for the second section of the n-bit DAW code.

[0006] A second aspect of the invention comprises a method for differential clock duty rate correction (DCC), comprising: generating an n-bit DAW code (DAW = digital-to-analog converter) according to a duty rate correction, wherein the DAW code has a first section and a second section; receiving the second section of the DAW code at a current DAW, wherein the current DAW generates a reference current in response to the second section of the DAW code; controlling current sources in a hybrid current injector for DAW codes in the first section of the n-bit DAW code to generate a correction current; and generating the correction current in the hybrid current injector for DAW codes in the second section of the n-bit DAW code based on the reference current.

[0007] A third aspect of the invention provides a differential clock-rate correction (DCC) circuit comprising: an n-bit digital-to-analog converter (DAW) code corresponding to a DCC correction, wherein the n-bit DAW code comprises a first section with the first m bits of the n-bit DAW code and a second section with bits m+1 to n of the n-bit DAW code; a hybrid current injector for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein the hybrid current injector is controlled by DAW codes in the first section of the n-bit DAW code;and a taper-current DAW for receiving the second section of the n-bit DAW code and outputting a corresponding reference current to the hybrid current injector, wherein the hybrid current injector generates the correction current in response to the reference current; wherein the taper-current DAW generates a constant reference current for DAW codes in the first section of the n-bit DAW code; and wherein the DCC circuit has an essentially linear DCC step transfer function.

[0008] The above and other features of the invention are evident from the following more specific description of the embodiments of the invention. Brief description of the drawings

[0009] The embodiments of this invention are described in detail with reference to the following figures, where identical designations denote identical elements. Fig. Figure 1 shows a conventional duty cycle correction (DCC) circuit with analog-controlled dynamic current sources. Fig. Figure 2 shows a conventional DCC circuit with digitally controlled dynamic current sources. Fig. Figure 3 shows a differential clock DCC circuit with hybrid current injectors and a taper current digital-to-analog converter (DAW) according to embodiments. Fig. Figure 4 shows a taper current DAW according to embodiments. Fig. Figure 5 shows a hybrid current injector with a taper current DAW according to embodiments. Fig. Figure 6 shows a diagram of the duty cycle step size compared to the DAW code for the conventional DCC circuit. Fig. 1 and the in Fig. 5 DCC circuits shown according to embodiments. Fig. Figure 7 shows a flowchart of a process for differential clock-duty correction according to embodiments.

[0010] The drawings of the invention are not necessarily to scale. They are intended to illustrate typical aspects of the invention and should therefore not be considered to limit its scope. In the drawings, identical reference numerals represent identical elements. Detailed description

[0011] The following description refers to the accompanying drawings, which form part thereof and show exemplary embodiments in which the present teaching can be implemented. These embodiments are described in sufficient detail to enable a person skilled in the art to put the present invention into practice. However, other embodiments may be used and modifications made without departing from the scope of the present invention. The following description is therefore for illustrative purposes only.

[0012] Conventional duty cycle correction circuits (DCC circuits), such as those in Fig. The DCC circuit shown in Figure 1 typically exhibits range and resolution specifications that can represent conflicting requirements, especially if the DCC circuit does not have a linear DCC step transfer function (e.g., the DCC step size varies depending on the DAW current). Typically, the range is reduced until the largest duty cycle step meets a minimum resolution specification. However, conventional DCC circuits designed specifically for a linear transfer function often require more area and more complex wiring for implementation. This frequently results in additional parasitic capacitance, which can limit the bandwidth or increase the power consumption of the clock circuit. In some implementations, semiconductor devices in DCC circuits may operate in undesirable regions (e.g., the subthreshold region) across portions of the dynamic range.In the sub-threshold operating range, the component-to-component mismatch is amplified, and transistor models are typically less accurate. This can lead to a highly non-linear DCC step size or, in the worst case, to unforeseen and uncorrectable DCD.

[0013] According to the representation in Fig. Figure 1 uses a conventional differential DCC circuit 10 and an analog-controlled current injector 12. The current injector 12 is also commonly referred to as a charge injector because a fixed amount of charge is injected over a specific clock period. The current injector is configured to add a fixed amount of correction current to a clock signal (e.g., CLKT_IN) with a first polarity and to subtract the same amount of correction current from a clock signal (e.g., CLKC_IN) with the opposite polarity. In the DCC circuit 10, a comparator 16 outputs a signal DCC_COMP_OUT, which corresponds to the difference between the duty cycles of the clock signals CLKT_IN and CLKC_IN at the measurement nodes 18 and 20. The DCC_COMP_OUT signal indicates the direction of the required duty cycle correction. A digital logic 22 increases / decreases the DAW code or adjusts the sign bit to an n-bit (e.g. 64-bit) current DAW 24.The DAW 24 outputs a reference stream I corresponding to the received DAW code. ref to the current injector 12. In response, the current injector 12 adds a correction current to / from the clock signal CLKT_IN at a correction node 26 corresponding to the received sign bit and adds the same amount, but with the opposite sign, of the correction current to / from the clock signal CLKC_IN at a correction node 28. The current drawn by the current injector 12 changes depending on the compensated node voltage. When the feedback loop converges and the duty cycle distortion (DCD) is driven to a magnitude of less than one bit of the correction resolution, the current injector 12 has adjusted the rise / fall time at correction nodes 26 and 28 to shift the DCD with an open loop at the sensing nodes 18 and 20.

[0014] The current injector 12 typically comprises a plurality of semiconductor devices (e.g., transistors). When the DAW code of the n-bit DAW 24 increases from 0 to n (e.g., n = 64), the reference current I supplied by the DAW 24 increases. ref The gate bias of the components within current injector 12 is incrementally increased. The components transition from the subthreshold region to the saturation region, approaching triode operation. As the gate bias of the components in current injector 12 incrementally increases, the components in current injector 12 deliver incrementally more current, but the output voltage range over which they operate in saturation decreases. For example, at lower DAW codes provided for the DAW 24, the components in current injector 12 may operate in the subthreshold region, while at higher DAW codes, the components in current injector 12 may operate in saturation. At V gs < V tA weak inversion or a current below the threshold is present. In this operating mode, I increases. ds depending on V gs exponentially. As soon as V gs > V t is, rises I ds as square of V gs The DAW code, in which the current sources transition from the sub-threshold range, depends on the size of the components.

[0015] As the components in the current injector 12 transition through these operating ranges, the incremental current addition decreases nonlinearly (e.g., the actual step size decreases with increasing DAW code of DAW 24). This can lead to significant nonlinearity in the DCC step size, particularly in the portion of the range where the current sources operate below the threshold. Furthermore, this can result in a time-delay step size at the correction nodes 26, 28, which can be up to 5 times larger at the lowest DAW codes than at the highest. This can also affect the area of ​​the DCC circuit 10 that is limited by the maximum step size at the DAW code transitions 0 → 1 / 1 → 0. An example of the degree of nonlinearity suffered by a differential DCC circuit such as the differential DCC circuit 10 is shown by the dashed line in the Fig. The table shown in section 6 indicates the keying step size in comparison to the DAW code.

[0016] Fig. Figure 2 shows a conventional DCC circuit 40 with digitally controlled dynamic current sources. In contrast to the one in Fig. In the DCC circuit 10 shown in Figure 1, which includes an analog-controlled current injector 12, the DCC circuit 40 has positive and negative current DACs that are directly connected to the correction nodes 26, 28. For example, as shown in Fig. Figure 2 shows a positive current DAW 42 and a negative current DAW 44 coupled to correction node 26, while a positive current DAW 44 and a negative current DAW 48 are coupled to correction node 28.

[0017] A comparator 16 outputs a signal DCC_COMP_OUT, which corresponds to the difference between the duty cycles of the clock signals CLKT_IN and CLKC_IN at measurement nodes 18 and 20. The DCC_COMP_OUT signal is fed to the digital logic 50, which increments or decrements the DAW code and the sign bit of decoder 52 accordingly. Decoder 52 outputs DAW codes according to the required correction current to the positive and negative current DACs 42 and 44 coupled to correction node 26 and to the positive and negative current DACs 46 and 48 coupled to correction node 28. In response, the DACs 42, 44, 46, 48 with positive and negative current are configured to selectively add or subtract a fixed amount of correction current to node 26 and an equal amount, but with opposite polarity, to node 28.The incremental addition / subtraction of the current at nodes 26 and 28 incrementally distorts the clock duty cycle, effectively canceling the DCD measured at CLKT_OUT / CLKC_OUT with an open loop.

[0018] Since all DACs with positive and negative current in DCC circuit 40 have the same operating point regardless of the DAW code, DCC circuit 40 incorporates a much more linear transfer function of the DAW code with respect to duty cycle correction than DCC circuit 10. However, achieving such linearity comes at the cost of increased area (e.g., > 4X), wiring complexity (e.g., > 4X), and parasitic capacitance (e.g., > 5X) compared to DCC circuit 10.

[0019] Fig. 3 and Fig. Figure 4 shows a differential DCC circuit 100 with a hybrid current injector 102 connected to correction nodes 106 and 108, and a taper current DAW 110, depending on the embodiment. In contrast to the conventional DCC circuits 10 and 40 described above, the DCC circuit 100 provides both analog and digital control of the current sources that form the hybrid current injector 102. Compared to conventional DCC circuits, the DCC circuit 100 offers a more linear DCC step transfer function, prevents all current source components from operating below the threshold, and can be implemented with fewer wires and lower parasitic capacitance in a smaller area.

[0020] In the DCC circuit 100, the hybrid current injector 102 is configured to add / subtract a fixed amount of correction current to a clock signal CLKT_IN, CLKC_IN of a first polarity, and to add / subtract the same amount, but with the opposite sign, of correction current to the clock signal CLKT_IN, CLKC_IN of the opposite polarity. In the DCC circuit 100, a comparator 112 outputs a signal DCC_COMP_OUT, which corresponds to the difference between the duty cycles of the differential clock signals CLKT_IN, CLKC_IN at the measuring nodes 114, 116. The DCC_COMP_OUT signal is provided to the digital logic 118, which increments or decrements the DAW code and sets the sign bit of the decoder 52 accordingly. The digital logic 118 outputs a DAW code, which is typically an incremental change (e.g. ± 1) of the previous DAW code or a change in the sign bit, to a decoder 122 (e.g.a 6-bit binary-to-thermometer code). In response, decoder 122 outputs an n-bit thermometer DAW code (e.g., 64-bit).

[0021] The DAW code output by Decoder 122 is divided into several sections according to embodiments. For example, an n-bit DAW code output by Decoder 122 can have a first section P1 containing the first m least significant bits of the DAW code and a second section P2 containing the remaining bits (e.g., m+1 to n bits) of the DAW code. In the case of a 64-bit DAW code (e.g., n=64), the first section P1 of the DAW code can, for example, comprise the first 16 least significant bits (e.g., bits 0:15), and the second section P2 of the DAW code can comprise the remaining 48 bits (e.g., bits 16:63). According to the representation in Fig. 3 and Fig. Section 4 is the first section P1 of a 64-bit DAW code (e.g., bits 0:15) intended as a digital control input for the hybrid current injector 102. The second section P2 of the 64-bit DAW code (e.g., bits 16:63) is input into the taper current DAW 110, which is configured to provide a reference current I. ref output as an analog control input to the hybrid current injector 102. The reference current derived from the taper current DAW 110 remains constant over the first section P1 of the n-bit DAW code.

[0022] The taper current DAW 110 can be implemented, according to embodiments, as an n-bit (e.g., 64-bit) current DAW weighted in thermometer code. Fig. Figure 4 is a non-restrictive example of such a taper current DAW 110. As shown, each slice (leg) 124 of the taper current DAW 110 is weighted as necessary to compensate for any residual non-linearity of the analog current sources in the hybrid current injector 102. For example, as shown in Fig. As shown in Figure 4, in the case of larger DCC step sizes at lower DAW codes and smaller DCC step sizes at higher DAW codes, the slices 124 of the tapered-current DAW 110 corresponding to the lower DAW codes are assigned a lower weight (e.g., a weight < 1) compared to the slices 124 of the taper-current DAW 110 at higher DAW codes. This effectively linearizes the DCC step size across the entire dynamic range (e.g., a reduction of up to 5x). Therefore, maximum linearity in the DCC step transfer function can be achieved by adjusting the effective "weight" of each DAW slice 124.

[0023] According to the representation in Fig. 3 and Fig. 5. The second section P2 of the 64-bit DAW code (e.g., bits 16:63) is entered into the taper-stream DAW 110, which is configured to provide a reference stream I. ref as an analog control input to the hybrid current injector 102. If the DAW code is reduced, for example, from 63 to 16, the taper current DAW 110 reduces the reference current I. ref , which is input into the hybrid current injector 102 by a fixed amount. In response to this and based on the received sign bit, the hybrid current injector 102 is configured to inject a fixed amount of correction current (e.g., I). refThe DCC current is added / subtracted from a clock signal CLKT_IN and CLKC_IN with a first polarity, and the same amount, but with the opposite polarity, of the correction current is added / subtracted from the clock signal CLKT_IN and CLKC_IN with the opposite polarity. Due to the use of the taper current DAW 110, the DCC step size remains essentially linear when the DAW code is reduced (e.g., from 63 to 16).

[0024] The reference current I ref This is provided for the catch diodes 126 in the hybrid current injector 102 and sets the gate bias of these diodes. The gate bias is applied to the transistors of the current sources in the hybrid current injector 102 to provide the required amount of correction current. Since the DAW code is lowered (e.g., from 63 to 16) and the magnitude of the reference current I refSince the current is reduced accordingly by the taper current DAW 110, the transistors in the hybrid current injector 102 operate in the saturated range. For DAW codes below m+1, the reference current derived in the taper current DAW 110, and thus the current density in the current sources of the hybrid current injector 102, remains constant. The current sources in the hybrid current injector 102 are dimensioned such that operation below the threshold is avoided for all DAW codes with the code m+1 (e.g., 16) as the limiting condition.

[0025] While the use of the taper current DAW 110 compensates for the inherent non-linearity of adjustable analog current sources, the hybrid injector 102 is further configured to account for DCC step size variations caused by subthreshold components, which can occur at low DAW code levels. For example, the current sources in each of the hybrid current injectors 102 can be adjusted according to the settings in Fig. In the embodiments shown in Figure 5, the current sources (slices) 128 are divided into sets of m parallel-connected current sources 128, each current source 128 being directly activated / deactivated by one of the m DAW codes in the first section P1 of the DAW codes (bits 0:15). For example, for a DAW code of m, all m of the current sources 128 are activated; for a DAW code of m-1, m-1 of the current sources 128 are activated, and so on. Thus, the magnitude of the correction current applied to the correction nodes 106, 108 can be increased / decreased as needed by selectively activating / deactivating one or more of the m current sources 128 in accordance with the first section P1 of the DAW code output by the decoder 122. In other words, the first section P1 of the DAW code output by the decoder controls the effective "size" of the current sources in the hybrid current injector 102. The advantage is that the reference current I ref, which is output by the taper current DAW 110, and the current density of the current sources of the hybrid current injector 102 remains at a constant level sufficient to ensure that the transistors of the current sources in the hybrid current injector 102 do not operate in the subthreshold region, thereby improving the linearity of the DCC step transfer function at low DAW codes. The solid line in the Fig. The diagram of the duty cycle step against the DAW code shown in Figure 6 is an example of the improvements in linearity achieved by the differential DCC circuit 100 according to embodiments of the invention.

[0026] In summary, as described above, the first section P1 of the DAW code (e.g., bits 0:15) can be used to directly control the m current sources 128 in the hybrid current injector 102, thereby preventing the current source components from operating below the threshold and optimizing the linearity of the DCC step transfer function at low DAW codes. The second section P2 of the DAW code (e.g., bits 16:63) can be used to control the magnitude of the reference current I. ref to control the output from the taper current DAW 110, thereby optimizing the linearity of the DCC step transfer function at higher DAW codes.

[0027] Fig.Figure 7 shows a flowchart of a process for differential clock duty cycle correction according to embodiments. In process A1, an n-bit DAW code (DAW = digital-to-analog converter) corresponding to a duty cycle correction is updated according to a measured duty cycle correction. In process A2, for DAW codes in a first section P1 of the n-bit DAW code (yes in process A2), the DAW code in process A3 is used to directly control current sources in a hybrid current injector 102 to generate a change in a correction current. As described above, the reference current provided by the taper current DAW 110 remains constant. For DAW codes in a second section P2 of the n-bit DAW code (no at process A2), the taper current DAW 110 is increased / decreased accordingly to generate a reference current at process A4, and at process A5 the hybrid current injector generates a correction current based only on the change in the reference current.

[0028] The terminology used herein serves only to describe certain embodiments and is not intended to limit the invention. As used herein, the singular forms "a" and "the" are to include the plural forms unless the context clearly indicates otherwise. Furthermore, the terms "includes" and / or "comprehensive" as used in this description are to be understood as indicating the presence of specified features, integers, steps, operations, elements, and / or components, but not as excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.“Optional” or “choice” means that the event or circumstance described below may or may not occur, and that the description includes cases in which the event occurs and cases in which it does not occur.

[0029] An imprecise language, such as that used throughout this description and in the claims, can serve to modify any quantitative representation that could permissibly vary without altering the fundamental function to which it refers. Accordingly, a value modified by one or more terms such as "approximately," "about," and "essentially" is not restricted to the precisely stated value. At least in some cases, the imprecise language can correspond to the accuracy of an instrument for measuring the value. Here, and throughout this description and in the claims, range restrictions may be combined and / or interchanged. These ranges are identified and include all subranges contained therein, unless the context or language indicates otherwise.The “approximate value” applied to a particular value of a range applies to both values ​​and, unless otherwise dependent on the accuracy of the instrument measuring the value, may mean + / - 10% of the stated value(s).

[0030] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims shall comprise each structure, material, or action for performing the function in combination with other claimed elements, as specifically claimed. The description of the present invention has been provided for illustrative and descriptive purposes and is neither intended to be exhaustive nor limited to the invention as presented. Many modifications and variations are apparent to a person skilled in the art without deviating from the scope and essence of the disclosure.The embodiment was selected and described to best explain the principles of the invention and its practical application, and to enable those other than the person skilled in the art to understand the invention for different embodiments with different modifications suitable for the respective uses under consideration.

Claims

[1] Differential clock duty cycle (DCC) circuit (100), comprising: a hybrid current injector (102) with current sources (128) for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node (106) and subtracted from a clock signal of an opposite polarity at a second correction node (108), and wherein several of the current sources (128) in the hybrid current injector (102) are controlled by a first section of an n-bit digital-to-analog converter (DAW) code to generate the correction current; and a current-to-digital-to-analog converter, DAW, (110) for receiving a second, distinct section of the n-bit DAW code and for outputting a corresponding reference current to the current sources (128) in the hybrid current injector (102), wherein the current sources (128) generate the correction current in response to the reference current output by the current DAW (110) for the second section of the n-bit DAW code. [2] DCC circuit (100) according to claim 1, wherein the current DAW (110) generates a constant reference current over the first section of the n-bit DAW code. [3] DCC circuit (100) according to claim 1, wherein the first section of the n-bit DAW code comprises m least significant bits of the n-bit DAW code. [4] DCC circuit (100) according to claim 3, wherein the second section of the n-bit DAW code comprises bits m+1 to n of the n-bit DAW code. [5] DCC circuit (100) according to claim 1, wherein the current sources (128) comprise a plurality of semiconductor devices, and wherein none of the semiconductor devices operates in a subthreshold range. [6] DCC circuit (100) according to claim 1, wherein the DCC circuit (100) has a substantially linear DCC step transfer function. [7] DCC circuit (100) according to claim 6, wherein the current DAW (110) comprises a taper current DAW (110). [8] DCC circuit (100) according to claim 7, wherein the taper current DAW (110) has a plurality of slices and wherein each of the plurality of slices is weighted to linearize the DCC step transfer function. [9] DCC circuit (100) according to claim 8, wherein the slices of the taper current DAW (110) corresponding to lower DAW codes have a lower weighting than the slices of the taper current DAW (110) corresponding to higher DAW codes. [10] DCC circuit (100) according to claim 1, wherein the first section of the n-bit DAW code directly activates or deactivates one or more of the current sources (128) to generate the correction current. [11] DCC circuit (100) according to claim 1, further comprising: a comparator (112) for comparing a duty cycle of a clock signal with a first polarity at a first measuring node (114) and a duty cycle of a clock signal with an opposite polarity at a second measuring node (116) and for outputting a difference signal; digital logic (118) for generating the correction code and a sign bit indicating a direction of the duty cycle correction; and a decoder (122) for receiving the correction code and outputting the DAW code. [12] Differential clock rate correction (DCC) methods, comprising: a generation of an n-bit digital-to-analog converter (DAW) code corresponding to a keying rate correction, wherein the DAW code has a first section and a second section; a receiving of the second part of the DAW code at a current digital-to-analog converter, DAW, (110), wherein the current DAW (110) generates a reference current in response to the second part of the DAW code; for DAW codes in the first section of the n-bit DAW code, a control of current sources (128) in a hybrid current injector (102) to generate a correction current; and for DAW codes in the second section of the n-bit DAW code, a generation of the correction current in the hybrid current injector (102) based on the reference current. [13] Method according to claim 12, wherein the current DAW (110) generates a constant reference current over the first section of the n-bit DAW code. [14] Method according to claim 12, wherein the first section of the n-bit DAW code comprises m least significant bits of the n-bit DAW code. [15] Method according to claim 14, wherein the second section of the n-bit DAW code comprises bits m+1 to n of the n-bit DAW code. [16] Method according to claim 12, wherein the first section of the n-bit DAW code directly controls an effective size of the current sources (128) in the hybrid current injector (102) to generate the correction current. [17] Method according to claim 12, wherein the current sources (128) comprise a plurality of semiconductor devices, wherein the method further comprises biasing the current sources (128) with the reference current when the correction current is generated in response to DAW codes in the first section of the n-bit DAW code, wherein the biasing prevents the semiconductor devices in the current sources (128) from operating in a subthreshold range. [18] Method according to claim 12, wherein the current DAW (110) comprises a taper current DAW (110) with a plurality of slices, wherein the method further comprises weighting each of the plurality of slices to linearize a DCC step transfer function. [19] Differential clock rate correction (DCC) circuit (100), comprising: an n-bit digital-to-analog converter (DAW) code corresponding to a DCC correction, wherein the n-bit DAW code comprises a first section with the first m bits of the n-bit DAW code and a second section with bits m+1 to n of the n-bit DAW code; a hybrid current injector (102) for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node (106) and subtracted from a clock signal of an opposite polarity at a second correction node (108), and wherein the hybrid current injector (102) is controlled by DAW codes in the first section of the n-bit DAW code; and a taper current digital-to-analog converter, DAW, (110) for receiving the second section of the n-bit DAW code and outputting a corresponding reference current to the hybrid current injector (102), wherein the hybrid current injector (102) generates the correction current in response to the reference current; wherein the taper-stream DAW (110) generates a constant reference stream for DAW codes in the first section of the n-bit DAW code; and wherein the DCC circuit (100) has a substantially linear DCC step transfer function. [20] DCC circuit (100) according to claim 19, wherein the taper current DAW (110) comprises a plurality of slices, and wherein each of the plurality of slices is weighted to partially linearize the DCC step transfer function.

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