Method with a wafer-to-wafer bond structure and package and package component with such

Abstract

Method comprising: Thinning a first wafer to expose metal vias; Forming a bonding layer over the metal vias, wherein the metal vias extend through the bonding layer; Positioning a second wafer on the first wafer, wherein bond pads of the second wafer are aligned with the metal vias of the first wafer; Bonding the bond pads of the second wafer to the metal vias of the first wafer without using a bonding material between the bond pads and the metal vias; and Joining the bond layer of the first wafer with a bond layer of the second wafer.

Description

BACKGROUNDSemiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers onto a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon. Typically, dozen or hundreds of integrated circuits are fabricated on a single semiconductor wafer. The individual chips are singulated by sawing the integrated circuits along scribe lines. The individual chips are then packaged individually, in multichip modules or in packages (packages) of other types.The semiconductor industry has experienced rapid growth due to the continued improvement in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum size of features (e.g., from smaller and smaller semiconductor process nodes to sub-20 nm nodes), which allows more components to be integrated on a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and shorter latency times has recently increased, the need for smaller and more conservative package technologies for semiconductor chips has also increased.With the advancement of semiconductor technology, stacked semiconductor devices, e.g., three-dimensional integrated circuits (3D ICs), have appeared as an effective alternative to further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on various semiconductor wafers. In order to further reduce the form factor of the semiconductor device, two or more semiconductor wafers may be stacked on each other. POP (package-on-package) devices are a type of 3D IC in which chips are packaged and then packaged together with one or more other packaged chips.The invention provides a method according to claim 1, a packet according to claim 11 and a packet component according to claim 16. Embodiments are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with common industry practice. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1 to 2, 3 ato 3 d, and 4 to 10 illustrate intermediate steps in a process for forming a first wafer of a package, in accordance with some embodiments. FIGS. 11 through 19 illustrate intermediate steps in a process for forming a second wafer of a package, in accordance with some embodiments. FIGS. 20 a, 20 band 21 to 26 illustrate a wafer stack configuration according to some embodiments. FIGS. 27-30 illustrate a process for forming a two-layer wafer stack, in accordance with some embodiments. FIGS. 31 through 32 illustrate a process for using a two-layer wafer stack, in accordance with some embodiments. FIGS. 33-34 illustrate a process for forming a four-layer wafer stack, in accordance with some embodiments. FIGS. 35-36 illustrate a process for using a four-layer wafer stack, in accordance with some embodiments. FIGS. 37 ato 37 d illustrate a process for using a single-layer, two-layer, and / or four-layer stack, in accordance with some embodiments. FIGS. 38 ato 38 b illustrate a process for forming a packet using a single-layer, two-layer, and / or four-layer stack, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. These are of course merely exemplary embodiments and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower / r / s," "above," "upper / r / s," and the like may be used herein to simplify the description to describe the relationship of an element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly.Embodiments provide a multi-chip stack structure. In some embodiments, combinations of single, dual, and four layer wafer structures may be attached to a device wafer, such as a control wafer. Each of the multilayer structures may include active devices and through vias through the substrate of the wafer. Prior to bonding a wafer to another wafer, the substrate may be thinned to expose the through vias. A bonding layer can then be formed in such a way that the continuous vias pass through the bonding layer. The through vias may be bonded to bond pads (bond pads) of the next wafer. The multichip structures can be produced in advance and subsequently bonded to a further wafer, for example a control wafer.FIGS. 1-7 illustrate intermediate steps of a process for forming and preparing chips 112. One or more of the chips 112 may be configured as a logic chip, such as a CPU chip, a microcontroller (MCU) chip, an input / output (I / O) chip, a baseband (BB) chip, an application processor (AP) chip, a system on a chip (SoC), a system on integrated chip (SoIC), or the like. One or more of the chips 112 may also be a memory chip, such as a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip, or the like. In the illustrated embodiments, one or more chips or stacks of chips may be bonded to the chips 112.Referring to FIG. 1, a top view of a wafer 100 having multiple dies 112 is illustrated, in accordance with some embodiments. The chips 112 may be configured to have the same chip function or different chip functions, respectively. Between the chips 112 there are cut lanes 111 which are provided for singulating the chips 112 in a subsequent process. The chips 112 may be considered as package areas and the intersecting lanes 111 may be considered as non-package areas. In some embodiments, no active or passive components are formed in the cutting lanes 111, that is to say in such embodiments the cutting lanes 111 are free of active or passive components.In FIG. 2, a cross-sectional view of a portion of the wafer 100 is illustrated. In the illustrated section, a first die 112 and a second die 112 are illustrated and separated by a dicing street 111. Details are omitted for simplicity. It should be understood that the illustrations regarding the chips 112 are for information purposes and are not to be considered limited to any particular configuration.The chips 112 may include a substrate 115 having one or more active or passive devices formed therein. The substrate 115 may be formed of silicon, but may be formed of other Group III, IV, and / or V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate may also be in the form of a silicon-on-insulator (SOI) substrate. The SOI substrate may include a layer of a semiconductor material (e.g., silicon, germanium, and / or the like) formed over an isolation layer (e.g., a buried oxide and / or the like) formed on a silicon substrate. In addition, other applicable substrates may include multilayer substrates, gradient substrates, hybrid orientation substrates, any combinations thereof, and / or the like.In the illustrated embodiments, the wafer 100 includes a device region 110 for each of the chips 112. The device regions 110 may include embedded devices such as transistors 118 or other active devices such as diodes and possibly passive devices such as capacitors, inductors, resistors, or the like. Above the device area 110 is an interconnect structure (interconnect structure) 130 that interconnects devices and directs input / output signals to the devices.The interconnect structure 130 may include dielectric layers as well as metal lines and vias formed in dielectric layers, the details of which are not shown for simplicity. The dielectric layers of the interconnect structure 130 may also be referred to as inter-metal dielectric layers (IMD layers). Some or all of the dielectric layers may be formed of a low-k dielectric material having a dielectric constant (k-value) of less than about 3.0 or about 2.5. The dielectric layers of the interconnect structure 130 may be formed of black diamond (registered trademark of Applied Materials), a low-k carbonaceous dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. According to other embodiments of the present disclosure, some or all of the dielectric layers are formed of dielectric materials having a k value that is not low, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. According to some embodiments of the present disclosure, forming the dielectric layers of the interconnect structure 130 includes depositing a mitogen-containing dielectric material and then performing a curing process to drive off the mitogen and therefore the remaining dielectric layers become porous. Etch stop layers, which may be formed of silicon carbide, silicon nitride, or the like, may be formed between IMD layers.The metal lines and vias of the interconnect structure 130 are formed in the dielectric layers of the interconnect structure 130. Accordingly, the interconnect structure 130 may include a plurality of metal layers (metal lines in the same layer) interconnected by the vias of the interconnect structure 130. The metal lines and vias may be formed of copper or copper alloys, and may also be formed of other metals. The forming process may include simple damascene processes and dual damascene processes. In a simple damascene process, a trench is first formed in one of the dielectric layers of the interconnect structure 130 and then filled with a conductive material. A planarization process, such as a CMP process, is then performed to remove the excess portions of the conductive material higher than the top surface of the IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, the via opening underlying and being connected to the trench. The conductive material is then filled into the trench and via opening to form a metal line and via. The conductive material may include a diffusion barrier and a copper-containing metallic material over the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.According to some embodiments of the present disclosure, the dielectric layers 132 are formed over the interconnect structure 130. The dielectric layers 132 may be formed of multiple layers. In some embodiments, the dielectric layers 132 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like.Via openings corresponding to vias 120 may be formed through dielectric layers 132 and into substrate 115. In some embodiments, the via openings may expose metallic features of the interconnect structure 130 for coupling to the active and / or passive devices in the device area 110. One or more of the via openings corresponding to the vias 120 may not expose metallic features of the interconnect structure 130, such that a via material subsequently formed in the via opening is not coupled to any of the devices in the device region 110 and may be considered a dummy via. The via openings may be formed using a photolithography process that uses, for example, photoresists and / or hard masks that are formed and patterned over the dielectric layer 132. Anisotropic etching may be used to form the via openings through the photoresists and / or hard masks.The vias 120 and contact pads (contact pads) 125 may be formed over the dielectric layers 132. The vias 120 and the contact pads 125 may be formed by processes similar to the formation of the vias and metal lines of the interconnect structure 130 described above, but other suitable processes may be used. For example, a seed layer may be deposited in the via openings, and the vias may be formed by depositing a conductive material in the via openings on the seed layer, for example, by electroplating or electroless plating. The contact pads 125 may be formed simultaneously or in a subsequent similar process. The vias 120 and the contact pads 125 may be formed of copper or copper alloys, and may also be formed of other metals.In some embodiments, the chips 112 include one or more known good chips (KGDs) that have been function tested. In some embodiments, the dies 112 that fail the test may not be subjected to further processing and recycled or discarded. In other embodiments, the dies 112 that failed the test may remain in the wafer 100 along with the KGDs during further processing and may be recycled or discarded at a later stage. For example, in embodiments with wafer-to-wafer bonding in processes, an entire non-singulated wafer is bonded to the wafer 100, while in embodiments with chip-to-wafer or chip-to-chip bonding in processes, singulated chips are bonded to the wafer 100 or singulated chips are bonded to singulated chips of the wafer 100, respectively. Thus, in some embodiments, only those chips 112 that are KGDs are subjected to subsequent processing for packaging, and chips that fail the CP test are not packaged.FIGS. 3 a, 3 b, 3 cand 3 d illustrate various embodiments for using the wafer 100 and the chips 112 in a packaging process. In FIGS. 3 aand 3 b, the wafer 100 remains intact and is attached to a carrier substrate 190, and in FIGS. 3 cand 3 d, the wafer 100 is singulated to release the chips 112. The KGDs may then be attached to the carrier substrate 190. In FIGS. 3 aand 3 c, the wafer 100 and / or the chips 112 are rotated (i.e. they are turned over and attached to the carrier substrate 190 directed downward). In FIGS. 3 band 3 d, the wafer 100 and / or the chips 112 remain directed upward and the back side (non-active side) of the wafer 100 and / or the chips 112 is attached to the carrier substrate 190.Generally, during subsequent processing steps, the carrier substrate 190 provides temporary mechanical and structural support to various features (e.g., the wafer 100). In this way, damage to the chips 112 is reduced or prevented. The carrier substrate 190 may include, for example, glass, ceramic, solid silicon, and the like. A separation layer 150 may be used to attach the wafer 100 and / or the chips 112 to the carrier substrate 190. In some embodiments, the carrier substrate 190 may be substantially free of active devices and / or functional circuitry. In some embodiments, the carrier substrate 190 may comprise bulk silicon, and the wafer 100 and / or the chips 112 may be attached to the carrier substrate 190 through a dielectric separation layer 150. In some embodiments, the carrier substrate 190 may include a tether.The release layer 150 may be any die attach film or adhesive, epoxy, ultraviolet (UV) adhesive (which loses adhesion when exposed to UV radiation), or the like. The separation layer 150 may be formed on the surface of the carrier substrate 190 or on the surface of the wafer 100 and / or the chips 112 using a deposition process, a spin coating, a printing process, a lamination process, or the like. In other embodiments, the release layer 150 may be a thermal release layer, wherein the adhesion strength of the release layer is substantially reduced after the release layer 150 is exposed to a suitable heat source.In some embodiments, to attach the wafer 100 and / or the chips 112 to the carrier substrate 190, a fusion bonding process is used in which an insulating layer of the wafer 100 is directly bonded to a dielectric separation layer 150 to form an insulator-to-insulator bond. Further details regarding fusion bonding are discussed below in connection with wafer-to-wafer bonding described below with reference to FIG. 20 a.In some embodiments, e.g. in FIGS. 3 cand 3 d, the wafer 100 is singulated into individual chips 112, for example by sawing, laser ablation or the like. Subsequently, the chips may be positioned on the carrier substrate 190 by a placement process. A gap fill material 155 may then be deposited to encapsulate the chips 112 and then ground back such that a top surface of the gap fill material 155 is flush with a top surface of the chips 112. The gap fill material 155 may include a molding compound such as an epoxy resin, a resin, a moldable polymer, polyimide, and the like. The molding compound may be applied while being substantially liquid and then cured by a chemical reaction such as an epoxy resin or resin. In other embodiments, the molding compound may be an ultraviolet (UV) or thermosetting polymer applied as a gel or a deformable solid. In some embodiments, the gap fill material 155 may comprise a non-polymer such as silicon dioxide, silicon nitride, or the like, for example, another oxide or nitride deposited using any suitable process. The gap fill material 155 may be formed by, for example, a CVD, PECVD, or ALD deposition process, FCVD, or a glass spin-on process. For ease of reference, the resulting structure may be referred to as wafer 100', however, it should be appreciated that this is not a real wafer, but may be used as a substitute designation for wafer 100 in the further description.In some embodiments, wafer 100 or wafer 100' is directed downward in FIGS. 4-7, such as in FIGS. 3a and 3c. In such embodiments, the back side of wafer 100 or wafer 100' may be thinned. Although the structure of FIG. 3a is illustrated, it should be understood that it may be replaced by the structure (referred to as wafer 100') of FIG. 3c. It may also be replaced by the structures of FIGS. 3 band 3 d; however, since these structures are oriented upward, in such embodiments, the processes illustrated in FIGS. 4 to 7 are omitted. In FIG. 4, the wafer 100 is thinned to reduce the thickness of the wafer 100. Thinning may be performed by a CMP process, grinding, etching, or other suitable process. Thinning exposes the vias 120 in the wafer 100 and / or the chips 112 and also reduces the thickness of the wafer 100 and / or the chips 112 to provide better heat dissipation and take up less vertical space. After thinning, the wafer 100 and / or the chips 112 may have a thickness of about 2 to 100 μm, e.g., between about 10 and 50 μm. In some embodiments, a top surface of the gap fill material 155 and a top surface (the backside) of the wafer 100 and / or the chips 112 are substantially coplanar within process variations.In other embodiments, rather than prior to thinning, the vias 120 may be formed after thinning the wafer 100 and / or the chips 112. In such embodiments, the vias 120 may be formed using processes and materials similar to those described above for forming the vias, e.g., the interconnect structure 130.FIGS. 5-7 include a process for adding a bonding layer to the back side of the thinned substrate 115 of FIG. 4, in accordance with some embodiments. In FIG. 5, the substrate 115 may be recessed by any suitable process, for example, by an etch back process using a suitable wet or dry etch process. Thus, upper sidewalls of the vias 120 may be exposed. In some embodiments, the substrate 115 may be recessed by a depth of between 0.8 μm and about 3 μm, but other dimensions are also contemplated and may be used.In FIG. 6, a bond layer 160 may be deposited over the exposed portions of the vias 120. The bonding layer 160 may be made of any suitable insulating material, such as an oxide such as silicon oxide, a nitride such as silicon nitride, a polyimide, or the like. The bond layer 160 may be deposited using any suitable process. The bonding layer 160 may be formed by, for example, a CVD, PECVD, or ALD deposition process, FCVD, or a glass spin-on process.In FIG. 7, the bond layer 160 may be planarized, for example, by a CMP process, thereby forming a top surface of the vias 120 flush with the bond layer 160. The thickness of the bond layer 160 may be between about 0.8 μm and 3 μm, but other dimensions are also contemplated and may be used.FIGS. 8-10 include a process for adding a bonding layer to the back side of the thinned substrate 115 of FIG. 4, in accordance with some embodiments. In FIG. 8, a bonding layer 160 is deposited on the substrate 115 and the vias 120. The bond layer 160 may be formed using processes and materials similar to those discussed above with respect to FIG. 6. The thickness of the bond layer 160 may be between about 0.8 μm and 3 μm, but other dimensions are also contemplated and may be used.In FIG. 9, openings are formed in the bonding layer 160 corresponding to the vias 120. The openings may be formed using any suitable technique, such as laser or mechanical drilling or photolithography technology. In some embodiments, the openings may have a greater width than the vias 120.In FIG. 10, via extensions 165 are deposited in the openings of the bond layer 160. The via extensions 165 may be made of the same material or a different material than the material of the vias 120. The via extensions 165 may be formed by any suitable technique, such as using PVD, CVD, electroplating, electroless plating, etc. In some embodiments, a seed layer and / or a barrier layer may be deposited in the opening and over the bond layer 160 prior to depositing the via extensions 165. The material of the via extensions 165 may protrude above the openings and above the bond layer 160. After the deposition of the material of the via extensions 165, a planarization technique such as a CMP may be used to render the via extensions 165 flush with the bond layer 160. In some embodiments, via extensions 165 may be wider than vias 120, thereby forming a pad region.In embodiments, in a wafer-to-wafer or a wafer-to-chip bonding process, a wafer or a wafer stack may be bonded to the wafer 100 and / or the chips 112. In embodiments where a wafer stack is used, the wafer stack may be formed separately and bonded to the wafer 100 and / or the chips 112 as a pre-formed wafer stack. These embodiments will be described below.In FIG. 11, a top view of a wafer 200 having multiple chips 212 is illustrated, in accordance with some embodiments. The chips 212 may be configured to have the same chip function or different chip functions, respectively. In some embodiments, the chips 212 may be formed as a logic chip, such as a CPU chip, MCU chip, I / O chip, BB chip, AP chip, SoC, SoIC, or the like. In other embodiments, one or more of the chips 212 may be a memory chip, such as a DRAM chip or an SRAM chip, or the like. In the illustrated embodiments, multiple ones of the wafers 200 may be stacked to form a memory device stack. Between the chips 212 there are cutting lanes 211, which are provided for singulating the chips 212 in a subsequent process. The chips 212 may be considered as package areas and the intersecting lanes 211 may be considered as non-package areas. In general, no active or passive components are formed in the cutting lanes 211, i.e., the cutting lanes 211 are free of active or passive components.In FIG. 12, a cross-sectional view of a portion of wafer 200 is illustrated. In the illustrated section, a first die 212 and a second die 212 are illustrated and separated by a dicing street 211. Details are omitted for simplicity. It should be understood that the illustrations regarding the chips 212 are for information purposes and are not to be considered limited to any particular configuration.The chips 212 may include a substrate 215 having one or more passive devices formed therein. The substrate 215 may be formed from materials similar to those discussed above with respect to the substrate 115 and will not be repeated herein.The wafer 200 includes a device region 210 for each of the chips 212. The device regions 210 may be similar to the device regions 110 in that they include embedded devices such as transistors or other active devices such as diodes and possibly passive devices such as capacitors, inductors, resistors, or the like. Above the device area 210 is an interconnect structure (interconnect structure) 230 that connects devices together and passes input / output signals to the devices. The interconnect structure 230 may be formed using similar materials and processes as the interconnect structure 130 described above. In particular, the interconnect structure 230 may include multiple ILD layers, including an uppermost ILD layer, which in turn may include multiple layers, such as described above with respect to the dielectric layer 132.In FIG. 13, via openings 219 may be formed through the interconnect structure 230 and into the substrate 215. In some embodiments, the via openings may expose metallic features of the interconnect structure 230 for coupling to the active and / or passive devices in the device area 210. One or more of the via openings 219 may not expose metallic features of the interconnect structure 230, such that a via material subsequently formed in the via openings 219 is not coupled to any of the devices in the device region 210 and may be considered a dummy via. The via openings 219 may be formed using a photolithography process that uses, for example, photoresists and / or hard masks formed and patterned over the top dielectric layer of the interconnect structure 230. Anisotropic etching may be used to form the via openings through the photoresist and / or hard masks. Via openings 219 may be formed in substrate 215 in any structure.In FIG. 14, material for vias 220 may be formed over interconnect structure 230, in accordance with some embodiments. The vias 220 may be formed by processes similar to the formation of the vias of the interconnect structure 130 described above, but other suitable processes may be used. For example, a seed layer may be deposited in the via openings 219, and the vias 220 may be formed by depositing a conductive material in the via openings 219 on the seed layer, for example, by electroplating, electroless plating, PVD, CVD, or the like. In some embodiments, contact pads 225 (see FIG. 16 ) may be formed simultaneously. The vias 220 may be formed of copper or copper alloys, and may also be formed of other metals. The material for the vias 220 may protrude beyond the via openings 219 and cover portions of the interconnect structure 230.In FIG. 15, a planarization or grinding process may be used to render a top surface of vias 220 flush with a top surface of interconnect structure 230. In FIG. 16, contact pads 225 are formed. Contact pads 225 aare physically and electrically coupled to a via 220, and contact pads 225 bare not physically coupled to a via 220, but may be physically and electrically coupled to a metal line in interconnect structure 230. Therefore, they may also be electrically coupled to a via 220 via the interconnect structure 230. The contact pads 225 may be formed using any suitable process. For example, a resist layer may be deposited and patterned to form openings corresponding to the contact pads 225. A seed layer may be deposited in the openings and over the resist layer. Next, the contact pads 225 may be deposited using any suitable process and then made flush as desired. Finally, the resist layer may be removed, thereby also removing the seed layer and, if present, metal deposited on the seed layer over the resist layer. In another embodiment, contact pads 225 may also be deposited by forming a capping layer of conductive material and etching to remove the non-retention portions of the conductive material.In another embodiment, a dielectric layer may be deposited over the interconnect structure 230, openings corresponding to the contact pads 225 may be formed in the dielectric layer, a seed layer may be deposited in the openings, and the material of the contact pads 225 may be deposited in the openings on the seed layer. A planarization process may then provide a flat top surface.In FIG. 17, a dielectric layer 235 is deposited over the contact pads 225. In some embodiments, the dielectric layer 235 (or a sub-layer thereof) may correspond to the dielectric layer used to assist in the formation of the contact pads 225. The thickness of the dielectric layer 235 may be greater than the thickness of the contact pads 225 by 0 nm to 50 nm. In other words, in some embodiments, the dielectric layer 235 may be thicker than the contact pads 225, while in other embodiments, the dielectric layer 235 may have a top surface that is flush with the top surface of the contact pads 225.In FIG. 17, a dielectric layer 240 may also be deposited over the contact pads 225 as part of a bond structure 260 (see FIG. 19 ). The dielectric layer 235 and the dielectric layer 240 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like, and may be formed using any suitable process. The dielectric layer 235 and the dielectric layer 240 may be formed by, for example, a CVD, PECVD, or ALD deposition process, FCVD, or a glass spin-on process.In FIG. 18, bond pad vias 245 are formed. Bond pad vias 245 may be formed using processes and materials similar to vias 220 described above. In another embodiment, bond pad vias 245 may be formed simultaneously with bond pads 255 (see FIG. 19 ).In FIG. 19, a bonding layer 250 is deposited over the dielectric layer 240. The bond pads 255 are formed in the bond layer 250. The bond pads may be formed using any of the materials and processes described above with respect to the contact pads 225. In some embodiments, bond layer 250 is formed prior to forming bond pad vias 245. Then, bond pad vias 245 and bond pads 255 may be formed simultaneously by first forming openings in bond layer 250 corresponding to bond pads 255 and then openings in dielectric layer 240 corresponding to bond pad vias 245. Next, a barrier layer may be deposited simultaneously for both the bond pad vias 245 and the bond pads 255 in the openings, and then the conductive material of the bond pads 255. Finally, any excess conductive material present may be removed by a planarization or grinding process that renders the top surfaces of bond pads 255 and bond layer 250 flush.In some embodiments, the bond layer 250 may be formed of any suitable material and have a thickness between about 0.8 μm and about 3 μm, but other dimensions may also be used. In some embodiments, the bonding layer 250 may be formed of an oxide such as silicon oxide, a nitride such as silicon nitride, a polyimide, or the like. In some embodiments, the bonding layer 250 may be formed of the same material used to form the bonding layer 160. The bonding layer 250 is used to form a fusion bond with a further bonding layer 250 during a wafer-to-wafer bonding process. A similar process may also be used to form a fusion bond between the bond layer 250 and the bond layer 160 (see FIGS. 7 and 9 ).In FIG. 20 a, wafer 200 is inverted and bonded to wafer 100, for example, that of FIG. 7 or 10. The bonding technique used may be a hybrid bonding technique in which the bonding layer 160 of the wafer 100 and the bonding layer 250 of the wafer 200 are joined by fusion bonding and the bonding pad 255 is directly bonded to the via 120 by a direct metal-to-metal bond without using an intervening bonding material such as a solder or other eutectic material. Hybrid bonding has the advantage that no solder material is required between the two bonded connectors. Hybrid bonding creates a bonding interface between two devices that includes a direct metal-to-metal bond of the metallic features in a first device to metallic features in a second device, and a fusion bond (or dielectric-to-dielectric bond) of insulating materials in the first device to insulating materials in the second device. Any suitable hybrid bonding process may be used.In the hybrid bonding process, the bond pads 255 and the bond layer 250 are aligned and contacted with the vias 120 and the bond layer 160 of the wafer 100. Subsequently, an anneal may be performed to directly bond the conductive materials and to join the insulating materials together by fusion bonding. The anneal causes inter-diffusion of the metals in bond pads 255 and via 120 to cause direct metal-to-metal bonding. The anneal also causes the bond layer 250 and the bond layer 160 to be joined together by fusion bonding where they are in direct contact with each other by forming chemical bonds between the two layers. For example, the atoms (e.g., oxygen atoms) in one of the insulating materials of the bonding layers 160 and 250 may form chemical bonds (e.g., O-H bonds) with the atoms (e.g., hydrogen atoms) in the other of the bonding layers 160 and 250. The resulting bonds between the bonding layers 160 and 250 are insulator-to-insulator bonds. Slight asperities of the surfaces of the bond structures can be compensated for by the annealing process while the structures are held together by pressure. In some embodiments, a compressive force of about 1 to 10 Newtons may be applied to compress bond pads 255 and vias 120 and compress bond layer 250 and bond layer 160. In other embodiments, no compressive force is used. The hybrid bonding process may be performed at an ambient pressure of about 0.1 MPa to about 10 MPa, for example about 0.5 MPa (i.e., from about 1 atm to about 100 atm, for example about 5 atm). The material expansion at the annealing temperature may complete the bonding and substantially eliminate voids.Depending on the robustness of the material of the bond layers 160 and 250, the anneal temperature in the hybrid bonding process may be between about 150° C. and about 400° C. In embodiments where both bonding layers 160 and 250 are formed of inorganic dielectric materials such as an oxide or oxynitride, the annealing temperature may be between about 150° C. and about 400° C. The anneal time of the hybrid bonding process may be between about 0.5 hours and 5 hours.By forming the bonding layers 160 and 250 specifically for bonding the wafer 200 to the wafer 100, a better fusion bond can be formed. In particular, a thickness of the bonding layers 160 and 250 between about 0.8 μm and 3 μm or more represents a bonding layer thickness sufficient to allow formation of chemical bonds. The minimum target thickness of 0.8 μm is important for several reasons. This thickness provides a certain tolerance for layer thickness variations of the two bonding layers 160 and 250. Due to the variation in layer thickness, voids between the two layers can be observed when the two bonding layers 160 and 250 are joined. At the minimum thickness of about 0.8 μm, the bonding layer 160 and the bonding layer 250 may each extend vertically during the anneal, which helps fill such voids. The minimum thickness of 0.8 μm also offers sufficient opportunity to form bonds between the bond layers 160 and 250. In other words, chemical or covalent bonds may form between materials in the bond layer 160 and materials in the bond layer 250 during the annealing process(s). A minimum thickness of about 0.8 μm provides enough material for bonding so that the localized bonds in the bonding layer 160 as well as the bonding layer 250 can break and re-form as cross bonds with the opposing bonding layer 250 and 160, respectively. The minimum thickness of 0.8 μm also provides enough material to withstand multiple annealing cycles. As noted above and in the discussion below, subsequent structures (e.g., wafer 200, wafer stack 300, or wafer stack 400) may also be bonded in a subsequent anneal process after the various structures are bonded together in an anneal process. As discussed above, each annealing process may last between 0.5 hours and 5 hours. Therefore, the bonding layers 160 and the bonding layers 250 need to withstand multiple annealing processes. A minimum thickness of the bond layers 160 and 250 of about 0.8 μm provides adequate robustness to withstand these anneal cycles. It should be noted that in some embodiments, depending on the material of the bond layers 160 and 250, other thicknesses are contemplated, including thicknesses less than 0.8 μm. It is also understood that overall thickness variations may cause the thickness of the bond layers 160 and 250 to be less than 0.8 μm in some areas.The bonded conductive materials of bond pads 255 and vias 120 may have distinct interfaces. That is, after bonding, it is still possible to view the interface and determine that the bond pads 255 and the vias 120 have been separately formed and joined together. Similarly, the bonded insulating materials of the bonding layer 250 and the bonding layer 160 may also have a distinct interface.FIG. 20 aincludes an enlarged (enlarged) portion of the bonding interface. In this enlarged portion, a barrier layer 221 is illustrated as surrounding the via 220. Similarly, a barrier layer 121 is illustrated as surrounding via 120, and a barrier layer 246 is illustrated as surrounding bond pad vias 245.FIG. 20 b illustrates a hybrid bonding process in which the lower structure is not directed downward but rather directed upward, such as provided in FIGS. 3 band 3 d. In particular, FIG. 20 bcomprises the structure illustrated in FIG. 3 das a lower structure. The enlarged portion of FIG. 20 b illustrates a metal-to-metal bond of two bond pads and the fusion bonding of the bond layer 250 to the dielectric layer 132 after the hybrid bonding process. The enlarged portion also illustrates metallic features 131 including metal lines and vias in the interconnect structure 130, where some vias 120 may be electrically and physically coupled to the metallic features 131 in the interconnect structure 130, while others may not be coupled. Although the structure of FIG. 3 dis illustrated, the enlarged portion is also applicable to the structure of FIG. 3 bor 3 d.In FIG. 21, wafer 200 is thinned using any suitable process. Thinning may be performed by a CMP process, grinding, etching, or other suitable process. Thinning exposes the vias 220 in the chips 212 and also reduces the thickness of the chips 212 to provide better heat dissipation and take up less space. After thinning, the wafer 200 and the chips 212 may have a thickness of about 2 μm to 500 μm, for example between about 10 μm and 50 μm. In some embodiments, a top surface of the substrate 215 of the wafer 200 and a top surface of the vias 220 are flush with each other.In FIGS. 22-24, wafer 200 is prepared to be bonded to another wafer by adding a back bond layer 265 (FIG. 24 ), according to embodiments. In some embodiments, such as illustrated in FIG. 22, the substrate 215 of the wafer 200 may be recessed to expose the top sidewalls of the vias 220. This process may be similar to the process described above with respect to recessing the substrate 115 in FIG. 5. In particular, the substrate may be recessed by a depth of 0.8 μm to about 3 μm; in other words, the vias 220 may protrude from the substrate 215 by 0.8 μm to about 3 μm. In FIG. 23, the back bond layer 265 may be deposited over the exposed vias 220. The back bond layer 265 may be deposited using processes and materials similar to those described above with respect to the bond layer 160 of FIG. 6. In FIG. 24, the back bond layer 265 may be planarized by a CMP or grinding process to render the top surfaces of the back bond layer 265 flush with the top surfaces of the vias 220. This process may be similar to the process described above with respect to the bond layer 160 and the vias 120 of FIG. 7.In other embodiments, similar to the bonding layer 160 described above with reference to FIG. 8, the substrate 215 may not be recessed and the back bonding layer 265 may be deposited on the substrate 215 and the exposed vias 220. Next, similar to the process described above with reference to FIG. 9, openings may be formed in the back bond layer 265. Then, similar to the process described above with reference to FIG. 10, via extensions may be formed in the openings and the top surfaces of the via extensions may be configured flush with the top surface of the back bond layer 265.In FIG. 25, according to some embodiments, wafer 200 is bonded to wafer 200 aand another wafer 200 bis bonded to wafer 200 a. Wafer 200 bmay be bonded to wafer 200 ausing a hybrid bonding technique, such as that described above with reference to FIG. 20 a. In each subsequent hybrid bonding technique, structures already connected to a hybrid bonding technique may undergo an increase in their bond strength when performing the bonding anneal. Thus, in some embodiments, the bond strength may be different between different structures.In FIG. 26, the thinning process and formation of a back bond layer 265 as described above with reference to FIGS. 21 to 24 may be repeated on the wafer 200 band further wafers 200 up to a wafer 200 nmay be stacked and bonded using hybrid bonding techniques as described above with reference to FIG. 20 a. The total number of wafers 200 may be between about 1 and 16 or more. In some embodiments, each wafer 200 may be bonded with a minimum bond anneal time, e.g., between 30 min and 60 min, until the last wafer 200 nis bonded, which uses a longer bond anneal time, thereby increasing the bond strength of the already bonded structures and simultaneously decreasing the overall processing time. In some embodiments, the bond strength between the first bonded wafers is then greater than for later bonded wafers. For example, the bonding strength between wafers 200 aand 200 bmay be the greatest, the bonding strength between wafers 200 band 200 cmay be the second greatest, and so on.FIGS. 27-30 illustrate a process for forming a two-layer wafer stack 300 according to some embodiments that may be used for attaching to the wafer 100. In FIG. 27, the wafer 200 from FIG. 19 is attached as wafer 200 ato a carrier substrate 305 by a separating layer 310. The carrier substrate 305 and the separation layer 310 may be formed of similar materials as the carrier substrate 190 and the separation layer 150 described above with reference to FIGS. 3 a, 3 b, 3 cand 3 d. In FIG. 28, the processes described above with reference to FIGS. 21 to 24 may be performed to thin the wafer 200 aand form the back bonding layer 265 of the wafer 200 a.In FIG. 29, a second wafer 200 bis bonded to the first wafer 200 aby a hybrid bonding process as described above with reference to FIG. 20 a. In FIG. 30, the carrier substrate 305 may be removed, thereby forming the two-layer wafer stack 300. The carrier substrate 305 may be removed by irradiating the release layer 310 with UV radiation, a mechanical grinding process, an etch back process, a heating process, combinations thereof, or the like.In FIG. 31, the two-layer wafer stack 300 is bonded to the wafer 100, for example that of FIG. 10. The two-layer wafer stack 300 may be bonded to the wafer 100 using a hybrid bonding process, such as that described above with reference to FIG. 20 a.In FIG. 32, the two-layer wafer stack 300 becomes the wafer stack 300 a, and the process of bonding a two-layer wafer stack 300 may be repeated any number of times to bond a total of n two-layer wafer stacks 300 to the wafer 100. The total number of wafers 200 is 2 times n. Prior to bonding each other two-layer wafer stack 300, the previous two-layer wafer stack 300 may be processed to thin the top wafer 200 of the two-layer wafer stack 300 and form the back bond layer 265, such as described above with reference to FIGS. 21-24. In some embodiments, each wafer stack 300 may be bonded with a minimum bonding anneal time, e.g., between 30 min and 60 min, until the last wafer stack 300 nis bonded, which uses a longer bonding anneal time, thereby increasing the bond strength of the already bonded structures and simultaneously decreasing the overall processing time. In some embodiments, the bond strength between two-layer wafer stacks 300 is then greater than for later bonded wafer stacks. For example, the bond strength between wafer stacks 300 aand 300 bmay be the greatest, the bond strength between wafer stacks 300 band 300 cmay be the second greatest, and so on. Additionally, in some embodiments, the bond strength between the individual wafers 200 within the wafer stack 300 is greater than the bond strength between the wafer stacks 300.In FIG. 33, a four-layer wafer stack 400 is formed of individual wafers 200 including a wafer 200 a, a wafer 200 b, a wafer 200 c, and a wafer 200 d, according to some embodiments. The four-layer wafer stack 400 may be formed by continuing the process to add additional wafers 200, e.g., to the structure of FIG. 29. Prior to bonding each other wafer 200, the previous wafer 200 may be processed to thin the wafer 200 and form the back bond layer 265 as described above with reference to FIGS. 21-24. In some embodiments, each wafer 200 may be bonded with a minimum bond anneal time, e.g., between 30 min and 60 min, until the last wafer 200 dis bonded, which uses a longer bond anneal time, thereby increasing the bond strength of the already bonded structures and simultaneously decreasing the overall processing time.In FIG. 34, a four-layer wafer stack 400 is formed of two-layer wafer stacks 300 in accordance with some embodiments. The four-layer wafer stack 400 in FIG. 34 may be formed by adding another two-layer wafer stack 300 (see FIG. 30 ), for example, to the structure of FIG. 29. In another embodiment, a two-layer wafer stack 300, for example, that of FIG. 30, may be attached to a carrier substrate, and thereafter another two-layer wafer stack 300 or two wafers 200 may be bonded to the first two-layer wafer stack 300. In another embodiment, a two-layer wafer stack 300 may be bonded to a wafer 200, for example the structure of FIG. 28, and then another wafer 200. Prior to bonding each other wafer 200 or dual layer wafer stack 300, the previous wafer 200 or top wafer 200 of dual layer wafer stack 300 may be processed to thin wafer 200 and form back bond layer 265, such as described above with reference to FIGS. 21-24.In FIG. 35, the carrier substrate 405 may be removed, thereby forming the four-layer wafer stack 400. The four-layer wafer stack 400 is bonded to the wafer 100, for example, that of FIG. 10.In FIG. 36, the four-layer wafer stack 400 becomes the wafer stack 400 a, and the process for bonding a four-layer wafer stack 400 may be repeated any number of times to bond a total of n four-layer wafer stacks 400 to the wafer 100. The total number of wafers 200 is 4 times n. Prior to bonding each other four-layer wafer stack 400, the previous four-layer wafer stack 400 may be processed to thin the top wafer 200 of the four-layer wafer stack 400 and form the back bond layer 265, such as described above with reference to FIGS. 21-24. In some embodiments, each wafer stack 400 may be bonded with a minimum bonding anneal time, e.g., between 30 min and 60 min, until the last wafer stack 400 nis bonded, which uses a longer bonding anneal time, thereby increasing the bond strength of the already bonded structures and simultaneously decreasing the overall processing time. In some embodiments, the bond strength between four-layer wafer stacks 400 is then greater than in the case of later bonded wafer stacks 400. For example, the bond strength between wafer stacks 400 aand 400 bmay be the greatest, the bond strength between wafer stacks 400 band 400 cmay be the second greatest, and so on. In addition, in some embodiments, the bonding strength between the individual wafers 200 within the respective wafer stacks 400 is greater than the bonding strength between the wafer stacks 400.In FIGS. 37 a, 37 b, 37 cand 37 d, any combination of any number of wafers 200, two-layer wafer stacks 300 and / or four-layer wafer stacks 400 may be bonded in any order to the wafer 100 resulting from FIGS. 3 aand 3 bor the wafer 100' resulting from FIGS. 3 cand 3 d. It is noted that in FIGS. 37 band 37 d, the dielectric layer 132 may be synonymous with the bonding layer 160. In some embodiments, wafer 100' may be modified to add an upper bonding layer 160 over gap fill material 155 by recessing gap fill material 155 and depositing bonding layer 160 where gap fill material 155 has been removed. In other embodiments, wafer 100' may be modified to add an upper bonding layer 160 over gap fill material 155 by depositing a bonding layer 160 over gap fill material 155 and over chips 112, forming openings in bonding layer 160 exposing contact pads 125, and expanding contact pads 125 through the openings into bonding layer 160. These processes are described above with reference to FIGS. 5 to 6 and FIGS. 8 to 10, and may be modified as necessary from these embodiments.In some embodiments, each wafer 200, two-layer wafer stack 300 or four-layer wafer stack 400 may be bonded with a minimum bonding anneal time, e.g., between 30 min and 60 min, until the last wafer 200 or wafer stack 300 or 400 is bonded, respectively, using a longer bonding anneal time, thereby increasing the bond strength of the already bonded structures and simultaneously decreasing the overall processing time.The total number of wafers 200 may be determined by the combination of the individual wafers 200, dual-layer wafer stacks 300 and four-layer wafer stacks 400. The total number of wafers 200 may be between one wafer 200 and about twenty wafers 200, for example. Prior to bonding each additional wafer 200, dual layer wafer stack 300 or four layer wafer stack 400, the previous wafer 200, dual layer wafer stack 300 or four layer wafer stack 400, respectively, may be processed to thin the top wafer 200 and form the back bond layer 265, such as described above with reference to FIGS. 21-24.In an embodiment, each wafer 200 may be a memory wafer and a stack of wafers 200 may form a memory cube. The memory cube may include, for example, eight wafers 200. In some embodiments, in addition to a design number of wafers 200, one or more extra wafers 200 may be included to provide replacement capacity in the event that one or more of the wafers 200 fails a test. For example, in one embodiment, nine wafers 200 may be bonded to wafer 100 or wafer 100', which may be a memory controller. If it is determined that one of the nine wafers 200 is defective, the memory controller may be programmed to bypass the defective wafer 200 without losing the functionality of the entire combination of memory and controller.In some embodiments, one or more of the various layers of the wafers 200 may have different functionality.In FIG. 38a, after thinning the top wafer 200 (i.e., wafer 200n), the carrier substrate 190 is removed, then the packages 500 are singulated, and then connectors 515 are formed on the front side of wafer 100 / 100'. These processes may be performed in any suitable order. In some embodiments, first the carrier substrate 190 is removed, then the connectors 515 are formed, and then the packages 500 are singulated. In other embodiments, first the packages 500 with the carrier substrate 190 thereon are singulated, then the carrier substrate 190 is removed, and then the connectors 515 are formed. These processes will be described in more detail below.An optional thermal interface (TIM) material 540 and a heat dissipation structure 550, which will be described in more detail below, are also illustrated in FIG. 38 a. FIG. 38 aalso includes an optional redistribution structure 530, which may be formed using materials and processes similar to those described above with respect to the interconnect structure 130, and are not repeated here.The packages 500 may be singulated using any suitable cutting technique 560. The cutting technique 560 may include dry etching, wet etching, anisotropic etching, or plasma etching using suitable etchants. The cutting technique 560 may include multiple passes of a laser to laser separate the packages 500. The cutting technique 560 may include a mechanical process, such as a saw, configured to cut to a desired depth. A combination of the aforementioned cutting techniques 560 may also be used. The separation takes place in the non-package regions (outside the regions of the packages 500, see e.g. the cutting lanes 111 in FIG. 1 and the cutting lanes 211 in FIG. 11 ). Dicing cuts through the processed wafer stacks down to the separation layer 150. In some embodiments, singulation may proceed further through the separation layer 150 and also further into or through the carrier substrate 190.Connectors 515 are formed on a front side of the wafer 100. The connectors 515 may be formed using any suitable process and include various configurations. In some embodiments, the connectors 515 may be controlled collapse chip connection (C4) bumps, micro bumps, solder bumps, or the like. For example, openings (not shown) may be formed in a passivation layer deposited on the front side of the wafer 100, the opening exposing metallic features, such as contact pads 125 of the wafer 100 or metal lines of the optional redistribution structure 530. Connectors 515 are formed in the openings. In some embodiments, a UBM (under bump metallurgy) layer may be formed in the openings prior to forming the connectors 515. In the illustrated embodiment, the connectors 515 have lower portions 505 (closer to the wafer 100) comprising a conductive material and upper portions 510 (further away from the wafer 100) comprising a solder material. The bottom portions 505 and the top portions 510 may also be referred to as conductive pillars 505 and solder caps 510, respectively.The connectors 515 may be coupled to conductive features of the wafer 100 as well as to individual ones of the wafers 200 ato 200 n, through the vias 120 / 220, the bond pad vias 245, and the interconnect structures 130, 230, and / or 530.Optional thermal interface material (TIM) 540 is formed over the packages 500. The TIM 540 is a material having good thermal conductivity that may be greater than about 5 W / m·K and may be equal to or greater than about 50 W / m·K or 100 W / m·K. The optional heat dissipation structure 550 may be attached through the TIM 540, which may also be adhesive. The heat dissipation structure 550 has high thermal conductivity and may be formed using a metal, a metal alloy, or the like. For example, the heat dissipation structure 550 may include a metal such as Al, Cu, Ni, Co, and the like, or an alloy thereof. The heat dissipation structure 550 may also be formed of a composite material selected from the group consisting of silicon carbide, aluminum nitride, graphite, and the like. The heat dissipation structure 550 may be used to dissipate heat through each of the bonded wafers 100 / 100' and the wafers 200. The through vias 120 of the wafer 100 / 100' and the through vias 220 of the wafer 200 may effectively remove the heat generated by the device regions 110 (see FIG. 2 ) and / or the device regions 210 (see FIG. 12 ). When the through vias 120 and the through vias 220 are aligned with each other, such as as illustrated, heat dissipation may be more efficient. However, in some embodiments, depending on the design of the device regions 110 and the device regions 210 and the routing of the metal lines and the through vias in the interconnect structures 130 and 230, it is also contemplated that the through vias 120 and the through vias 220 are not aligned with each other or may be omitted as appropriate.FIG. 38b is similar to FIG. 38a, except that wafer 100 / 100' is directed upwardly so that the back side of the wafer is directed downwardly (as illustrated in FIGS. 37b and 37d, for example). In such embodiments, the carrier substrate 190 may be removed and the substrate 115 of the wafer 100 may be thinned to expose the vias 120. Then, a redistribution structure 530 may be formed to interconnect the vias 120 on the back side of the wafer 100 / 100' or the front side of the package 500 as needed. Redistribution structure 530 may be formed using processes and materials similar to interconnect structure 130 described above with respect to FIG. 2. Then, similar to the description above with reference to FIG. 38 a, the packages 500 may be singulated, the connectors 515 formed, the TIM 540 formed, and the heat dissipation structure 550 deposited.Figures 38a and 38b also provide a combined view of wafer 100 / 100' illustrating both wafer 100 and wafer 100' of Figures 37a, 37b, 37c and 37d. In particular, the gap filling material 155 according to FIGS. 37 cand 37 dis illustrated in the left half of FIGS. 38 aand 38 b, whereas the gap filling material 155 according to FIGS. 37 aand 37 bis not used in the right half of FIGS. 38 aand 38 b.Embodiments include a stack process with hybrid wafer-to-wafer bonding to provide great flexibility in forming a packaged device having multiple functions. To achieve a high quality bond between the wafers, a bond layer may be formed on adjacent dies to provide fusion bonding between the bond layers that is less prone to errors than other bonding processes. By providing a contact area (e.g., contact pad) that is larger than an adjacent metallic feature, which may be a portion of a via, for example, the metallic features of the wafer may be flexibly aligned. Additionally, the metallic features, such as through vias, may be used to conduct signals through and / or remove heat from the entire package structure.An embodiment is a method that includes thinning a first wafer to expose metal vias. A bonding layer is formed over the metal vias, the metal vias extending through the bonding layer. A second wafer is pressed against the first wafer with bond pads of the second wafer aligned with the metal vias of the first wafer, and the bond pads of the second wafer are bonded to the metal vias of the first wafer without using a bonding material between the bond pads and the metal vias. The bonding layer of the first wafer is joined to a bonding layer of the second wafer. In an embodiment, forming the bond layer may include: recessing a first material surrounding the metal vias; depositing a second material corresponding to the bond layer; and planarizing the second material to render a top surface of the second material flush with top surfaces of the metal vias. In an embodiment, forming the bond layer may include: depositing the bond layer over the metal vias; forming openings in the bond layer, the openings corresponding to the metal vias; depositing a metal via extension in the openings, the metal via extension being physically coupled to the metal vias; and planarizing the metal via extension to render a top surface of the bond layer flush with top surfaces of the metal vias. In an embodiment, the first wafer and the second wafer together form a first wafer stack, further optionally comprising: pressing the first wafer stack against a third wafer, wherein bond pads of the first wafer are aligned with metallic features of the third wafer; bonding the bond pads of the first wafer to the metallic features of the third wafer without using a bonding material between the bond pads and the metallic features; and joining a bond layer of the first wafer to a bond layer of the third wafer. In an embodiment, the first wafer may include a controller for controlling devices in the first wafer stack. In an embodiment, the first wafer is directed downward and the third wafer is directed upward, bonding a side of the third wafer to a side of the first wafer. In one embodiment, the method may comprise: singulating a stacked component package from the first wafer and the second wafer. In an embodiment, the first wafer and the second wafer together form a first wafer stack, the method may further include: forming a second wafer stack that may include a two-layer wafer stack; thinning the second wafer to expose second metal vias of the first wafer stack; forming a second bonding layer over the second metal vias, the second metal vias extending through the second bonding layer; pressing the second wafer stack against the first wafer stack, with bond pads of the second wafer stack aligned with the second metal vias; bonding the bond pads of the second wafer stack to the second metal vias of the first wafer stack without using a bonding material between the bond pads of the second wafer stack and the second metal vias; and joining the second bonding layer to a bonding layer of the second wafer stack to form a first four-layer wafer stack. In an embodiment, the method includes bonding bond pads of the first four-layer wafer stack to metallic features of the third wafer without using a bonding material between the bond pads and the metallic features; and joining a bond layer of the first four-layer wafer stack to a bond layer of the third wafer. In an embodiment, each of the wafers in the first four-layer wafer stack is directed downward. In an embodiment, the bonding layer of the first wafer has a thickness between 0.8 μm and 3 μm.Another embodiment is a package including a first device, a second device, and a third device. The first device may include a first set of vias, first active devices, and a first interconnect structure, the first set of vias traversing the first interconnect structure from a front side of the first device to a back side of the first device, the first active devices being adjacent to the first interconnect structure. The second device may include a second set of vias, second active devices, a second interconnect structure, a second front bond layer, and a second back bond layer, the second back bond layer being on a back side of the second device, the second back bond layer may include a first dielectric material, the second front bond layer being bonded to the first device, the second set of vias traversing the second back bond layer from the second front bond layer. The third device may include a third set of vias, third active devices, a third interconnect structure, and a third front bond layer, wherein the third front bond layer may include a same dielectric material as the first dielectric material, wherein the third set of vias traverse the third device from the third front bond layer to a back side of the third device, wherein the second back bond layer is bonded to the third front bond layer. In an embodiment, the third front bond layer may include a set of bond pad vias and a set of bond pads, each of the bond pads having an interface with a corresponding via of the second set of vias. In an embodiment, the package may include: a thermal interface material disposed on the third device, wherein the thermal interface material is in contact with the third set of vias and a heat dissipation feature is disposed over the thermal interface material. In an embodiment, the first device is laterally surrounded by a gap fill material, wherein the second front bonding layer overlaps the gap fill material. In an embodiment, the first device may further include a first set of bond pads electrically coupled to the first set of vias, the first set of bond pads directly bonded to second bond pads disposed on the second front bond layer. In an embodiment, the second front bonding layer and the second rear bonding layer each have a thickness between 0.8 μm and 3 μm.Another embodiment is a package component comprising a first wafer bonded to a second wafer, wherein metal vias of the first wafer are directly bonded to bond pads of the second wafer at a bonding interface, and a first bond layer of the first wafer is joined to a second bond layer of the second wafer, wherein the first bond layer is disposed at a back side of the first wafer, wherein the metal vias of the first wafer traverse the first bond layer, a semiconductor substrate, and a first interconnect of the first wafer. In an embodiment, the package component may include: a third wafer, wherein a fourth bonding layer of the third wafer is bonded to a third bonding layer of the second wafer; and a fourth wafer, wherein a sixth bonding layer of the fourth wafer is bonded to a fifth bonding layer of the third wafer. In an embodiment, the first wafer, the second wafer, the third wafer, and the fourth wafer are directed downward. In an embodiment, the bond pads of the second wafer are coupled to a second interconnect of the second wafer by bond pad vias through the second bond layer. In an embodiment, a first dielectric material of the first bonding layer is the same as a second dielectric material of the second bonding layer, and the first bonding layer and the second bonding layer each have a thickness between 0.8 μm and 3 μm.

Claims

A method comprising: thinning a first wafer to expose metal vias; forming a bonding layer over the metal vias, the metal vias extending through the bonding layer; positioning a second wafer on the first wafer, bond pads of the second wafer aligned with the metal vias of the first wafer; bonding the bond pads of the second wafer to the metal vias of the first wafer without using a bonding material between the bond pads and the metal vias; and joining the bond layer of the first wafer to a bond layer of the second wafer.The method of claim 1, wherein forming the bond layer comprises: recessing a first material surrounding the metal vias; depositing a second material corresponding to the bond layer; and planarizing the second material to render a top surface of the second material flush with top surfaces of the metal vias.The method of claim 1, wherein forming the bond layer comprises: depositing the bond layer over the metal vias; forming openings in the bond layer, the openings corresponding to the metal vias; depositing a metal via extension in the openings, the metal via extension being physically coupled to the metal vias; and planarizing the metal via extension to render a top surface of the bond layer flush with top surfaces of the metal vias.The method of any preceding claim, wherein the first wafer and the second wafer together form a first wafer stack, further comprising: positioning the first wafer stack on a third wafer, wherein bond pads of the first wafer are aligned with metallic features of the third wafer; bonding the bond pads of the first wafer to the metallic features of the third wafer without using a bonding material between the bond pads and the metallic features; and joining a bond layer of the first wafer to a bond layer of the third wafer.The method of claim 4, wherein the first wafer comprises a controller for controlling devices in the first wafer stack.The method of claim 4 or 5, wherein the first wafer is directed downward and the third wafer is directed upward, wherein a side of the third wafer is bonded to a side of the first wafer.The method of any preceding claim, wherein the bonding layer of the first wafer has a thickness between 0.8 μm and 3 μm.The method of any preceding claim, wherein the first wafer and the second wafer together form a first wafer stack, further comprising: forming a second wafer stack comprising a two-layer wafer stack; thinning the second wafer to expose second metal vias of the first wafer stack; forming a second bonding layer over the second metal vias, the second metal vias extending through the second bonding layer; positioning the second wafer stack on the first wafer stack, with bond pads of the second wafer stack aligned with the second metal vias; bonding the bond pads of the second wafer stack to the second metal vias of the first wafer stack without using a bonding material between the bond pads of the second wafer stack and the second metal vias; and joining the second bonding layer to a bonding layer of the second wafer stack to form a first four-layer wafer stack.The method of claim 7, further comprising: positioning the first four-layer wafer stack on a third wafer, wherein bond pads of the first four-layer wafer stack are stacked on metal features of the third wafer; bonding the bond pads of the first four-layer wafer stack to the metal features of the third wafer without using a bonding material between the bond pads and the metal features; and joining a bond layer of the first four-layer wafer stack to a bond layer of the third wafer.The method of any of the preceding claims 8 to 9, wherein each wafer in the first four-layer wafer stack is directed downward.A package comprising: a first device, the first device comprising a first set of vias, first active devices, and a first interconnect structure, the first set of vias traversing the first interconnect structure from a front side of the first device to a back side of the first device, the first active devices being adjacent to the first interconnect structure; a second device, the second device comprising a second set of vias, second active devices, a second interconnect structure, a second front bond layer, and a second back bond layer, the second back bond layer being on a back side of the second device, the second back bond layer comprising a first dielectric material, the second front bond layer being bonded to the first device, the second set of vias traversing the second back bond layer from the second front bond layer; and a third device, wherein the third device comprises a third set of vias, third active devices, a third interconnect structure, and a third front bond layer, wherein the third front bond layer comprises a same dielectric material as the first dielectric material, wherein the third set of vias traverse the third device from the third front bond layer to a back side of the third device, wherein the second rear bond layer is bonded to the third front bond layer, wherein the third device comprises a third set of bond pads directly bonded to the second set of vias without using an intervening bond material.The package of claim 11, wherein the second front bonding layer and the second back bonding layer each have a thickness between 0.8 μm and 3 μm.The package of claim 11 or 12, further comprising: a thermal interface material disposed on the third device, wherein the thermal interface material is in contact with the third set of vias and a heat dissipation feature is disposed over the thermal interface material.The package of any of the preceding claims 11 to 13, wherein the first device is laterally surrounded by a gap fill material, the second front bonding layer overlapping the gap fill material.The package of any of the preceding claims 11 to 14, wherein the first device further comprises a first set of bond pads electrically coupled to the first set of vias, the first set of bond pads directly bonded to second bond pads disposed on the second front bond layer.A package component comprising: a first wafer bonded to a second wafer, wherein metal vias of the first wafer are directly bonded to bond pads of the second wafer at a bonding interface without using an intervening bonding material, and a first bond layer of the first wafer is joined to a second bond layer of the second wafer, wherein the first bond layer is disposed at a back side of the first wafer, wherein the metal vias of the first wafer traverse the first bond layer, a semiconductor substrate, and a first interconnect of the first wafer.The package component of claim 16, further comprising: a third wafer, wherein a fourth bonding layer of the third wafer is bonded to a third bonding layer of the second wafer; and a fourth wafer, wherein a sixth bonding layer of the fourth wafer is bonded to a fifth bonding layer of the third wafer.The package component of claim 17, wherein the first wafer, the second wafer, the third wafer, and the fourth wafer are directed downward.The package component of any of the preceding claims 16 to 18, wherein the bond pads of the second wafer are coupled to a second interconnect of the second wafer by bond pad vias through the second bond layer.The package component of any of the preceding claims 16 to 19, wherein a first dielectric material of the first bonding layer is the same as a second dielectric material of the second bonding layer; and wherein the first bonding layer and the second bonding layer each have a thickness between 0.8 μm and 3 μm.

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