INTERCONNECT STRUCTURE WITH STACK OF DIELECTRIC CUTTING LAYER AND Etching Stop LAYER AND METHOD

Abstract

A method for forming a semiconductor device, wherein the method comprises: Forming a first conductive feature (112) in a first dielectric layer (111) arranged over a substrate (101); Forming a metal cover layer (116) over an upper surface of the first conductive feature (112) distal to the substrate (101); selective formation of a dielectric cover layer (117) over an upper surface of the first dielectric layer (111) and laterally adjacent to the metal cover layer (116), wherein the metal cover layer (116) is exposed by the dielectric cover layer (117); and Forming an etch stop layer stack (118) over the metal cover layer (116) and the dielectric cover layer (117), wherein the etch stop layer stack (118) has several etch stop layers, wherein the dielectric cover layer (117) is formed from a nitride-containing dielectric material, wherein the formation of the etch stop layer stack (118) exhibits: Forming a layer (119) of aluminium nitride over the metal cover layer (116) and the dielectric cover layer (117); Forming a layer of oxygen-doped silicon carbide (123) over the layer of aluminum nitride (119); and Forming a layer of aluminum oxide (125) over the layer of oxygen-doped silicon carbide (123), the formation of the etch stop layer stack (118) further comprises: Forming another layer of aluminium oxide (121) between the layer of aluminium nitride (119) and the layer of oxygen-doped silicon carbide (123).

Description

BACKGROUND

[0001] High-density integrated circuits, such as very large-scale integration (VLSI) circuits, are typically formed with multiple metallic interconnects to serve as three-dimensional wiring patterns. The purpose of the multiple interconnects is to properly interconnect densely packed devices. As integration levels increase, the effect of parasitic capacitance between the metallic interconnects, which leads to RC delay and crosstalk, increases accordingly. To reduce the parasitic capacitance and increase the conduction speed between the metallic interconnects, low-k dielectric materials are commonly used to form inter-layer dielectric (ILD) and inter-metal dielectric (IMD) layers.

[0002] Metal lines and vias are formed in the IMD layers. A formation process may include forming an etch stop layer over first conductive features and forming a low-k dielectric layer over the etch stop layer. The low-k dielectric layer and the etch stop layer are patterned to form a trench and a via opening. The trench and via opening are then filled with a conductive material, followed by a planarization process to remove excess conductive material, forming a metal line and a via.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2013 / 0 277 853 A1 and US 2017 / 0 278 742 A1.

[0004] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 to 7 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to one embodiment. Fig. 8 to 10 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to another embodiment. Fig. 11 illustrates a cross-sectional view of a semiconductor device according to another embodiment. Fig. 12 illustrates a cross-sectional view of a semiconductor device according to another embodiment. Fig. 13 illustrates a cross-sectional view of a semiconductor device according to another embodiment. Fig. 14 illustrates a flowchart of a method of forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not necessarily in direct contact.

[0007] Furthermore, spatially relative terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.Throughout the description of the present text, unless otherwise indicated, the same or similar reference numerals in different figures refer to the same or a similar element formed by a same or similar forming process using one or more same or similar materials.

[0008] According to some embodiments, an interconnect structure of a semiconductor device and the method for forming it are provided. According to some embodiments of the present disclosure, forming an interconnect structure includes forming a metal cap over a first conductive feature (e.g., a conductive line) disposed in a first dielectric layer. A dielectric capping layer, which is a nitride-containing dielectric material, is selectively formed on the top surface of the first dielectric layer and laterally adjacent to the metal capping layer. The dielectric capping layer may be formed by a selective deposition process or by an ion implantation process.The dielectric cap layer reduces leakage current paths between adjacent conductive lines in the first dielectric layer at the interface between the first dielectric layer and a subsequently formed second dielectric layer and improves time-dependent dielectric brakedown (TDDB) behavior. Next, an etch stop layer stack comprising a plurality of etch stop layers (e.g., three or four etch stop layers) is formed on the dielectric cap layer and the metal cap layer. In some embodiments, the etch stop layer stack includes an aluminum nitride layer, a first aluminum oxide layer, an oxygen-doped silicon carbide (ODC) layer, and a second aluminum oxide layer formed sequentially over the dielectric cap layer and the metal cap layer.The film regime of the etch stop layer stack realizes several advantages. For example, the etch stop layer stack prevents copper in the first conductive feature from diffusing upward into the etch stop layers and the overlying second dielectric layer. The upward diffusion of copper can reduce the etch rates of the second dielectric layer and the etch stop layer stack in the subsequent etch process for forming vias. These reduced etch rates can cause the etching of the via openings to stop prematurely, resulting in a failure of the electrical connection between the vias and the underlying conductive lines. The film regime of the etch stop layer prevents the above-mentioned problem by preventing copper diffusion. Other advantages include a better etch selectivity window and further reduced leakage current.

[0009] Fig. 1 to 7 illustrate cross-sectional views of a semiconductor device 100 at various stages of manufacturing according to one embodiment. The semiconductor device 100 may be a device wafer including active devices (e.g., transistors, diodes, or the like) and / or passive devices (e.g., capacitors, inductors, resistors, or the like). In some embodiments, the semiconductor device 100 is an interposer wafer, which may optionally include active devices and / or passive devices. According to another embodiment of the present disclosure, the semiconductor device 100 is a package substrate strip, which may be package substrates with cores therein or coreless package substrates. In the subsequent discussion, a device wafer is used as an example of the semiconductor device 100.It will be apparent to one skilled in the art that the teachings of the present disclosure may also be applied to interposer wafers, package substrates, or other semiconductor structures.

[0010] As in Fig. 1, the semiconductor device 100 includes a semiconductor substrate 101 and integrated circuit devices 103 (e.g., active devices, passive devices) formed on or in the semiconductor substrate 101 (may also be referred to as substrate 101). The semiconductor substrate 101 may include a semiconductor material, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 101 may include other semiconductor materials, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used.

[0011] In the example of Fig. 1, integrated circuit devices 103 are formed on or in the semiconductor substrate 101. Example integrated circuit devices 103 include transistors (e.g., complementary metal-oxide semiconductor (CMOS) transistors), resistors, capacitors, diodes, and the like. The integrated circuit devices 103 may be formed using any suitable method; the details are not discussed further here.

[0012] After the integrated circuit devices 103 are formed, an interlayer dielectric (ILD) layer 107 is formed over the semiconductor substrate 101 and over the integrated circuit devices 103. The ILD layer 107 may fill spaces between the gate stacks of the transistors (not shown) of the integrated circuit devices 103. According to some embodiments, the ILD layer 107 comprises silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethylorthosilicate (TEOS), or the like.The ILD layer 107 may be formed using spin coating, flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like.

[0013] We stay with Fig. 1. Contact plugs 105 are formed in the ILD layer 107, electrically coupling the integrated circuits 103 to overlying conductive features, such as metal lines, vias, and conductive posts. Note that throughout this disclosure, unless otherwise stated, "conductive features" refers to electrically conductive features. According to some embodiments, the contact plugs 105 are formed from a conductive material such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.Forming the contact plugs 105 may include forming contact openings in the ILD layer 107, forming one or more conductive materials in the contact openings, and performing a planarization process, such as chemical mechanical polishing (CMP), to make the top surface of the contact plugs 105 flush with the top surface of the ILD layer 107.

[0014] Next, a plurality of intermetal dielectric (IMD) layers, such as 109 and 111, are formed over the ILD layer 107. The IMD layers 109 and 111 may be formed from a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. According to some embodiments, the IMD layers 109 and 111 are formed from a low-k dielectric material having a dielectric constant (k) of less than 3.0, such as about 2.5, about 2.0, or even lower. The IMD layers 109 and 111 may comprise Black Diamond (a registered trademark of Applied Materials), a carbonaceous low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like.Forming each of the IMD layers 109 and 111 may include depositing a porogen-containing dielectric material over the ILD layer 107 and then performing a curing process to expel the porogen, thereby forming, for example, the pore-containing IMD layer. Other suitable methods may also be used to form the IMD layers 109 and 111. In an exemplary embodiment, the IMD layers 109 and 111 are formed from SiCO using a chemical vapor deposition (CVD) process, wherein each of the IMD layers 109 and 111 (for example, SiCO) has a thickness between about 20 nm and about 60 nm and has a k value between about 2.8 and about 3.5.A concentration of oxygen in the IMD layers 109 and 111 may be between about 40 atomic percent (at%) and about 55 at%, a concentration of carbon in the IMD layers 109 and 111 may be between about 5 at% and about 20 at%, and a concentration of silicon in the IMD layers 109 and 111 may be between about 39 at% and about 40 at%.

[0015] As in Fig. 1, conductive features 112 (e.g., metal lines) are formed in the IMD layer 111. In the illustrated example, the conductive features 112 are metal lines comprising a diffusion barrier layer 113 (which may also be referred to as a barrier layer) and a conductive material 115 (e.g., copper or a copper-containing material) over the diffusion barrier layer 113. The diffusion barrier layer 113 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. After the diffusion barrier layer 113 is formed, the conductive material 115 is formed over the diffusion barrier layer 113. Forming the conductive features 112 may comprise a single damascene process, although other suitable formation methods may be used.The conductive feature 112 may also be referred to below as a conductive line 112 or a metal line 112, although it should be understood that the conductive feature 112 may also be or include other features, such as a via or a conductive line with an underlying via connected to the conductive line. Although . Fig. 1 illustrates one or more IMD layers 109 formed between the IMD layer 111 and the ILD layer 107, this is merely a non-limiting example. It will be apparent to those skilled in the art that the IMD layer 111 may be formed directly on the ILD layer 107 (e.g., physically contacting it). Furthermore, although in Fig. 1, conductive features, such as conductive lines and / or vias, are formed in the IMD layers 109 to electrically couple the conductive lines 112 to the integrated circuit elements 103.

[0016] Next, a metal cap layer 116 is formed (e.g., selectively formed) on the upper surfaces of the conductive lines 112. The portion of the metal cap layer 116 on each conductive line 112 is also referred to as a metal cap 116 for the underlying conductive line 112. In some embodiments, the metal cap layer 116 is formed from an electrically conductive material, such as a metal or a metal-containing material. According to some embodiments of the present disclosure, the metal cap layer 116 is formed from cobalt (Co), CoWP, CoB, tungsten (W), tantalum (Ta), nickel (Ni), molybdenum (Mo), titanium (Ti), iron (Fe), combinations thereof, and / or alloys thereof. A suitable formation method, such as PVD, CVD, PECVD, ALD, or the like, may be used to form the metal cap layer 116. For example, a thickness of the metal cap layer 116 may be between about 2 nm and about 4 nm.

[0017] In the example of Fig. 1, the metal cap 116 on each conductive line 112 has the same width as the conductive line 112, such that sidewalls of the metal cap 116 are aligned (e.g., vertically aligned) with respective sidewalls of the barrier layer 113 of the conductive line 112. In other embodiments, the metal cap 116 on each conductive line 112 has the same width as the conductive material 115 of the conductive line 112, such that sidewalls of the metal cap 116 are aligned (e.g., vertically aligned) with respective sidewalls of the conductive material 115.

[0018] In some embodiments, the metal cap layer 116 is formed by a selective deposition process having a first deposition rate on the conductive line 112 and a second deposition rate on the IMD layer 111, wherein the first deposition rate is higher than the second deposition rate. After the selective deposition process, an etching process is performed to remove the metal cap layer 116 from the upper surfaces of the IMD layer 111. In another embodiment, the metal cap layer 116 is deposited over the conductive lines 112 and the IMD layer 111.Next, a patterned mask layer (e.g., a patterned photoresist layer) is formed over the metal cap layer 116, wherein portions of the metal cap layer 116 above (e.g., directly above) the conductive lines 112 are covered by the patterned mask layer, and portions of the metal cap layer 116 above (e.g., directly above) the IMD layer 111 are exposed by patterns (e.g., openings) of the patterned mask layer. Subsequently, an etching process is performed to remove the portions of the metal cap layer 116 exposed by the patterns of the patterned mask layer. After the etching process, the patterned mask layer is removed by a suitable process, such as ashing.

[0019] We now turn Fig. 2, where a dielectric capping layer 117 is formed (e.g., selectively formed) on the top surface of the IMD layer 111. In some embodiments, the dielectric capping layer 117 is a nitride-containing dielectric material, such as SiN x , SiON x or SiCN x , where x can be 1 or 2. A thickness of the dielectric capping layer 117 can be between about 0.5 nm and about 5 nm or between about 1 nm and about 5 nm. A density of the dielectric capping layer 117 can be between about 1.5 g / cm 3 and about 3.2 g / cm 3 be.

[0020] In the example of Fig. 2, the dielectric capping layer 117 is formed by a suitable deposition process, such as PECVD. In some embodiments, the PECVD process is performed using a nitrogen-containing gas source, such as N2, NH3, NO, or N2O. A carrier gas, such as Ar, N2, O3, or a mixture of He and O2, is used to transport the nitrogen-containing gas source into a process chamber for the PECVD process. After the dielectric capping layer 117 is formed, a concentration of nitride in the dielectric capping layer 117 is, in some embodiments, between about 2 at% and about 10 at%. Besides the PECVD process, other methods for forming the dielectric capping layer 117 are possible and are intended to be fully included within the scope of the present disclosure.For example, an embodiment in which the dielectric cap layer 117 is formed by an ion implantation process will be described below with reference to FIG. Fig. 8-10 discussed.

[0021] In some embodiments, the material of the dielectric capping layer 117 is formed at a first deposition rate on the IMD layer 111 during the PECVD process for forming the dielectric capping layer 117 and is formed at a second deposition rate on the metal capping layer 116, wherein the first deposition rate is higher than the second deposition rate. After the PECVD process, an etching process may be performed to remove the material of the dielectric capping layer 117 from the top surface of the metal capping layer 116, and the remaining portions of the material of the dielectric capping layer 117 on the top surface of the IMD layer 111 form the dielectric capping layer 117.

[0022] In the example of Fig. 2, the dielectric cap layer 117 laterally adjoins the metal cap layer 116. A lower surface 117L of the dielectric cap layer 117 physically contacts a top surface 111U of the IMD layer 111 and is flush with a top surface 115U of the conductive material 115 (or a top surface of the barrier layer 113) remote from the substrate 101. A top surface 117U of the dielectric cap layer 117, in the illustrated example, is flush with a top surface 116U of the metal cap layer 116. In another embodiment, the top surface 117U is lower than the top surface 116U of the metal cap layer 116, for example, vertically between the top surface 116U of the metal cap layer and the top surface 111U of the IMD layer 111.In another embodiment, the top surface 117U of the dielectric cap layer 117 is, for example, less than about 5 nm higher (extends farther from the substrate 101) than the top surface 116U of the metal cap layer. As shown in FIG. Fig. 2, the dielectric cap layer 117 covers the top surface 111U of the IMD layer 111 and extends continuously along the top surface 111U of the IMD layer 111 from one conductive line 112 to an adjacent conductive line 112.

[0023] In some embodiments, by forming the dielectric cap layer 117 between adjacent conductive lines 112, leakage current paths between adjacent conductive lines 112 at the interface between the IMD layer 111 and an overlying dielectric layer (see, for example, 127 in Fig. 4) is reduced or prevented, thereby improving device performance and reducing power consumption. Furthermore, the time-dependent dielectric breakdown (TDDB) behavior of the resulting device is also improved compared to a reference design without the dielectric cap layer 117.

[0024] Next, Fig. 3, an etch stop layer stack 118 is formed over the dielectric cap layer 117 and over the metal cap layer 116. In the example of Fig. 3, the etch stop layer stack 118 includes a plurality of etch stop layers (ESLs) 119, 121, 123, and 125. Therefore, forming the etch stop layer stack 118 includes forming the ESLs 119, 121, 123, and 125 sequentially over the dielectric cap layer 117 and over the metal cap layer 116.

[0025] In some embodiments, the ESL 119 is formed from a metal nitride that has good adhesion to the underlying metal cap layer 116 and the IMD layer 111. For example, the ESL 119 may be formed from aluminum nitride (AlN), aluminum oxynitride (AlNO), manganese nitride (Mn3N2), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or the like. In the discussion herein, the ESL 119 may alternatively be referred to as an aluminum nitride layer 119, although it should be understood that the ESL 119 may also be formed from other suitable materials instead of aluminum nitride, such as those listed above.

[0026] According to some embodiments, the ESL 119 is formed using a suitable formation method, such as PVD, CVD, ALD, or the like. The precursors for forming the ESL 119 may include a nitrogen-containing process gas, such as NH3, and an aluminum-containing process gas, such as trimethylaluminum (TMA) (Al2(CH3)6) or the like. In an exemplary deposition process (e.g., an ALD process), the nitrogen-containing process gas and the aluminum-containing process gas are alternately introduced into the process chamber and then purged out to grow aluminum nitride atomic layers in each cycle of the deposition process.

[0027] According to some embodiments, the thickness of the ESL 119 is in a range between about 0.5 nm and about 3 nm. The thickness of the ESL 119 should be within a suitable range. If the ESL 119 is too thick (e.g., thicker than about 3 nm), undercuts may occur when etching through the ESL 119 in subsequent processes. If the ESL 119 is too thin (e.g., thinner than about 0.5 nm), the ESL 119 may not effectively stop the etching of the overlying layers.

[0028] The temperature of the semiconductor device 100 during the deposition of the aluminum nitride layer 119 is controlled to be within a suitable range, such as between approximately 300°C and 380°C. It is understood that the temperature of the semiconductor device 100 affects the deposition rate. If the temperature is too low (e.g., lower than approximately 300°C), the deposition rate may be too low to be economical for semiconductor manufacturing due to the long time required to form the aluminum nitride layer 119. If the temperature is too high (e.g., higher than approximately 380°C), the resulting aluminum nitride layer 119 is crystalline (e.g., polycrystalline), which may lead to increased copper diffusion from the conductive line 112 to overlying layers.Therefore, the temperature of the semiconductor device 100 during the deposition of the aluminum nitride layer 119 is selected to be in a range between about 300°C and about 380°C in some embodiments to avoid the above-mentioned problems.

[0029] The aluminum nitride layer 119 in its as-deposited state may (optionally) contain some crystalline structures, such as polycrystalline structures, in which grains are located. Some grains may be interconnected, while some other grains may be buried in amorphous structures. The copper in the conductive line 112 may diffuse upward along the grain boundaries into overlying layers that are formed later. Therefore, to reduce the upward diffusion of copper, a treatment process (also referred to as an amorphization process) is performed after the deposition of the aluminum nitride layer 119 to convert the polycrystalline structures (if any) in the aluminum nitride layer 119 into amorphous structures, so that the entire aluminum nitride layer 119 is amorphous.Since the amorphous aluminum nitride layer 119 has no grain boundaries, it is better able to prevent the diffusion of copper.

[0030] According to some embodiments of the present disclosure, the treatment process (e.g., a plasma process) for the as-deposited aluminum nitride layer 119 is performed using a process gas comprising NH3, N2, or a combination thereof. Other gases, such as argon, may also be added. In the treatment process, the aluminum nitride layer 119 is bombarded. The bombardment destroys the crystalline structures. In addition, hydrogen and nitrogen may be introduced into the aluminum nitride layer 119 because hydrogen and nitrogen atoms are contained in the process gas (e.g., NH3). Accordingly, the aluminum nitride layer 119 may include hydrogen doped into it as a result of the treatment process.According to some embodiments, the aluminum nitride layer 119 has a hydrogen atom percentage in the range between about 1 at% and about 3 at% after the amorphization process.

[0031] The treatment process also has the effect of changing the aluminum-to-nitrogen atomic ratio (hereinafter referred to as the Al:N atomic ratio), which also influences whether the resulting aluminum nitride layer 119 has crystalline or amorphous structures. For example, an unprocessed crystalline aluminum nitride layer may have an Al:N atomic ratio close to 1:1. The addition of nitrogen atoms through the amorphization process changes this ratio. For example, when nitrogen is used for bombardment, nitrogen atoms bond to aluminum atoms, so that an aluminum atom can be cross-linked to more than one nitrogen atom (which in turn can bond to hydrogen atoms). This makes it easier to form amorphous structures.Furthermore, the bonding of a single aluminum atom to more than one nitrogen atom prevents recrystallization of the aluminum nitride layer 119, even if the temperature is high enough for recrystallization in subsequent processes. Since the added nitrogen atoms may also be bonded to hydrogen atoms, the treatment process also introduces hydrogen into the aluminum nitride layer 119.

[0032] According to some embodiments of the present disclosure, the NH3 gas (if used) during the treatment process has a flow rate in the range between about 50 sccm and about 500 sccm. The N2 gas (if used) has a flow rate in the range between about 1,000 sccm and about 3,000 sccm. The temperature of the semiconductor device 100 during the treatment process may be in the range between about 340°C and about 400°C.

[0033] According to some embodiments, the treatment process is or includes a plasma treatment, which may be a direct plasma process, wherein the plasma is generated in the same process chamber in which the semiconductor device 100 is treated. The plasma treatment process is performed using both high-frequency radio-frequency (HFRF) power (e.g., having a frequency of approximately 13.56 MHz) and low-frequency radio-frequency (LFRF) power (e.g., having a frequency of approximately 350 kHz). The HFRF power is used for ionization and to generate a plasma, and the LFRF power is used to bombard the aluminum nitride layer 119 for the purpose of amorphization. According to some embodiments of the present disclosure, the HFRF power is in the range between approximately 400 watts and approximately 800 watts.

[0034] The LFRF power is selected to be within a suitable range. If the LFRF power is too low (e.g., lower than about 90 watts), the nitrogen ions may not be effectively doped into the aluminum nitride layer 119. If the LFRF power is too high (e.g., higher than about 135 watts), severe plasma-induced damage to layers or structures beneath the aluminum nitride layer 119 may occur. According to some embodiments of the present disclosure, the LFRF power is selected to be in the range between about 90 watts and about 135 watts to avoid the above-mentioned problems.

[0035] In some embodiments, the aluminum nitride layer 119 after the treatment process has an aluminum atomic percentage in a range between about 55 at% and about 63 at%, a nitride atomic percentage in a range between about 37 at% and about 43 at%, and a carbon atomic percentage in a range between about 0.5 at% and about 2 at%. In some embodiments, if the atomic percentages of the various materials (e.g., aluminum, nitride, carbon) of the aluminum nitride layer 119 are within the ranges described above, the physical properties of the aluminum nitride layer 119 may correspond to the etch-selective capability of the etch stop layer stack 118, where the “etch-selective capability” of the etch stop layer stack 118 means that during the subsequent etch processes for forming trench openings 131T and via openings 131V (see, for example, Fig. 5) the etching processes can maintain anisotropy along the desired etching direction (e.g., vertical) in the etch stop layer stack 118.

[0036] We stay with Fig. 3, where the ESL 121 is formed on the ESL 119. The ESL 121 is formed in an exemplary embodiment from aluminum oxide (AlO x, where x is the atomic ratio of oxygen to aluminum). The ESL 121 may also be formed from other materials that have high etch selectivity relative to the underlying ESL 119 and the overlying ESL 123. Formation methods for the ESL 121 include ALD, CVD, PECVD, or the like. According to some embodiments of the present disclosure, the ESL 121 is formed using precursors comprising a metal-containing precursor such as TMA and an oxygen-containing precursor such as H2O, O3, or the like. The thickness of the ESL 121 may range between about 1 nm and about 5 nm. In some embodiments, the thickness of the aluminum nitride layer 119 and the ESL 121 is determined, for example, by the etch-selective capability of the etch stop layer stack 118 and / or the reliability window of the formed device.

[0037] In some embodiments, the ESL 121, after its formation, has an aluminum atomic percentage in a range between about 40 at% and about 45 at%, an oxygen atomic percentage in a range between about 55 at% and about 60 at%, and a carbon atomic percentage in a range between about 0.5 at% and about 1 at%. In some embodiments, when the atomic percentages of the various materials (e.g., aluminum, oxygen, carbon) of the ESL 121 are within the ranges described above, the physical properties of the ESL 121 may correspond to the etch-selective capability of the etch stop layer stack 118.

[0038] The ESL 121 improves the etch selectivity of the etch stop layer stack 118 and, in some embodiments, helps further reduce the leakage current between the conductive lines 112. Furthermore, the process of forming the aluminum nitride layer 119 and the ESL 121 may improve the adhesion between the metal cap layer 116 and the conductive material 115 (e.g., copper), thereby reducing or avoiding problems caused by the diffusion of copper metal, such as copper pits formed on copper metal lines or open copper metal lines.

[0039] Next, the ESL 123 is formed on the ESL 121. In an exemplary embodiment, the ESL 123 is formed from oxygen-doped silicon carbide (ODC), also known as silicon oxycarbide (SiOC). The ESL 123 may also be formed from another material, such as nitrogen-doped silicon carbide (NDC), SiC, or the like. The deposition process for the ESL 123 may be CVD or another suitable process, such as ALD, PECVD, high-density plasma CVD (HDPCVD), or the like. The thickness of the ESL 123 may range between about 2 nm and about 10 nm.

[0040] In some embodiments, the precursors for forming the ESL 123 depend on the desired composition of the ESL 123 and may include silicon (Si), carbon (C), hydrogen (H), nitrogen (N), oxygen (O), boron (B), and / or the like. According to some embodiments, the precursors include a gas selected from 1-methylsilane (Si(CH)H3, also known as 1MS), 2-methylsilane (Si(CH)2H2, also known as 2MS), 3-methylsilane (Si(CH)3H, also known as 3MS), 4-methylsilane (Si(CH)4, also known as 4MS), or combinations thereof. An inert gas such as He, N2, Ar, Xe, or the like may be used as the ambient gas. If ODC is to be formed, carbon dioxide (CO2) may also be added to provide oxygen. If NDC is to be formed, NH3 may be added to provide nitrogen.Furthermore, the precursors may contain boron-containing gases such as B2H6, BH3 or combinations thereof to provide boron in the resulting ESL 123.

[0041] In addition to the precursors described above, one or more carbon source gases may be added to increase the carbon content in the resulting ESL 123. The carbon source gas may be a carbon-rich source, meaning that the atomic percentage of carbon in the carbon source gas is high, for example, greater than about 10 at% or greater than about 20 at% or 30 at%. In an exemplary embodiment, the carbon source gas is a carbon-hydrogen-containing gas selected from C2H4, C2H6, and combinations thereof. With the additional carbon provided by the carbon source gas, the carbon percentage in the resulting ESL 123 is increased, and the properties of the ESL 123 are improved. According to some embodiments, the ratio of the flow rate of the carbon source gas to the flow rate of all 1Ms / 2Ms / 3Ms / 4Ms gases is greater than about 2 to 4.

[0042] According to some embodiments, the formation of the ESL 123 is performed in a chamber, for example, using PECVD, where the temperature of the semiconductor device 100 may be between about 300°C and about 500°C, and the chamber pressure may be between about 266 Pa and about 1333 Pa. The energy source for forming the ESL 123 may include HFRF power and LFRF power. When forming the ESL 123, the HFRF power source may provide power between about 100 watts and about 1,000 watts, while the LFRF power source could provide power of less than about 135 watts, and the power could even be zero watts (meaning no low-frequency power is provided). The high-frequency radio frequency power and the LFRF power may be provided simultaneously.

[0043] In some embodiments, the ESL 123, after its formation, has an oxygen atom percentage in a range between about 40 at% and about 50 at%, a silicon atom percentage in a range between about 36 at% and about 40 at%, and a carbon atom percentage in a range between about 15 at% and about 20 at%. In some embodiments, when the atom percentages of the various materials (e.g., oxygen, silicon, carbon) of the ESL 123 are within the ranges described above, the physical properties of the ESL 123 may correspond to the etch-selective capability of the etch stop layer stack 118.

[0044] Next, ESL 125 is formed over ESL 123. In an exemplary embodiment, ESL 125 is formed from the same material as ESL 121, such as aluminum oxide. The formation method, dimensions (e.g., thickness), and material composition (e.g., atomic percentage of various elements) of ESL 125 may be the same or similar to those of ESL 121 and are therefore not repeated. In an exemplary embodiment, ESL 119 is formed from aluminum nitride, ESL 121 is formed from aluminum oxide, ESL 123 is formed from ODC, and ESL 125 is formed from aluminum oxide.

[0045] Each of the ESLs 121, 123, and 125 can have a polycrystalline or amorphous structure, which can be achieved by adjusting the deposition temperature. Since the diffusion of copper atoms is blocked by the underlying ESL 119, whether the ESLs 121, 123, and 125 are polycrystalline or amorphous has no effect on the upward diffusion of copper atoms.

[0046] In the example of Fig. 3, the etch stop layer stack 118 comprises four ESLs (119, 121, 123, and 125). According to alternative embodiments of the present disclosure, the etch stop layer stack 118 comprises three ESLs (see Fig. 11 and Fig. 12), such as ESLs 119, 123 and 125. Details of the alternative embodiments are described below with reference to the Fig. 11 and Fig. 12 discussed.

[0047] Next, as in Fig. 4, an IMD layer 127 is formed over the etch stop layer stack 118. The IMD layer 127 may be formed by a same or similar formation method using one or more of the same or similar materials as the IMD layer 111; therefore, no details are repeated.

[0048] Next, a mask layer 129 is formed over the IMD layer 127. During subsequent processing, a pattern is transferred to the mask layer 129, for example, using photolithography and etching techniques. The mask layer 129 can then be used as a patterning mask for etching the underlying IMD layer 127. The mask layer 129 can be formed from a masking material such as silicon nitride, titanium nitride, titanium oxide, or the like, or a combination thereof, using a process such as CVD, PVD, ALD, or the like, or a combination thereof.

[0049] Next, Fig. 5, the mask layer 129 is patterned, and the patterns of the mask layer 129 are transferred to the IMD layer 127, for example, by one or more etching processes to form openings 131. In the example of Fig. 5, each of the openings 131 includes a via opening 131V and a trench opening 131T overlying the via opening 131V. In one embodiment, to form the via openings 131V and the trench openings 131T, a first etching process (e.g., an anisotropic etching process) is performed using the patterned mask layer 129 as the etch mask to form the trench openings 131T by etching into the IMD layer 127 from the top surface of the IMD layer 127. The first etching process is stopped once the depth of the openings 131 reaches the target depth of the trench openings 131T. Next, a second mask layer (not illustrated), such as a photoresist layer, is formed to fill the openings 131 and is formed over the top surface of the mask layer 129.The second mask layer is then patterned, wherein the structures (openings) of the second mask layer correspond to the positions of the via openings 131V. Next, a second etch process (e.g., an anisotropic etch process) is performed, using the patterned second mask layer as an etch mask, to form the via openings 131V. Note that the second etch process may stop at the ESL 125 (e.g., when the ESL 125 is exposed). Further etching steps, as described in more detail below, are performed to extend the via openings 131V through the etch stop layer stack 118 and expose the metal cap layer 116. In addition to the method described above, other methods for forming the via openings 131V and the trench openings 131T are also possible and are intended to be fully within the scope of the present disclosure.

[0050] According to some embodiments of the present disclosure, the etching of the IMD layer 127 is performed using a process gas comprising fluorine and carbon, wherein fluorine is used for etching and carbon is used to generate a plasma that can protect the sidewalls of the resulting via opening 131V and the trench openings 131T. With an appropriate ratio of fluorine and carbon, the via opening 131V and the trench openings 131T can have desirable profiles (e.g., sidewall profiles). For example, the process gases for the etching include one or more fluorine- and carbon-containing gases, such as C4F8 and / or CF4, and a carrier gas, such as N2.

[0051] In the illustrated embodiment, the etching of the IMD layer 127 stops at the ESL 125. Next, the ESL 125 (for example, AlO x) is etched, for example, by a dry etching process followed by a wet etching process. In some embodiments, the dry etching process is performed using etching gases, such as a mixture of BCl3 and Cl2. The wet etching may be performed, for example, using phosphoric acid. Next, the ESL 123 (for example, ODC) is etched, for example, using an etching gas containing a fluorine- and carbon-containing gas, such as CF4, and one or more other gases, such as argon. Next, the ESL 121 (for example, AlO x ) etched. In the illustrated embodiment, the ESL 121 and the ESL 125 are made of the same material (for example, AlO x) is formed, and therefore, the same etching processes used to etch ESL 125 can be performed again to etch ESL 121. Next, ESL 119 (e.g., AlN) is etched through, for example, using a mixture of BCl3, Cl2, and argon. ESL 119 can also be etched using a wet etching process, for example, using phosphoric acid. After ESL 119 is etched, metal cap layer 116 is exposed.

[0052] Forming the amorphous ESL 119 (e.g., AlN) has the advantage of improving the above-mentioned etching of the IMD layer 127 and the etch stop layer stack 118. The amorphous structure of the ESL 119, which has no grains and grain boundaries, can effectively prevent the copper atoms in the conductive lines 112 from diffusing upward into the etch stop layer stack 118 and the IMD layer 127. Otherwise, if the ESL 119 has polycrystalline structures, copper can diffuse along the grain boundaries into the etch stop layer stack 118 and the overlying IMD layer 127. The diffused copper can reduce the etch rates when etching the ESLs 119 / 121 / 123 / 125 and the IMD layer 127. The reduced etch rates may cause the etching for forming the via openings 131V within the etch stop layer stack 118 or even within the IMD layer 127 to stop prematurely.This effect is referred to as undercutting of the etch stop layer stack 118 and the IMD layer 127. As a result of the undercutting, the subsequently formed vias in the via openings 131V are unable to form an electrical connection to the conductive lines 112, leading to circuit failure. The amorphization process disclosed herein ensures that the ESL 119 has an amorphous structure to prevent copper diffusion, thus avoiding the problem of undercutting. As a result, the reliability and production yield of the device are improved.

[0053] Next, Fig. 6 conductive features 132 are formed in the openings 131. Each of the conductive features 132, in the illustrated example, includes a via 138 and a conductive line 136. Each of the vias 138 electrically couples an overlying conductive line 136 to an underlying conductive line 112.

[0054] In some embodiments, to form the conductive features 132, a barrier layer 133 (e.g., conformal) is formed to line sidewalls and bottoms of the openings 131. The barrier layer 133 may also be formed over the top surface of the mask layer 129 (see Fig. 5). Next, a conductive material 135 is formed over the barrier layer 133 to fill the openings 131. The barrier layer 133 and the conductive material 135 may be the same or similar to the barrier layer 113 and the conductive material 115, respectively, and may be formed using one or more of the same or similar formation methods; therefore, no details are repeated.

[0055] After the barrier layer 133 and the conductive material 135 are formed, a planarization process, such as CMP, is performed to remove recessed portions of the barrier layer 133 and the conductive material 135 from the top surface of the IMD layer 127. In the illustrated embodiment, the planarization process also removes the mask layer 129. After the planarization process, remaining portions of the barrier layer 133 and the conductive material 135 in the via openings 131V form the vias 138, and remaining portions of the barrier layer 133 and the conductive material 135 in the trench openings 131T form the conductive lines 136.

[0056] Next, Fig. 7, a metal cap layer 146 is formed (e.g., selectively formed) over the top surfaces of the conductive features 132. Next, a dielectric cap layer 137 is formed over the top surface of the IMD layer 127, and thereafter, an etch stop layer stack 148 comprising ESLs 139, 141, 143, and 145 is formed on the metal cap layer 146 and the dielectric cap layer 137. The metal cap layer 146 and the dielectric cap layer 137 may be formed from the same or similar materials as the metal cap layer 116 and the dielectric cap layer 117, respectively, and may be formed using the same or a similar formation process; therefore, no details are repeated. In addition, ESLs 139, 141, 143 and 145 may be constructed from the same or similar materials using the same or similar formation process as ESLs 119, 121, 123 and 145 respectively.125, which is why no details are repeated.

[0057] To complete the fabrication of the semiconductor device 100, additional processing may be performed. For example, additional IMD layers and additional conductive features (e.g., vias, conductive lines) may be formed over the etch stop layer stack 148 to form interconnect structures that electrically connect the integrated circuit devices 103 to form functional circuits. Furthermore, solder metallization (UBM) structures may be formed over the interconnect structures, and external connectors (e.g., copper pillars and / or solder bumps) may be formed over the UBM structures to electrically connect to the functional circuits of the semiconductor device 100. No details are discussed here.

[0058] Fig. 8 to 10 illustrate cross-sectional views of a semiconductor device 100A at various manufacturing stages according to another embodiment. The semiconductor device 100A is similar to the semiconductor device 100, but the dielectric cap layer 117 is formed by a different amorphization process. In particular, in Fig. 8, an ion implantation process 120 is performed to convert upper portions (e.g., portions distal from the substrate 101) of the IMD layer 111 into the dielectric cap layer 117.

[0059] According to some embodiments of the present disclosure, the ion implantation process is performed using a nitrogen-containing process gas, such as NH3 or N2O. In some embodiments, the process gas is ignited into a plasma, and ions of the process gas (e.g., nitrogen ions) are implanted into the upper portions of the IMD layer 111 to convert the upper portions of the IMD layer 111 into the nitrogen-containing dielectric capping layer 117. In some embodiments, the dielectric capping layer 117 is a nitride-containing dielectric material, such as SiN x , SiON x or SiCN x , where x can be 1 or 2. A thickness of the dielectric capping layer 117 can be between about 0.5 nm and about 5 nm or between about 1 nm and about 5 nm. A density of the dielectric capping layer 117 can be between about 1.5 g / cm 3 and about 3.2 g / cm 3The dielectric cap layer 117 may have a nitrogen atom percentage in a range between about 2 at% and about 10 at%.

[0060] In the example of Fig. 8, the lower surface 117L of the dielectric cap layer 117 is closer to the substrate 101 than the upper surface 115U of the conductive material 115 of the conductive line 112. The upper surface 117U of the dielectric cap layer 117 is flush with the upper surface 115U of the conductive material 115. The upper surface 111U of the IMD layer 111 is below the upper surface 115U of the conductive material 115.

[0061] Next, Fig. 9, the etch stop layer stack 118, which includes the ESLs 119, 121, 123, and 125, is formed over the metal cap layer 116 and the dielectric cap layer 117. The formation of the etch stop layer stack 118 is the same as or similar to the formation of the etch stop layer stack 118 in Fig. 2, therefore no details are repeated. It should be noted that the upper surface of the ESL 119 above the metal cover layer 116 may be flat, as indicated by the solid line 119U in Fig. 9, or may be non-flat (e.g., curved)—for example, due to the vertical offset between the top surface of the metal cap layer 116 and the top surface of the dielectric cap layer 117. For example, portions of the top surface of the ESL 119 may be curved above (e.g., directly above) the metal cap layer 116, as illustrated by dashed line 119U'. In the subsequent figures, the top surface of the ESL 119 is illustrated as a flat surface, it being understood that at least portions of the top surface of the ESL 119 may be non-flat (e.g., curved).

[0062] Next, processing steps that are the same or similar to those described above in the Fig. 4-7, to form the semiconductor device 100A in Fig. 10. To simplify the description, no details are repeated.

[0063] Fig. 11 illustrates a cross-sectional view of a semiconductor device 100B according to another embodiment. The semiconductor device 100B is similar to the semiconductor device 100 of Fig. 7, but the etch stop layer stacks 118 and 148 in Fig. 11 comprise three etch stop layers instead of four etch stop layers as in Fig. 7. In particular, the etch stop layer stack 118 comprises the ESL 119 (for example, AlN), the ESL 123 (for example, ODC), and the ESL 125 (for example, AlO x ). Similarly, the etch stop layer stack 148 comprises the ESL 139 (e.g., AlN), the ESL 143 (e.g., ODC), and the ESL 145 (e.g., AlO x ) on.

[0064] Fig. 12 illustrates a cross-sectional view of a semiconductor device 100C according to another embodiment. The semiconductor device 100C is similar to the semiconductor device 100A of Fig. 10, but the etch stop layer stacks 118 and 148 in Fig. 12 comprise three etch stop layers instead of four etch stop layers as in Fig. 10. In particular, the etch stop layer stack 118 comprises the ESL 119 (for example, AlN), the ESL 123 (for example, ODC), and the ESL 125 (for example, AlO x ). Similarly, the etch stop layer stack 148 comprises the ESL 139 (e.g., AlN), the ESL 143 (e.g., ODC), and the ESL 145 (e.g., AlO x ). The dielectric cover layers 117 and 137 of Fig. 12 are formed by ion implantation.

[0065] Fig. 13 illustrates a cross-sectional view of a semiconductor device 100D according to another embodiment. The semiconductor device 100D is similar to the semiconductor device 100 of Fig. 7, but at least one of the vias 138 (e.g., the via 138 on the left) is formed so as to be misaligned with the underlying conductive line 112 (e.g., due to mask alignment inaccuracies in the manufacturing process), such that a portion of the bottom surface of the via 138 extends beyond lateral extents (e.g., beyond sidewalls) of the conductive line 112 and contacts (e.g., physically contacts) the dielectric cap layer 117. Due to the electrical isolation provided by the dielectric cap layer 117, in some embodiments, leakage current between the misaligned via 138 and the conductive lines 112 is reduced or prevented.

[0066] Embodiments of the present disclosure realize several advantageous features. For example, the dielectric cap layer 117 reduces leakage current paths between adjacent conductive lines 112, thereby improving device performance and reducing power consumption. Furthermore, the time-dependent dielectric brakedown (TDDB) behavior of the device is also improved. The film regime of the etch stop layer stack (e.g., 118, 148) provides further advantages. For example, thanks to the formation of the amorphous etch stop layer 119, there are no grain boundaries in the etch stop layer 119 through which copper atoms could migrate, thus preventing the copper atoms from diffusing into the overlying etch stop layers and dielectric layers (e.g., 127).Since copper atoms can cause under-etching of the dielectric layers and etch stop layers, blocking copper diffusion eliminates under-etching, thereby improving device reliability and production yield.

[0067] Fig. 14 illustrates a flowchart of a method for fabricating a semiconductor structure according to some embodiments. It should be understood that the Fig. 14 is only one example of many possible embodiments. Many variations, alternatives, and modifications will occur to those skilled in the art. For example, various steps as in Fig. 14 may be illustrated, added, omitted, replaced, rearranged or repeated.

[0068] As in Fig.14, in block 1010, a first conductive feature is formed in a first dielectric layer disposed over a substrate. In block 1020, a metal cap layer is formed over a top surface of the first conductive feature distal from the substrate. In block 1030, a dielectric cap layer is selectively formed over a top surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed through the dielectric cap layer. In block 1040, an etch stop layer stack is formed over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

[0069] According to one embodiment of the present disclosure, a method of forming a semiconductor device comprises: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal capping layer over a top surface of the first conductive feature distal from the substrate; selectively forming a dielectric capping layer over a top surface of the first dielectric layer and laterally adjacent to the metal capping layer, wherein the metal capping layer is exposed through the dielectric capping layer; and forming an etch stop layer stack over the metal capping layer and the dielectric capping layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.In one embodiment, the method further comprises: forming a second dielectric layer over the etch stop layer stack; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the metal cap layer. In one embodiment, forming the metal cap layer comprises selectively forming an electrically conductive material over the top surface of the first conductive feature. In one embodiment, the dielectric cap layer is formed from a nitride-containing dielectric material. In one embodiment, the nitride-containing dielectric material is silicon nitride, silicon oxynitride, or silicon carbonitride. In one embodiment, a thickness of the dielectric cap layer is between about 1 nm and about 5 nm.In one embodiment, selectively forming the dielectric capping layer comprises selectively depositing the nitride-containing dielectric material over the top surface of the first dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) process. In one embodiment, the PECVD process is performed using a precursor comprising N2, NH3, NO, or N2O. In one embodiment, selectively forming the dielectric capping layer comprises converting an upper layer of the first dielectric layer into the dielectric capping layer by performing an ion implantation process. In one embodiment, the ion implantation process is performed using a gas source comprising NH3 or N2O.In one embodiment, forming the etch stop layer stack comprises: forming a layer of aluminum nitride over the metal cap layer and the dielectric cap layer; forming a layer of oxygen-doped silicon carbide over the layer of aluminum nitride; and forming a layer of aluminum oxide over the layer of oxygen-doped silicon carbide. In one embodiment, forming the etch stop layer stack further comprises forming another layer of aluminum oxide between the layer of aluminum nitride and the layer of oxygen-doped silicon carbide.

[0070] According to one embodiment of the present disclosure, a method of forming a semiconductor device comprises: forming first conductive features in a first dielectric layer disposed over a substrate, wherein first surfaces of the first conductive features distal from the substrate are flush with a first surface of the first dielectric layer; selectively forming a metal capping layer on the first surfaces of the first conductive features; selectively forming a dielectric capping layer on the first surface of the first dielectric layer, wherein the dielectric capping layer is laterally adjacent to the metal capping layer,wherein the dielectric capping layer is formed from a nitride-containing dielectric material; forming a plurality of etch stop layers sequentially on the metal capping layer and on the dielectric capping layer; forming a second dielectric layer on the plurality of etch stop layers; and forming second conductive features in the second dielectric layer, wherein the second conductive features extend through the plurality of etch stop layers and are electrically coupled to respective ones of the first conductive features. In one embodiment, selectively forming the dielectric capping layer comprises depositing the nitride-containing dielectric material on the first surface of the first dielectric layer while maintaining a top surface of the metal capping layer distal from the substrate free of the nitride-containing dielectric material.wherein the nitride-containing dielectric material extends continuously between adjacent ones of the first conductive features. In one embodiment, selectively forming the dielectric capping layer comprises converting an upper portion of the first dielectric layer proximate the first surface of the first dielectric layer into the dielectric capping layer through an ion implantation process. In one embodiment, forming the plurality of etch stop layers comprises: forming a first etch stop layer comprising aluminum nitride over the metal capping layer and the dielectric capping layer; forming a second etch stop layer comprising oxygen-doped silicon carbide over the first etch stop layer; and forming a third etch layer comprising aluminum oxide,above the second etch stop layer. In one embodiment, forming the second conductive features comprises: forming conductive lines in the second dielectric layer; and forming vias underlying the conductive lines, wherein upper portions of the vias are located in the second dielectric layer and lower portions of the vias extend through the plurality of etch stop layers and are electrically coupled to the first conductive features.

[0071] According to one embodiment of the present disclosure, a semiconductor device comprises: a substrate; a first dielectric layer over the substrate; a first conductive feature in the first dielectric layer; a metal capping layer on the first conductive feature; a dielectric capping layer on a top surface of the first dielectric layer distal from the substrate, the dielectric capping layer laterally adjacent to the metal capping layer, the dielectric capping layer comprising a nitride-containing dielectric material, a top surface of the metal capping layer distal from the substrate being free of the dielectric capping layer; an etch stop layer stack on the metal capping layer and the dielectric capping layer, the etch stop layer stack comprising a plurality of etch stop layers; a second dielectric layer on the etch stop layer stack;and a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the first conductive feature. In one embodiment, the etch stop layer stack comprises: a first etch stop layer comprising aluminum nitride over the metal cap layer and the dielectric cap layer; a second etch stop layer comprising oxygen-doped silicon carbide over the first etch stop layer; and a third etch layer comprising aluminum oxide over the second etch stop layer. In one embodiment, the second conductive feature comprises: a metal line in the second dielectric layer, wherein a bottom surface of the metal line facing the substrate is spaced from the etch stop layer stack;and a via underlying and connected to the metal line, the via extending through the etch stop layer stack and contacting the metal cap layer;

Claims

[1] A method of forming a semiconductor device, the method comprising: Forming a first conductive feature (112) in a first dielectric layer (111) disposed over a substrate (101); Forming a metal cap layer (116) over a top surface of the first conductive feature (112) distal from the substrate (101); selectively forming a dielectric capping layer (117) over a top surface of the first dielectric layer (111) and laterally adjacent to the metal capping layer (116), wherein the metal capping layer (116) is exposed through the dielectric capping layer (117); and Forming an etch stop layer stack (118) over the metal cap layer (116) and the dielectric cap layer (117), the etch stop layer stack (118) comprising a plurality of etch stop layers, wherein the dielectric cover layer (117) is formed from a nitride-containing dielectric material, wherein forming the etch stop layer stack (118) comprises: Forming a layer (119) of aluminum nitride over the metal cap layer (116) and the dielectric cap layer (117); forming a layer of oxygen-doped silicon carbide (123) over the layer of aluminum nitride (119); and Forming a layer of aluminum oxide (125) over the layer of oxygen-doped silicon carbide (123), wherein forming the etch stop layer stack (118) further comprises: Forming a further layer of aluminum oxide (121) between the layer of aluminum nitride (119) and the layer of oxygen-doped silicon carbide (123). [2] The method of claim 1, further comprising: Forming a second dielectric layer (127) over the etch stop layer stack (118); and Forming a second conductive feature (132) in the second dielectric layer (127), wherein the second conductive feature (132) extends through the etch stop layer stack (118) and is electrically coupled to the metal cap layer (116). [3] The method of claim 1, wherein forming the metal cover layer (116) comprises: selectively forming an electrically conductive material over the top surface of the first conductive feature (112). [4] A method according to any one of the preceding claims, wherein the nitride-containing dielectric material is silicon nitride, silicon oxynitride or silicon carbonitride. [5] The method of any preceding claim, wherein a thickness of the dielectric cap layer (117) is about 1 nm to about 5.0 nm. [6] A method according to any one of the preceding claims, wherein the selective formation of the dielectric cap layer (117) comprises: selectively depositing the nitride-containing dielectric material over the upper surface of the first dielectric layer (111) using a plasma-enhanced chemical vapor deposition (PECVD) process. [7] The method of claim 6, wherein the PECVD process is carried out using a precursor containing N2, NH3, NO or N2O. [8] The method of any one of the preceding claims 1 to 5, wherein the selective formation of the dielectric cap layer (117) comprises: Converting an upper layer of the first dielectric layer (111) into the dielectric cap layer (117) by performing an ion implantation process. [9] The method of claim 8, wherein the ion implantation process is carried out using a gas source containing NH3 or N2O. [10] A method of forming a semiconductor device, comprising: Forming first conductive features (112) in a first dielectric layer (111) disposed over a substrate (101), wherein first surfaces of the first conductive features (112) distal from the substrate (101) are flush with a first surface of the first dielectric layer (111); selectively forming a metal cap layer (116) on the first surfaces of the first conductive features (112); selectively forming a dielectric capping layer (117) on the first surface of the first dielectric layer (111), the dielectric capping layer (117) being laterally adjacent to the metal capping layer (116), the dielectric capping layer (117) being formed from a nitride-containing dielectric material; Forming a plurality of etch stop layers (118) successively on the metal cover layer (116) and on the dielectric cover layer (117); Forming a second dielectric layer (127) on the plurality of etch stop layers (118); and Forming second conductive features (132) in the second dielectric layer (127), wherein the second conductive features (132) extend through the plurality of etch stop layers (118) and are electrically coupled to the respective first conductive features (112), wherein forming the plurality of etch stop layers (118) comprises: Forming a first etch stop layer (119) comprising aluminum nitride over the metal cap layer (116) and the dielectric cap layer (117); Forming a second etch stop layer (123) comprising oxygen-doped silicon carbide over the first etch stop layer (119); and Forming a third etching layer (125) comprising aluminum oxide over the second etch stop layer (123), wherein forming the plurality of etch stop layers (118) further comprises: Forming a further layer (121) of aluminum oxide between the first (119) and second etch stop layer (123). [11] The method of claim 10, wherein selectively forming the dielectric cap layer (117) comprises: Depositing the nitride-containing dielectric material on the first surface of the first dielectric layer (111) while leaving a top surface of the metal cap layer (116) distal from the substrate (101) free of the nitride-containing dielectric material, wherein the nitride-containing dielectric material extends continuously between adjacent first conductive features of the first conductive features (112). [12] The method of claim 10 or 11, wherein selectively forming the dielectric cap layer (117) comprises: Converting an upper portion of the first dielectric layer (111) close to the first surface of the first dielectric layer (111) into the dielectric cap layer (117) by an ion implantation process. [13] The method of any one of the preceding claims 10 to 12, wherein forming the second conductive features (132) comprises: forming conductive lines in the second dielectric layer (127); and Forming vias underlying the conductive lines, wherein upper portions of the vias lie in the second dielectric layer (127) and lower portions of the vias extend through the plurality of etch stop layers (118) and are electrically coupled to the first conductive features (112). [14] Semiconductor device comprising: a substrate (101); a first dielectric layer (111) over the substrate (101); a first conductive feature (112) in the first dielectric layer (111); a metal cap layer (116) on the first conductive feature (112); a dielectric capping layer (117) on an upper surface of the first dielectric layer (111) distal from the substrate (101), the dielectric capping layer (117) being laterally adjacent to the metal capping layer (116), the dielectric capping layer (117) comprising a nitride-containing dielectric material, an upper surface of the metal capping layer (116) distal from the substrate (101) being free of the dielectric capping layer (117); an etch stop layer stack (118) on the metal cap layer (116) and the dielectric cap layer (117), the etch stop layer stack (118) comprising a plurality of etch stop layers; a second dielectric layer (127) on the etch stop layer stack (118); and a second conductive feature (132) in the second dielectric layer (127), the second conductive feature (132) extending through the etch stop layer stack (118) and being electrically coupled to the first conductive feature (112), wherein the etch stop layer stack (118) comprises: a first etch stop layer (119) comprising aluminum nitride over the metal cap layer (116) and the dielectric cap layer (117); a second etch stop layer (123) comprising oxygen-doped silicon carbide over the first etch stop layer (119); and a third etching layer (125) comprising aluminum oxide over the second etch stop layer (123), wherein the etch stop layer stack (118) further comprises: a further layer (121) of aluminum oxide between the first (119) and second etch stop layer (123). [15] The semiconductor device of claim 14, wherein the second conductive feature (132) comprises: a metal line in the second dielectric layer (127), wherein a lower surface of the metal line facing the substrate (101) is spaced from the etch stop layer stack (118); and a via underlying and connected to the metal line, the via extending through the etch stop layer stack (118) and contacting the metal cap layer (116).

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