Contacts for semiconductor devices and methods to form them

Abstract

Semiconductor device comprising: a first interlayer dielectric layer, ILD layer (96), over a transistor structure (109); a first contact (108) extending through the first ILD layer (96), wherein the first contact (108) is electrically coupled to a first source / drain region (92) of the transistor structure (109), an upper surface of the first contact (108) is convex and the upper surface of the first contact (108) is arranged below an upper surface of the first ILD layer (96); a second ILD layer (114) above the first ILD layer (96) and the first contact (108); and a second contact (116) extending through the second ILD layer (114), wherein the second contact (116) is electrically coupled to the first contact (108), wherein a contact etch stop layer, CESL (112), is arranged over the first ILD layer (96) and the first contact (108), wherein the CESL (112) over the first contact (108) comprises sections having convex upper surfaces.

Description

BACKGROUND

[0001] Semiconductor devices are used in several electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum element size, allowing more components to be integrated into a given area. However, with decreasing minimum element sizes, further problems arise that need to be addressed.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2015 / 0 123 286 A1, US 2007 / 0 007 653 A1, US 2014 / 0 151 893 A1, US 2008 / 0 079 090 A1, US 10 224 242 B1 and DE 10 2019 215 117 A1.

[0004] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. Fig. 1 illustrates an example of a nanostructure field effect transistor (nano-FET) in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 12E, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 19E, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 20E, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C and Fig. 23D are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various elements of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or devices discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be designed accordingly.

[0008] Various embodiments provide improved conductive contacts, methods of forming the improved conductive contacts, and semiconductor devices with the improved conductive contacts. The method includes forming a conductive contact. A planarization process, such as chemical mechanical polishing (CMP), an etch-back process, or combinations thereof, may be performed on the conductive contact. An annealing process is performed on the conductive contact. The annealing process may be performed in the presence of hydrogen gas (H2) and at a temperature greater than about 100°C. The annealing process helps reduce oxidation of the conductive contact, reduces the contact resistance (Rc) between the conductive contact and a conductive element formed over and coupled to the conductive contact, provides device reinforcement, and offers improved device performance.The annealing process may restructure the conductive contact, such as recrystallizing the conductive contact, which may cause the conductive contact material to shrink and reshape a top surface of the conductive contact. For example, before the annealing process, the conductive contact may have a planar top surface. After the annealing process, the top surface of the conductive contact may be restructured to have a convex shape. This shape change may increase a contact area between the conductive element and the conductive contact, further reducing contact resistance, providing device reinforcement, and enabling improved device performance.

[0009] Embodiments are described below in a particular context in which a die comprises nanostructure FETs. However, various embodiments may also be applied to dies comprising other transistor types (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with the nanostructure FETs.

[0010] Fig. 1 illustrates an example of nanostructure FETs (e.g., nanowire FETs, nanosheet FETs (nanoFETs), or the like) in a three-dimensional view. The nanoFETs include nanostructures 55 (e.g., nanosheets, nanowires, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate). The nanostructures 55 serve as channel regions for the nanostructure FETs. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 68 are disposed between adjacent fins 66. The fins 66 may protrude over and between adjacent isolation regions 68. Although the isolation regions 68 are described / illustrated as being separate from the substrate 50, the term “substrate” as used herein may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions.Furthermore, although a lower portion of the fins 66 is illustrated as a single, continuous material with the substrate 50, the lower portion of the fins 66 and / or the substrate 50 may be comprised of a single material or multiple materials. In this context, the fins 66 refer to the portion extending between the adjacent isolation regions 68.

[0011] The gate dielectric layers 100 are located above the top surfaces and sidewalls of the fins 66 and along the top surfaces, sidewalls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are located above the gate dielectric layers 100. Epitaxial source / drain regions 92 are arranged on the fins 66 on opposite sides of the gate dielectric layers 100 and the gate electrodes 102.

[0012] Fig. 1 further illustrates reference cross-sections used in later figures. Cross-section AA' runs along a longitudinal axis of a gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of a nanostructure FET. Cross-section BB' is perpendicular to cross-section AA' and runs parallel to a longitudinal axis of a fin 66 of the nanostructure FET and in a direction in which, for example, current flows between the epitaxial source / drain regions 92 of the nanostructure FET. Cross-section CC' runs parallel to cross-section AA' and extends through the epitaxial source / drain regions 92 of the nanostructure FET. The subsequent figures refer to these reference cross-sections for the sake of clarity.

[0013] Some embodiments discussed herein are discussed in the context of nanostructure FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices, such as planar FETs or fin-field-effect transistors (FinFETs).

[0014] The Fig. 2 to 23D are cross-sectional views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Fig. 2 to 5, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A and 23A illustrate the Fig. 1 illustrated reference cross section A-A'. The Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 11D, Fig. 12B, Fig. 12D, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 19E, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 20E, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E, Fig. 22B, Fig. 22C, Fig. 23B, Fig. 23C and Fig. 23D illustrate the Fig. 1 illustrated reference cross section B-B'. The Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C and Fig. 12E illustrate the Fig. 1 illustrated reference cross section C-C'.

[0015] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsemide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0016] The substrate 50 includes an n-type region 50N and a p-type region 50P. The n-type region 50N may be used to form n-type devices, such as NMOS transistors, e.g., n-type nanostructure FETs. The p-type region 50P may be used to form p-type devices, such as PMOS transistors, e.g., p-type nanostructure FETs. The n-type region 50N may be physically separated from the p-type region 50P (as illustrated by divider 20), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-region 50N and one p-region 50P are illustrated, any number of n-regions 50N and p-regions 50P may be provided.

[0017] Furthermore, Fig. 2, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration, and as discussed in more detail below, the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to form channel regions of nanostructured FETs in the p-type region 50P. The first semiconductor layers 51 are removed and the second semiconductor layers 53 are patterned to form channel regions of nanostructured FETs in the n-type region 50N.However, in some embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nanostructure FETs in the n-type region 50N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nanostructure FETs in the p-type region 50P.

[0018] In some embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nanostructured FETs in both the n-type region 50N and the p-type region 50P. In some embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nanostructured FETs in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously.

[0019] The multilayer stack 64 is illustratively illustrated as comprising three layers each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 may comprise any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first semiconductor layers 51 may be formed from a first semiconductor material suitable for p-type nanostructure FETs, such as silicon germanium or the like. The second semiconductor layers 53 may be formed from a second semiconductor material suitable for n-type nanostructure FETs, such as silicon, silicon carbon, or the like.For illustrative purposes, the multilayer stack 64 is illustrated with a bottom semiconductor layer suitable for p-type nanostructure FETs (e.g., the first semiconductor layers 51). In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanostructure FETs (e.g., the second semiconductor layers 53).

[0020] The first semiconductor materials and the second semiconductor materials may be materials that have a high etch selectivity to each other. Thus, the first semiconductor layers 51 formed from the first semiconductor materials can be removed without significantly removing the second semiconductor layers 53 formed from the second semiconductor materials in the n-type region 50N. This allows the second semiconductor layers 53 to be patterned to form channel regions of n-type nanostructure FETs. Similarly, the second semiconductor layers 53 formed from the second semiconductor materials can be removed without significantly removing the first semiconductor layers 51 formed from the first semiconductor materials in the p-type region 50P. This allows the first semiconductor layers 51 to be patterned to form channel regions of p-type nanostructure FETs.

[0021] In Fig. 3, fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 may be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 may further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from the first semiconductor layers 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from the second semiconductor layers 53. The first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55.

[0022] The fins 66 and the nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and the nanostructures 55 can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, which can create structures that have smaller pitches than is possible with a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers are used to pattern the fins 66.

[0023] In Fig. 3, the fins 66 in the n-type region 50N and in the p-type region 50P are illustrated with substantially equal widths for illustrative purposes. In some embodiments, the widths of the fins 66 in the n-type region 50N may be greater or smaller than the widths of the fins 66 in the p-type region 50P. While each of the fins 66 and the nanostructures 55 is illustrated with a consistently constant width, in some embodiments, the fins 66 and / or the nanostructures 55 may further have tapered sidewalls such that a width of each of the fins 66 and / or the nanostructures 55 continuously increases toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and may be trapezoidal in shape.

[0024] In Fig. 4, shallow trench isolation (STI) regions 68 are formed adjacent to the fins 66. The STI regions 68 may be formed by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, as well as between adjacent fins 66. The insulating material may be an oxide (such as silicon oxide), a nitride, the like, or a combination thereof. The insulating material may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by an acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process may be performed once the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55.Although the insulating material is illustrated as a single layer, embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately illustrated) may be formed along surfaces of the substrate 50, the fins 66, and the nanostructures 55. A fill material, such as that discussed above, may then be formed over the liner.

[0025] A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 so that the upper surfaces of the nanostructures 55 and the insulating material are complete upon completion of the planarization process.

[0026] The insulating material is then cut out to form the STI regions 68. The insulating material is cut out such that the nanostructures 55 and the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 68. Furthermore, the upper surfaces of the STI regions 68 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The upper surfaces of the STI regions 68 may be formed flat, convex, and / or concave by a suitable etching. The STI regions 68 may be cut out using an acceptable etching process, such as a process that selectively acts on the insulating material material (e.g., it etches the insulating material material faster than the material of the fins 66 and the nanostructures 55). Oxide removal with dilute hydrofluoric acid (dHF) can be used.

[0027] The above with reference to the Fig. The process described in Figures 2 through 4 is only one example of how the fins 66 and the nanostructures 55 may be formed. In some embodiments, the fins 66 and / or the nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be excised such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first and second semiconductor materials.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth. This may avoid prior and / or subsequent implantations, although in situ and implant doping may be used together.

[0028] Furthermore, the first semiconductor layers 51 (and the resulting nanostructures 52) and the second semiconductor layers 53 (and the resulting second nanostructures 54) are illustrated and discussed here only for illustrative purposes, as they comprise the same materials in the p-type region 50P and in the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may comprise different materials or be formed in a different order in the p-type region 50P and in the n-type region 50N.

[0029] Furthermore, Fig. 4 Suitable wells (not separately illustrated) may be formed in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins 66, the nanostructures, and the STI regions 68 in the n-region 50N and in the p-region 50P. The photoresist is patterned to expose the p-region 50P. The photoresist may be formed using a spin-on technique and may be patterned using acceptable photolithography techniques. When the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P and the photoresist can serve as a mask to essentially prevent n-type impurities from being implanted into the n-type region 50N.The n-impurities may be phosphorus, arsenic, antimony or the like, which in the region are present in a concentration in the range of about 10. 13 atoms / cm 3 up to about 10 14 atoms / cm 3 are implanted. After implantation, the photoresist is removed, such as by an acceptable ash process.

[0030] After or before implanting the p-region 50P, a photoresist or other masks (not separately illustrated) are formed over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and in the n-region 50N. The photoresist is patterned to expose the n-region 50N. The photoresist may be formed using a spin-on technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-region 50N, and the photoresist may serve as a mask to substantially prevent p-type impurities from being implanted into the p-region 50P. The n-type impurities may be boron, boron fluoride, indium, or the like, present in the region at a concentration in the range of about 10 13 atoms / cm 3 up to about 10 14 atoms / cm 3implanted. After implantation, the photoresist can be removed, such as by an acceptable ash process.

[0031] Following the implantation of the n-type region 50N and the p-type region 50P, an anneal may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the built-up materials or epitaxial fins may be doped in-situ during growth, which may eliminate the implantations, although both in-situ and implant doping may be used simultaneously.

[0032] In Fig. 5, a dummy dielectric layer 70 is formed on the fins 66 and / or the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally built using acceptable techniques.

[0033] A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by CMP. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques to deposit the selected material. The dummy gate layer 72 may be made of other materials that exhibit high etch selectivity toward etching isolation regions.

[0034] The mask layer 74 may be deposited over the dummy gate layer 72. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is only illustrative and only covers the fins 66 and the nanostructures 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions 68. Thus, the dummy dielectric layer 70 may extend between the dummy gate layer 72 and the STI regions 68.

[0035] Fig. 6A to 23D illustrate various further steps in the manufacture of devices of the embodiment. Fig. 7A, Fig. 7C, Fig. 8A, Fig. 8C, Fig. 9A, Fig. 9C, Fig. 10A, Fig. 10C, Fig. 11A, Fig. 11C, Fig. 12A, Fig. 12C, Fig. 12E, Fig. 13A, Fig. 14A and Fig. 15A illustrate elements in either the n-regions 50N or the p-regions 50P. In the Fig. 6A and Fig. 6B, the mask layer 74 (see Fig. 5) patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 can then be transferred to the dummy gate layer 72 and to the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the nanostructures 55. The pattern of the masks 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective fins 66. The masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can be collectively referred to as "dummy gate structures."

[0036] In the Fig. 7A to 7C, a first spacer layer 80 and a second spacer layer 82 are formed over the dummy gate structures, the nanostructures 55, and the STI regions 68. The first spacer layer 80 and the second spacer layer 82 are subsequently patterned to serve as spacers for forming self-aligned source / drain regions. Fig. 7A to 7C, the first spacer layer 80 is formed on the top surfaces of the STI regions 68, the top surfaces and sidewalls of the nanostructures 55 and the masks 78, as well as the sidewalls of the dummy gates 76, the dummy gate dielectrics 71, and the fins 66. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposition by CVD, ALD, or the like. The second spacer layer 82 may be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0037] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantations for lightly doped source / drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the above-mentioned Fig. 4, a mask, such as a photoresist, may be formed over the n-type region 50N while the p-type region 50P is exposed. Impurities of a suitable type (e.g., p) may be implanted into the exposed fins 66 and the nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while the n-type region 50N is exposed. Impurities of a suitable type (e.g., n) may be implanted into the exposed fins 66 and the nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurities may be any of the previously discussed n-type impurities, and the p-type impurities may be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have an impurity concentration in the range of about 1×10 15 atoms / cm 3 up to about 1×10 19 atoms / cm3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0038] In the Fig. 8A to 8C, the first spacer layer 80 and the second spacer layer 82 (see Fig. 7A to 7C) to form first spacers 81 and second spacers 83. As discussed in more detail below, the first spacers 81 and the second spacers 83 serve to self-align later-formed source / drain regions and to protect sidewalls of the fins 66 and / or the nanostructure 55 during further processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, so that the first spacer layer 80 may act as an etch stop layer when patterning the second spacer layer 82, and the second spacer layer 82 may act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etch process in which the first spacer layer 80 acts as an etch stop layer. Remaining portions of the second spacer layer 82 form second spacers 83, as shown in FIG. Fig. 8C. The second spacers 83 then serve as a mask while exposed portions of the first spacer layer 80 are etched, forming first spacers 81, as shown in the Fig. 8B and Fig. 8C illustrated.

[0039] As in Fig. 8C, the first spacers 81 and the second spacers 83 are arranged on the side walls of the fins 66 and / or nanostructures 55. As shown in Fig. 8B, in some embodiments, the second spacer layer 82 may be removed over the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71, and only the first spacers 81 are disposed on the sidewalls of the masks 78, the dummy gates 76, and the dummy dielectric layers 60. In some embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71.

[0040] It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different order of steps may be used (e.g., the first spacers 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, the n- and p-type devices may be formed using different structures and steps.

[0041] In the Fig. 9A to 9C, first cutouts 86 are formed in the nanostructures 55, the fins 66, and the substrate 50. Epitaxial source / drain regions are subsequently formed in the first cutouts 86. The first cutouts 86 may extend through the first nanostructures 52, the second nanostructures 54, and into the substrate 50. As shown in Fig. 9C, the upper surfaces of the STI regions 68 may be flush with the lower surfaces of the first cutouts 86. In various embodiments, the fins 66 may be etched such that the lower surfaces of the first cutouts 86 are disposed above the upper surfaces of the STI regions 68, below the upper surfaces of the STI regions 68, or the like. The first cutouts 86 may be formed by etching the nanostructures 55, the fins 66, and the substrate 50 using an anisotropic etch process such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask portions of the nanostructures 55, the fins 66, and the substrate 50 during the etch processes used to form the first cutouts 86. A single etching process or multiple etching processes may be used to etch each layer of the nanostructures 55, the fins 66 and / or the substrate 50.Time-bound etching processes may be used to stop the etching of the first cutouts 86 after the first cutouts 86 reach a desired depth.

[0042] In the Fig. 10A to 10C, portions of the sidewalls of the layers of the multilayer stack 64 formed from the first semiconductor materials (e.g., the first nanostructures 52) exposed through the first cutouts 86 are etched to form sidewall cutouts 88 in the n-type region 50N, and portions of the sidewalls of the layers of the multilayer stack 64 formed from the second semiconductor materials (e.g., the second nanostructures 54) exposed through the first cutouts 86 are etched to form sidewall cutouts 88 in the p-type region 50P. Although the sidewalls of the first nanostructures 52 and the second nanostructures 54 are adjacent to the sidewall cutouts 88 in Fig. 10B as straight, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as a wet etching method or the like. The p-type region 50P may be protected with a mask (not separately illustrated) while etchants that selectively act on the first semiconductor materials are used to etch the first nanostructures 52. Thus, the second nanostructures 54 and the substrate 50 in the n-type region 50N remain relatively unetched compared to the first nanostructures 52. Similarly, the n-type region 50N may be protected with a mask (not separately illustrated) while etchants that selectively act on the second semiconductor materials are used to etch the second nanostructures 54. Thus, the first nanostructures 52 and the substrate 50 in the p-type region 50P remain relatively unetched compared to the second nanostructures 54.In an embodiment where the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54 comprise, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructures 52 in the n-type region 50N. A wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the second nanostructures 54 in the p-type region 50P.

[0043] In the Fig. 11A to 11D, first inner spacers 90 are formed in the sidewall cutouts 88. The first inner spacers 90 can be formed by depositing an inner spacer layer (not separately illustrated) over the Fig. 10A to 10C. The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as lower dielectric constant (low-k) materials with a k value below approximately 3.5, may be used. The inner spacer layer may be anisotropically etched using a process such as RIE, NBE, or the like to form the first inner spacers 90.

[0044] Although the outer sidewalls of the first inner spacers 90 are illustrated as being flush with the sidewalls of the second nanostructures 54 in the n-region 50N and flush with the sidewalls of the first nanostructures 52 in the p-region 50P, the outer sidewalls of the first inner spacers 90 may extend beyond or be cut out from the sidewalls of the second nanostructures 54 and / or the first nanostructures 52. Furthermore, the outer sidewalls of the first inner spacers 90 may be concave or convex, although the outer sidewalls of the inner spacers 90 may Fig. 11B as just illustrated. As an example, Fig. 11D shows an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are cut out from the sidewalls of the second nanostructures 54 in the n-region 50N. Furthermore, in Fig. 11D, the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are cut out opposite the sidewalls of the first nanostructures 52 in the p-region 50P.

[0045] The first inner spacers 90 act as isolation elements between subsequently formed source / drain regions (such as the epitaxial source / drain regions 92 described below with reference to the Fig. 12A to 12E) and gate structures (such as the gate structures comprising the gate dielectric layers 100 and the gate electrodes 102, which are discussed below with reference to the Fig. 17A and Fig. 17B). The first inner spacers 90 may also prevent damage to the epitaxial source / drain regions 92 by subsequent etch processes, such as etch processes used to form the gate structures including the gate dielectric layers 100 and the gate electrodes 102.

[0046] In the Fig. 12A to 12E, epitaxial source / drain regions 92 (which may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C) are formed in the first cutouts 86 (illustrated in the Fig. 11B to 11D). In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructures 54 in the n-type region 50N and to the first nanostructures 52 in the p-type region 50P, thereby improving performance. As shown in Fig. 12B, the epitaxial source / drain regions 92 are formed in the first cutouts 86 such that each of the dummy gates 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by appropriate lateral distances to prevent short circuits between the epitaxial source / drain regions 92 and subsequently formed gate structures (such as the gate structures comprising the gate dielectric layers 100 and gate electrodes 102, which will be described below with reference to Fig. 17A and Fig. 17B). In some embodiments, the epitaxial source / drain regions 92 may have heights H 14in the range of about 20 nm to about 70 nm.

[0047] The epitaxial source / drain regions 92 in the n-type region 50N, e.g., the NMOS region, may be formed by masking the p-type region 50P, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first cutouts 86 in the n-type region 50N. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for n-type nanostructure FETs. In embodiments where the second nanostructures 54 are made of silicon, the epitaxial source / drain regions 92 may comprise, for example, materials that exert tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have raised surfaces from the respective upper surfaces of the nanostructures 55 and may have facets.

[0048] The epitaxial source / drain regions 92 in the p-type region 50P, e.g., the PMOS region, may be formed by masking the n-type region 50N, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first cutouts 86 in the p-type region 50P. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for p-type nanostructure FETs. In embodiments where the first nanostructures 52 are made of silicon germanium, the epitaxial source / drain regions 92 may, for example, comprise materials that exert compressive stress on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have raised surfaces from the respective surfaces of the nanostructures 55 and may have facets.

[0049] The epitaxial source / drain regions 92, the nanostructures 55, the fins 66, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have an impurity concentration between approximately 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3 The n- and / or p-type impurities for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during construction.

[0050] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the n-region 50N and in the p-region 50P, the upper surfaces of the epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause the merging of adjacent epitaxial source / drain regions 92 of a same nanostructure FET, as by Fig. 12C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in Fig. 12E. In the Fig. 12C and Fig. In the embodiments illustrated in FIG. 12E, the first spacers 81 may be formed extending to upper surfaces of the STI regions 68, thereby blocking epitaxial growth. In some embodiments, the first spacers 81 may cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some embodiments, the standoff etch used to form the first spacers 81 may be adjusted to remove the spacer material, allowing the epitaxial source / drain regions 92 to extend to the surfaces of the STI regions 68.

[0051] The epitaxial source / drain regions 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed from different semiconductor materials and doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B and a higher dopant concentration than the third semiconductor material layer 92C.In embodiments where the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0052] Fig. 12D illustrates an embodiment in which the sidewalls of the first nanostructures 52 in the n-region 50N and the sidewalls of the second nanostructures 54 in the p-region 50P are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are cut out from the sidewalls of the second nanostructures 54 and the first nanostructures 52. As in Fig. 12D, the epitaxial source / drain regions 92 may be formed in contact with the first inner spacers 90 and may extend past the sidewalls of the second nanostructures 54 in the n-type region 50N and past the sidewalls of the first nanostructures 52 in the p-type region 50P.

[0053] In the Fig. 13A and Fig. 13B, a contact etch stop layer (CESL) 94 and a first interlayer dielectric (ILD) 96 are deposited over the epitaxial source / drain regions 92, the dummy gate structures, and the first spacers 81. The CESL 94 may comprise a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying first ILD 96. The CESL 94 may be deposited by ALD, CVD, or the like. The CESL 94 is optional and may be omitted in some embodiments. The first ILD 96 may be formed from a dielectric and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectrics may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.Other insulating materials formed by an acceptable process may be used.

[0054] In the Fig. 14A and Fig. 14B, a planarization process, such as CMP, is performed to level the top surfaces of the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78. The planarization process may also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along sidewalls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, the CESL 94, and the first ILD 96 are in-plane with each other (within process variations). Accordingly, the top surfaces of the dummy gate 76 are exposed through the first ILD 96 and the CESL 94. In some embodiments, the masks 78 may remain. In this case, the planarization process levels the top surfaces of the first ILD 96 and the CESL 94 with the top surfaces of the masks 78 and the first spacers 81.After the planarization process, the first ILD 96 may have a height H15 above the top surfaces of the epitaxial source / drain regions 92 in the range of about 10 nm to about 60 nm.

[0055] In the Fig. 15A and Fig. 15B, the dummy gates 76, the dummy gate dielectrics 71, and the masks 78, if present, are removed, forming second cutouts 98. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 71 are removed by one or more etching processes, such as anisotropic dry etching processes. The etching processes may include a dry etching process using reactant gas(es) that selectively etch the dummy gates 76 (at a faster rate than the first ILD 96, the CESL 94, or the first spacers 81). Each of the second cutouts 98 exposes and / or overlies portions of the nanostructures 55 that will function as channel regions in the subsequently completed nanostructure FETs. The portions of the nanostructures 55 that will function as channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 71 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 71 can then be removed after the dummy gates 76 are removed.

[0056] In the Fig. 16A and Fig. 16B, the first nanostructures 52 in the n-type region 50N and the second nanostructures 54 in the p-type region 50P are removed, extending the second cutouts 98. The first nanostructures 52 may be removed by forming a mask (not separately illustrated) over the p-type region 50P and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52. The second nanostructures 54, the fins 66, the substrate 50, the STI regions 68, the first ILD 96, and the CESL 94 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 are made of, e.g., SiGe and the second nanostructures 54 are made of, e.g., SiGe. B. Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like may be used to remove the first nanostructures 52 in the n-region 50N.

[0057] The second nanostructures 54 in the p-type region 50P may be removed by forming a mask (not separately illustrated) over the n-type region 50N and performing an isotropic etching process, such as wet etching or the like, using etchants selective for the materials of the second nanostructures 54. The first nanostructures 52, the fins 66, the substrate 50, the STI regions 68, the first ILD 96, and the CESL 94 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise, e.g., SiGe, and the first nanostructures 52 comprise, e.g., Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures 54 in the p-type region 50P.

[0058] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously. For example, the first nanostructures 52 in both the n-type region 50N and the p-type region 50P may be removed, or the second nanostructures 54 in both the n-type region 50N and the p-type region 50P may be removed. In such embodiments, the channel regions of n-type nanostructure FETs and p-type nanostructure FETs may have the same material composition, such as silicon, silicon germanium, or the like.

[0059] In Fig. 17A to 17B, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. The gate dielectric layers 100 are conformally deposited in the second cutouts 98. In the n-type region 50N, the gate dielectric layers 100 may be formed on the top surfaces and sidewalls of the fins 66 and on the top surfaces, sidewalls, and bottom surfaces of the second nanostructures 54. In the p-type region 50P, the gate dielectric layers 100 may be formed on the top surfaces and sidewalls of the fins 66, on the top surfaces and sidewalls of the first nanostructures 52A, and on the top surfaces, sidewalls, and bottom surfaces of the first nanostructures 52B and 52C. The gate dielectric layers 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94 and the STI regions 58, on the top surfaces and sidewalls of the first spacers 81 and on the sidewalls of the first inner spacers 90.

[0060] According to some embodiments, the gate dielectric layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, or the like, or combinations thereof. In some embodiments, the gate dielectric layers 100 may, for example, comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 comprise a high-k dielectric, and in these embodiments, the gate dielectric layers 100 may have a k value greater than about 7.0. The gate dielectric layers 100 may comprise a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-type region 50N and the p-type region 50P.The formation method of the gate dielectric layers 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0061] The gate electrodes 102 are deposited over the gate dielectric layers 100 and fill the remaining portions of the second cutouts 98. The gate electrodes 102 may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in the Fig. 17A and Fig. 17B, ​​the gate electrodes 102 may include any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers comprising the gate electrodes 102 may be deposited in the n-type region 50N between adjacent ones of the second nanostructures 54 and between the second nanostructures 54A and the fins 66. Furthermore, any combination of the layers forming the gate electrodes 102 may be deposited in the p-type region 50P between adjacent ones of the first nanostructures 52.

[0062] The formation of the gate dielectric layers 100 in the n-type region 50N and in the p-type region 50P may occur simultaneously, such that the gate dielectric layers 100 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes, such that the gate dielectric layers 100 may be made of different materials and / or have a different number of layers. The formation of the gate electrodes 102 in the n-type region 50N and in the p-type region 50P may occur simultaneously, such that the gate electrodes 102 in each region are formed from the same materials. The gate electrodes 102 in each region may be formed by different processes, such that the gate electrodes 102 may be made of different materials and / or have a different number of layers.Different masking steps can be used to mask and expose appropriate regions when using separate processes.

[0063] After the second cutouts 98 are filled, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102 located above the top surfaces of the first ILD 96, the CESL 94, and the first spacers 81. The remaining material portions of the gate electrodes 102 and the gate dielectric layers 100 form replacement gate structures of the resulting nanostructure FETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as "gate structures." The epitaxial source / drain regions 92, the first nanostructures 52 or second nanostructures 54, and the gate structures (including the gate dielectric layers 100 and the gate electrodes 102) may collectively be referred to as transistor structures 109.

[0064] In the Fig. 18A and Fig. 18B, the gate structures (comprising the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) are cut out such that cutouts are formed directly above the gate structures and between opposing portions of the first spacers 81. An etch stop layer 103 may be deposited over the cut-out gate structures. The etch stop layer 103 may comprise a conductive material, such as tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like. The etch stop layer 103 may have a different etch rate than a subsequently formed gate mask. The etch stop layer 103 may be deposited by ALD, CVD, PVD, or the like. In some embodiments, the etch stop layer 103 is formed from tungsten, such as fluorine-free tungsten (FFW) deposited by a selective deposition process, such as a selective CVD process.Since the etch stop layer 103 is formed of a conductive material, it can be used to stop the etching process and adjust the contact resistance to the gate structures. In some embodiments, the etch stop layer 103 may comprise a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0065] A gate mask 104 having one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is deposited over the etch stop layer 103 and fills the remainder of the cutout. The deposition of the gate mask 104 may be followed by a planarization process to remove excess portions of the dielectric, such as portions of the gate mask 104 extending over the first ILD 96, the CESL 94, and the first spacers 81. Subsequently formed gate contacts (such as the gate contacts 118 and the butt contacts 120, which will be described further below with reference to Fig. 22A to 22C) penetrate the gate mask 104 to contact the upper surfaces of the cut-out etch stop layer 103.

[0066] In the Fig. 19A to 19E, silicide regions 106 and first source / drain contacts 108 are formed through the first ILD 96 and the CESL 94. The first ILD 96 and the CESL 94 may be etched to form cutouts exposing surfaces of the epitaxial source / drain regions 92. The cutouts may be formed by etching with anisotropic etch processes, such as RIE, NBE, or the like. In some embodiments, the cutouts may be etched through the first ILD 96 with a first etch process and then through the CESL 94 with a second etch process. A mask, such as a photoresist, may be formed and patterned over the first ILD 96 to mask portions of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104 prior to the first etch process and the second etch process. In some embodiments, the etch processes may overetch, and therefore the cutouts may extend into the epitaxial source / drain regions 92.The lower surfaces of the cutouts may be at the same height (e.g., at the same height or at the same distance from the substrate 50) or lower than the upper surfaces of the epitaxial source / drain regions 92 (e.g., closer to the substrate 50).

[0067] After the cutouts are formed, the silicide regions 106 may be formed over the epitaxial source / drain regions 92. In some embodiments, the silicide regions 106 are formed by first depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon germanium, germanium, or the like) over the exposed portions of the epitaxial source / drain regions 92 to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or their alloys. A thermal annealing process may then be performed to form the silicide regions 106. Unreacted portions of the deposited metal are removed by an etching process.Although referred to as silicide regions, the silicide regions 106 may be replaced with germanide regions, silicon germanide regions (e.g., regions comprising silicide and germanide), or the like. In one embodiment, the silicide regions 106 comprise TiSi and have a thickness in the range of about 2 nm to about 10 nm.

[0068] The first source / drain contacts 108 are then formed over the silicide regions 106 and fill the cutouts. The first source / drain contacts 108 may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the first source / drain contacts 108 each comprise a barrier layer and a conductive material over the conductive material. The conductive material of each of the first source / drain contacts 108 may be electrically coupled to the underlying epitaxial source / drain regions 92 through the silicide regions 106. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), copper (Cu), a copper alloy, silver (Ag), gold (Au), aluminum (Al), nickel (Ni), or the like.After the first source / drain contacts 108 are formed, a planarization process, such as a CMP, may be performed to remove excess material from the surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104.

[0069] The Fig. 19B to 19E illustrate the first source / drain contacts 108 according to various embodiments. As in Fig. 19B, the upper surfaces of the first source / drain contacts 108 may be level with the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104 after the planarization process. In the Fig. 19B, the first source / drain contacts 108 may have heights H1 in the range of about 28 nm to about 33 nm and widths W1 in the range of about 14 nm to about 16 nm. The ratio of the heights H1 of the first source / drain contacts 108 to the heights H 14of the epitaxial source / drain regions 92 may range from about 0.2 to about 2 or from about 0.2 to about 5.

[0070] As in the Fig. 19C to 19E, a common top surface of the first source / drain contacts 108, the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104 may be non-planar after the planarization process. Due to various process factors between the first source / drain contacts 108, the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, such as a pattern charge effect, differences between etch rates, differences between mechanical polishing rates, differences in reactions on a slurry, and the like, for example, the planarization process may produce a non-planar top surface, as shown in FIGS. Fig. 19C to 19E illustrated. Fig. 19C illustrates an embodiment in which the upper surfaces of the first source / drain contacts 108 are arranged above the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104. In the Fig. 19C, the first source / drain contacts 108 may have heights H2 in the range of about 31 nm to about 36 nm and widths W2 in the range of about 14 nm to about 16 nm. The ratio of the heights H2 of the first source / drain contacts 108 to the heights H 14 of the epitaxial source / drain regions 92 may range from about 0.25 to about 2.

[0071] During the planarization process, a dishing effect may also occur, leading to the formation of cutouts 105 in the upper surfaces of the first source / drain contacts 108, as shown in the Fig. 19D and Fig. 19E illustrated. Fig. 19D illustrates an embodiment in which the upper surfaces of the first source / drain contacts 108 are arranged above the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81 and the gate mask 104, and the dishing effect occurs such that cutouts 105 are formed in the upper surfaces of the first source / drain contacts 108. In the Fig. 19D, the first source / drain contacts 108 may have heights H3 in the range of about 31 nm to about 33 nm, widths W3 in the range of about 14 nm to about 16 nm, and recesses 105 may have depths D1 in the range of about 0 nm to about 2 nm. The ratio of the heights H3 of the first source / drain contacts 108 to the heights H 14 of the epitaxial source / drain regions 92 may range from about 0.2 to about 2. Fig. 19E illustrates an embodiment in which portions of the upper surfaces of the first source / drain contacts 108 are arranged on the same plane as the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, and the dishing effect occurs such that cutouts 105 are formed in the upper surfaces of the first source / drain contacts 108. In the Fig. 19E, the first source / drain contacts 108 may have heights H4 in the range of about 30 nm to about 33 nm, widths W4 in the range of about 14 nm to about 16 nm, and recesses 105 may have depths D2 in the range of about 0 nm to about 2 nm. The ratio of the heights H4 of the first source / drain contacts 108 to the heights H 14 of the epitaxial source / drain regions 92 may range from about 1 / 6 to about 2.

[0072] In the Fig. 20A to 20E, an annealing process is performed on the first source / drain contacts 108. The annealing process may be performed at a temperature greater than about 100°C, a temperature in the range of about 20°C to about 500°C, or the like, a pressure in the range of about 1 Torr to about 50 Torr, and for a duration in the range of about 10 seconds to about 100 seconds. In some embodiments, the annealing process may be performed in an atmosphere that may include a reducing agent and inert gases. For example, the annealing process may be performed in an atmosphere that may include hydrogen (H2), a mixture of hydrogen and argon (Ar), a mixture of nitrogen (N2) and hydrogen, argon, a mixture of hydrogen and helium (He), air, a vacuum, combinations thereof, or the like.In some embodiments, hydrogen gas may be supplied to a chamber in which the annealing process is performed at a flow rate in the range of about 500 sccm to about 5,000 sccm. The annealing process may be performed in situ (e.g., in a process chamber used to form the first source / drain contacts 108) or ex situ (e.g., in a process chamber separate from the process chamber for forming the first source / drain contacts 108).

[0073] The annealing process may restructure the first source / drain contacts 108. More specifically, the annealing process may cause recrystallization in the first source / drain contacts 108, which may reduce the resistance of the first source / drain contacts 108 and improve device performance. The recrystallization of the first source / drain contacts 108 may cause the volume of the first source / drain contacts 108 to shrink and the first source / drain contacts 108 to have convex upper surfaces, as shown in the Fig. 20B and Fig. 20C. The convex shape of the upper surfaces of the first source / drain contacts 108 may be a result of the cohesion within the materials of the first source / drain contacts 108. Forming the first source / drain contacts 108 with convex surfaces may provide a contact area between the first source / drain contacts 108 and the subsequently formed source / drain contacts (such as the second source / drain contacts 116 and the butt contacts 120, which are described further below with reference to Fig. 22A to 22C), which further reduces contact resistance and improves device performance. In some embodiments, performing the annealing process on the first source / drain contacts 108 may reduce the height of the first source / drain contacts 108 from about 1% to about 60%, or from about 1% to about 30%, compared to the heights of the first source / drain contacts 108 prior to performing the annealing process.

[0074] Fig. 20B illustrates the first source / drain contacts 108 of Fig. 19B after performing the annealing process. As in Fig. 20B, the upper ends of the upper surfaces of the first source / drain contacts 108 may be disposed after the annealing process at a distance D3 below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 2 nm to about 3 nm; the lower extents of the upper surfaces of the first source / drain contacts 108 may be disposed at a distance D4 below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 3 nm to about 6 nm; the first source / drain contacts 108 may have heights H5 ranging from about 25 nm to about 30 nm, and the first source / drain contacts 108 may have widths W5 ranging from about 14 nm to about 16 nm. The ratio of the heights H5 of the first source / drain contacts 108 to the heights H 14of the epitaxial source / drain regions 92 may be in the range of about 0.2 to about 2. The ratio of the heights H5 of the first source / drain contacts 108 to the heights H 15 the first ILD 96 can range from about 0.5 to about 1.5. Fig. 20C illustrates the first source / drain contacts 108 from Fig. 19C after completing the tempering process. As in Fig. 20C, after the annealing process, the upper extents of the upper surfaces of the first source / drain contacts 108 may be arranged at a distance D5 above the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104 in the range of about 10 nm to about 25 nm; the lower extents of the upper surfaces of the first source / drain contacts 108 may be level with the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104; the first source / drain contacts 108 may have heights H6 in the range of about 28 nm to about 33 nm, and the first source / drain contacts 108 may have widths W6 in the range of about 14 nm to about 16 nm. The ratio of the heights H6 of the first source / drain contacts 108 to the heights H 14of the epitaxial source / drain regions 92 may be in the range of about 0.25 to about 2. The ratio of the heights H6 of the first source / drain contacts 108 to the heights H 15 the first ILD 96 can range from about 1 to about 1.5.

[0075] In some embodiments, the recrystallization of the first source / drain contacts may result in the first source / drain contacts 108 having concave top surfaces, as shown in the Fig. 20D and Fig. 20E, flat surfaces or the like. The concavity or convexity of the upper surfaces of the first source / drain contacts 108 may depend on the composition of the first source / drain contacts 108 as well as the conditions of the annealing process performed on the first source / drain contacts 108. Fig. 20D illustrates the first source / drain contacts 108 from Fig. 19D after performing the annealing process. As in Fig. 20D, the upper ends of the upper surfaces of the first source / drain contacts 108 may be arranged after the annealing process at a distance D6 above the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 10 nm to about 25 nm; the lower extents of the upper surfaces of the first source / drain contacts 108 may be arranged at a distance D7 below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 10 nm to about 25 nm; the first source / drain contacts 108 may have heights H7 ranging from about 26 nm to about 30 nm, and the first source / drain contacts 108 may have widths W7 ranging from about 14 nm to about 16 nm. The ratio of the heights H7 of the first source / drain contacts 108 to the heights H14 of the epitaxial source / drain regions 92 may be in the range of about 0.2 to about 2.The ratio of the heights H7 of the first source / drain contacts 108 to the heights H. 15 the first ILD 96 can range from about 0.5 to about 1.5. Fig. 20E illustrates the first source / drain contacts 108 from Fig. 19E after performing the annealing process. As in Fig. 20E, the upper ends of the upper surfaces of the first source / drain contacts 108 may be disposed after the annealing process at a distance D8 below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 10 nm to about 25 nm; the lower extensions of the upper surfaces of the first source / drain contacts 108 may be disposed at a distance D9 below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104, ranging from about 10 nm to about 25 nm; the first source / drain contacts 108 may have heights H8 ranging from about 27 nm to about 30 nm, and the first source / drain contacts 108 may have widths W8 ranging from about 14 nm to about 16 nm. The ratio of the heights H8 of the first source / drain contacts 108 to the heights H 14of the epitaxial source / drain regions 92 may be in the range of about 1 / 6 to about 2. The ratio of the heights H8 of the first source / drain contacts 108 to the heights H 15 the first ILD 96 can range from about 1 / 3 to about 1.

[0076] The annealing process may further reduce the metal oxides at the surface of the first source / drain contacts 108. For example, in embodiments where the annealing process is performed in a hydrogen-containing atmosphere, the hydrogen may reduce any metal oxides at the surface of the first source / drain contacts 108. This further reduces the contact resistance of the first source / drain contacts 108 and improves device performance. In an embodiment where the first source / drain contacts 108 comprise cobalt, the metal oxides in the first source / drain contacts 108 may be reduced by one of the following reactions: Co3O4 + H2 → 3CoO + H2O CoO + H2 → Co + H2O Co3O4 + 4H2 → 3Co + 4H2O

[0077] In the Fig. 21A to 21E are accessible via the Fig. 20A to 20E, a second CESL 112 and a second ILD 114 are each formed. The second CESL 112 may comprise a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying second ILD 114. The second CESL 112 may be deposited by a conformal deposition process, such as ALD, CVD, or the like. Thus, a top surface of the second CESL 112 may have a profile that matches or is similar to that of the top surfaces of the underlying first source / drain contacts 108, the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104. In the Fig. 21B, at least portions of the upper surface of the second CESL 112 may be disposed below a top surface of the first ILD 96. The second CESL 112 may include cutouts over the first source / drain contacts 108 that include convex upper surfaces. In the embodiment illustrated in Fig. 21C, portions of the second CESL 112 above the first source / drain contacts 108 may extend over portions of the second CESL 112 above the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104. The portions of the second CESL 112 above the first source / drain contacts 108 may have convex upper surfaces. In the embodiment illustrated in Fig. 21D, portions of the second CESL 112 above the first source / drain contacts 108 may extend over portions of the second CESL 112 above the first ILD 96, the CESL 94, the first spacers 81, and the gate mask 104. The portions of the second CESL 112 above the first source / drain contacts 108 may have concave top surfaces. In the embodiment illustrated in Fig. 21E, at least portions of the top surface of the second CESL 112 may be disposed below a top surface of the first ILD 96. The second CESL 112 may include cutouts over the first source / drain contacts 108 that include concave top surfaces. The second CESL 112 is optional and may be omitted in some embodiments. In some embodiments, the second ILD 114 may have a height H 16 above the second CESL 112 in the range of about 10 nm to about 70 nm.

[0078] The second ILD 114 may be formed from a dielectric and deposited by any suitable process, such as CVD, PECVD, or FCVD. Suitable dielectrics may include PSG, BSG, BPSG, USG, or the like. Other insulating materials formed by an acceptable process may be used. After the second ILD 114 is deposited, a planarization process, such as CMP, may be performed to planarize a top surface of the second ILD 114. In the Fig. 21B and Fig. 21E, the second ILD 114 may extend below a top surface of the first ILD 96.

[0079] In the Fig. 22A to 22C, second source / drain contacts 116, gate contacts 118, and / or blunt contacts 120 (which may each also be referred to as contact plugs) are formed, extending through the second ILD 114 and the second CESL 112. Openings for the second source / drain contacts 116 are formed through the second ILD 114 and the second CESL 112. Openings for the gate contacts 118 are formed through the second ILD 114, the second CESL 112, and the gate mask 104. Openings for the butt contacts 120 are formed through the second ILD 114, the second CESL 112, and the gate mask 104. The openings may be formed using acceptable photolithography and etching techniques. A lining, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 114. The remaining liner and conductive material form the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 in the openings. The butt contacts 120 may be useful for forming circuitry in various regions, such as in an SRAM cell.

[0080] The second source / drain contacts 116 are electrically coupled to the epitaxial source / drain regions 92 through the first source / drain contacts 108 and the silicide regions 106. The gate contacts 118 are electrically coupled to the gate electrodes 102 through the etch stop layer 103. The butt contacts 120 are electrically coupled to the epitaxial source / drain regions 92 through the first source / drain contacts 108 and the silicide regions 106 and to the gate electrodes 102 through the etch stop layer 103. The second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 may be formed in different processes or in the same process. Even though they are shown in the same cross-sections, it should be noted that each of the second source / drain contacts 116 and the gate contacts 118 may be formed in different cross-sections, which may prevent short circuits between the contacts.

[0081] As in Fig. 22B, the second source / drain contacts 116 may have heights H9 in the range of about 15 nm to about 60 nm and widths W9 in the range of about 5 nm to about 17 nm. The gate contacts 118 may have heights H 10 in the range of about 20 nm to about 85 nm and widths W 10 in the range of about 3 nm to about 17 nm. As described in Fig. 22C, the abutment contacts can have 120 widths W 11 in the range of about 28 nm to about 50 nm, the portions of the butt contacts 120 that physically contact the first source / drain contacts 108 may have heights H9 in the range of about 15 nm to about 60 nm, and the portions of the butt contacts 120 that physically contact the etch stop layer 103 may have heights H 10 in the range of about 20 nm to about 85 nm.

[0082] In the Fig. 23A to 23D, an annealing process is performed on the second source / drain contacts 116, the gate contacts 118 and the butt contacts 120. The annealing process shown in the Fig. 23A to 23D may be used in addition to or instead of the annealing process shown in Fig. 20A to 20E and discussed with reference thereto. The annealing process may be performed at a temperature greater than about 100°C, a temperature in the range of about 20°C to about 500°C, or the like, a pressure in the range of about 1 Torr to about 50 Torr, and for a duration in the range of about 10 seconds to about 100 seconds. In some embodiments, the annealing process may be performed in an atmosphere that may include a reducing agent and inert gases. For example, the annealing process may be performed in an atmosphere that may include hydrogen, a mixture of hydrogen and argon, a mixture of nitrogen and hydrogen, argon, a mixture of hydrogen and helium, air, a vacuum, combinations thereof, or the like. In some embodiments, hydrogen gas may be supplied to a chamber in which the annealing process is performed at a flow rate in the range of about 500 sccm to about 5.000 sccm. The annealing process may be performed in situ (e.g., in a process chamber used to form the second source / drain contacts 116, the gate contacts 118, and / or the butt contacts 120) or ex situ (e.g., in a process chamber separate from the process chamber used to form the second source / drain contacts 116, the gate contacts 118, and / or the butt contacts 120).

[0083] The annealing process may restructure the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120. More specifically, the annealing process may cause recrystallization in the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120, which may reduce the resistance of the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 and improve device performance. The recrystallization of the second source / drain contacts 116, the gate contacts 118 and the abutment contacts 120 may result in the volume of the second source / drain contacts 116, the gate contacts 118 and the abutment contacts 120 shrinking and in the second source / drain contacts 116, the gate contacts 118 and / or the abutment contacts 120 having convex upper surfaces, as shown in the Fig. 23A to 23D. In some embodiments, the upper surfaces of the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 may have one of the configurations described above with reference to Fig. 22A to 22E. In some embodiments, performing the annealing process on the second source / drain contacts 116, the gate contacts 118, and / or the butt contacts 120 may reduce the height of the first source / drain contacts 108 from about 1% to about 60%, or from about 1% to about 30%, compared to the heights of the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 prior to performing the annealing process.

[0084] The Fig. 23A and Fig. 23C illustrate the gate contacts 118 of the Fig. 22A and Fig. 22B after performing the annealing process. As shown in the Fig. 23A and Fig. 23C, after the annealing process, the upper ends of the upper surfaces of the gate contacts 118 can be arranged at a distance D 12 below the upper surfaces of the second ILD 114 in the range of about 0 nm to about 2 nm; the lower ends of the upper surfaces of the gate contacts 118 may be at a distance D 13 be arranged below the upper surfaces of the second ILD 114 in the range of about 0 nm to about 5 nm; the gate contacts 118 may have heights H 12 in the range of about 17 nm to about 85 nm, and the gate contacts 118 may have widths W 13 in the range of about 3 nm to about 17 nm. The ratio of the heights H 12 the gate contacts 118 to the heights H 16 the second ILD 114 may be in the range of about 0.5 to about 1.5. Fig. 23B illustrates the second source / drain contacts 116 after performing the annealing process. As in Fig. 23B, after the annealing process, the upper extensions of the upper surfaces of the second source / drain contacts 116 may be at a distance D 10 below the upper surfaces of the second ILD 114, ranging from about 0 nm to about 2 nm; the lower ends of the upper surfaces of the second source / drain contacts 116 may be at a distance D 11 below the upper surfaces of the second ILD 114 in the range of about 0 nm to about 5 nm; the second source / drain contacts 116 may have heights H 11 in the range of about 12 nm to about 60 nm, and the second source / drain contacts 116 may have widths W 12 in the range of about 5 nm to about 17 nm. The ratio of the heights H 11 the second source / drain contacts 116 to the heights H 16 the second ILD 114 may be in the range of about 0.5 to about 1.5. As in Fig.23D, after the annealing process, the upper extensions of the upper surfaces of the abutment contacts 120 can be spaced apart by a distance D 14 below the upper surfaces of the second ILD 114 in the range of about 0 nm to about 5 nm; the lower ends of the upper surfaces of the abutment contacts 120 may be at a distance D 15 be arranged below the upper surfaces of the second ILD 114 in the range of about 0 nm to about 9 nm; the abutment contacts 120 may have heights H 13 in the range of about 7 nm to about 60 nm, and the abutment contacts 120 may have widths W 14 in the range of about 28 nm to about 50 nm. The ratio of the heights H 13 the contact points 120 to the heights H 16 the second ILD 114 may be between about 0.5 and about 1.5.

[0085] The annealing process may further reduce the metal oxides on the surfaces of the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120. For example, in embodiments where the annealing process is performed in a hydrogen-containing atmosphere, the hydrogen may reduce any metal oxides on the surface of the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120. This further reduces the contact resistance of the first source / drain contacts 108 and improves device performance.

[0086] Embodiments may achieve advantages. For example, performing the annealing process on any of the first source / drain contacts 108, the second source / drain contacts 116, the gate contacts 118, and the butt contacts 120 may reduce / prevent oxidation of the contacts, which lowers contact resistance, provides device reinforcement, and improves device performance. Furthermore, the annealing causes the top surfaces of the contacts to be reshaped to have a planar shape, such as a convex shape, that increases a contact area between the contacts and the subsequently formed contacts connected to the contacts. This further lowers contact resistance, provides device reinforcement, and improves device performance.

[0087] According to one embodiment, a semiconductor device comprises a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled to a first source / drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled to the first contact. In one embodiment, a top surface of the second contact is convex, and the top surface of the second contact is disposed below a top surface of the second ILD layer.In one embodiment, the second contact comprises a butt contact, and the second contact is further electrically coupled to a gate electrode of the transistor structure. In one embodiment, the first contact comprises cobalt. In one embodiment, the semiconductor device further comprises a contact etch stop layer (CESL) over the first ILD layer and the first contact, wherein the second ILD layer is located over the CESL and the CESL has a non-planar top surface. In one embodiment, an upper extent of the top surface of the first contact is 2 nm to 3 nm below the top surface of the first ILD layer. In one embodiment, the semiconductor device further comprises a third contact extending through the second ILD layer, wherein the third contact is electrically coupled to a gate electrode of the transistor structure, and a top surface of the third contact is convex.

[0088] According to another embodiment, a semiconductor device comprises a first interlayer dielectric (ILD) layer over a transistor structure, the first ILD layer having a planar top surface; and a first contact extending through the first ILD layer, the first contact being electrically coupled to the transistor structure, a top surface of the first contact being non-planar, and the top surface of the first contact being at least partially disposed at a different level than the planar top surface of the first ILD layer. In one embodiment, the top surface of the first contact is convex and disposed below the top surface of the first ILD layer. In one embodiment, the top surface of the first contact is convex and disposed above the top surface of the first ILD layer. In one embodiment, the top surface of the first contact is concave and disposed below the top surface of the first ILD layer.In one embodiment, the top surface of the first contact is concave and disposed above the top surface of the first ILD layer. In one embodiment, the semiconductor device further comprises a second ILD layer enclosing a gate electrode of the transistor structure; and a second contact extending through the second ILD layer and electrically coupled to a source / drain region of the transistor structure, wherein the first ILD layer overlies the second ILD layer and the second contact, and the first contact is electrically coupled to one of the second contact and the gate electrode. In one embodiment, the first ILD layer encloses a gate electrode of the transistor structure, and the first contact is electrically coupled to a source / drain region of the transistor structure.

[0089] According to another embodiment, a method comprises forming a first interlayer dielectric (ILD) layer over a transistor structure; etching a first opening extending through the first ILD layer; depositing a first contact in the first opening; planarizing the first ILD layer and the first contact; and annealing the first contact, wherein a top surface of the first contact is non-planar after annealing the first contact. In one embodiment, the first contact is annealed in a hydrogen-containing atmosphere. In one embodiment, the first contact is annealed at a temperature greater than 100°C. In one embodiment, the top surface of the first contact is disposed over a top surface of the first ILD layer after the first ILD layer and the first contact are planarized.In one embodiment, the top surface of the first contact is concave after planarizing the first ILD layer and the first contact, and the top surface of the first contact is concave after annealing the first contact. In one embodiment, the top surface of the first contact is flat after planarizing the first ILD layer and the first contact, and the top surface of the first contact is convex after annealing the first contact.

Claims

[1] A semiconductor device comprising: a first interlayer dielectric layer, ILD layer (96), over a transistor structure (109); a first contact (108) extending through the first ILD layer (96), the first contact (108) being electrically coupled to a first source / drain region (92) of the transistor structure (109), an upper surface of the first contact (108) being convex, and the upper surface of the first contact (108) being disposed below an upper surface of the first ILD layer (96); a second ILD layer (114) over the first ILD layer (96) and the first contact (108); and a second contact (116) extending through the second ILD layer (114), the second contact (116) being electrically coupled to the first contact (108), wherein a contact etch stop layer, CESL (112), is disposed over the first ILD layer (96) and the first contact (108), the CESL (112) over the first contact (108) comprising portions having convex upper surfaces. [2] The semiconductor device according to claim 1, wherein an upper surface of the second contact (116) is convex, and the upper surface of the second contact (116) is disposed below an upper surface of the second ILD layer (114). [3] The semiconductor device of claim 2, wherein the second contact (116) comprises an abutment contact, and wherein the second contact (116) is further electrically coupled to a gate electrode of the transistor structure (109). [4] A semiconductor device according to any preceding claim, wherein the first contact (108) comprises cobalt. [5] A semiconductor device according to any preceding claim, wherein the second ILD layer (114) is located above the CESL (112). [6] A semiconductor device according to any preceding claim, wherein an upper extent of the upper surface of the first contact (108) is 2 nm to 3 nm below the upper surface of the first ILD layer (96). [7] A semiconductor device according to any one of the preceding claims, further comprising a third contact extending through the second ILD layer (114), the third contact being electrically coupled to a gate electrode of the transistor structure (109), a top surface of the third contact being convex. [8] Semiconductor device comprising: a first interlayer dielectric layer, ILD layer (96), over a transistor structure (109), the first ILD layer (96) having a planar top surface; and a first contact (108) extending through the first ILD layer (96), the first contact (108) being electrically coupled to the transistor structure (109), an upper surface of the first contact (108) being non-planar, and the upper surface of the first contact (108) being at least partially disposed at a level different from the planar upper surface of the first ILD layer (96), wherein a contact etch stop layer, CESL (112), is disposed over the first ILD layer (96) and the first contact (108), the CESL (112) over the first contact (108) comprising portions having convex upper surfaces. [9] The semiconductor device of claim 8, wherein the top surface of the first contact (108) is convex and is disposed below the top surface of the first ILD layer (96). [10] The semiconductor device of claim 8, wherein the top surface of the first contact (108) is convex and is disposed over the top surface of the first ILD layer (96). [11] A semiconductor device according to any one of the preceding claims 8 to 10, further comprising: a second ILD layer enclosing a gate electrode of the transistor structure (109); and a second contact extending through the second ILD layer and electrically coupled to a source / drain region (92) of the transistor structure (109), wherein the first ILD layer (96) overlies the second ILD layer and the second contact, wherein the first contact (108) is electrically coupled to the second contact or the gate electrode. [12] A semiconductor device according to any one of the preceding claims 8 to 11, wherein the first ILD layer (96) encloses a gate electrode of the transistor structure (109), and wherein the first contact (108) is electrically coupled to a source / drain region (92) of the transistor structure (109). [13] Method comprising: Forming a first interlayer dielectric layer, ILD layer (96), over a transistor structure (109); etching a first opening extending through the first ILD layer (96); depositing a first contact (108) in the first opening; Planarizing the first ILD layer (96) and the first contact (108); Annealing the first contact (108), wherein a top surface of the first contact (108) is non-planar after annealing the first contact (108); and Forming a contact etch stop layer, CESL (112), over the first ILD layer (96) and the first contact (108), the CESL (112) over the first contact (108) comprising portions having convex top surfaces. [14] The method of claim 13, wherein the first contact (108) is annealed in a hydrogen-containing atmosphere. [15] The method of claim 13 or 14, wherein the first contact (108) is annealed at a temperature greater than 100°C. [16] The method of any one of the preceding claims 13 to 15, wherein the upper surface of the first contact (108) is disposed over an upper surface of the first ILD layer (96) after planarizing the first ILD layer (96) and the first contact (108). [17] The method of any one of the preceding claims 13 to 15, wherein the top surface of the first contact (108) is flat after planarizing the first ILD layer (96) and the first contact (108), and wherein the top surface of the first contact (108) is convex after annealing the first contact (108).

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