Extreme ultraviolet (EUV) photomask and method for manufacturing a semiconductor device using the same

Abstract

Method comprising: Forming (S10a) a first photomask (200a) including N mask chip regions (205_Ca) and a first mask scribe track region (205_Sa) surrounding each of the N mask chip regions (205_Ca); Forming (S10b) a second photomask (200b) including M mask chip regions (205_Cb) and a second mask scribe track region (205_Sb) surrounding each of the M mask chip regions (205_Cb); Performing (S20a) a first semiconductor process including a first photolithography process using the first photomask (200a) on a semiconductor wafer (WF); and Performing (S20b) a second semiconductor process including a second photolithography process using the second photomask (200b) on the semiconductor wafer (WF), wherein the first photolithography process is an extreme ultraviolet, EUV, photolithography process, the first photomask (200a) is an EUV photomask, N is a natural number of 2 or more, and M = 2 * N, and wherein the semiconductor wafer (WF) has a plurality of shot regions (SA1-SA6), and each of the plurality of shot regions (SA1-SA6) has M wafer chip regions (WF_C1, WF_C2, WF_C3, WF_C4) corresponding to the M mask chip regions (205_Cb), and a wafer scribe track region (WF_SL) surrounding each of the M wafer chip regions (WF_C1, WF_C2, WF_C3, WF_C4).

Description

Background1. Area

[0001] The present disclosure relates to an extreme ultraviolet (EUV) photomask, an extreme ultraviolet photolithography process apparatus, an extreme ultraviolet photolithography process, a method of manufacturing a semiconductor device using the same, and a semiconductor device and a semiconductor system prepared using the same. 2. Description of related technology

[0002] With the advancement of high-level integration and size reduction of semiconductor devices, technology for forming circuit patterns of the semiconductor device in a relatively small area is required. To meet these technical requirements, the wavelength of a light source used in a photolithography process can be shorter. For example, the wavelength of a light source used in the photolithography process can be shorter when using g-line light (436 nm), i-line light (365 nm), a KrF laser beam (248 nm), and / or an ArF laser beam (193 nm).

[0003] Recently, an extreme ultraviolet (EUV) photolithography process using extreme ultraviolet (EUV) light has been proposed. Since such EUV light can be absorbed by most refractive optical materials, an EUV photolithography process generally uses a reflective optical system instead of a refractive optical system and an EUV photomask.

[0004] From US 2004 / 0 009 431 A1 a mask for use in various types of structuring in the manufacture of a semiconductor component is known.

[0005] From US 6 331 885 B1 a scanning exposure apparatus and a scanning exposure method are known, which are preferably used for performing a scanning exposure with a large mask having a size of not less than 9 inches, and an apparatus manufactured by the scanning exposure method.

[0006] From US 2011 / 0 285 975 A1 a method for managing an EUV exposure mask for use in a lithography process that uses EUV light (extreme ultraviolet radiation) as an exposure light source and an exposure method that uses the EUV exposure mask are known.

[0007] From US 2016 / 0 161 837 A1, a reflective mask blank is known which is capable of facilitating the detection of impurities or scratches and other critical defects by preventing the detection of pseudo-defects attributable to the surface roughness of a substrate or film during a defect inspection using a highly sensitive defect inspection device.

[0008] A phase shift mask for extreme ultraviolet lithography is known from US 2018 / 0 143 527 A1.

[0009] From US 2020 / 0 073 225 A1, an extreme ultraviolet (EUV) mask is known which comprises a multilayer Mo / Si stack comprising alternating Mo and Si layers arranged over a first main surface of a mask substrate, a ruthenium (Ru) capping layer arranged over the multilayer Mo / Si stack, and an absorption layer on the capping layer.

[0010] US Pat. No. 5,250,983 A discloses a photomask for fabricating a semiconductor device. The photomask contains a plurality of tip patterns provided with alignment marks. Summary

[0011] One aspect of the present invention is to provide a method of manufacturing a semiconductor device using an extreme ultraviolet photomask.

[0012] According to one aspect, a method according to the invention includes: forming a first photomask including N mask chip regions and a first mask scribe track region surrounding each of the N mask chip regions; forming a second photomask including M mask chip regions and a second mask scribe track region surrounding each of the M mask chip regions; performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer, wherein the first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M = 2 * N.The semiconductor wafer has a plurality of shot regions, and each of the plurality of shot regions has M wafer chip regions corresponding to the M mask chip regions and a wafer scribe track region surrounding each of the M wafer chip regions.

[0013] According to a further aspect, a method according to the invention comprises: loading a semiconductor wafer into a wafer holder of an extreme ultraviolet (EUV) photolithography device equipped with an extreme ultraviolet (EUV) photomask; in the EUV photolithography device, sequentially performing a shot process a plurality of times, wherein the shot process includes aligning the semiconductor wafer and irradiating light from an extreme ultraviolet (EUV) light source onto the semiconductor wafer; and loading the semiconductor wafer from the EUV photolithography device, wherein the semiconductor wafer undergoes a plurality of shot processes.firing regions, each firing region of the plurality of firing regions has an upper firing region formed by one firing process of the firing process performed the plurality of times, and a lower firing region formed by another firing process of the firing process performed the plurality of times, a central region of each firing region has a wafer alignment mark region, and the wafer alignment mark region has alignment patterns of a first wafer alignment mark formed by the one firing process and alignment patterns of a second wafer alignment mark formed by the another firing process.

[0014] According to another aspect, an extreme ultraviolet (EUV) photomask is provided, comprising: a mask substrate having a first surface and a second surface opposite the first surface; a mask layout region on the first surface of the mask substrate; and a boundary region on the first surface of the mask substrate surrounding the mask layout region, the mask layout region comprising: a plurality of extreme ultraviolet (EUV) mask chip regions arranged on the first surface of the mask substrate;and an extreme ultraviolet (EUV) mask scribe track region disposed on the first surface of the mask substrate and surrounding the plurality of EUV mask chip regions, wherein the EUV mask scribe track region has a first side and a second side opposite the first side, and wherein the EUV mask scribe track region has test layout patterns and mask alignment layout patterns, and wherein the mask alignment layout patterns include: a first mask alignment layout pattern adjacent to a center region on the first side and a second mask alignment layout pattern adjacent to a center region on the second side;

[0015] According to another aspect of one or more embodiments, a method for manufacturing a semiconductor device is also disclosed. The method includes forming an extreme ultraviolet (EUV) photomask and exposing a semiconductor wafer using the EUV photomask. The EUV photomask includes a mask layout region and a boundary region surrounding the mask layout region.In the EUV photomask, the mask layout region includes a plurality of mask chip regions and a mask scribe track region surrounding the plurality of mask chip regions, wherein the mask scribe track region includes a first mask alignment layout pattern in a first mask alignment mark region and a second mask alignment layout pattern in a second mask alignment mark region, and the first mask alignment mark region is adjacent to a center region on a first side of the mask layout region and the second mask alignment mark region is adjacent to a center region on a second side of the mask layout region opposite to the first side. Short description of the drawings

[0016] For a clearer understanding of the above and other aspects, the following detailed description in conjunction with the attached drawings will provide: Fig. 1 is a view schematically illustrating an extreme ultraviolet (EUV) photolithography process apparatus according to an embodiment; Fig. 2A-2C are process flow diagrams schematically illustrating a method of manufacturing a semiconductor device according to various embodiments; Fig. 3 is a process flow diagram schematically illustrating a photolithography process for manufacturing a semiconductor device according to an embodiment; Fig. 4A to 4C are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to an embodiment; Fig. 5 is a cross-sectional view schematically illustrating an extreme ultraviolet (EUV) photomask for manufacturing a semiconductor device according to an embodiment; Fig. 6A is a plan view schematically illustrating a first photomask for manufacturing a semiconductor device according to an embodiment; Fig. 6B is a plan view schematically illustrating a second photomask for manufacturing a semiconductor device according to an embodiment; Fig. 7 is a plan view schematically illustrating a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment; Fig. 8 is a plan view schematically illustrating a shot region of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment; Fig. 9A and Fig. 9B are plan views illustrating exposing a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment by a first photolithography process; Fig. 10A and Fig. 10B are plan views illustrating exposing a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment by a second photolithography process; Fig. 11 is a plan view showing a wafer alignment mark formed using the first photolithography process of Fig. 9A and Fig. 9B, according to one embodiment; Fig. 12A to 12F are plan views showing modified examples of a wafer alignment mark formed using the first photolithography process of Fig. 9A and Fig. 9B, according to various embodiments; Fig. 13 is a plan view showing a wafer alignment mark formed using the second photolithography process of Fig. 10A and Fig. 10B, according to various embodiments; Fig. 14A is a plan view illustrating a wafer alignment mark formed using a first photolithography process and a wafer alignment mark formed using a second photolithography process for manufacturing a semiconductor device according to an embodiment; Fig. 14B is a cross-sectional view showing the portion of Fig. 14A along line II' schematically; and Fig. 15 is a perspective view schematically illustrating a system including a semiconductor package formed by a method of manufacturing a semiconductor device, according to one embodiment. Detailed description

[0017] Embodiments are described below with reference to the attached drawings.

[0018] Referring to Fig. 1, an extreme ultraviolet (EUV) photolithography process apparatus according to one embodiment is described. Fig. 1 is a view schematically illustrating an extreme ultraviolet (EUV) photolithography process apparatus according to an embodiment.

[0019] Referring to Fig. 1, an extreme ultraviolet (EUV) photolithography process apparatus 1 may include an exposure chamber 80, an extreme ultraviolet light source system SO, a lithography device LA, a projection system PS, a mask holder 190 on which a photomask 200 is mounted, and a wafer holder 150 on which a semiconductor wafer WF is mounted.

[0020] The wafer holder 150 can move the semiconductor wafer WF to change an exposed area of ​​the semiconductor wafer WF.

[0021] The exposure chamber 80 may include an internal space 85, and the extreme ultraviolet light source system SO, the lithography device LA, the projection system PS, the mask holder 190, and the wafer holder 150 may be arranged in the internal space 85. In some embodiments, some components of the extreme ultraviolet light source system SO, the lithography device LA, the projection system PS, the mask holder 190, and the wafer holder 150 may be arranged outside the exposure chamber 80. For example, in some embodiments, a portion of the light source system SO may be arranged outside the exposure chamber 80.

[0022] In the mask holder 190, the photomask 200 may be secured to the mask holder 190 by an electrostatic force generated by a power supply 195. The semiconductor wafer WF may be loaded onto and / or off the wafer holder 150.

[0023] In order to prevent a first light 50a of extreme ultraviolet light generated from the extreme ultraviolet light source system SO from being absorbed by a gas, the internal space 85 of the exposure chamber 80 may be provided to have a negative pressure state of 5 Pa or less, or may be provided to have a vacuum state.

[0024] In some embodiments, the extreme ultraviolet (EUV) light may have a wavelength of about 4 nm to about 124 nm.

[0025] In other embodiments, the extreme ultraviolet (EUV) light may have a wavelength of about 4 nm to about 20 nm.

[0026] In still further embodiments, the extreme ultraviolet (EUV) light may have a wavelength of approximately 13.5 nm.

[0027] The extreme ultraviolet light source system SO may include a light source chamber 10, an extreme ultraviolet light source 30 as a driving light source, and a droplet supply 20. The extreme ultraviolet light source system SO may generate extreme ultraviolet light with a wavelength of less than approximately 100 nm. The extreme ultraviolet light source 30 may, for example, be a plasma light source. Additionally, the plasma light source may use a CO2 laser as an excitation light source and may be a laser-produced plasma (LPP) light source targeted to a droplet consisting of any of tin (Sn), lithium (Li), and xenon (Xe). The extreme ultraviolet light source system SO according to one embodiment may use a master oscillator power amplifier (MOPA) method.For example, a seed laser can be used to generate a pre-pulse and a main pulse, the pre-pulse can be emitted to a droplet, the main pulse can be emitted back to the droplet to generate a plasma, and the plasma can be used to emit extreme ultraviolet light.

[0028] In an interior of the light source chamber 10 of the extreme ultraviolet light source system SO, a laser beam supplied by the extreme ultraviolet light source 30 and a droplet supplied by the droplet supply 20 can collide more than 50,000 times per second to generate a plasma. A collector of the light source chamber 10 can collect extreme ultraviolet (EUV) light emitted from the plasma in all directions, can concentrate the collected EUV light in a forward direction, and can transmit the concentrated EUV light to the lithography device LA.

[0029] The lithography apparatus LA may include a plurality of mirrors for guiding a first light 50a of the extreme ultraviolet light emitted from the extreme ultraviolet light source system SO through the lithography apparatus and irradiating a second light, which has been guided through the lithography apparatus LA, onto a surface of the photomask 200 of the mask holder 190. Fig. 1 shows only two mirrors 62 and 64 for the sake of simplicity of the drawings and description. That is, although the example from Fig. 1 illustrates two mirrors 62 and 64, the embodiments are not so limited and in some embodiments more than two mirrors may be provided.

[0030] The projection system PS may include a plurality of mirrors to guide a third light 50c of the extreme ultraviolet light reflected by the photomask 200 and a fourth light 50d guided through the projection system PS onto a surface of the semiconductor wafer WF on the wafer holder 150 to expose a photoresist layer on the surface of the semiconductor wafer WF. Fig. 1 shows only two mirrors 72 and 74 for the sake of simplicity of the drawings and description. That is, although the example from Fig. 1 illustrates two mirrors 72 and 74, the embodiments are not so limited and in some embodiments more than two mirrors may be provided.

[0031] A method of manufacturing a semiconductor device according to an embodiment is described with reference to Fig. 2A, Fig. 2B and Fig. 2C.

[0032] Fig. 2A-2C are process flow diagrams schematically illustrating a method of manufacturing a semiconductor device according to various embodiments. Fig. 2A is a process flow diagram schematically illustrating a method of manufacturing a semiconductor device according to an embodiment, and Fig. 2B is a view illustrating operation S10 of the method of Fig. 2A schematically, and Fig. Figure 2C is a view illustrating operation S20 of the method of Fig. 2A shows the schematic in more detail.

[0033] Referring to Fig. 2A, Fig. 2B and Fig. 2C, a plurality of photomasks may be formed (S10). For example, a first photomask may be formed (S10a) including "N" mask chip regions and a first mask scribe track region surrounding each of the "N" mask chip regions. A second photomask may be formed (S10b) including "M" mask chip regions and a second mask scribe track region surrounding each of the "M" mask chip regions. Thus, forming the plurality of photomasks may include forming the first photomask and the second photomask.

[0034] In some embodiments, "N" may be a natural number of 2 or more, and "M" may be two times "N." That is, "M" may be two times "N," i.e., M=2*N. For example, in some embodiments, "N" may be 2 and "M" may be 4.

[0035] In embodiments, the "mask die area" of the photomask may refer to an area where a circuit layout pattern is located. The "mask scribe track area" of the photomask may refer to an area where a test layout pattern and an alignment layout pattern are located.

[0036] In embodiments, the term “mask chip region” may be defined as a region for transferring a circuit layout pattern of a photomask to a chip region of a semiconductor wafer.

[0037] In embodiments, the term “mask scribe track region” may be defined as a region for transferring a layout pattern of a test element pattern and a layout pattern of an alignment mark in a photomask to a scribe track region of a semiconductor wafer.

[0038] Among the plurality of photomasks, one or more photomasks may be an extreme ultraviolet (EUV) photomask that reflects light, and another of the one or more photomasks may be an EUV photomask or a light-transmitting photomask that transmits light. The EUV photomask may be used in an EUV photolithography process using extreme ultraviolet light from a light source, and the light-transmitting photomask may be used in a photolithography process using a g-line light with a wavelength of approximately 436 nm, an i-line light with a wavelength of approximately 365 nm, a KrF laser beam with a wavelength of approximately 248 nm, and / or an ArF excimer laser beam with a wavelength of approximately 193 nm from a light source.

[0039] In some embodiments, the first photomask may be an EUV photomask and the second photomask may be an EUV photomask.

[0040] In other embodiments, the first photomask may be an EUV photomask and the second photomask may be a transmissive photomask.

[0041] Semiconductor processes using the plurality of photomasks may be performed on a semiconductor wafer (S20). For example, a first semiconductor process using a first photomask may be performed on the semiconductor wafer (S20a). A second semiconductor process using a second photomask may be performed on the semiconductor wafer (S20b). The second semiconductor process may be performed after the first semiconductor process has been performed. In some embodiments, the first semiconductor process may be the same process as the second semiconductor process. In other embodiments, the first semiconductor process may be a different process than the second semiconductor process.

[0042] The semiconductor wafer may be cut to form a plurality of semiconductor chips (S30). Cutting the semiconductor wafer may include cutting along a scribe track region of the semiconductor wafer to separate chip regions of the semiconductor wafer. The plurality of semiconductor chips may be packaged to form a plurality of semiconductor packages (S40). Each of the plurality of semiconductor packages may be configured as an electronic component (e.g., 1002, 1003a, 1003b, or 1004 of Fig. 15) in different systems (e.g. 1000 from Fig. 15). Such a system will be described later with reference to Fig. 15 described.

[0043] The semiconductor processes (S20) using the plurality of photomasks may include performing a photolithography process. Hereinafter, a photolithography process for manufacturing a semiconductor device according to an embodiment will be described with reference to Fig. 3 and 4A to 4C.

[0044] Fig. 3 is a process flow diagram schematically illustrating a photolithography process for manufacturing a semiconductor device according to an embodiment, and Fig. 4A to 4C are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0045] Referring to Fig. 3, Fig. 4A, Fig. 4B and Fig. 4C, a semiconductor wafer 100 including a photoresist layer 120 may be loaded into a photolithography processing device (S 110). The photoresist layer 120 may be spin-coated on a surface of the semiconductor wafer 100. The semiconductor wafer 100 may include a semiconductor substrate 105, a lower layer 109 on the semiconductor substrate 105, and the photoresist layer 120 coated on the lower layer 109.

[0046] In some embodiments, when the photolithography process device is the EUV photolithography process device 1 as shown in Fig. 1, a thickness of the photoresist layer may be approximately 200 nm to approximately 600 nm. However, the thickness of the photoresist layer is not limited to a thickness of approximately 200 nm to approximately 600 nm, and in some embodiments, the thickness of the photoresist layer may be less than approximately 200 nm or greater than approximately 600 nm.

[0047] A one-shot process, including wafer alignment and light irradiation by a light source, may be performed sequentially a plurality of times to expose the photoresist layer 120 of the semiconductor wafer 100 (S120). The semiconductor wafer 100 may be unloaded from the photolithography device (S130). The exposed photoresist layer 120 of the semiconductor wafer 100 may be developed to form a photoresist pattern 120a (S140).

[0048] An etching process using the photoresist pattern 120a as an etching mask may be performed. The lower layer 109 of the semiconductor wafer 100 may be etched by the etching process using the photoresist pattern 120a as an etching mask to form lower patterns 110 including an alignment mark 110a, a test element pattern 110t, a guard ring pattern 110g, and circuit patterns 110c (S150). For example, the alignment mark 110a and the test element pattern 110t may be formed in a scribe track region 100_S of the semiconductor wafer 100, and the guard ring pattern 110g and the circuit patterns 110c may be formed in a chip region 100_C of the semiconductor wafer 100.

[0049] In some embodiments, the guard ring pattern 110g may be omitted. In other words, in some embodiments, the lower patterns 110 may omit the guard ring pattern 110g. A semiconductor wafer 100a including the photoresist pattern 120a and the lower patterns 110 may be formed.

[0050] Subsequently, the photoresist pattern 120a may be removed (S160). Thus, after the photoresist pattern 120a has been removed, a semiconductor wafer 100b containing the lower patterns 110 may be formed as shown in Fig. 4C shown.

[0051] With reference to Fig. 5, an extreme ultraviolet (EUV) photomask for fabricating a semiconductor device according to one embodiment is described.

[0052] Fig. 5 is a cross-sectional view schematically illustrating an extreme ultraviolet (EUV) photomask for manufacturing a semiconductor device according to an embodiment.

[0053] Referring to Fig. 5, an extreme ultraviolet (EUV) photomask may include a mask substrate 203, a stacked structure 220 disposed beneath the mask substrate 203, a backside layer 215 disposed upon the stacked structure 220, a capping layer 230 disposed beneath the stacked structure 220, and a plurality of mask patterns 240 disposed beneath the capping layer 230. For example, the mask substrate 203 may include a first surface 203s1 and a second surface 203s2 that are opposite to each other, the stack structure 220 may be arranged on the first surface 203s1 of the mask substrate 203, the cap layer 230 may be arranged on the stack structure 220, the plurality of mask patterns 240 may be arranged on the cap layer 230, and the backside layer 215 may be in contact with the second surface 203s2 of the mask substrate 203.

[0054] The mask substrate 203 may contain a material (LTEM) with low thermal expansion. For example, the mask substrate 203 may contain a silicon material.

[0055] Stacked structure 220 may include a silicon layer 222 and a metal layer 224 that are alternately and repeatedly stacked. Metal layer 224 may be a molybdenum layer. Cap layer 230 may be a ruthenium layer.

[0056] Each of the mask patterns 240 may include a first mask pattern 242 contacting the cap layer 230 and a second mask pattern 244 beneath the first mask pattern 242. The first mask pattern 242 may be an absorber containing a TaBN material. The second mask pattern 244 may be an anti-reflection layer containing a lawrencium material.

[0057] In some embodiments, the second mask pattern 244 may be omitted.

[0058] In embodiments, the terms “on” or “above” and “below” may be used to indicate a vertical positional relationship of components based on the cross-sectional view of Fig. 5, and the terms “on” or “over” and “below” may be replaced with the terms “below” and “on” or “over” or may be replaced with the terms “first” and “second”, depending on a direction of view.

[0059] The extreme ultraviolet (EUV) photomask 200 may include a mask layout region 205 and a boundary region 210 surrounding the mask layout region 205. The mask layout region 205 may be a region in which a mask layout pattern of the extreme ultraviolet (EUV) photomask 200 is formed. The boundary region 210 may be a region surrounding the mask layout region 205 and may be a region in which the mask layout pattern is not formed. As shown in Fig. 1, the second light 50b incident on the photomask 200 and the third light 50c reflected from the photomask may be inclined about an axis perpendicular to a surface of the photomask 200.

[0060] The mask layout region 205 of the extreme ultraviolet (EUV) photomask 200 may include a mask chip region 205_C and a mask scribe track region 205_S surrounding the mask chip region 205_C.

[0061] In embodiments, the mask chip region 205_C may be referred to as an “extreme ultraviolet (EUV) mask chip region” and the mask scribe track region 205_S may be referred to as an “extreme ultraviolet (EUV) mask scribe track region.”

[0062] The mask patterns 240 may include a mask circuit layout pattern 240c formed in the mask chip region 205_C, a guard ring layout pattern 240g disposed in a portion of the mask chip region 205_C adjacent to the mask scribe track region 205_S, a mask alignment layout pattern 240a and test layout pattern 240t formed in the mask scribe track region 205_S, and a boundary mask pattern 240d disposed in the boundary region 210. In some embodiments, the mask patterns 240 may omit the guard ring layout pattern 240g.

[0063] In some embodiments, an angle 55 between the second light 50b incident on the photomask 200 and an axis perpendicular to a surface of the photomask 200 may be about 5 degrees to about 10 degrees.

[0064] In other embodiments, angle 55 may be approximately 5 degrees to approximately 7 degrees. For example, in further embodiments, angle 55 may be approximately 6 degrees.

[0065] A first photomask and a second photomask for manufacturing a semiconductor device according to an embodiment are described with reference to Fig. 6A and Fig. 6B.

[0066] Fig. 6A is a plan view schematically illustrating a first photomask for manufacturing a semiconductor device according to an embodiment, and Fig. 6B is a plan view schematically illustrating a second photomask for manufacturing a semiconductor device according to an embodiment.

[0067] Referring to Fig. 6A, a first photomask 200a may be an EUV photomask according to some embodiments. The first photomask 200a may include a mask layout region 205a and a boundary region 210a surrounding the mask layout region 205a.

[0068] The mask layout area 205a may include "N" mask chip areas 205_Ca and a first mask scribe track area 205_Sa surrounding each of the "N" mask chip areas 205_Ca. "N" may be a natural number of 2 or more. For example, the mask chip areas 205_Ca may include a first mask chip area 205_C1a and a second mask chip area 205_C2a.

[0069] The mask chip areas 205_Ca and the first mask scribe track area 205_Sa can be formed on the Fig. 5 shown first surface 203s1 of the mask substrate 203.

[0070] In each of “N” mask chip areas 205_Ca (ie both in the first mask chip area 205_C1a and in the second mask chip area 205_C2a), the Fig. 5 shown mask circuit layout pattern 240c.

[0071] The Fig. The test layout pattern 240t shown in Figure 5 may be arranged in the first mask scribe track area 205_Sa. The test layout pattern 240t may be a test layout pattern of a test element group.

[0072] A first mask alignment mark area M_AL_La and a second mask alignment mark area M_AL_Lb, which are spaced apart from each other, may be arranged in the first mask scribe track area 205_Sa.

[0073] The mask layout region 205a may have a first side S1 and a second side S2 that are opposite to each other. In this case, the first side S1 and the second side S2 of the mask layout region 205a may also be described as a first side S1 and a second side S2 of the first mask scribe track region 205_Sa. Thus, the first and second sides S1 and S2 of the mask layout region 205a may be replaced with, or described as, the first and second sides S1 and S2 of the first mask scribe track region 205_Sa.

[0074] The first mask alignment marking area M_AL_La may be adjacent to a central area of ​​the first side S1 of the mask layout area 205a, and the second mask alignment marking area M_AL_Lb may be adjacent to a central area of ​​the second side S2 of the mask layout area 205a. For example, in the Fig. 6A, the first mask alignment mark area M_AL_La may be arranged to be adjacent to a lower edge, e.g., the center region of the first side S1 of the mask layout area 205a, and the second mask alignment mark area M_AL_Lb may be arranged to be adjacent to an upper edge, e.g., the center region of the second side S2 of the mask layout area 205a.

[0075] A first mask alignment layout pattern 240a_1 may be arranged in the first mask alignment marking area M_AL_La, and a second mask alignment layout pattern 240a_2 may be arranged in the second mask alignment marking area M_AL_Lb. Thus, the Fig. 5 may include the first and second mask alignment layout patterns 240a_1 and 240a_2 arranged in the first mask scribe track area 205_Sa.

[0076] In some embodiments, the first mask alignment layout pattern 240a_1 may have the same shape as a shape of the second mask alignment layout pattern 240a_2. That is, the first mask alignment layout pattern 240a_1 and the second mask alignment layout pattern 240a_2 may have the same shape. For example, the first mask alignment layout pattern 240a_1 and the second mask alignment layout pattern 240a_2 may be line patterns that are parallel to each other. In this case, the line patterns may be referred to as bar patterns.The line patterns of the first mask alignment layout pattern 240a_1 and the second mask alignment layout pattern 240a_2 may extend in a first direction Y, and the first mask alignment mark region M_AL_La including the first mask alignment layout pattern 240a_1 and the second mask alignment mark region M_AL_Lb including the second mask alignment layout pattern 240a_2 may be spaced apart from each other in the first direction Y. The first direction Y may be perpendicular to the first and second sides S1 and S2 of the first mask scribe track region 205_Sa.

[0077] In some embodiments, the first mask alignment layout pattern 240a_1 and the second mask alignment layout pattern 240a_2 may have different shapes and / or different numbers of line patterns.

[0078] Referring to Fig. 6B, a second photomask 200b may be an EUV photomask or a transmissive photomask, according to some embodiments.

[0079] The second photomask 200b may include a mask layout area 205b and a border area 210b surrounding the mask layout area 205b.

[0080] The mask layout area 205b may include “M” mask chip areas 205_Cb and a second mask scribe track area 205_Sb surrounding each of the “M” mask chip areas 205_Cb. “M” may be twice the Fig. 6A. That is, "M" may be two times "N" such that M=2*N. For example, "N" may be 2 and "M" may be 4. For example, the mask chip regions 205_Cb may include a first mask chip region 205_C1b, a second mask chip region 205_C2b, a third mask chip region 205_C3b, and a fourth mask chip region 205_C4b.

[0081] The mask layout region 205b may include an upper mask layout region 205_b1 and a lower mask layout region 205_b2 having a mirror-symmetric structure. For example, the upper mask layout region 205_b1 may include "N" mask chip regions 205_Cb, for example, the first mask chip region 205_C1b and the second mask chip region 205_C2b, and the lower mask layout region 205_b2 may include "N" mask chip regions 205_Cb, for example, the third mask chip region 205_C3b and the fourth mask chip region 205_Cb4.

[0082] A central mask alignment mark area M_AL_U may be arranged in a central area of ​​the mask layout area 205b.

[0083] In the as in Fig. 6B, a horizontal axis Cx passing through a center of the mask layout area 205b may pass through a central portion of the central mask alignment mark area M_AL_U.

[0084] An upper mask alignment layout pattern 240b may be arranged in the middle mask alignment mark area M_AL_U.

[0085] In some embodiments, the upper mask alignment layout pattern 240b may be line patterns that are parallel to each other or bar patterns that are parallel to each other.

[0086] An example of a semiconductor wafer WF for manufacturing a semiconductor device according to some embodiments is described with reference to Fig. 7 and Fig. 9 shown.

[0087] Fig. 7 is a plan view schematically illustrating a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment, and Fig. 8 is a plan view showing a firing range under the Fig. 7 schematically shows the majority of firing areas.

[0088] Referring to Fig. 7 and Fig. 8, a semiconductor wafer WF may include a plurality of shot regions SA arranged in a row direction (+X direction or -X direction) and a column direction (+Y direction or -Y direction) according to some embodiments. For example, Fig. 7 firing ranges SA1-SA6. As in Fig. As shown in Figure 8, each shot area SA may include a plurality of wafer chip areas. For example, one shot area SA among the plurality of shot areas SA may include a plurality of wafer chip areas WF_C1, WF_C2, WF_C3, and WF_C4, and a wafer scribe track area WF_SL surrounding each of the plurality of wafer chip areas WF_C1, WF_C2, WF_C3, and WF_C4.

[0089] As in Fig. As shown in Figure 7, the plurality of firing areas SA may include a first firing area SA1, a second firing area SA2, and a third firing area SA3 arranged sequentially in the +X direction. The plurality of firing areas SA may further include a sixth firing area SA6 arranged adjacent to the first firing area SA1 in the -Y direction, a fifth firing area SA5 arranged adjacent to the second firing area SA2 in the -Y direction, and a fourth firing area SA4 arranged adjacent to the third firing area SA3 in the -Y direction.

[0090] The number of the plurality of wafer chip regions WF_C1, WF_C2, WF_C3 and WF_C4 may be the same as the “M” mask chip regions 205_Cb, as shown in Fig. 6B. Thus, the majority of wafer chip areas WF_C1, WF_C2, WF_C3, and WF_C4 may be "M."

[0091] As in Fig. As shown in Figure 8, the single-shot area SA may include a wafer alignment area WF_AL located in a central portion of the single-shot area SA. The wafer alignment area WF_AL may be located in a wafer scribe track area WF_SL.

[0092] The operation S20a for performing a first semiconductor process using a first photomask on a first semiconductor wafer described with reference to Fig. 2C is shown, with reference to Fig. 9A and Fig. 9B together with Fig. 4A and Fig. 6A.

[0093] Fig. 9A and Fig. 9B are plan views illustrating exposing a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment by a first photolithography process.

[0094] Referring to Fig. 9A and Fig. 9B together with Fig. 2C, Fig. 4A and Fig. 6A, the semiconductor wafer may be used in operation S20a to perform the first semiconductor process using the first photomask on the wafer with reference to Fig. 2C may be a semiconductor wafer WFa having the majority of shot areas SA as shown in Fig. 7 and Fig. 8 may include the semiconductor wafer WF. For example, in the semiconductor wafer WFa, each of the plurality of shot areas SA may include the plurality of wafer chip areas WF_C1, WF_C2, WF_C3 and WF_C4 as shown in Fig. 8, and the wafer scribe track area WF_SL surrounding each of the plurality of wafer chip areas WF_C1, WF_C2, WF_C3 and WF_C4.

[0095] The semiconductor wafer WFa can have the first photoresist layer (e.g. 120 of Fig. 4A) formed on a surface thereof. The first photomask may be one of the photomasks described with reference to Fig. 5 and Fig. 6A shown first photomasks (200 from Fig. 5 and Fig. 200a from Fig. 6A).

[0096] The operation S20a for performing the first semiconductor process using the first photomask (e.g., 200 of Fig. 5 and Fig. 200a from Fig. 6A) on the semiconductor wafer WFa may include S120 sequentially performing a shooting process including wafer alignment and light emission by a light source a plurality of times to form the photoresist layer (120 of Fig. 4A) of the Fig. 3 and 4A to 4C.

[0097] In operation S20a for performing the first semiconductor process using the first photomask (200 of Fig. 5 and Fig. 200a from Fig. 6A) on the semiconductor wafer WFa, the one-shot process can be performed with respect to any one-shot region of the semiconductor wafer WFa, for example, half of the first shot region SA1. For example, a first shot process can cover approximately half of the photoresist layer (120 of Fig. 4A) in the first shot region SA1. In this case, half of the first shot region SA1 may be one half of the "M" wafer chip regions WF_C1, WF_C2, WF_C3, and WF_C4 in the first shot region SA1 formed by a first shot process, e.g., a region containing "N" wafer chip regions.

[0098] In operation S20a for performing the first semiconductor process using the first photomask (200 of Fig. 5 and Fig. 200a from Fig. 6A) on the semiconductor wafer WFa, a process for exposing the photoresist layer (120 of Fig. 4A) of firing areas arranged in any row direction (+X direction), for example the first to third firing areas SA1, SA2 and SA3 (see Fig. 7), described.

[0099] After performing the first shot process twice for exposing an upper region of the first shot region SA1, for example, wafer chip regions WF_C1 and WF_C2 of the plurality of wafer chip regions WF_C1, WF_C2, WF_C3 and WF_C4 in one shot region, the Fig. 1 wafer holder shown (150 from Fig. 1) can be used to move the semiconductor wafer WFa in the -X direction such that the second shot area SA2 can be moved to a position where the first shot area SA1 was located. After aligning the semiconductor wafer WFa, the first shot process can be performed twice on an upper area of ​​the second shot area SA2 to expose WF_C1 and WF_C2 of the second shot area SA2. The wafer holder can then be used to move the semiconductor wafer WFa again in the -X direction such that the third shot area SA3 can be moved to a position where the first shot area SA1 was located. After aligning the semiconductor wafer WFa, the first shot process can be performed twice on an upper area of ​​the third shot area SA3 to expose WF_C1 and WF_C2 of the third shot area SA3.After sequentially performing the first shot process at each of the plurality of shot areas arranged in the +X direction (in this example, SA1-SA3), the semiconductor wafer WFa can be removed using the wafer holder (150 of FIG. Fig. 1) are moved in the +Y direction, and a remaining half of the third shot area SA3, a remaining half of the second shot area SA2, and a remaining half of the first shot area SA1 can be sequentially exposed in a similar manner while moving the semiconductor wafer WFa in the -X direction. In other words, WF_C1, WF_C2 from SA1, WF_C1, WF_C2 from SA2, WF_C1, WF_C2 from SA3, WF_C3, WF_C4 from SA3, WF_C3, WF_C4 from SA2, and WF_C3, WF_C4 from SA1 can be exposed in this order. It should be noted that in the example of Fig. 9A and Fig. 9B, the upper half of the shot areas SA is exposed first, and then the lower half of the shot areas SA is exposed. However, this is merely an example, and in other embodiments, the lower half of the shot areas SA may be exposed first, and then the upper half thereof may be exposed.

[0100] In this case, the upper region of the firing area may denote a half planar region of the firing area located in the +Y direction in the plan view, and the lower region of the firing area may denote a half planar region of the firing area located in the -Y direction in the plan view.

[0101] Two shot processes can be performed in any one-shot area of ​​the semiconductor wafer WFa, for example, the first shot area SA1, to deposit the photoresist layer (120 of Fig. 4A) of the first shot area SA1.

[0102] In some embodiments, “N” wafer die areas formed by transferring in Fig. 6 shown “N” mask chip areas 205_Ca into the upper area of ​​the first shot area SA1, for example wafer chip areas designated by WF_C1 and WF_C2, as shown in Fig. 8, and a first wafer scribe track area WF_SL_1 formed by transferring the Fig. 6A. Similarly, the “N” wafer chip regions formed by transferring the Fig. 6A into the lower region of the first shot region SA1, for example, wafer chip regions designated by WF_C3 and WF_C4, as shown in Fig. 8, and a second wafer scribe track area WF_SL_2, which is formed by transferring the Fig. 6A. Thus, the first shot region SA1 may include a wafer scribe track region WF_SLa including the first and second wafer scribe track regions WF_SL_1 and WF_SL_2, and the wafer chip regions (WF_C1a, WF_C2a, WF_C3a, and WF_C4a of Fig. 9B), which are formed as two times “N”, e.g. as many as “M”, as in Fig. 6B shown.

[0103] Each shot area of ​​the semiconductor wafer WFa, for example, the first shot area SA1, may have a first wafer alignment mark area WF_AL_1 and a second wafer alignment mark area WF_AL_2 formed by transferring the first mask alignment mark area M_AL_La and the second mask alignment mark area M_AL_Lb formed in Fig. 6A are formed by the shooting process performed on the upper half of the wafer chip regions of the first shooting region SA1, and may include a third wafer alignment mark region WF_AL_3 and a fourth wafer alignment mark region WF_AL_4 formed by transferring the first mask alignment mark region M_AL_La and the second mask alignment mark region M_AL_Lb shown in Fig. 6A are formed by the shooting process performed on the lower half of the wafer chip regions of the first shooting region SA1.

[0104] The first wafer alignment mark region WF_AL_1 and the second wafer alignment mark region WF_AL_2 may be spaced apart from each other in the +Y direction. The third wafer alignment mark region WF_AL_3 and the fourth wafer alignment mark region WF_AL_4 may be spaced apart from each other in the +Y direction. Within the first shot area SA1, the second and third wafer alignment mark regions WF_AL_2 and WF_AL_3 may be adjacent to each other or overlap each other to form a lower middle wafer alignment mark region WF_ALa.

[0105] In the first shot area SA1, the first wafer alignment mark area WF_AL_1 may be arranged adjacent to a central portion of an upper edge of the first shot area SA1, and the fourth wafer alignment mark area WF_AL_4 may be arranged adjacent to a central portion of a lower edge of the first shot area SA1. The lower central wafer alignment mark area WF_ALa may be arranged in a central portion between the first wafer alignment mark area WF_AL_1 and the fourth wafer alignment mark area WF_AL_4.

[0106] The process for exposing the photoresist layer (120 from Fig. 4A) of the firing areas arranged in any row direction (+X direction), for example the first to third firing areas SA1, SA2 and SA3 (see Fig. 7), has been described. However, it is understood that a similar method for exposing the photoresist layer (120 of Fig. 4A) of the shot regions arranged in other rows of the semiconductor wafer WFa. For example, a similar method can be used to expose the sixth to fourth shot regions SA6, SA5, and SA4, as well as other rows.

[0107] Next, operation S20b for performing a second semiconductor process using a second photomask on a semiconductor wafer described with reference to Fig. 2C, with reference to Fig. 10A and Fig. 10B together with Fig. 4A and Fig. 6B.

[0108] Fig. 10A and Fig. 10B are plan views illustrating exposing a plurality of shot regions of a semiconductor wafer for manufacturing a semiconductor device according to an embodiment by a second photolithography process.

[0109] Referring to Fig. 10A and Fig. 10B together with Fig. 2C, Fig. 4A and Fig. 6B, the semiconductor wafer may be used in operation S20b to perform the second semiconductor process using the second photomask on the wafer with reference to Fig. 2C may be a semiconductor wafer WFb in which other layers for performing the second semiconductor process are formed on the semiconductor wafer shown in Fig. 9A and Fig. 9B after the operation S20a for performing the first semiconductor process using the first photomask (200a of Fig. 6A). For example, the semiconductor wafer WFb in operation S20b for performing the second semiconductor process using the second photomask may be a wafer on which a second photoresist layer is formed on the semiconductor wafer WFa formed as shown in Fig. 9A and Fig. 9B. In this case, the second photoresist layer may be formed as the photoresist layer 120 of Fig. 4A can be understood.

[0110] In operation S20b for performing the second semiconductor process using the second photomask on the semiconductor device with reference to Fig. 2C, the second photomask can be the one shown in Fig. 6B shown second photomask (200b in Fig. 6B). In some embodiments, the second photomask (200b of Fig. 6B) the photomask 200, as in Fig. 5. In another example, the second photomask (200b of Fig. 6B) be a translucent photomask.

[0111] The semiconductor wafer WFb may include the plurality of shot regions SA including the plurality of wafer chip regions WF_C1, WF_C2, WF_C3 and WF_C4 and the wafer scribe track region WF_SL, identical to the semiconductor wafer WF in Fig. 7 and Fig. 8.

[0112] In operation S20b for performing the second semiconductor process using the second photomask (200b in Fig. 6B) on the semiconductor wafer WFb, a second shot process may be performed in a shot region of the semiconductor wafer WFb, for example, in an entire area of ​​the first shot region SA1. For example, in the second shot process, the photoresist layer (120 of Fig. 4A) of the first shot area SA1 is fully exposed. In this case, the entire area of ​​the first shot area SA1 may be an area comprising “M” wafer chip areas WF_C1, WF_C2, WF_C3 and WF_C4, as shown in Fig. 8, contains.

[0113] In operation S20b for performing the second semiconductor process using the second photomask (200b in Fig. 6B) on the semiconductor wafer WFb, a process for exposing the photoresist layer (120 of Fig. 4A) of firing areas arranged in any row direction (+X direction), for example the first to third firing areas SA1, SA2 and SA3.

[0114] In operation S20b for performing the second semiconductor process using the second photomask (200b in Fig. 6B) on the semiconductor wafer WFb, the Fig. 1 wafer holder shown (150 from Fig. 1) After performing the second shot process for exposing the entire area of ​​the first shot area SA1, for example, all of the plurality of wafer chip areas WF_C1, WF_C2, WF_C3, and WF_C4 in the first shot area SA1 simultaneously, the second shot area SA2 can be moved to a position where the first shot area SA1 was located, and after aligning the semiconductor wafer WFb, the second shot process can be performed once on the entire area of ​​the second shot area SA2 to expose all of the plurality of wafer chip areas WF_C1, WF_C2, WF_C3, and WF_C4 in the second shot area SA2 simultaneously. Fig. 1 wafer holder shown (150 from Fig. 1) can be used to move the semiconductor wafer WFb again in the -X direction, the third shot region SA3 can be moved to a position where the second shot region SA2 was located, and after aligning the semiconductor wafer WFb, the second shot process can be performed once on the entire area of ​​the third shot region SA3 to simultaneously expose all of the plurality of wafer chip regions WF_C1, WF_C2, WF_C3, and WF_C4 in the third shot region SA3. Thus, the second shot process performed once can be sequentially performed on each of the shot regions arranged in the +X direction. Thus, the photoresist layer (120 of Fig. 4A) of the first to third shot areas SA1, SA2 and SA3 are exposed sequentially.

[0115] In the same way as the photoresist layer (120 in Fig. 4A) of the first to third shot areas SA1, SA2 and SA3 are exposed sequentially, the wafer holder (150 from Fig. 1) are used to move the semiconductor wafer WFb in the +Y direction, the fourth shot area SA4, the fifth shot area SA5, and the sixth shot area SA6 can be sequentially exposed while sequentially moving the semiconductor wafer WFb in the -X direction. The first shot area SA1 can expose the wafer scribe track area WF_SLb and the wafer chip areas WF_C1b, WF_C2b, WF_C3b, and WF_C4b, which are formed in the same amount as "M", as shown in Fig. 6B shown.

[0116] Each shot area of ​​the semiconductor wafer WFb, for example the first shot area SA1, may include an upper middle wafer alignment mark area WF_ALb formed by transferring the Fig. 6B is formed by the second shot process. In the first shot region SA1, the upper middle wafer alignment mark region WF_ALb may be arranged in the middle portion of the first shot region SA1.

[0117] As in Fig. 9A and Fig. 9B, in the first shot area SA1 of the semiconductor wafer WFa, the second and third wafer alignment mark areas WF_AL_2 and WF_AL_3 may be adjacent to each other or overlap each other to form a lower middle wafer alignment mark area WF_ALa. An example of the lower middle wafer alignment mark area WF_ALa including the second and third wafer alignment mark areas WF_AL_2 and WF_AL_3 adjacent to each other will be described below with reference to Fig. 11 shown.

[0118] Referring to Fig. 11, the lower middle wafer alignment mark area WF_ALa of the semiconductor wafer WFa, as shown in Fig. 9B, a wafer alignment mark ALK_L including a first lower wafer alignment mark ALK_La in the second wafer alignment mark region WF_AL_2 formed by the first shot process performed on the upper half of the wafer die regions of the one-shot region, and a second lower wafer alignment mark ALK_Lb in the third wafer alignment mark region WF_AL_3 formed by the first shot process performed on the lower half of the wafer die regions of the one-shot region.

[0119] In some embodiments, the first lower wafer alignment mark ALK_La and the second lower wafer alignment mark ALK_Lb may have a symmetric structure with respect to a central horizontal axis Cx.

[0120] The first lower wafer alignment mark ALK_La and the second lower wafer alignment mark ALK_Lb may be alignment patterns having a linear shape or a bar shape and extending in the +Y direction.

[0121] In some embodiments, the first lower wafer alignment mark ALK_La may have a shape that extends from the second lower wafer alignment mark ALK_Lb in the +Y direction. Thus, the lower wafer alignment mark ALK_L may be an alignment pattern with a linear shape or a bar shape.

[0122] Next, each with reference to Fig. 12A and Fig. 12F, various modified examples of the lower wafer alignment mark ALK_L are described, which includes patterns of the first lower wafer alignment mark ALK_La formed by the previous first shot process and patterns of the second lower wafer alignment mark ALK_Lb formed by the last first shot process, as in Fig. 11 shown.

[0123] In a modified example, referring to Fig. 12A, a lower wafer alignment mark ALK_L1 in the modified example may include alignment patterns of a first lower wafer alignment mark ALK_La1 and alignment patterns of a second lower wafer alignment mark ALK_Lb1, both of which are continuous in the +Y direction, but in which central axes Cz1a and Cz1b are not aligned in the +Y direction. For example, the central axes Cz1a of the alignment patterns of the first lower wafer alignment mark ALK_La1 in the +Y direction and the central axes Cz1b of the alignment patterns of the second lower wafer alignment mark ALK_Lb1 in the +Y direction, which are adjacent to each other in the +Y direction, may not be aligned.The alignment patterns of the first lower wafer alignment mark ALK_La1 and the alignment patterns of the second lower wafer alignment mark ALK_Lb1 may have a linear shape or a bar shape, each extending in the +Y direction.

[0124] In a modified example, referring to Fig. 12B, a lower wafer alignment mark ALK_L2 in the modified example may include alignment patterns of a first lower wafer alignment mark ALK_La2 and alignment patterns of a second lower wafer alignment mark ALK_Lb2 that are adjacent to each other in the +Y direction but spaced apart from each other in the +Y direction. Thus, a lower middle wafer alignment mark region WF_ALaa including the lower wafer alignment mark ALK_L2 may include a second wafer alignment mark region WF_AL_2a including the first lower wafer alignment mark ALK_La2, and a third wafer alignment mark region WF_AL_3a including the second wafer alignment mark ALK_Lb2.

[0125] A central axis Cz1a of each of the alignment patterns of the first lower wafer alignment mark ALK_La2 and a central axis Cz1b of each of the alignment patterns of the second lower wafer alignment mark ALK_Lb2 may not be aligned. However, embodiments are not limited to this. For example, a central axis Cz1a of each of the alignment patterns of the first lower wafer alignment mark ALK_La2 and a central axis CZ1b of each of the alignment patterns of the second lower wafer alignment mark ALK_Lb2 may be aligned in the +Y direction, but may be spaced apart from each other in the +Y direction. The alignment patterns of the first lower wafer alignment mark ALK_La2 and the alignment patterns of the second lower wafer alignment mark ALK_Lb2 may have a linear shape or a bar shape, each extending in the +Y direction.

[0126] In a modified example, referring to Fig. 12C, a lower wafer alignment mark ALK_L3 in the modified example may include alignment patterns of a first lower wafer alignment mark ALK_La3 and alignment patterns of a second lower wafer alignment mark ALK_Lb3, which include a region OV that partially overlap each other in the +Y direction. Thus, a lower middle wafer alignment mark region WF_ALab including the lower wafer alignment mark ALK_L3 may include a second wafer alignment mark region WF_AL_2b including the first lower wafer alignment mark ALK_La3, and a third wafer alignment mark region WF_AL_3b including the second lower wafer alignment mark ALK_Lb3.

[0127] A central axis Cz1a of each of the alignment patterns of the first lower wafer alignment mark ALK_La3 and a central axis Cz1b of each of the alignment patterns of the second lower wafer alignment mark ALK_Lb3 may not be aligned. However, embodiments are not limited to this. For example, a central axis Cz1a of each of the alignment patterns of the first lower wafer alignment mark ALK_La3 and a central axis Cz1b of each of the alignment patterns of the second lower wafer alignment mark ALK_Lb3 may be aligned in the +Y direction, but may include the region OV that partially overlaps each other in the +Y direction. The alignment patterns of the first lower wafer alignment mark ALK_La3 and the alignment patterns of the second lower wafer alignment mark ALK_Lb3 may have a linear shape or a bar shape, each extending in the +Y direction.

[0128] In a modified example, referring to Fig. 12D, a lower wafer alignment mark ALK_L4 in the modified example may include patterns of a first lower wafer alignment mark ALK_La4 and patterns of a second lower wafer alignment mark ALK_Lb4 arranged alternately and repeatedly in the +X direction. Thus, a lower middle wafer alignment mark region WF_ALac including the lower wafer alignment mark ALK_L4 may be provided. In this case, the second wafer alignment mark region WF_AL_2 and the third wafer alignment mark region WF_AL_3 may be arranged as shown in Fig. 11, overlap each other to form the lower middle wafer alignment mark area WF_ALac.

[0129] The patterns of the first lower wafer alignment mark ALK_La4 and the patterns of the second lower wafer alignment mark ALK_Lb4 may have a linear shape or a bar shape, each extending in the +Y direction.

[0130] In a modified example, referring to Fig. 12E, a lower wafer alignment mark ALK_L5 in the modified example may include patterns of a first lower wafer alignment mark ALK_La5 and patterns of a second lower wafer alignment mark ALK_L5b that are alternately arranged in the +X direction, but have end portions that are not aligned in the +X direction. Thus, a lower middle wafer alignment mark region WF_ALad that includes the lower wafer alignment mark ALK_L5 may be provided. In this case, the second wafer alignment mark region WF_AL_2 and the third wafer alignment mark region WF_AL_3 shown in Fig. 11 overlap each other to form the lower middle wafer alignment mark area WF_ALad.

[0131] The patterns of the first lower wafer alignment mark ALK_La5 and the patterns of the second lower wafer alignment mark ALK_Lb5 may have a linear shape or a bar shape, each extending in the +Y direction.

[0132] In a modified example, referring to Fig. 12F, a lower wafer alignment mark ALK_L6 in the modified example may include a first lower wafer alignment mark ALK_La6 and a second lower wafer alignment mark ALK_Lb6 arranged alternately and repeatedly in the +X direction, but having different numbers of patterns. For example, the "x" pattern of the first lower wafer alignment mark ALK_La6 and the "y" pattern of the second lower wafer alignment mark ALK_Lb6 may be arranged alternately and repeatedly in the +X direction. In this case, "x" and "y" may be different positive integers. For example, "x" may be 2 and "y" may be 3. Alternatively, "x" may be 1 and "y" may be 2 or 3. The patterns of the first lower wafer alignment mark ALK_La6 and the patterns of the second lower wafer alignment mark ALK_Lb6 may have a linear shape or a bar shape, each extending in the +Y direction.

[0133] Thus, a lower middle wafer alignment mark area WF_ALae containing the lower wafer alignment mark ALK_L6 may be provided. In this case, the second wafer alignment mark area WF_AL_2 and the third wafer alignment mark area WF_AL_3 shown in Fig. 11 overlap each other to form the lower middle wafer alignment mark area WF_ALae.

[0134] In other embodiments, the second wafer alignment mark area WF_AL_2 and the third wafer alignment mark area WF_AL_3 may include patterns with different sizes and / or different widths.

[0135] Next, as previously with reference to Fig. 10A and Fig. 10B, the upper middle wafer alignment mark area WF_ALb may be arranged in a middle area within the first shot area SA1 of the semiconductor wafer WFb. An example of the upper middle wafer alignment mark area WF_ALb will be described below with reference to Fig. 13 shown.

[0136] Referring to Fig. 13, the upper middle wafer alignment mark area WF_ALb of the semiconductor wafer WFb, as shown in Fig. 10A and Fig. 10B, include an upper wafer alignment mark ALK_U. The upper wafer alignment mark ALK_U may be alignment patterns having a linear shape or a bar shape, each extending in the +Y direction.

[0137] Next, an example of a central wafer alignment mark area WF_AL of a semiconductor wafer WFc according to an embodiment will be described with reference to Fig. 14A and Fig. 14B.

[0138] Fig. 14A may be a top view of an example of a central wafer alignment mark area WF_AL of a semiconductor wafer WFc according to an embodiment, and Fig. 14B is a cross-sectional view showing the section along line II' of Fig. 14A schematically shows.

[0139] Referring to Fig. 14A and Fig. 14B, a middle wafer alignment mark region WF_AL of a semiconductor wafer WFc may include a lower wafer alignment mark ALK_L and an upper wafer alignment mark ALK_U according to one embodiment.

[0140] As with reference to Fig. 11, the lower wafer alignment mark ALK_L in the lower middle wafer alignment mark area (WF_ALa of Fig. 11) be trained. As in Fig. 11, the lower wafer alignment mark ALK_L may include the first lower wafer alignment mark ALK_La and the second lower wafer alignment mark ALK_Lb arranged with the first horizontal axis Cx interposed therebetween.

[0141] In some embodiments, the lower wafer alignment mark ALK_L may be associated with any of the lower wafer alignment marks ALK_L1 to ALK_L6 described with reference to Fig. 12A to 12F.

[0142] The upper wafer alignment mark ALK_U can be formed in the upper middle wafer alignment mark area (WF_ALb of Fig. 13) be trained as described in relation to Fig. 13 shown.

[0143] The lower middle wafer alignment mark area (WF_ALa in Fig. 11) and the upper middle wafer alignment mark area (WF_ALb in Fig. 13) may overlap each other and may be defined as a central wafer alignment mark area WF_AL.

[0144] In some embodiments, the lower wafer alignment mark ALK_L may be formed on a semiconductor substrate 305 of the semiconductor wafer WFc.

[0145] In some embodiments, the upper wafer alignment mark ALK_U may be formed on an insulating layer 330 covering the lower wafer alignment mark ALK_L on the semiconductor substrate 305.

[0146] The lower alignment patterns of the lower wafer alignment mark ALK_L and the upper alignment patterns of the upper wafer alignment mark ALK_U can be arranged alternately in the +X direction. Alignment information can be obtained using the lower alignment patterns of the lower wafer alignment mark ALK_L and the upper alignment patterns of the upper wafer alignment mark ALL_U.

[0147] The lower wafer alignment mark ALK_L and the upper wafer alignment mark ALK_U may provide different pieces of alignment information. For example, the lower wafer alignment mark ALK_L and the upper wafer alignment mark ALK_U may each be used as alignment marks for aligning wafers in an exposure process. Alternatively, the lower wafer alignment mark ALK_L and the upper wafer alignment mark ALK_U may each be used as overlay alignment marks in an exposure process.

[0148] Fig. 15 is a perspective view schematically illustrating a system including a semiconductor package formed by a method of manufacturing a semiconductor device according to an embodiment.

[0149] Referring to Fig.15, an electronic system 1000 may include a main substrate 1001, a controller 1002 mounted on the main substrate 1001, one or more first semiconductor packages 1003a and 1003b, and a second semiconductor package 1004.

[0150] In some embodiments, the one or more first semiconductor packages 1003a and 1003b may include a non-volatile memory device.

[0151] For example, the one or more first semiconductor packages 1003a and 1003b may include a NAND flash memory device.

[0152] In some embodiments, the second semiconductor package 1004 may include a volatile memory device. For example, the second semiconductor package 1004 may include a DRAM device.

[0153] The one or more first semiconductor packages 1003a and 1003b and the second semiconductor package 1004 may be connected to the controller 1002 through wiring patterns 1005 formed on the main substrate 1001.

[0154] The main substrate 1001 may include a connector 1006 including a plurality of pins that may be connected to an external host. The number and arrangement of the plurality of pins in the connector 1006 may vary according to a communication interface between the electronic system 1000 and the external host. In embodiments, the electronic system 1000 may communicate with the external host according to any interface of a Universal Serial Bus (USB), a Peripheral Component Interconnection Express (PCIe), a Serial Advanced Technology Attachment (SATA), an M-Phy for Universal Flash Memory (UFS), or the like.

[0155] In some embodiments, the electronic system 1000 may be powered by power supplied from the external host through the connector 1006. The electronic system 1000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 1002, and the one or more first semiconductor packages 1003a and 1003b.

[0156] The controller 1002 may write data to or read data from the one or more first semiconductor packages 1003a and 1003b and may improve an operating speed of the electronic system 1000.

[0157] The second semiconductor package 1004 may be a buffer memory that reduces a difference in speed between the one or more first semiconductor packages 1003a and 1003b, which may be a data storage space, and the external host. The second semiconductor package 1004 included in the electronic system 1000 may also operate as a cache memory type and may provide a space that temporarily stores data in a control operation of the one or more first semiconductor packages 1003a and 1003b. When the second semiconductor package 1004 is included in the electronic system 1000, the controller 1002 may further include a DRAM controller that controls the second semiconductor package 1004, in addition to a NAND controller that controls the one or more first semiconductor packages 1003a and 1003b.

[0158] In some embodiments, the one or more first semiconductor packages 1003a and 1003b may be formed using the photomask, the photolithography process using the photomask, and the semiconductor process including the photolithography process according to various embodiments described above.

[0159] In some embodiments, the second semiconductor package 1004 may be formed using the photomask, the photolithography process using the photomask, and the semiconductor process including the photolithography process as described above.

[0160] In some embodiments, the controller 1002 may be manufactured using the photomask, the photolithography process using the photomask, and the semiconductor process including the photolithography process according to various embodiments described above.

[0161] According to various embodiments, a photomask, a method of forming the photomask, a photolithography process using the photomask, a semiconductor process using the photolithography process, a method of manufacturing a semiconductor device using the semiconductor process, a semiconductor device formed by the method, and a system including the semiconductor device may be provided.

[0162] According to various embodiments, a method of manufacturing a semiconductor device may be provided using a semiconductor process configured to form one (1) center alignment mark by two (2) shot processes and a semiconductor process configured to form one (1) center alignment mark by one (1) shot process.

[0163] According to various embodiments, a method of manufacturing a semiconductor device may be provided using a first semiconductor process configured to form one (1) center alignment mark by two (2) shot processes and a second semiconductor process configured to form one (1) center alignment mark by one (1) shot process.

[0164] Various advantages and effects of the present inventive concept are not limited to the above description and can be more easily understood in the process of describing specific embodiments.

[0165] Although embodiments have been shown and described above, it will be apparent to one skilled in the art that modifications and variations may be made without departing from the scope defined by the following claims.

Claims

[1] Method comprising: Forming (S10a) a first photomask (200a) including N mask chip regions (205_Ca) and a first mask scribe track region (205_Sa) surrounding each of the N mask chip regions (205_Ca); Forming (S10b) a second photomask (200b) including M mask chip regions (205_Cb) and a second mask scribe track region (205_Sb) surrounding each of the M mask chip regions (205_Cb); Performing (S20a) a first semiconductor process including a first photolithography process using the first photomask (200a) on a semiconductor wafer (WF); and Performing (S20b) a second semiconductor process including a second photolithography process using the second photomask (200b) on the semiconductor wafer (WF), wherein the first photolithography process is an extreme ultraviolet, EUV, photolithography process, the first photomask (200a) is an EUV photomask, N is a natural number of 2 or more, and M = 2 * N, and wherein the semiconductor wafer (WF) has a plurality of shot regions (SA1-SA6), and each of the plurality of shot regions (SA1-SA6) has M wafer chip regions (WF_C1, WF_C2, WF_C3, WF_C4) corresponding to the M mask chip regions (205_Cb), and a wafer scribe track region (WF_SL) surrounding each of the M wafer chip regions (WF_C1, WF_C2, WF_C3, WF_C4). [2] The method of claim 1, wherein the first photolithography process using the first photomask (200a) comprises sequentially performing a first shot process a plurality of times, the first shot process comprising aligning the semiconductor wafer (WF), irradiating light from an EUV light source (30) onto a surface of the semiconductor wafer (WF), and performing the first shot process twice in each of the plurality of shot regions (SA1-SA6) of the semiconductor wafer (WF). [3] The method according to claim 2, wherein performing the first shot process twice in each of the plurality of shot regions (SA1-SA6) of the semiconductor wafer (WF) comprises: performing the first shot process twice in an upper region of a first shot region (SA1) among the plurality of shot regions (SA1-SA6) of the semiconductor wafer (WF), and performing the first shot process twice in a lower area of ​​the first shot area (SA1). [4] The method according to claim 3, wherein, after the first weft process has been performed twice in the upper region of the first weft region (SA1) and before the first weft process has been performed twice in the lower region of the first weft region (SA1), the first weft process is sequentially performed in one or more weft regions adjacent to the first weft region (SA1). [5] The method according to claim 3 or 4, wherein each shot region of the plurality of shot regions (SA1-SA6) of the semiconductor wafer (WF) has a wafer alignment mark region (WF_AL), the wafer alignment mark region (WF_AL) being arranged within the wafer scribe track region (WF_SL). [6] The method according to claim 5, wherein the wafer alignment mark region (WF_AL) comprises alignment patterns of a first lower wafer alignment mark (WF_AL_2) formed by the first shot process performed on the upper region and alignment patterns of a second lower wafer alignment mark (WF_AL_3) formed by the first shot process performed on the lower region. [7] The method according to claim 6, wherein the alignment patterns (ALK_La) of the first lower wafer alignment mark (WF_AL_2) and the alignment patterns (ALK_Lb) of the second lower wafer alignment mark (WF_AL_3) each have a linear shape or a bar shape extending in a first direction. [8] The method according to claim 7, wherein the alignment patterns (ALK_La) of the first lower wafer alignment mark (WF_AL_2) are adjacent to the alignment patterns (ALK_Lb) of the second lower wafer alignment mark (WF_AL_3) in the first direction. [9] The method according to claim 7, wherein the alignment patterns (ALK_La4) of the first lower wafer alignment mark (WF_AL_2) and the alignment patterns (ALK_Lb4) of the second lower wafer alignment mark (WF_AL_3) are alternately and repeatedly arranged in a second direction, the second direction intersecting the first direction. [10] The method according to any one of claims 6 to 9, wherein the second photolithography process using the second photomask (200b) comprises sequentially performing (S20b) a second shooting process a plurality of times, the second shooting process comprising aligning the semiconductor wafer (WF), irradiating light from the EUV light source (30) or a light source having a wavelength longer than extreme ultraviolet light onto the surface of the semiconductor wafer (WF), and performing the first shooting process once in each of the plurality of shooting regions (SA1-SA6) of the semiconductor wafer (WF). [11] The method according to claim 10, wherein the wafer alignment mark area (WF_AL) includes alignment patterns on an upper wafer alignment mark (ALK_U) formed by the second shot process, the first lower wafer alignment mark (WF_AL_2) is formed at a height level which is the same height level as a height level at which the second lower wafer alignment mark (WF_AL_3) is formed, and the upper wafer alignment mark (ALK_U) is formed at a height level that is higher than the height level at which the first and second lower wafer alignment marks (WF_AL_2, WF_AL_3) are formed. [12] Method comprising: Loading a semiconductor wafer (WF) into a wafer holder (150) of an extreme ultraviolet, EUV, photolithography device (1) equipped with an extreme ultraviolet, EUV, photomask (200); in the EUV photolithography device (1), sequentially performing a shooting process a plurality of times, wherein the shooting process comprises aligning the semiconductor wafer (WF) and emitting light (50a-50d) from an extreme ultraviolet, EUV, light source (30) onto the semiconductor wafer (WF); and Loading the semiconductor wafer (WF) from the EUV photolithography device (1), wherein the semiconductor wafer (WF) has a plurality of shot regions (SA1-SA6), each shot region of the plurality of shot regions (SA1-SA6) has an upper shot region formed by one shot process of the shot process performed a plurality of times, and a lower shot region formed by another shot process of the shot process performed a plurality of times, a central region of each shot region (SA1-SA6) has a wafer alignment marking region (WL_AL), the wafer alignment mark region (WL_AL) has alignment patterns of a first wafer alignment mark (WF_AL_2) formed by the one shooting process and alignment patterns of a second wafer alignment mark (WF_AL_3) formed by the further shooting process. [13] The method according to claim 12, wherein the alignment patterns of the first wafer alignment mark (WF_AL_2) and the alignment patterns of the second wafer alignment mark (WF_AL_3) each have a linear shape or a bar shape extending in a first direction, and the alignment patterns of the first wafer alignment mark (WF_AL_2) are repeatedly arranged while being spaced from each other in a second direction intersecting the first direction. [14] The method of claim 13, wherein the alignment patterns (ALK_La) of the first wafer alignment mark (WF_AL-2) are adjacent to the alignment patterns (ALK_Lb) of the second wafer alignment mark (WF_AL_3) in the first direction. [15] The method according to claim 13, wherein the alignment patterns (ALK_La4) of the first wafer alignment mark (WF_AL_2) and the alignment patterns (ALK_Lb4) of the second wafer alignment mark (WF_AL_3) are arranged alternately and repeatedly in the second direction. [16] Extreme ultraviolet (EUV) photomask, comprising: a mask substrate (203) having a first surface (203s1) and a second surface (203s2) opposite to the first surface (203s1); a mask layout area (205a) on the first surface (203s1) of the mask substrate (203); and a boundary region (210a) on the first surface (203s1) of the mask substrate (203) surrounding the mask layout region (205a), wherein the mask layout area (205a) comprises: a plurality of extreme ultraviolet, EUV, mask chip regions (205_Ca) arranged on the first surface (203s1) of the mask substrate (203); and an extreme ultraviolet, EUV, mask scribe track region (205_Sa) arranged on the first surface of the mask substrate (203) and surrounding the plurality of EUV mask chip regions (205_Ca), wherein the EUV mask scribe track region (205_Sa) has a first side (S1) and a second side (S2) opposite the first side (S1), wherein the EUV mask scribe track area (205_Sa) has test layout patterns (240t) and mask alignment layout patterns (240a), and wherein the mask alignment layout patterns (240a) comprise: a first mask alignment layout pattern (M_AL_La) adjacent to a center region on the first side (S1) and a second mask alignment layout pattern (M_AL_Lb) adjacent to a center region on the second side (S2). [17] The extreme ultraviolet (EUV) photomask of claim 16, further comprising: a stack structure (220) arranged on the first surface (203s1) of the mask substrate (203); and Mask patterns (240) arranged on the stack structure (220) and containing an absorber (242), wherein the mask patterns (240) form circuit patterns (240c) of the plurality of extreme ultraviolet, EUV, mask chip regions (205_Ca), the first mask alignment layout pattern (M_AL_La) and the second mask alignment layout pattern (M_AL_Lb). [18] The extreme ultraviolet (EUV) photomask of claim 17, wherein the first and second mask alignment layout patterns (M_AL_La, M_AL_Lb) comprise line patterns (240a_1, 240a_2) extending in a first direction, and wherein the first direction is perpendicular to the first and second sides (S1, S2) of the EUV mask scribe track region (205_Sa). [19] Extreme ultraviolet (EUV) photomask according to claim 17 or 18, further comprising: a back layer (215) contacting the second surface (203s2) of the mask substrate (203); and a cover layer (230) arranged on the stack structure (220), wherein the mask patterns (240) are arranged on the cover layer (230), and the stack structure (220) comprises a silicon layer and a metal layer which are alternately stacked.

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