Structure and method for controlling an electrostatic discharge (ESD) event in a resistor-capacitor circuit

Abstract

Circuit structure comprising: a resistor-capacitor circuit (RC circuit) (110) having a first node (A), a second node (B) separated from the first node (A) by a resistive element (112) and a capacitive element (114), and a third node (C) between the resistive element (112) and the capacitive element (114); a trigger transistor (122) having a pair of source / drain (S / D) terminals connected between the first node (A) and the second node (B) in parallel with the RC circuit (110) and a gate terminal coupled to the third node (C) of the RC circuit (110); a mirror transistor (126) having a pair of S / D terminals coupled between the first node (A) and the second node (B) in parallel with the RC circuit (110), and a gate terminal coupled to the gate terminal of the trigger transistor (122), wherein a current through the pair of S / D terminals of the mirror transistor (126) is smaller than a current through the pair of S / D terminals of the trigger transistor (122); and a snapback device (130) having a gate terminal (T Gate ) for controlling the current flow in the snapback device (130), the snapback device (130) comprising: a P-well (142) having a first N-doped region (146) coupled to one of the first nodes (A), an N-well (144) adjacent to the P-well (142) and having a first P-doped region (148) coupled to the second node (B), wherein a current path from the first node (A) to the second node (B) runs through the snapback device (130) in parallel with the RC circuit (110), and at least one doped region within the P-well (142) or the N-well (144) coupled to a selected one of the pair of S / D terminals of the mirror transistor (126) and the gate terminal (T Gate ) of the snapback device (130), wherein the at least one doped region has a same doping type with respect to the P-well (142) or the N-well (144).

Description

Technical area

[0001] Embodiments of the invention generally relate to electronic circuits. More specifically, various embodiments of the invention provide a circuit structure and method for controlling an electrostatic discharge (ESD) event in a resistor-capacitor circuit. background

[0002] Electrical circuits, including integrated circuits (ICs), may contain elements to protect the device hardware against electrostatic discharge (ESD) voltages that can cause electrical short circuits, dielectric breakdown, and / or other failure modes. Ideally, ESD elements have no effect on device operation until an ESD event is detected by a pin on an IC, where the ESD event acts as a trigger voltage that turns on the ESD components and shunts current through the ESD element into the power or ground supply rails. ESD elements may be without operational purpose until a trigger voltage is applied to the ESD element to activate it. As demands for low leakage and longer battery life continue to increase, the typical current clamp that uses a large FET as the discharge element is often too leaky.Another problem often arises when the large FET is replaced with a snapback device to solve the leakage problem. A snapback device refers to a specific genus of devices in which the current flow, once enabled, can remain enabled even after a signal is applied to a gate terminal of the snapback device (i.e., "latchup"). Conventional configurations for ESD elements and / or other structures have been unable to provide stable trigger voltages while preventing latchup, ensuring that the ESD element is active only during an ESD event.

[0003] The document DE 10 2011 054 700 A1 relates to an ESD protection device and method. The semiconductor device comprises an ESD device region arranged in a semiconductor body; a first device region having a first conductivity type arranged on a second device region having a second conductivity type, the first and second conductivity types differing from one another, the first device region being coupled to a first ESD node and the second device region being arranged in the ESD region; a third device region of the second conductivity type arranged on the second device region; a fourth device region of the first conductivity type adjacent to the second device region, the fourth device region being arranged in the ESD region.a fifth device region of the second conductivity type arranged in the fourth device region, wherein the first device region, the second device region, the fourth device region, and the fifth device region form a controlled semiconductor rectifier (SCR), the fifth device region being coupled to a second ESD node; and a sixth device region of the second conductivity type adjacent to the fourth device region, an interface between the fourth device region and the sixth device region forming a diode junction.

[0004] Document DE 10 2013 112 339 A1 discloses an apparatus and method for active detection, timing, and protection with respect to transient electrical events. A protection circuit may generate a first activation signal in response to a transient electrical stress event via a first and a second node. A blocking circuit is configured to bias the base of a first bipolar driver transistor to slow the discharge of stored base charge of a first bipolar driver transistor, thereby allowing the first bipolar driver transistor to remain activated for a longer period of time than if the base of the first bipolar driver transistor had been biased to the same voltage as the emitter of the first bipolar transistor.

[0005] Document US 5,754,381 A relates to output ESD protection with a high-current-triggered lateral SCR. An output buffer in a CMOS circuit comprises an output pad; a VDD line providing a first supply voltage; a VSS line providing a second supply voltage; a first MOS device connected between the VDD line and the output pad; a second MOS device connected between the VSS line and the output pad; a lateral SCR device connected from the output pad to one of the VDD and VSS lines and connected in parallel with one of the first and second MOS devices; and a bypass diode connected to the other of the VDD and VSS lines and to the lateral SCR device. Summary

[0006] Aspects of the present invention provide a circuit structure comprising: a resistor-capacitor (RC) circuit having a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element; a trigger transistor having a pair of source / drain (S / D) terminals connected between the first node and the second node in parallel with the RC circuit, and a gate terminal coupled to the third node of the RC circuit;a mirror transistor having a pair of S / D terminals connected between the first node and the second node in parallel with the RC circuit, and a gate terminal coupled to the gate terminal of the trigger transistor, wherein a current through the pair of S / D terminals of the mirror transistor is less than a current through the pair of S / D terminals of the trigger transistor;and a snapback device having a gate terminal for controlling current flow in the snapback device, the snapback device comprising a P-well having a first N-doped region coupled to the first node, an N-well adjacent to the P-well and having a first P-doped region coupled to the second node, a current path from the first node to the second node through the snapback device being parallel to the RC circuit, and at least one doped region within the P-well or N-well coupled to a selected one of the pair of S / D terminals of the mirror transistor and defining the gate terminal of the snapback device, the at least one doped region having a same doping type with respect to the P-well or the N-well.

[0007] Further aspects of the present invention provide a method for controlling an electrostatic discharge (ESD) event in a resistor-capacitor (RC) circuit, the method comprising: transmitting an electrostatic discharge (ESD) current through a trigger transistor in parallel with a resistor-capacitor (RC) circuit, the RC circuit comprising a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node coupled to a gate of the trigger transistor between the resistive element and the capacitive element; transmitting a mirrored current through a mirror transistor in parallel with the trigger transistor, the mirror transistor being configured to transmit a current,which is smaller than the transmitted ESD current; and transmitting the mirrored current to a gate terminal of a snapback device electrically connected between the first node and the second node in parallel with the RC circuit to enable current flow from the first node to the second node through the snapback device during the transmission of the mirrored current to the gate terminal. The snapback device comprises a P-well having a first N-doped region coupled to the first node, an N-well adjacent to the P-well and having a first P-doped region coupled to the second node, wherein a current path from the first node to the second node through the snapback device is parallel to the RC circuit, and at least one doped region within the P-well or N-well,which is coupled to a selected one of the pair of S / D terminals of the mirror transistor and defines the gate terminal of the snapback device, wherein the at least one doped region has a same doping type with respect to the P-well or the N-well., Short description of the drawings

[0008] These and other features of this invention will be more readily understood from the detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings which illustrate various embodiments of the invention and in which: Fig. 1 shows a schematic view of a circuit structure for controlling an electrostatic discharge (ESD) event according to embodiments of the invention. Fig. 2 shows an illustrative graph of current versus gate voltage of a snapback device in operation according to embodiments of the invention. Fig. 3 shows a cross-sectional view of a snapback device within a circuit structure according to embodiments of the invention. Fig. 4 shows a cross-sectional view of a snapback device within a circuit structure according to further embodiments of the invention.

[0009] The drawings of the invention are not necessarily to scale. The drawings are intended to illustrate typical aspects of the invention and are therefore not to be considered limiting the scope of the invention. Like reference numerals represent like elements throughout the drawings. Detailed description

[0010] In this description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration certain exemplary embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and that modifications may be made without departing from the spirit and scope of the present teachings. This description, therefore, is illustrative only.

[0011] Embodiments of the invention provide a circuit structure and associated method for controlling an electrostatic discharge (ESD) event that reliably triggers in response to an ESD event without presenting a significant risk of latchup in a snapback device for conducting ESD currents in parallel with a resistor-capacitor (RC) circuit. The RC circuit may include a first node, a second node separated from the first node by a resistive element and a capacitive element, and a third node between the resistive element and the capacitive element. A trigger transistor having a pair of source / drain (S / D) terminals may be connected between the first and second nodes in parallel with the RC circuit, and the gate terminal of the trigger transistor is connected to the third node of the RC circuit.

[0012] When an ESD event occurs, a resulting voltage in the RC circuit allows current to flow through the trigger transistor in parallel with the RC circuit. The circuit comprises a mirror transistor with a gate terminal coupled to the gate terminal of the trigger transistor and source / drain terminals connected in parallel with the RC circuit. However, the mirror transistor can be designed to carry a much lower current than the trigger transistor (e.g., by being much smaller) and can therefore only replicate a portion of the current through the trigger transistor. A snapback device, in particular an electrical element in which current flow between anode and cathode terminals is only possible upon application of a voltage to its gate terminal ("T Gate") is connected to an S / D terminal of the mirror transistor. The anode / cathode terminals of the snapback device are connected in parallel to the RC circuit. By adjusting the ratio between the current of the trigger device and the current of the mirror device, the total amount of current required to trigger the terminal ("I trigger “). This allows the circuit to be electrically controlled with a high I trigger -value to avoid false triggering of the terminal.

[0013] Fig. 1 illustrates a schematic view of a circuit structure (hereinafter simply "structure") 100 according to embodiments of the invention. The structure 100 may be embodied as any type of electronic circuit and, in various embodiments, may be provided in the form of an integrated circuit (IC) or as part of such a structure. The structure 100 may include or otherwise be connected to opposing terminals of a resistor-capacitor (RC) circuit 110, which in various settings is also referred to as an "RC filter" or "RC network." The RC circuit 110 may include many electrically active elements, including multiple resistors, capacitors, diodes, and / or other devices.Regardless of structure or function, the RC circuit 110 can be schematically represented as having two electrical components: a resistive element 112 and a capacitive element 114 connected in series between an input terminal (“V. DD ”), which indicates, for example, a connection to a power supply, and an output connection (“V SS"), indicating, for example, a connection to ground. A first node A may indicate the "high voltage" terminal of the RC circuit 110, and a second node B may indicate the opposite "low voltage" or "ground" terminal of the RC circuit 110. Several features of the structure 100 may be connected in parallel with the RC circuit 110 between nodes A and B, as described herein. A third node C may indicate the junction between the resistive element 112 and the capacitive element 114 within the RC circuit 110. The third node C may be used to control the operation of the structure 100, for example, to respond to electrical current spikes during an ESD event, as described herein. Structure 100 is configured to respond to excessive charges and currents resulting from an ESD event by preventing current flow into active components (e.g., RC circuit 110). The input terminal V.DD can connect an input voltage and / or a signal to the RC circuit 110 via any wiring. The excess charge generated by an ESD event can be discharged via the input terminal V DD be transferred to structure 100.

[0014] The structure 100 may be in the form of a clamp configured to discharge such excess charges via the output terminal V SS from the power supply to ground. It is understood that the designations V DD and V SSfor the inputs and outputs of structure 100 and RC circuit 110 may be interchanged in further implementations. Structure 100 is designed not to operate under non-ESD conditions with voltage fluctuations. In particular, structure 100 remains inactive during turn-on and turn-off operations, where voltages may fluctuate, if these voltage fluctuations are not sufficient to trigger the transistor gate(s) of its components. Structure 100 is therefore designed to selectively permit current flow only upon detection of an ESD event.

[0015] A set of ESD elements 120 may be connected between the first node A and the second node B in parallel with the RC circuit 110, with portions of the ESD elements 120 coupled to the third node C. The ESD elements 120 may be selectively activated during an ESD event by responding to voltages or currents higher than those intended for the RC circuit 110. The ESD elements 120 may prevent current flow from the input terminal VDD to the output terminal VSS until a trigger voltage is applied to a trigger transistor 122 of the ESD element(s) 120. In various other examples, additional circuitry and / or current paths may be arranged between the RC circuit 110 and the ESD elements 120 to further control the circumstances under which the ESD elements 120 become electrically active.

[0016] The ESD elements 120 of structure 100 may include a plurality of transistors, each configured to respond to control the current flow through the ESD elements 120 during an ESD event. A transistor is an electrical component in which current flow between input and output nodes (e.g., source and drain terminals) is controlled by the voltage applied to a third "gate" terminal. The trigger transistor 122 may be coupled at its gate to the third node C of the RC circuit 110, such that an operating current or voltage of the RC circuit 110 controls whether the trigger transistor 122 is on or off. The trigger transistor 122 may be connected to the RC circuit 110 via a first inverter 124 connected in series between the third node C and the gate of the trigger transistor 122. The inverter 124 can convert the voltage at the third node C to the opposite polarity (e.g.from negative to positive or vice versa). The first inverter 124 may also be connected to nodes A, B in parallel with the RC circuit 110 to electrically power its inverting function in the structure 100. The first inverter 124 may operate in tandem with other inverters of the ESD elements 120 to ensure electrical stability and / or intentionally delay the time required for the structure 100 to respond to an ESD event. In further embodiments, the first inverter 124 may be omitted and / or replaced by multiple inverters. In any case, the electrical coupling from the third mode C to the gate of the trigger transistor 122 may cause voltage spikes that activate the trigger transistor 122.

[0017] The gate of trigger transistor 122 may be coupled to the gate terminal of a mirror transistor 126. Mirror transistor 126 may have source and drain terminals coupled between the first node A and the second node B of structure 100 in parallel with trigger transistor 122. Because mirror transistor 126 is coupled at its gate to the gate of trigger transistor 126, it may act as a "current mirror," where the source-drain current in mirror transistor 126 is proportional to the source-drain current in trigger transistor 122 by a fixed multiple. A current mirror refers to any circuit structure configured to copy the current through one device (e.g., the current through trigger transistor 122) in another device by its exact amount or by a factor between zero and one.A resistor 128 may be connected between the first node A and the source or drain terminal of the mirror transistor 126, e.g., to further reduce the voltage at the source or drain of the mirror transistor 126 compared to the voltage level VDD. The mirror transistor 126 may have a substantially lower conduction current than that allowed by the trigger transistor 122, e.g., to reduce the leakage current within active components (e.g., a snapback device 130 discussed herein) of the structure 100 that are coupled to the mirror transistor 126. The mirror transistor 126 may have a source-drain width that is substantially smaller than that of the trigger transistor 122. In such an example, the mirror transistor 126 may carry at most one-tenth of the current in the trigger transistor 122.In further examples, trigger transistor 122 may carry a current of no more than about two hundred milliamperes (mA), while mirror transistor 126 may carry a current of no more than about twenty mA. In another example, the source-drain width of trigger transistor 122 may be about two hundred micrometers (µm), while the source-drain width of mirror transistor 126 may be about ten µm (i.e., about twenty times smaller).

[0018] The source or drain of the mirror transistor 126 may be coupled to the second node B, thereby creating another parallel current path with respect to the RC circuit 110 and the trigger transistor 122. The other source or drain terminal of the mirror transistor 126 may be connected to a gate terminal T Gatethe snapback device 130. Similar to the trigger transistor 122, the ESD element(s) 120 may include at least a second inverter 132 connected between the gate terminal T Gate the snapback device 130 and the mirror transistor 126. The second inverter 132, which may have the same type of inverter as the first inverter 124 and / or a similar structure, may determine the voltage polarity between the gate of the mirror transistor 126 and T Gate of the snapback device 130, e.g., for further stability and / or to protect against false positive ESD voltages. The electrical coupling between the trigger transistor 122 and the mirror transistor 126 itself can act as a third inverter between the first inverter 124 and the second inverter 132, thereby producing a voltage of opposite polarity but smaller magnitude at the gate terminal T Gateof the snapback device 130. As mentioned elsewhere, the second inverter 132 may include multiple additional inverters and / or be omitted entirely in alternative configurations.

[0019] The snapback device 130 may additionally have a cathode terminal T Cat , which is coupled to the first node A, and an anode terminal T An, which is coupled to the second node B in parallel with the RC circuit 110. The term "snapback device" refers to a three-terminal electrical element that defines an electrical path from the cathode terminal to the anode terminal, with a gate terminal in electrical communication with the cathode and anode terminals. Applying a relatively small input current to the gate terminal enables current to flow from the cathode to the anode. A thyristor (SCR) is a commonly used type of snapback device because an SCR can have multiple doped semiconductor regions with different polarity and concentration. An SCR is particularly well suited as the snapback device 130 in the structure 100 because it can be easily integrated into semiconductor materials with other structures / devices formed therein. Other types of elements suitable for forming the snapback device 130 can include, for example,bidirectional thyristors or other thyristor-based protection devices (TSPDs), gas discharge tubes (GDTs), bipolar transistors with avalanche transitions and / or other electrical elements with similar characteristics.

[0020] With brief reference to Fig. Figure 2 is a graph of cathode-anode current (variable I, measured in mA) versus supply voltage (variable V DD , measured in volts (V)) for the snapback device 130 according to an example implementation to better illustrate the behavior of the structure 100. During non-ESD operation of the RC circuit 110, a non-ESD voltage ("V Stable ”) can be applied to the opposite RC circuit 110 without triggering the ESD element(s) 120. In this state, essentially no current can reach the gate terminal T Gateand thus essentially no current flows from the cathode to the anode in the snapback device 130 (ie, the snapback device 130 has a current I off When the supply voltage V DD increases due to an ESD event, the snapback device may allow a current to flow from the cathode to the anode (e.g., the snapback device 130 has a non-zero current I on because it diverts the overflow current from the first node A. A trigger voltage V trigger can indicate the ESD voltage at which the ESD element(s) 120 trigger(s) (ie, the cathode-to-anode current is activated), while I trigger can specify the ESD voltage at which the ESD element(s) 120 trigger(s). If the ESD current V triggerreaches or exceeds, the snapback device 130 returns to a state in which the current flow from cathode to anode is currently enabled (i.e., latchup). In this state, the snapback device 130 would permanently draw a higher current I even in non-ESD operation. latchup Embodiments of the invention avoid or prevent this problem by including the mirror transistor 126 ( Fig. 1). In order for the mirror transistor 126 to supply sufficient current to trigger the snapback device 130 by biasing the gate terminal (TGate), the trigger transistor 122 can be supplied with a significantly larger current. By configuring the circuit 100 for a specific current mirror ratio, the value of the trigger current I triggerFor example, if triggering the snapback device 130 requires a current of 5 mA from the mirror device 126, the trigger device 122 can supply a current of 200 mA, thereby causing I trigger can rise to over 205 mA.

[0021] In the Fig. 1 and Fig. 3, further exemplary subcomponents of the snapback device 130 are discussed. Here, the snapback device 130 may take the form of an SCR. The snapback device 130 may be formed from a substrate 140, for example, comprising one or more semiconductor materials. The substrate 140 may comprise any currently known or later developed semiconductor material, which may include, without limitation, silicon, germanium, silicon carbide, and those formed essentially of one or more III-V compound semiconductors having a composition represented by the formula AI X1 Ga X2 In X3 Ace Y1 PY2 N Y3 Sb Y4 where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, each greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates are II-VI compound semiconductors with the composition Zn A1 CD A2 See B1 The B2 , where A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1+A2+B1+B2=1 (1 is a total molar amount). All or part of the substrate 140 may be loaded.

[0022] Various portions of the substrate 140 may be doped based on the intended polarity and / or properties of the snapback device 130 and / or other device structures formed thereon to form a P-well 142 and an N-well 144 adjacent to the P-well 142. The P-well, in one example, is located to the right of the N-well 142 and is approximately the same size, but this is not required. Various active elements may be formed on or within the P-well 142 and / or N-well 144 to form electrical paths through the snapback device 130, electrically bias and / or influence current flow through the well(s) 142, 144, etc., without fundamentally altering the function of the active elements and / or affecting other structures formed over or in the substrate 140. In some embodiments (e.g.,Semiconductor-on-insulator (SOI) structures, one or more layers of a dielectric or other insulating material may be disposed vertically between the substrate 140 and one or both of the recesses 142, 144.

[0023] A "dopant" refers to an element that is introduced into the semiconductor to create either p-type (acceptors) or n-type (donors) conductivity. In the case of a silicon substrate, common dopants can include, for example, boron (B) and / or indium (In) for p-type doping. In n-type doping, the doped elements can include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). Doping involves introducing impurities (dopants) into the semiconductor substrate or into the elements formed on the semiconductor substrate. Doping is often performed using a mask (e.g., a layer of photoresist and / or another dopant-blocking component) so that only specific areas of the substrate are doped. In the example of doping by implantation, an ion implanter can be used. In further examples, in-situ doping or other doping techniques may be used.

[0024] Doping typically involves specifying a dopant, a dosage, and an energy level, and / or a resulting doping level. A dosage can be expressed in the number of atoms per square centimeter (cm 2 ) and an energy level (given in keV, kiloelectronvolts), resulting in a doping level (concentration in the substrate) of a number of atoms per cubic centimeter (cm 3 ). The number of atoms is usually expressed in exponential notation, where a number such as "3E15" means 3 times 10 to the power of 15, or a "3" followed by 15 zeros (3,000,000,000,000,000). An example of doping is the implantation of B (boron) with a dose of approximately 1E12 to 1E13 atoms / cm 2 and an energy of about 40 to 80 keV to achieve a doping level of 1E17 to 1E18 atoms / cm 3Doped portions of a substrate are known in the art as a "well." A well generally refers to the implanted / diffused region in a semiconductor wafer required for the implementation of a CMOS (complementary metal oxide semiconductor) cell. A "deep well" refers to doped semiconductor material located beneath active components and / or other wells. Depending on the characteristics of a device to be fabricated, portions of the semiconductor material on or above substrate 140 may be either N-type or P-type doped, as described herein.

[0025] Wells 142, 144 may be doped with additional materials at a higher concentration than well(s) 142, 144 and with different doping types to achieve the functions of snapback device 130 during operation. For example, P-well 142 may have a first N-doped region 146 connected to first node A, which may be the same node as cathode terminal T Cat and / or may include the same. The N-doped region 146 may therefore have the opposite doping type as the P-well 142. The N-well 144 may similarly have a first P-doped region 148 connected to the second node B, which may be the same node as the anode terminal T AnPortions of each well 142, 144 may physically separate the first N-doped region 146 from the first P-doped region 148. The arrangement of alternating doped regions within the snapback device 130 provides a current path L from the cathode terminal T Cat to the anode connection T An through the snapback device 130.

[0026] The snapback device 130 may include a first doped region 150 and / or a second doped region 152 respectively within the P-well 142 and the N-well 144 to provide a gate contact for controlling the current flow along the current path L. Each doped region 150, 152 may be of the same doping type as the corresponding well 142, 144 and may have a gate terminal T Gatecomprise or otherwise connected thereto. Here, the first doped region 150 may be P-type and located in the P-well 142, while the second doped region 152 may be N-type and located in the N-well 142. Optionally, the doped regions 150, 152 may be coupled to the output of the second inverter 132. The electrical coupling to the second doped region 152 is shown with dashed lines to indicate that it may be an additional or alternative coupling with respect to the first doped region 150. The transfer of a current to the doped region(s) 150, 152 of the snapback device may electrically bias the well(s) 142, 144 while allowing current to flow through the current path L.

[0027] With reference to Fig. 4, further embodiments of the snapback device 130 may include multiple doped regions coupled with voltages of opposite polarity to more tightly control the current flow through the current path L. In such cases, the snapback device 130 may include two gates T Gate1 and T Gate2 which may be coupled to the first doped region 150 and the second doped region 152. In this case, the doped regions 150 and 152 may be electrically connected to the input and output of the second inverter 132, respectively. In some configurations, the polarity of each of the gate terminals T Gate1 and T Gate2 be inverted relative to the second inverter 132. Such a connection allows the application of a single voltage to the gate terminals T Gate1 and T Gate2generate electrical currents in each doped region 150, 152 to simultaneously electrically bias the N-well 142 and P-well 144 with opposite voltage polarities. This can further control the leakage and turn-on of the snapback device 130.

[0028] With further reference to Fig. 1 and Fig. 3, methods according to the invention may include using the structure 100 during operation of a device for controlling ESD events to protect the RC circuit 110 from excessive electrical currents. Methods according to the invention may, for example, include transmitting an ESD current through the trigger transistor 122 of the ESD element(s) 120 in parallel with the RC circuit 110. The ESD current may result from an ESD event in one or more devices connected to the structure 100. The transmission of such a current through the trigger transistor 122 results in the mirror transistor 126, in parallel with the trigger transistor 122, also receiving a mirrored current, but lower than the current in the trigger transistor 122. The reduced current in the mirror transistor 126 is due, for example, to the mirror transistor 126 being significantly smaller (e.g.,a smaller source-drain width, as described herein), and / or the presence of resistor 128, where applicable. In an example implementation, the mirrored current in mirror transistor 126 may be at most about 1 / 10 of the current in trigger transistor 122. The mirrored current in mirror transistor 126 may be coupled to gate terminal T. Gate the snapback device 130, thereby enabling current to flow from cathode to anode along current path J ( Fig. 2). In the active state, the snapback device 130 electrically shorts the ESD current to bypass the RC circuit 110. The time delay between the activation of the trigger transistor 122 and the activation of the snapback device 130 may be insignificantly small (e.g., about one hundred picoseconds (ps)) to prevent any effect of ESD currents on the RC circuit 110 and the integrated circuit.

[0029] The descriptions of the various embodiments of the present invention are intended to be illustrative, but not exhaustive, and / or limited to the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application, and / or technical improvement over existing technologies, and / or to enable others than those skilled in the art to understand the embodiments described herein.

[0030] Embodiments of the invention may provide several technical and commercial advantages, some of which are discussed herein by way of example. For example, embodiments of structure 100 provide a structure that can respond to ESD events with conventional trigger voltage magnitudes while reducing the current or voltage required to enable electrical shorting through snapback device 130. Embodiments of the invention also prevent the gate voltage of snapback device 130 from reaching a value that risks "latchup" and permanent electrical shorting of RC circuit 110. In some cases, the size and electrical parameters of trigger transistor 122 and / or mirror transistor 126 may be chosen to suit different types of RC circuits 110 and / or devices electrically connected to structure 100.Compared to conventional structures for responding to ESD events that affect the RC circuit 110, embodiments of the structure 100 occupy a similar or smaller area than other circuits to temporarily bypass the RC circuit 110.

Claims

[1] Circuit structure comprising: a resistor-capacitor circuit (RC circuit) (110) having a first node (A), a second node (B) separated from the first node (A) by a resistive element (112) and a capacitive element (114), and a third node (C) between the resistive element (112) and the capacitive element (114); a trigger transistor (122) having a pair of source / drain (S / D) terminals connected between the first node (A) and the second node (B) in parallel with the RC circuit (110) and a gate terminal coupled to the third node (C) of the RC circuit (110); a mirror transistor (126) having a pair of S / D terminals coupled between the first node (A) and the second node (B) in parallel with the RC circuit (110), and a gate terminal coupled to the gate terminal of the trigger transistor (122), wherein a current through the pair of S / D terminals of the mirror transistor (126) is smaller than a current through the pair of S / D terminals of the trigger transistor (122); and a snapback device (130) having a gate terminal (T Gate ) for controlling the current flow in the snapback device (130), the snapback device (130) comprising: a P-well (142) having a first N-doped region (146) coupled to one of the first nodes (A), an N-well (144) adjacent to the P-well (142) and having a first P-doped region (148) coupled to the second node (B), wherein a current path from the first node (A) to the second node (B) runs through the snapback device (130) in parallel with the RC circuit (110), and at least one doped region within the P-well (142) or the N-well (144) coupled to a selected one of the pair of S / D terminals of the mirror transistor (126) and the gate terminal (T Gate ) of the snapback device (130), wherein the at least one doped region has a same doping type with respect to the P-well (142) or the N-well (144). [2] The circuit structure of claim 1, further comprising: a first inverter (124) having an input coupled to the third node (C) of the RC circuit (110) and an output coupled to the gate terminal of the trigger transistor (122); and a second inverter (132) having an input coupled to the selected one of the pair of S / D terminals of the mirror transistor (126) and an output coupled to the gate terminal (T Gate ) of the snapback device (130), wherein the trigger transistor (122) and the mirror transistor (126) are configured to reverse a voltage polarity between the output of the first inverter (124) and the input of the second inverter (132). [3] The circuit structure of claim 1, wherein the current through the pair of S / D terminals of the mirror transistor (126) is at most 1 / 10 of the current through the pair of S / D terminals of the trigger transistor (122). [4] The circuit structure of claim 1, wherein the current through the pair of S / D terminals of the mirror transistor (126) is at most about twenty milliamperes (mA) and the current through the pair of S / D terminals of the trigger transistor (122) is at most about two hundred mA. [5] The circuit structure of claim 1, wherein a source-drain width of the trigger transistor (122) is at most about four thousand micrometers (µm) and a source-drain width of the mirror transistor (126) is at most about two hundred µm. [6] The circuit structure of claim 1, further comprising a resistor (128) coupled between the selected one of the pair of S / D terminals of the mirror transistor (126) and the first node (A), the resistor (128) being configured to transmit the current through the mirror transistor (126). [7] The circuit structure of claim 1, wherein the snapback device (130) comprises a thyristor (SCR). [8] The circuit structure of claim 7, wherein at least one doped region within the P-well (142) or the N-well (144) comprises a second P-doped region within the P-well (142) and a second N-doped region within the N-well (144). [9] A method for controlling an electrostatic discharge (ESD) event in a resistor-capacitor (RC) circuit, the method comprising: transmitting an electrostatic discharge (ESD) current through a trigger transistor (122) in parallel with a resistor-capacitor (RC) circuit (110), the RC circuit (110) comprising a first node (A), a second node (B) separated from the first node (A) by a resistive element (112) and a capacitive element (114), and a third node (C) coupled to a gate of the trigger transistor (122) between the resistive element (112) and the capacitive element (114); transmitting a mirrored current through a mirror transistor (126) in parallel with the trigger transistor (122), wherein the mirror transistor (126) is configured to transmit a current that is smaller than the transmitted ESD current; and transferring the mirrored current to a gate terminal (T Gate) a snapback device (130) electrically connected between the first node (A) and the second node (B) in parallel with the RC circuit (110) to allow current to flow from the first node (A) to the second node (B) through the snapback device (130) during the transfer of the mirrored current to the gate terminal, wherein the snapback device (130) comprises: a P-well (142) having a first N-doped region (146) coupled to one of the first nodes (A), an N-well (144) adjacent to the P-well (142) and having a first P-doped region (148) coupled to the second node (B), wherein a current path from the first node (A) to the second node (B) runs through the snapback device (130) in parallel with the RC circuit (110), and at least one doped region within the P-well (142) or the N-well (144) coupled to a selected one of the pair of S / D terminals of the mirror transistor (126) and the gate terminal (T Gate ) of the snapback device (130), wherein the at least one doped region has a same doping type with respect to the P-well (142) or the N-well (144). [10] The method of claim 9, wherein transmitting the mirrored stream comprises: Prevent the mirrored current from exceeding approximately 1 / 10 of the transmitted ESD current. [11] The method of claim 9, wherein transmitting the ESD current comprises: preventing the ESD current from exceeding approximately two hundred milliamperes (mA), and transmitting the mirrored current comprises: preventing the mirrored current from exceeding approximately twenty milliamperes (mA). [12] The method of claim 9, further comprising: applying an inverted node voltage within the RC circuit (110) to a gate terminal of the trigger transistor (122) to transmit the ESD current through the trigger transistor (122), and wherein transmitting the mirrored current to the gate terminal (T Gate ) of the snapback device (130) comprises: applying an inverse of a source / drain voltage of the mirror transistor to the gate terminal of the snapback device. [13] The method of claim 9, wherein the snapback device (130) comprises a thyristor (SCR).

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