PHASE DETECTOR COMMAND PROGRESSION BETWEEN TRACKS IN MCM USR SERDES

Abstract

Multi-chip module (MCM) (102), comprising: an MCM substrate; and at least one data-generating integrated circuit IC(DPIC) (104) and one data-consuming integrated circuit IC(DCIC) (106), both mounted on the MCM substrate and connected to each other via a high-speed bus comprising at least one first and one second embedded clock data track (108); which includes the DCIC: a data recovery circuit (CDR) (116; 402A) configured to recover data from the first data track (Lane 3; Lane A 202; Lane B) and generate a phase correction signal from the first data track; and a data sampler (118; 402B, 402C) configured to recover the data from the second data track (Lane1, Lane2, Lane4, Lane5; LaneB 204; LaneA, LaneC) by sampling the second data track with a phase that is based on the first data track generated phase correction signaling reacts, and wherein the data recovery circuit (CDR) and the sampler each comprise first and second instances of a circuit that are configurable for operation in first and second configurations, wherein: In the first configuration (Master) (402A), the circuit is configured to restore the data and generate the phase correction signaling from a data track, and In the second configuration (Slave) (402B, 402C) the circuit is configured to receive the phase correction signaling from a peer circuit (Master) (116; 402A) and to restore the data from the data track based on the phase correction signaling received from the peer circuit.

Description

AREA OF INVENTION

[0001] The present invention relates generally to clock and data recovery (CDR) and in particular to the efficient implementation of CDR in multi-chip modules (MCMs). BACKGROUND OF THE INVENTION

[0002] Communication between integrated circuits (ICs) in a multi-chip module (MCM) typically occurs at high bit rates over a multitude of ultra-short-reach (USR) point-to-point lines. These USR lines often carry serialized data across multiple tracks using high-speed SERDES techniques. In some applications, the clock signal is not transmitted, and the receiving integrated circuits employ clock-data recovery (CDR) techniques to reconstruct the clock from the data.

[0003] In “A Digital Clock and Data Recovery Architecture for Multi-Gigabit / s Binary Links”, Sonntag and Stonick, IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, August, 2006, the authors describe a general architecture for digital clock and data recovery (CDR) for high-speed binary links, based on replacing elements of typical analog CDRs with digital components.

[0004] In “Parallel Ultra-Short Reach Die-to-Die Links”, PhD Thesis, Graduate Department of Electrical and Computer Engineering, University of Toronto, 2017, Behzad Dehlaghi Jadid describes the challenges and techniques typically used in USR communication.

[0005] Finally, US patent US 8 149 979 B2 describes a multi-track SERDES communication in which a clock track and a multitude of data tracks are sent from a sender to a receiver which extracts the input clock using CDR circuits and locks an internal clock with the extracted received clock.

[0006] Patent application US 2016 / 0182259 A1 describes devices and methods comprising an input for receiving an input signal, additional inputs for receiving clock signals with different phases for sampling the input signal, and a decision feedback equalizer (DFE) with DFE disks. The DFE disks contain a number of data comparators to provide data information based on the sampling of the input signal and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators in the DFE disks is not greater than the number of data comparators in the DFE disks. SUMMARY OF THE INVENTION

[0007] The invention is defined by the claims. To illustrate the invention, aspects and embodiments that may or may not fall within the scope of the claims are described here.

[0008] An embodiment of the present invention described herein provides a multi-chip module (MCM) comprising an MCM substrate and at least one data-generating IC (DPIC) and one data-consuming IC (DCIC), both mounted on the MCM substrate and interconnected via a high-speed bus containing at least one first and one second embedded clock data track. The DCIC includes a data recovery circuit (CDR) and a data sampler. The CDR is configured to recover data from the first data track and generate a phase correction signal from the first data track.The data sampler is configured to recover the data from the second data track by sampling the second data track with a phase that responds to the phase correction signaling generated from the first data track; and wherein the data recovery circuit (CDR) and the sampler each comprise first and second instances of a circuit that are configurable for operation in first and second configurations, wherein: in the first configuration, the circuit is configured to recover the data and generate the phase correction signaling from one data track, and in the second configuration, the circuit is configured to receive the phase correction signaling from a peer circuit and recover the data from the data track based on the phase correction signaling received from the peer circuit.

[0009] In some embodiments, the phase correction signaling includes phase increment and phase decrement signals. In one embodiment, the data sampler includes a phase shifter and a sample-and-hold device, wherein the phase shifter is configured to send a phase signal to the sample-and-hold device in response to the phase correction signaling, and the sample-and-hold device is configured to sample the second data track in response to the phase signaling.

[0010] In one exemplary embodiment, the circuit in the second configuration is further configured to transmit the phase correction signaling to an additional peer circuit. In one embodiment, the circuit includes a phase correction signaling generation circuit that is enabled in the first configuration and disabled in the second configuration. In one embodiment, the circuit is configured to detect an initial clock phase of the data track in the first configuration and then switch to the second configuration and track clock phase variations with respect to the peer circuit based on the received phase correction signaling.

[0011] In addition, a method in a multi-chip module (MCM) is provided according to one embodiment of the present invention. The method comprises communication within the MCM between a data-generating integrated circuit (DPIC) and a data-consuming integrated circuit (DCIC), both mounted on the MCM substrate and interconnected via a high-speed bus comprising at least a first and a second embedded clock data track. A data recovery circuit (CDR) in the DCIC is used to recover data from the first data track and generate a phase correction signal from the first data track. Data from the second data track is recovered in the DCIC using a data sampler by sampling the second data track with a phase that responds to the phase correction signal generated from the first data track.The data recovery circuit (CDR) and the sampler each comprise a first and a second instance of a circuit, which can be configured to operate in a first and a second configuration. Data and clock recovery involves: in the first configuration, the circuit recovering the data and generating the phase correction signal from a data track; and in the second configuration, receiving the phase correction signal from a peer circuit and recovering the data from the data track based on the phase correction signal received from the peer circuit.

[0012] In some embodiments, the phase correction signaling includes phase increment and phase decrement signals. In one embodiment, the data sampler comprises a phase shifter and a sample-and-hold device, wherein sampling the second data track includes sending a phase signal from the phase shifter to the sample-and-hold device in response to the phase correction signaling, and sampling the second data track by the sample-and-hold device in response to the phase signaling.

[0013] In an exemplary embodiment, the method in the second configuration further comprises transmitting the phase correction signal from the circuit to an additional peer circuit. In one embodiment, the circuit includes a phase correction signal generation circuit that is enabled in the first configuration and disabled in the second configuration. In another embodiment, the method further comprises capturing an initial clock phase of the data track in the circuit in the first configuration and then switching to the second configuration and tracking clock phase variations relative to the peer circuit based on the received phase correction signal.

[0014] Each feature of one aspect or embodiment can be applied to other aspects or embodiments in any suitable combination. In particular, each feature of one process aspect or embodiment can be applied to one device aspect or embodiment, and vice versa.

[0015] The present invention is understood from the following detailed description of its embodiments, together with the drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram schematically showing the ultra-short-reach (USR) communication between two integrated circuits in a multi-chip module (MCM) according to embodiments of the present invention; Fig.Figure 2 is a block diagram schematically showing the clock and data recovery of two data tracks in a data-consuming integrated circuit (DCIC) according to embodiments of the present invention. Fig. Figure 3 is a flowchart that schematically illustrates a method for clock and data recovery in a CDR and in an adjacent scanner according to embodiments of the present invention; and Fig. Figure 4 is a block diagram schematically showing the power-saving clock and data recovery with identical CDR units according to embodiments of the present invention. DETAILED DESCRIPTION OF THE EXECUTION FORM OVERVIEW

[0016] The term multi-chip module (MCM) generally refers to an electronic assembly comprising multiple integrated circuits (ICs) and / or discrete components integrated into a single device package, typically on a common substrate. Communication between the ICs within an MCM occurs over short distances and is sometimes referred to as ultra-short-reach (USR) communication. USR may also be referred to as a high-speed bus.

[0017] In high-performance MCMs, such as those used in network elements, communication between the MCM's ICs can be fast and is often handled by dedicated serializer / deserializer circuits (SERDES) coupled to physical layer units (PHYs) that transmit high-speed data over dedicated USR point-to-point lines. The integrated circuit or IC that transmits the data is referred to as the data-producing IC (DPIC), and the IC that receives the data over the dedicated USR lines is referred to as the data-consuming IC (DCIC).

[0018] The high-speed data transmission medium can comprise multiple tracks, with each track typically containing a symmetrical differential pair of lines that serially transmits symbols. The reference clock can be transmitted in a separate track or, alternatively, not transmitted at all.

[0019] Conventionally, clock and data recovery (CDR) circuits can be used in the DCIC to recover the data and clock from each track. A CDR aligns a reference clock with the transitions of the incoming data stream in phase ("clock recovery") and then samples the incoming data signal with the recovered clock or with a shifted version of it ("data recovery").

[0020] Phase alignment circuits (also called "locking") are relatively complex and consume a lot of power. When multiple tracks are implemented, the additional power and area added to the DCIC can be substantial.

[0021] The embodiments of the present invention disclosed herein provide devices and methods for energy- and area-efficient clock and data recovery in multi-track USR communication in integrated DCIC circuits of an MCM.

[0022] In some embodiments, the tracks fed into a DCIC are short and well-matched with respect to delay and / or interference; therefore, the phase differences between the tracks are small, and in some cases, these phase differences can be ignored. In other embodiments, the phase differences may be significant, but the variation of the phase differences over time can be ignored; this variation from the initial phase is referred to as "phase variation."

[0023] In one embodiment, the difference between the phase variations of adjacent tracks is small enough to be ignored. The DCIC incorporates sampling units (also called "samplers") for some of the tracks instead of complete CDRs. The sampling units are configured to receive phase correction signals, such as phase increment and phase decrement signals, from adjacent CDRs and adjust the sampling phase accordingly. This results in significant savings in area and power consumption.

[0024] In some embodiments, an initial phase is determined separately for the track, e.g., during the reset (methods for determining the initial phase are disclosed below). After the reset, the probes receive phase correction signals and follow the phase correction of the adjacent CDRs.

[0025] In one embodiment, the space saving is sacrificed, and identical CDR units are used. However, the CDRs can be configured, for example, by software, strap-pin, or mask options, to act as samplers that receive phase correction signals from neighboring CDRs and modify the sampling phase accordingly (and, optionally, pass the phase correction signals to other neighboring CDRs configured as samplers). Thus, in this embodiment, all CDRs are identical and have closely matched delays and induced noise; no space is saved, but power consumption is significantly reduced. SYSTEM DESCRIPTION

[0026] Fig.Figure 1 is a block diagram schematically illustrating the ultra-short-range (USR) communication between two integrated circuits in a multi-chip module (MCM) 102 according to embodiments of the present invention. The MCM comprises a first integrated circuit (IC-A) 104, which sends data to a second integrated circuit (IC-B) 106 via an ultra-short-range (USR) link comprising tracks 108, labeled track 1 to track 5.

[0027] In practice, the MCM can include other integrated circuits and / or discrete components, typically mounted on a common substrate; such elements are in Fig. Figure 1 is not shown for clarity. Furthermore, both IC-A 104 and IC-B 106 can be coupled to other ICs (or to each other) via additional connections not shown, USRs, or other means, and can transmit data in any direction. This is shown in Figure 1. Fig.1. Only one data path within the MCM 102, where IC-A serves as the data-producing IC (DPIC) and IC-B as the data-consuming IC (DCIC). In the following description, we will sometimes refer to IC-A and IC-B as DPIC and DCIC, respectively.

[0028] The DPIC 104 comprises Tx circuits 110 and a phase-locked loop (PLL) 112 which generates a transmit clock by multiplying an input reference clock by a pre-programmed fraction or integer (the multiplication is typically indirect - a PLL divides the transmit clock frequency, compares the result with a division of the reference clock and adjusts the transmit frequency accordingly to minimize the difference between the divided frequencies; thus, the reference clock frequency is essentially multiplied).

[0029] Each Tx circuit 110 encodes a corresponding data stream and transmits the encoded data on a corresponding data track 108 (e.g., using pulse amplitude modulation (PAM) 4 and 64 / 66 encoding). The transmit clock is embedded in the data tracks.

[0030] The DCIC includes a PLL 114, which generates a receive clock by multiplying an input reference clock by a pre-programmed fraction. In one embodiment, the same reference clock is input to both the PLL 112 and the PLL 114, which are pre-programmed with the same fraction; consequently, the DCIC receive clock and the DCIC receive clock, free of noise, have the same frequency.

[0031] The DCIC 106 also includes a clock and data recovery (CDR) circuit 116 coupled to track 3, and samplers 118 coupled to tracks 1, 2, 4 and 5.

[0032] The CDR 116 is configured to restore the embedded clock and sample the data from track 3. The CDR is also configured to output phase correction signals indicating phase corrections to the receiver clock that are necessary for accurate data sampling.

[0033] Since the USR tracks are short, the phase difference between the tracks can be small over time; once the initial phases are determined, all five tracks can be sampled with the shift relative to the initial phases. Therefore, data tracks 1, 2, 4, and 5 are coupled with scanners rather than CDRs. After determining the initial phases of each scanner, the scanners receive the phase correction signal from the CDR and sample data from their respective tracks.

[0034] According to the in Fig.In the embodiment shown in Figure 1, the recovery of clock and data from a group of USR tracks is area- and power-efficient - a single CDR circuit is implemented on one of the tracks, and the other tracks are coupled with simpler samplers that sample data in a phase that is corrected by the single CDR.

[0035] As can be seen, the structures of MCM 102, DPIC 104, and DCIC 106 described above are only examples. MCMs, DPICs, and DCICs in accordance with the disclosed techniques are not limited to the above description. For example, the number of lanes can differ from five. The CDR can be coupled to any lane (a lane geometrically close to the center may be preferred, although this is not essential, as its phase-shift variations may be closer to the average variation). In some embodiments, more than one CDR can be used; for example, each group of three adjacent lanes can have one CDR and two sensors phase-controlled by the CDR.

[0036] Fig.Figure 2 is a block diagram 200 that schematically shows the clock and data recovery of two data tracks in a data-consuming integrated circuit (DCIC) according to embodiments of the present invention.

[0037] This figure shows CDR 116 and one of the scanners 118 from Fig. 1 in detail.

[0038] A track A 202 is coupled to a CDR 116, and a track B 204, which closely approximates the interference of track A, is coupled to a sampler 118. The CDR 116 comprises a sample-and-hold (S&H) circuit 206, a phase detector 208, and a phase shifter 210. The S&H circuit 206 is configured to sample the incoming track in response to transitions in a "0" signal and a "90" signal input by the phase shifter 210. The two sampling points correspond to the phases of a receive clock (Rx clock) of the DCIC. In single-data-rate (SDR) transmission (sometimes also referred to as half-rate), sampling occurs on the positive edges of the signals, e.g., B, with a phase shift of 0° for the "0" signal and 90° for the "90" signal, relative to the Rx clock; in Dual Data Rate (DDR) (sometimes called full rate or(referred to as "full rate") sampling takes place on both edges of the signals, e.g. with phase shifts of 0° and 180° for the "0" signal and with phase shifts of 90° and 270° for the "90" signal.

[0039] The signal (designated as "sample @90") that the S&H samples in response to a transition at the "90" input is fed into the phase detector 208, which is configured to issue an increment or decrement command to the phase shifter 210. In one embodiment, when the levels sampled at 90° and 0° phases are equal, the phase detector generates an internal phase increment signal to delay the generation of the "0" and "90" signals, while when the levels are opposite, the phase detector generates an internal decrement signal to advance the generation of the "0" and "90" signals.

[0040] In some embodiments, the phase correction signals are low-pass filtered using an FIR (Finite Impulse Response) filter, an IIR (Infinite Impulse Response) filter, or another suitable filter. Such filters are not shown in the figures for clarity.

[0041] Since the sampled tracks contain data that may not switch at every clock transition, the internal increment and decrement signals are not generated at all clock transitions; however, in embodiments, data encoding ensures that, regardless of the original data, there are always enough transitions in the transmitted data to allow proper phase blocking (e.g., by 64 / 66 encoding and / or by pseudo-random encoding).

[0042] The increment / decrement signals generated by the phase detector 208 are fed into the phase shifter 210, which in turn increments or decrements the phase shift of the "0" and "90" signals relative to the phase of the Rx clock. For example, if the resolution of the generated phases is 22.5° and the phase delays of the "0" and "90" outputs relative to the low-to-high transition of the Rx clock are 135° and 225°, respectively, an increment input changes the phase shifts to 157.5° and 247.5°, while a decrement input changes the phase shifts to 112.5° and 202.5°.

[0043] The S&H 206 also samples track A at transitions in the "0" input to generate the recovered data output of the CDR 116. The sampled output, designated as "Sample @ 0", is fed into the phase detector 208 and output by the CDR 116 for further processing, such as deserialization and decoding.

[0044] Since track A and track B are synchronized with respect to delay variations and interference, the data and clock of track B can be reconstructed using the phase corrections extracted by the CDR 116. The sampler 118 coupled to track B comprises a phase shifter 212 and a sample-and-hold (S&H) circuit 214. The phase shifter is similar to the phase shifter 210, except that the phase shifter 212 does not produce the "90" output and can therefore be simpler and consume less power (in some embodiments, the same circuit is used, but the "90" output is not connected or is connected to a dummy load).

[0045] Similarly, the S&H 214 is like the S&H 206, except that the S&H 214 does not have a "90" input and does not scan the lane at transitions at a "90" input. Therefore, the S&H 214 can be simpler than the S&H 206 (in some embodiments, the same circuit can be used except that the "scan @90" output is not connected or is connected to a dummy load).

[0046] In summary, if two (or more) tracks are similar with respect to interference, one track can be coupled to a CDR circuit comprising a S&H, a phase detector, and a phase shifter, configured to detect the phase and increment or decrement the phase of a phase shifter that controls the sampling phases. The other track (or tracks) can be coupled to a sampler comprising a simpler S&H and a simpler phase shifter, configured to sample the data track (or tracks) at the correct phase by tracking the phase corrections generated by the CDR. In this way, according to the [reference to be added] Fig. In the embodiment described in section 2, the area and power consumption of circuits that restore clock and data from multiple adapted tracks can be significantly reduced.

[0047] The structures of the CDR 116 and the sampler 118 described above are, of course, only examples. CDRs and samples conforming to the disclosed techniques are not limited to the above description. For example, various suitable CDR architectures can be used, including over-sampling CDRs, DLL-based CDRs, PLL-based CDRs, and others. In some embodiments, some or all of the samples do not include phase shifters, and instead, the "0" output of the CDR is fed into the sampler's S&H units, either directly or via suitable delay circuits.

[0048] Fig. Figure 3 is a flowchart 300 that schematically shows a method for clock and data recovery in a CDR and in an adjacent scanner according to embodiments of the present invention. The flowchart is simultaneously read by a CDR 116 and an adjacent scanner 118 ( Fig. 2) executed.

[0049] The CDR first enters a check-equal-level step 302 and verifies whether the signal levels of the track are equal at 0° and 180°. Equal levels mean that there was no change in the bit level between the time phase=0° and phase=180°. In this case, the phase cannot be estimated, and the CDR returns to step 302 (the CDR returns to step 302 at the next time phase=0°).

[0050] If the signal levels are different in step 302, the CDR enters a 90° comparison step 304 and compares the signal level at 0° with the signal level at 90°. If the levels are the same, the CDR then enters step 306 "Incrementing the Phase" or step 308 "Decrementing the Phase" if the levels are not the same (this technique, also called "bang-bang", always corrects the phase in small steps, and there is no steady state in which the CDR does not change the phase on an edge in the data).

[0051] In step 306, the CDR increments the phase by a small value (e.g., 360° / 32 = 11.25°) and then enters a send-increment-to-sampler step 310, sends an increment phase signal to adjacent samples and then enters step 302 again for the next phase correction.

[0052] Similarly, in step 308 the CDR decrements the phase by a small value and then, in a send-decrement-to-sampler step 312, sends a decrement phase signal to adjacent samples, finally re-entering step 302 for the next phase correction.

[0053] The adjacent probe begins with a receive signal step 314, waiting until the CDR sends an increment or decrement phase signal. If the probe receives a signal from the CDR, it moves to a check increment / decrement step 316 and then to an increment phase step 318 if the received signal is an increment phase, or to a decrement phase step 320 if the signal is a decrement phase.

[0054] In steps 318 and 320, the scanner increments or decrements the sampling phases and then returns to step 314.

[0055] According to the in Fig.As shown in the flowchart 3, a CDR samples the signal upon detecting a transition in a coupled data track and then increments or decrements the sampling phases, depending on the signal level at a 90° phase. Adjacent samplers receive the increment / decrement phase signals from the CDR and adjust the sampling phases of the corresponding tracks accordingly; this saves power and space (compared to additional CDRs).

[0056] The flowchart 300 described above is given here only as an example. Flowcharts in accordance with the disclosed techniques are not limited to the description above. For example, step 314 can be combined with step 316; step 306 can be combined with step 310; and step 308 can be combined with step 312.

[0057] While the energy savings achieved in embodiments of the present invention are always desirable, the space savings can come at a cost. First, two types of cells must be maintained (CDR cells and sampler cells). Second, different cells are more difficult to match with respect to delay variations and induced noise. In some embodiments of the present invention, a single circuit is used, which can be configured to operate in one of two configurations: a CDR configuration (“master”) with full CDR functionality, and a sampler configuration (“slave”) in which the circuit receives the phase correction signal from an adjacent circuit with a master configuration (“peer circuit”) and samples the data accordingly. In the slave configuration, some of the CDR circuitry may be degraded to save power.

[0058] The CDR configuration can be done via software or defined, for example, by a band or mask option.

[0059] Fig. Figure 4 is a block diagram schematically illustrating the power-saving clock and data recovery using identical CDR units according to embodiments of the present invention. Three identical CDR circuits with different configurations are shown: a CDR 402A configured as a master and coupled to track B; a CDR 402B configured as a slave and coupled to track A; and a CDR 402C configured as a slave and coupled to track C, which is controlled externally. The three CDRs are located side by side, and additional CDRs that can be added are placed above CDR 402B or below CDR 402C. Adjacent CDRs are referred to as "adjacent CDRs".

[0060] The three CDR circuits are identical and therefore well matched with respect to delay variations and noise. Each CDR consists of an S&H 406, a phase detector 408, a phase shifter 410, and a three-way multiplexer 412.

[0061] The S&H 406 is like the S&H 214 ( Fig. 2), however, the 90° scanning is disabled in the slave configurations (and the corresponding power is saved). The phase detector 408 is like the phase detector 208 ( Fig. 2), except that in the slave configurations the phase detector is deactivated. The multiplexer 312 transmits an upper input, a middle input, or a lower input to the phase shifter 412, which is connected to the phase shifter 210 ( Fig. 2) may be identical.

[0062] The functionality of the subunits of the CDRs 402A, 402B, 402C is summarized in the following table: Master configured ECB slave configured ECT slave configured S&H Complete Sampling@90 disabled Sampling @90 disabled Phase detector Complete bypass bypass multiplexer Select middle entrance Select Lower Entrance Select Upper Entrance Phase shifter Complete Partially (only for phase "0") Partially (only for phase "0")

[0063] The multiplexing scheme allows the addition of further slave devices above and below the CDR devices shown. All devices added above CDR 402B are configured as ECB slaves, and all devices added below CDR 402C are configured as ECT slaves.

[0064] The vertical tile geometry of the CDR cells can be used when the cells are aligned along a vertical edge of the DCIC. In alternative embodiments, horizontal tiles can also be used, where the terms "bottom" and "top" are replaced by "left" and "right".

[0065] As mentioned previously, the configuration of the CDR units can be done via software, strapping inputs, mask options, or any other suitable technique.

[0066] Thus, according to the in Fig.In the 4 configurations shown, identical CDR units are used to recover clock and data from adjacent tracks; matching between the units enables high-data-rate USR communication, and significant power savings can be achieved by passing the phase control signals from a single master-configured CDR to multiple slave-configured CDRs.

[0067] As can be seen, the configuration of CDRs 402A, 402B, and 402C described above is only an example. CDRs conforming to the disclosed techniques are not limited to the above description. In some embodiments, for example, the accumulated delay by the multiplexers from a master-configured CDR to a remote CDR configured as a slave can be compensated for by advancing the Rx clock or by delaying the track of the remote CDR. In some embodiments, the multiplexer 412 is not implemented; instead, in a master-configured CDR, the output of the phase detector is routed to the input of the phase shifter; and in ECB- and ETB-configured CDRs, the inputs from a lower input and an upper input, respectively, are wired to the phase shifter. SETTING UP THE INITIAL PHASES

[0068] The disclosed techniques typically involve obtaining initial phase settings for the samplers and then, assuming that the phase changes for adjacent tracks are similar, tracking the changes of adjacent tracks that include CDRs. Methods for obtaining the initial phase settings are known in the art and are not described in the above embodiments. For example, a transmitter may initially or periodically send a "training sequence" containing a known sequence (e.g., alternating 1s and 0s); the sampler can then adjust the phase setting until the training sequence is received without errors. In another example, the sampler sets the initial phase by minimizing the CRC errors detected in the received data stream.

[0069] In some of the embodiments described above, all tracks are identical, and in the tracks where only one probe is used, the CDR is switched off to save power. However, in some embodiments, the CDR can switch on initially or periodically to determine the initial phase and then switch off. The determination of the initial phase can be triggered, for example, upon power-up, upon reset, or by a signal generated by a software or hardware circuit, e.g., at regular intervals.

[0070] The procedure from Fig. 3. The configuration of CDR 116, scanner 118, and configurable CDR 402 and all subunits thereof are exemplary methods and configurations shown only for conceptual clarity. Any other suitable methods and configurations may be used in alternative embodiments.

[0071] In various embodiments, the CDR 116, the probe 118 and the configurable CDR 402 can be implemented with suitable hardware, e.g. with one or more application-specific integrated circuits (ASIC) or field-programmable gate arrays (FPGA) or a combination of ASIC and FPGA.

[0072] Although the embodiments described here mainly address USR communication in MCMs, the methods and systems described here can also be used in other applications.

[0073] It is therefore understandable that the embodiments described above are given as examples and that the present invention is not limited to what has been specifically shown and described herein. Rather, the scope of the present invention includes combinations and subcombinations of the various features described herein, as well as variations and modifications thereof that would occur to a person skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated into the present patent application by reference are to be considered an integral part of the application, except that, to the extent that terms in these incorporated documents are defined in a manner that contradicts the definitions made explicitly or implicitly in the present description, only the definitions in the present description are to be taken into account.

[0074] It is understood that the aspects and embodiments described above are purely exemplary and that modifications can be made in detail within the scope of the claims.

[0075] Each device, method and feature disclosed in the description and (where applicable) in the claims and drawings may be provided independently or in any suitable combination.

[0076] The reference figures contained in the claims serve only for illustration and do not have a limiting effect on the scope of the claims.

Claims

[1] Multi-chip module (MCM) (102), comprising: an MCM substrate; and at least one data-generating integrated circuit IC(DPIC) (104) and one data-consuming integrated circuit IC(DCIC) (106), both mounted on the MCM substrate and connected to each other via a high-speed bus comprising at least one first and one second embedded clock data track (108); which includes the DCIC: a data recovery circuit (CDR) (116; 402A) configured to recover data from the first data track (Lane 3; Lane A 202; Lane B) and generate a phase correction signal from the first data track; and a data sampler (118; 402B, 402C) configured to recover the data from the second data track (Lane1, Lane2, Lane4, Lane5; LaneB 204; LaneA, LaneC) by sampling the second data track with a phase that is based on the first data track generated phase correction signaling reacts, and wherein the data recovery circuit (CDR) and the sampler each comprise first and second instances of a circuit that are configurable for operation in first and second configurations, wherein: In the first configuration (Master) (402A), the circuit is configured to restore the data and generate the phase correction signaling from a data track, and In the second configuration (Slave) (402B, 402C) the circuit is configured to receive the phase correction signaling from a peer circuit (Master) (116; 402A) and to restore the data from the data track based on the phase correction signaling received from the peer circuit. [2] Multi-chip module according to claim 1, wherein the phase correction signaling comprises phase increment and phase decrement signals. [3] Multi-chip module according to claim 1 or 2, wherein the data sampler (118; 402B, 402C) comprises a phase shifter (212; 410) and a sample and hold device (214; 406), wherein the phase shifter is configured to send a phase signal to the sample and hold device in response to the phase correction signal, and the sample and hold device is configured to sample the second data track in response to the phase signal. [4] Multi-chip module according to one of claims 1 to 3, wherein the circuit in the second configuration is further configured to transmit the phase control signaling to an additional peer circuit (master) (116; 402A). [5] Multi-chip module according to one of claims 1 to 4, wherein the circuit comprises a phase correction signal generation circuit (208; 408) which is enabled in the first configuration and disabled in the second configuration. [6] Multi-chip module according to any one of claims 1 to 5, wherein the circuit is configured to capture an initial clock phase of the data track in the first configuration and then switches to the second configuration and tracks clock phase fluctuations relative to the peer circuit based on the received phase correction signaling. [7] Method in a multi-chip module (MCM) (102) wherein the method comprises: Communicate in the multi-chip module (MCM) between a data-generating integrated circuit IC(DPIC) (104) and a data-consuming integrated circuit IC(DCIC) (106), both of which are mounted on the MCM substrate and connected to each other via a high-speed bus comprising at least a first and a second embedded clock data track (108); Recovering data from the first data track (Lane 3; Lane A 202; Lane B) and generating a phase correction signal from the first data track in the DCIC using a data recovery circuit (CDR) (116; 402A); and Recovering the data from the second data track (lane, lane 2, lane 4, lane 5; lane B 204; lane A, lane C) in the integrated circuit IC DCIC using a data sampler (118; 402B, 402C) by sampling the second data track with a phase that responds to the phase correction signaling generated from the first data track; and wherein the data recovery circuit (CDR) and the sampler each comprise a first and a second instance of a circuit that can be configured to operate in a first and a second configuration, and wherein the data and clock recovery comprises: in the first configuration (Master) (402A), a data recovery and generation of phase correction signaling from a data track by the circuit, and in the second configuration (Slave) (402B, 402C), receiving the phase correction signaling from a peer circuit (Master) (116; 402A) and restoring the data from the data track based on the phase correction signaling received from the peer circuit. [8] Method according to claim 7, wherein the phase correction signaling comprises phase increment and phase decrement signals. [9] Method according to claim 7 or 8, wherein the data sampler (118; 402B, 402C) comprises a phase shifter (212; 410) and a scan and hold device (214; 406), and wherein the scanning of the second data track comprises sending a phase signal from the phase shifter to the scan and hold device in response to the phase correction signal and scanning the second data track by the scan and hold device in response to the phase signal. [10] Method according to one of claims 7 to 9, further comprising in the second configuration the transmission of the phase control signaling from the circuit to an additional peer circuit (master) (116; 402A). [11] Method according to any one of claims 7 to 10, wherein the circuit comprises a phase correction signal generation circuit (208; 408) which is enabled in the first configuration and disabled in the second configuration. [12] Method according to any one of claims 7 to 11, comprising detecting, in the circuit, an initial clock phase of the data track in the first configuration, and then switching to the second configuration and tracking clock phase fluctuations relative to the peer circuit based on the received phase correction signaling.

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