Semiconductor chip device and method for testing the integrity of a memory

Abstract

Semiconductor chip device, comprising: a memory (101, 401) having a plurality of storage locations (102, 404); a memory access element (103, 404); an integrity check device (104, 404) which is configured to store a reference value (201, 301, 405) for a check function via values ​​stored in the memory locations (102, 404) and, upon a write access to a memory location (102, 404), to update a check value (202, 303, 406) with the value to be written by the write access if the check value (202, 303, 406) represents the value stored in the memory location (102, 404) before the write access, wherein the integrity check device (104, 404) is configured to generate the check value (202, 303, 406) for the check function, by reading the memory locations (102, 404) and, starting from an initial value, updating the check value (202, 303, 406) for each read memory location (102, 404) with the value read from the memory location (102, 404) so ​​that the check value (202, 303, 406) contains the value, wherein the integrity device is configured to wait for an idle processing of the memory access element (103, 404) in which the memory access element (103, 404) does not access the memory (101, 401) for the reading of the memory locations (102, 404); after generating the test value (202, 303, 406), to compare the reference value (201, 301, 405) and the test value (202, 303, 406) and to output a signal (407) depending on a result of the comparison.

Description

[0001] Embodiments generally relate to semiconductor chip devices such as data processing devices and data memories and methods for checking the integrity of a memory.

[0002] Electronic devices must be protected against attacks in a wide variety of applications. Typical examples are security ICs, hardware roots of trust (e.g., Trusted Platform Modules), chip cards that process and store secret data (e.g., keys or passwords) or data that must be protected from tampering (e.g., credit on a prepaid card), or control units, for example in a vehicle, whose correct functioning is important for the user's security. One possible point of attack for an electronic device is its memory, by manipulating which an attacker can obtain secret data or impair the correct functioning of the electronic device. Therefore, efficient mechanisms for protecting electronic memories against attacks (and also against spontaneous errors that are not the result of an attack) are desirable.

[0003] The publication DE 10 2017 202 611 A1 describes a device for forming a checksum for a memory area of ​​a memory device having a plurality of memory blocks, wherein the device is designed to determine a check value for each memory block as a function of the data of the respective memory block and to determine the checksum using a reversible mathematical function as a function of the check values ​​of the memory blocks of the memory area, as well as a device for modifying a checksum.

[0004] Publication EP 3 136 285 B1 describes a method for security-protected write operations and / or read operations on a memory module, wherein the following method steps are carried out: A first method step for transmitting user data to the memory module. A second method step for defining security information in a first memory area of ​​the memory module. A third method step for automatically updating at least one predefined part of the security information upon write access for the user data on the memory module and / or upon a predetermined trigger, wherein the memory module automatically determines the security information that is updated.

[0005] According to one embodiment, a semiconductor chip device is provided, comprising a memory with a plurality of memory locations, a memory access element and an integrity check device which is configured to store a reference value for a check function via values ​​stored in the memory locations, to update a check value with the value to be written by the write access during a write access to a memory location if the check value represents the value stored in the memory location before the write access, and to compare the reference value and the check value after generating the check value and to output a signal depending on a result of the comparison.

[0006] According to a further embodiment, a method for testing the integrity of a memory according to the semiconductor chip device described above is provided.

[0007] The figures do not represent actual dimensions but are intended to illustrate the principles of the various embodiments. Various embodiments are described below with reference to the following figures. Fig. 1 shows a data processing device according to an embodiment. Fig. 2 shows an example of a write access to a memory. Fig. 3 shows another example of a write access to the memory. Fig. 4 shows a semiconductor chip device according to an embodiment. Fig. 5 shows a flowchart illustrating a method for checking the integrity of a memory according to an embodiment.

[0008] Fig. 1 shows a data processing device 100.

[0009] The data processing device 100 may be any type of data processing device, such as a computer or a smartphone, a chip card (with any form factor) or a control device (e.g. with a microcontroller) used, for example, in a vehicle or an IoT (Internet of Things) device or an IoT device.

[0010] The data processing device 100 has a memory 101 containing storage locations 102. Each storage location 102 is formed by a group of memory cells, e.g., SRAM (Static Random Access Memory) cells or memory cells of another memory type, and enables the storage of a value (with a range of values ​​depending on the number of bits that can be stored by the group of memory cells).

[0011] A memory access element 103 accesses the memory 101, ie reads and / or writes data from or to the memory 101. The memory access element 103 can, for example, be a processor (e.g. a CPU) of the data processing device 100 (or an application executed on the processor or a process executed on the processor), which reads both data for processing or program code for execution from the memory 101 and writes results of the processing or execution into the memory 101.

[0012] However, the memory access element 103 can also be another element, such as a cache controller. For example, if the memory 101 is a cache memory, another memory for which the memory 101 is provided as a cache memory can be present, and a cache controller writes to the memory 101 to temporarily store ("cach") values ​​from the additional memory.

[0013] Values ​​stored in memory 101 are subject to attacks or even spontaneous errors (glitches) and can thus be altered. Particularly in safety-critical applications such as many chip cards and vehicle control systems, it is important to detect such changes and, thus, particularly attacks.

[0014] In order to prevent attacks on the memory 101, the memory integrity can be checked as a countermeasure in order to detect changes in the memory content caused, for example, by current peaks and disturbances, light or laser radiation, electromagnetic pulses, radioactive radiation, thermal effects or other effects.

[0015] Such a memory integrity check as a countermeasure against attacks can be carried out, for example, by means of: • EDC (Error Detection Code): Additional memory areas are provided for memory locations, each storing a type of checksum for the respective memory area. However, many such checksums must be stored for a memory, which requires a significant amount of additional chip space. • Parity: Only one bit is stored for a memory area to determine whether an odd or even number of bits is stored in the memory area. However, the error detection capability is very low in this case. • Digital signature: The memory contents are cryptographically hashed, and each resulting check value is compared with a corresponding expected value. However, a new check value must then be calculated for new content, and the contents of all memory cells to be protected must always be hashed. This leads to a loss of performance. • PFD (Post-Failure Detection): The memory is paused for its intended use (e.g., a CPU access), and an integrity checker (implementing a state machine) performs a sequential checksum calculation by accessing the memory contents. However, the interruption hinders data processing by the CPU and, for example, application execution, thus leading to a loss of performance.

[0016] According to various embodiments, a mechanism for checking the integrity of a memory is provided, which allows the integrity of the memory 101 to be checked in parallel with accesses to the memory by a memory access element 103, which is referred to as OAC (Online Array Check). In this case, a checksum (generally the value of a check function) is calculated during operation (i.e., at runtime) and determined as one of the two inputs (reference for the checksum or current verifier value for the checksum) for a verification in the form of a PFD. The mechanism can be implemented in an area-efficient manner and results in only a small loss of performance, since calculating the checksum does not hinder accesses to the memory by the memory access element 103 (at least in most cases).

[0017] According to various embodiments, an integrity checker 104 is provided that accesses memory 101. Integrity checker 104 can be implemented in hardware or in software running on a processor. The processor that implements integrity checker 104 can also be the same processor that implements memory access element 103. For example, a processor executes two processes, one corresponding to memory access element 103 (e.g., an application) and one implementing integrity checker 104.

[0018] The integrity device 104 has a first memory area 105 for a reference value and a second memory area 106 for a (current) check value of the checksum. Depending on the implementation of the integrity checking device 104, the memory areas 105, 106 are, for example, registers or memory areas in a working memory of the data processing device 100. The integrity checking device 104 also has a comparator 107 (which, depending on the implementation of the integrity device, can be a hardware circuit or a programmed function).

[0019] The integrity checker 104 calculates checksums over the contents of memory locations 102 at various times. Once it has completed calculating a checksum over the contents of memory locations 102 (i.e., over the values ​​stored therein) at a first point in time, it stores this sum as a reference value in the first memory area (reference memory area) 105. Alternatively, the reference value can also be generated by an initializing write to the memory area to be protected. It then begins to calculate a checksum over the contents of memory locations 102 again as a check value.Since the integrity checker 104 reads the memory locations 102 (and thus any changes to the memory locations are incorporated into the check value), and this reading does not occur simultaneously for all memory locations 102, the integrity checker 104 generates the check value over a certain period of time, with the second memory area (check value memory area) 106 always storing the current status of this check value. Starting from an initial value (typically zero), the integrity checker 104 updates the check value for each read memory location (e.g., by XORing the previous value with the read value) and stores the result in the second memory area 106, which can accordingly also be viewed as an accumulator.

[0020] Once it has finished calculating the check value (i.e., it has read all memory locations and updated the check value with the values ​​read from them, so that the check value contains all read values ​​in this sense), it compares the check value with the reference value. If the two do not match, it interprets this as an error (possibly caused by an attack) and outputs an alarm signal (or error signal), to which other components of the data processing device 100 can respond appropriately, e.g., by stopping processing, performing a reset, warning a user, etc.

[0021] If the test value matches the reference value, the integrity check device 104 begins to calculate a new test value.

[0022] According to various embodiments, a mechanism is provided that allows this periodic sequence (where a period is the time between two comparisons) to occur during the operation of the memory access element, ie while the memory access element also accesses the memory 101 and possibly changes the contents of memory locations. This mechanism is described below with reference to Fig. 2 and Fig. 3. It should be noted that in the event of an intentional change (write access), the reference value and, if applicable, the check value must be adjusted accordingly so that the intentional change is not recognized as an error.

[0023] Fig. 2 shows an example of a write access.

[0024] For simplicity, memory 101 has only eight memory locations. In practice, memory 101 can have significantly more memory locations. However, a total memory comprising several such memories 101 (e.g., each with its own integrity check device 104) can also be provided to enable more frequent checking (since fewer memory locations need to be read before a check, i.e., a comparison, can take place).

[0025] In this example, each memory location 102 stores an 8-bit value, represented in hexadecimal form. This is provided for simplicity's sake, and each memory location can also store more bits, such as 32 bits or 64 bits.

[0026] It is assumed that the integrity checker 104 has calculated a reference value 201 from the values ​​at a previous point in time, for example by XOR combination of the stored values, so that the reference value 201 is also an 8-bit value.

[0027] Since determining or setting the reference value 201 (e.g., after a previous comparison of the reference value and the previous check value), the integrity check device 104 has begun to calculate a (current) check value 202. To do so, it reads the memory locations sequentially and accumulates the read values ​​(e.g., by XOR combination).

[0028] It is believed that at a time when Fig. 2, the integrity checker 104 proceeds from top to bottom and has accumulated the values ​​of the first four memory locations. Now, a write access is performed by the memory access element. The seventh memory location is to be overwritten, in this example, the value 7A with the value 1E.

[0029] Since this affects the reference value, the integrity checker 104 adjusts the reference value accordingly by replacing 7A with 1E: Reference value_new=Reference value_old+7A+1E=46+7A+1E=22 where the XOR combination is written as '+'. To do this, it reads the old value 7A before writing the new value 1E to the memory location.

[0030] In addition, the integrity checker 104 checks whether the write access affects the current check value. Since the memory access occurs at the seventh memory location, this is not the case, as the check value only includes (contains) the first four values, and the write access changes the seventh value.

[0031] Fig. 3 shows another example of further access to memory locations.

[0032] The memory access is the same as in the example of Fig. 2. In this case, however, it is assumed that it takes place at a later time at which the integrity check device 104 has already calculated the check value 302 to such an extent that it includes the values ​​of the first seven memory locations.

[0033] With regard to the reference value 301, the integrity check device 104 changes compared to the example from Fig. 2 nothing, she must in turn replace it accordingly by Reference value_new=Reference value_old+7A+1E=46+7A+1E=22 adjust.

[0034] In contrast to the example of Fig. 2, the memory access in this example also affects the check value 302, since the value of the seventh memory location is already included in the check value. The integrity check device 104 detects this and adjusts the check value 302 by Pru¨fwert_neu=Pru¨fwert_old+7A+1E=78+7A+1E=1C To do this, it reads the old value 7A before writing the new value 1E to the memory location.

[0035] This allows the integrity check device 104 to correctly calculate the reference value and the check value, even when write accesses to the memory 101 are being performed. Thus, the memory access element 103 does not need to be stopped (or denied access to the memory 101) for the duration of the check value calculation, since the reference value and the check value are always adjusted accordingly.

[0036] A further problem, however, is that the integrity checker 104 wants to read a memory location in the memory 101 to calculate the check value, but the memory access element wants to access the memory 101 (read or write) at the same time. Such a collision can be resolved in various ways according to various embodiments: • A dual-port memory is used as the memory, with one port being used by the memory access element 103 and one port being used by the integrity check device 104. This allows simultaneous access to the memory. • The integrity checker 104 waits for a point in time at which the memory access element 103 does not access the memory 101. To increase the frequency of such points in time, an overall memory of the data processing device 100 can be divided into several memories 101. Even if the memory is not divided in this way, there is typically idle time during processing (e.g., a wait state) in which the memory access element 103 (e.g., a CPU) does not access the memory 101 and the integrity checker 104 can access it. It can also be provided that the integrity checker 104 can block accesses to the memory 101 by the memory access element 103 if the integrity checker 104 accesses the memory 101 too infrequently to obtain enough accesses within a period to calculate the check value.For example, if the memory 101 has 1000 memory locations, an access takes one clock cycle, and a period length of 4000 clock cycles (i.e., an integrity check every 4000 clock cycles) is provided, it is sufficient for the integrity check device 104 to access the memory 101 on average every fourth clock cycle. It can, for example, block accesses by the memory access element 103 if it has not received access for three clock cycles in order to reliably achieve this interval.

[0037] In summary, according to various embodiments, a semiconductor chip device is provided as described in Fig. 4 is shown.

[0038] Fig. 4 shows a semiconductor chip device 400 (ie, a device with or consisting of one or more semiconductor chips) according to an embodiment.

[0039] The data processing device 400 has a memory 401 with a plurality of memory locations 402 and a memory access element 403.

[0040] The data processing device 400 further comprises an integrity check device 404 which is configured to store a reference value 405 for a checksum of values ​​stored in the memory locations 402, to update a check value 406 with the value to be written by the write access during a write access to a memory location if the check value 406 represents (i.e. contains) the value stored in the memory location before the write access, and to compare the reference value 405 and the check value 406 after generating the check value (i.e. after generating the check value by reading out all stored values) and to output a signal 407 depending on a result of the comparison.

[0041] In other words, according to various embodiments, it is possible for an integrity check of a memory to be performed based on a check value of a check function during operation (i.e., without pausing processing that accesses the memory) by adjusting the check value, if necessary, during a write access. This avoids losses in processing performance caused by the integrity check. Compared to an integrity check using EDCs, a significantly smaller space requirement is required for the integrity check, since only two values ​​for the check function (reference value and check value for the check function) need to be stored.

[0042] The memory locations 402 are not necessarily all memory locations of the memory 401, ie the method can also be applied to a subset of the memory locations of a memory.

[0043] The test function is, for example, a checksum such as an XOR operation of the stored values ​​or, more generally, a commutative operation of a mapping of the contents of the memory locations to be checked, ie, if the values ​​W 0 , W 1 , .... W n are, then the test value is equal to f 0 (W0) + f 1 (W1) + .. f n (W n ) with illustrations (e.g. weightings) f 0 ...f n .

[0044] According to various embodiments, a method is carried out as described in Fig. 5 is shown.

[0045] Fig. 5 shows a flowchart 500 illustrating a method for checking the integrity of a memory.

[0046] In 501, a reference value for a test function is stored over the values ​​stored in memory locations of a memory.

[0047] In 502, upon a write access to a memory location, a check value is updated with the value to be written by the write access if the check value represents the value stored in the memory location before the write access.

[0048] In 503, after the test value has been generated, the reference value and the test value are compared and a signal is output depending on the result of the comparison.

[0049] According to one embodiment, a data processing device is provided with storage means for storing a reference value for a checksum over the values ​​stored in memory locations of a memory, updating means for updating, in the case of a write access to a memory location, a check value with the value to be written by the write access if the check value represents the value stored in the memory location before the write access, and comparison means for comparing, after generating the check value, the reference value and the check value and outputting an error signal depending on a result of the comparison.

[0050] Various examples of implementation are given below.

[0051] Embodiment 1 is a semiconductor chip device as described with reference to Fig. 4 described.

[0052] Embodiment 2 is a semiconductor chip device according to embodiment 1, wherein the integrity check device is configured to form the check value at times when the access element does not need to provide data for other receivers.

[0053] Embodiment 3 is a semiconductor chip device according to embodiment 2 or 3, wherein the integrity check device is configured to generate the check value for the check function by reading the memory locations and, starting from an initial value, updates the check value for each read memory location with the value read from the memory location, so that the check value contains the value, wherein the integrity check device is configured to check, upon a write access to the memory by the memory access element, whether the write access should be made to a memory location that stores a value with which it has already updated the check value for the check function, and, if the write access should be made to a memory location that stores a value with which it has already updated the check value for the check function, to read the memory location again and adapt the check value thus,that instead of the read value, it contains the value to be written by the memory access.

[0054] Embodiment 4 is a semiconductor chip device according to any one of embodiments 1 to 3, wherein the test function is a commutative operation of a mapping of the stored values.

[0055] Embodiment 5 is a semiconductor chip device according to embodiment 4, wherein the commutative operation is an XOR combination.

[0056] Embodiment 6 is a semiconductor chip device according to one of the embodiments 1 to 5, wherein the integrity check device is configured to generate the reference value so that it represents the values ​​stored in the memory locations, and is configured to adapt the reference value during the write access so that it represents the value to be written by the memory access instead of the value stored in the memory cell to which the write access is made before the write access.

[0057] Embodiment 7 is a semiconductor chip device according to one of embodiments 1 to 6, wherein the memory is a dual-port memory with a first port and a second port, the memory access element is configured to access the memory by means of the first port, and the integrity check device is configured to read the stored values ​​by means of the second port.

[0058] Embodiment 8 is a semiconductor chip device according to one of embodiments 1 to 6, wherein the integrity check device is configured to wait for a time at which the memory access element is not accessing the memory in order to read out one of the stored values ​​for generating the check value.

[0059] Embodiment 9 is a semiconductor chip device according to embodiment 8, wherein the integrity check device is configured to prohibit the memory access element from accessing the memory and instead to perform a read access to the memory to generate the check value if it would otherwise have to wait more than a maximum time for a time at which the memory access element does not access the memory.

[0060] Embodiment 10 is a semiconductor chip device according to any one of embodiments 1 to 9, wherein the memory access element is a data processing unit that accesses the memory, wherein the memory is a working memory or one or more registers.

[0061] Embodiment 11 is a semiconductor chip device according to any one of embodiments 1 to 10, wherein the integrity check device is configured to output the signal when the reference value does not match the check value.

[0062] Embodiment 12 is a semiconductor chip device according to one of embodiments 1 to 11, wherein the one integrity check device is configured to periodically generate the check value, compare it with the reference value, and output the signal depending on a result of the comparison.

[0063] Embodiment 13 is a method for checking the integrity of a memory as described above with reference to Fig. 5 described.

[0064] Embodiments described in connection with the semiconductor chip device apply analogously to the method for testing the integrity of a memory.

[0065] The procedure of Fig.5 may be performed by one or more computers (or, more generally, semiconductor chip devices) having one or more data processing units. The term "data processing unit" may be understood as any type of entity that enables the processing of data or signals. The data or signals may, for example, be handled according to at least one (i.e., one or more than one) specific function performed by the data processing unit. A data processing unit may be an analog circuit, a digital circuit, a logic circuit, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a crypto processor, a cache controller, a DMA controller, a field-programmable gate array (FPGA) integrated circuit, or any combination thereof.Any other way of implementing the respective functions described in more detail herein can also be understood as a data processing unit or logic circuit arrangement. One or more of the method steps described in detail here can be carried out (e.g., implemented) by a data processing unit through one or more special functions performed by the data processing unit. One or more such data processing units can implement one or more data processing devices. The integrity checking device is, for example, configured to generate the check value while a data processing unit executes a program that processes values ​​that the memory stores and / or contains instructions that the memory stores. The data processing unit is then, for example, the memory access element. List of reference symbols 100 data processing device 101 Memory 102 memory locations 103 Access element 104 Integrity testing device 105, 106 Memory areas for checksums 107 comparators 201 Reference value 202 test value 301 Reference value 302 test value 400 semiconductor chip devices 401 Memory 402 memory locations 403 Access Element 404 Integrity check device 405 Reference value 406 Test value 407 Signal 500 Flowchart 501-503 Processing

Claims

[1] A semiconductor chip device comprising: a memory (101, 401) having a plurality of storage locations (102, 404); a memory access element (103, 404); an integrity check device (104, 404) which is configured to store a reference value (201, 301, 405) for a check function via values ​​stored in the memory locations (102, 404) and, upon a write access to a memory location (102, 404), to update a check value (202, 303, 406) with the value to be written by the write access if the check value (202, 303, 406) represents the value stored in the memory location (102, 404) before the write access, wherein the integrity check device (104, 404) is configured to generate the check value (202, 303, 406) for the check function, by reading the memory locations (102, 404) and, starting from an initial value, updating the check value (202, 303, 406) for each read memory location (102, 404) with the value read from the memory location (102, 404) so ​​that the check value (202, 303, 406) contains the value, wherein the integrity device is configured to wait for an idle processing of the memory access element (103, 404) in which the memory access element (103, 404) does not access the memory (101, 401) for the reading of the memory locations (102, 404); after generating the test value (202, 303, 406), to compare the reference value (201, 301, 405) and the test value (202, 303, 406) and to output a signal (407) depending on a result of the comparison. [2] Semiconductor chip device according to claim 1, wherein the integrity checking device (104, 404) is arranged to form the check value (202, 303, 406) at times when the access element (103, 404) does not have to provide data for other receivers. [3] Semiconductor chip device according to claim 2, wherein the integrity checking device (104, 404) is configured to check, during a write access to the memory (101, 401) by the memory access element (103, 404), whether the write access is to be made to a memory location (102, 404) that stores a value with which it has already updated the check value (202, 303, 406) for the check function, and, if the write access is to be made to a memory location (102, 404) that stores a value with which it has already updated the check value (202, 303, 406) for the check function, to read out the memory location (102, 404) again and to adapt the check value (202, 303, 406) such that it contains the value to be written by the memory access instead of the read-out value. [4] Semiconductor chip device according to one of claims 1 to 3, wherein the test function is a commutative operation of a mapping of the stored values. [5] The semiconductor chip device according to claim 4, wherein the commutative operation is an XOR combination. [6] Semiconductor chip device according to one of claims 1 to 5, wherein the integrity check device (104, 404) is arranged to generate the reference value (201, 301, 405) so that it represents the values ​​stored in the memory locations (102, 404), and is arranged to adapt the reference value (201, 301, 405) during the write access so that it represents the value to be written by the memory access instead of the value stored in the memory cell to which the write access is made before the write access. [7] Semiconductor chip device according to one of claims 1 to 6, wherein the memory (101, 401) is a dual-port memory with a first port and a second port, the memory access element (103, 404) is configured to access the memory (101, 401) by means of the first port and the integrity check device (104, 404) is configured to read out the stored values ​​by means of the second port. [8] Semiconductor chip device according to one of claims 1 to 6, wherein the integrity checking device (104, 404) is configured to wait for a time at which the memory access element (103, 404) is not accessing the memory (101, 401) in order to read out one of the stored values ​​for generating the check value (202, 303, 406). [9] Semiconductor chip device according to claim 8, wherein the integrity check device (104, 404) is configured to prohibit the memory access element (103, 404) from accessing the memory (101, 401) and instead to perform a read access to the memory (101, 401) to generate the check value (202, 303, 406) if it would otherwise have to wait more than a maximum time for a point in time at which the memory access element (103, 404) does not access the memory (101, 401). [10] Semiconductor chip device according to one of claims 1 to 9, wherein the memory access element (103, 404) is a data processing unit that accesses the memory (101, 401), the memory (101, 401) being a working memory or one or more registers. [11] Semiconductor chip device according to one of claims 1 to 10, wherein the integrity check device (104, 404) is arranged to output the signal (407) if the reference value (201, 301, 405) does not match the check value (202, 303, 406). [12] Semiconductor chip device according to one of claims 1 to 11, wherein the one integrity test device (104, 404) is arranged to generate the test value (202, 303, 406) periodically, to compare it with the reference value (201, 301, 405) and to output the signal (407) depending on a result of the comparison. [13] A method for checking the integrity of a memory (101, 401), comprising: Storing a reference value (201, 301, 405) for a test function via the values ​​stored in memory locations (102, 404) of a memory (101, 401); Updating, in the case of a write access by a memory access element (103, 404) to a memory location (102, 404), a check value (202, 303, 406) with the value to be written by the write access, if the check value (202, 303, 406) represents the value stored in the memory location (102, 404) before the write access, wherein the check value (202, 303, 406) is generated for the check function, is carried out by reading the memory locations (102, 404) and, starting from an initial value, updating the test value (202, 303, 406) for each read memory location (102, 404) with the value read from the memory location (102, 404), so that the test value (202, 303, 406) contains the value, wherein, for reading the memory locations (102, 404), an idle processing of the memory access element (103, 404) is waited for, in which the memory access element (103, 404) does not access the memory (101, 401), and Comparing, after generating the test value (202, 303, 406), the reference value (201, 301, 405) and the test value (202, 303, 406) and outputting a signal (407) depending on a result of the comparison.

Images