Semiconductor devices and power converter device

Abstract

Semiconductor device, exhibiting: - an insulating layer (1); - a foil conductor (2) which is provided on a lower surface of the insulating layer (1); - a circuit structure (3, 3a, 3b) which is provided on an upper surface of the insulating layer (1); - a multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) which are mounted on an upper surface of the circuit structure (3, 3a, 3b); - a first wiring board (6) which is connected to the upper surface of the circuit structure (3, 3a, 3b) and allows an externally supplied current to flow through the circuit structure (3, 3a, 3b); and - a second wiring board (7, 7a, 7b) which connects the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) and allows the current flowing through the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) via the circuit structure (3, 3a, 3b) to flow, where: - the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) are arranged along one extension direction of the second wiring board (7, 7a, 7b), - in a current path which leads from the first wiring board (6) through the second wiring board (7, 7a, 7b) via the circuit structure (3, 3a, 3b) and the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16), an electrical resistance of the current path which leads through the semiconductor element arranged on a downstream side is lower than an electrical resistance of the current path which leads through the semiconductor element arranged on an upstream side, and - the current path from the first wiring board (6) to the second wiring board (7) is U-shaped in a top view.

Description

Background of the invention; Field of the invention

[0001] The present invention relates to semiconductor devices and a power converter device. Description of the state of the art

[0002] Typically, in semiconductor devices, a reduction in wiring inductance is required. For example, Japanese patent application JP 2015-018 943 A discloses a technique in which, in a power semiconductor module comprising a first wiring layer that contacts the contact electrodes of a semiconductor element and a second wiring layer that is opposite and electrically connected to the first wiring layer, the wiring inductance is reduced by reversing the direction of the current flowing through the first wiring layer and the direction of the current flowing through the second wiring layer.

[0003] However, in the technology described in Japanese patent application JP 2015-018 943 A, it is necessary that the first wiring layer and the second wiring layer are vertically opposite each other, and therefore there is little degree of freedom in terms of design, which has left this a problem of difficulty with regard to miniaturizing a device.

[0004] JP 2010-153 639 A relates to a power semiconductor device capable of suppressing property variations in a resin-based insulating layer, and to a method for its fabrication. The power semiconductor device consists of a power semiconductor element, a termination frame, a heat spreader, and a heat dissipation element. The heat spreader has a surface on which the power semiconductor element is mounted. The heat dissipation element is connected to the opposite surface of the heat spreader. The heat dissipation element comprises a resin insulating layer and a pair of metal foils bonded to the resin insulating layer on both sides.

[0005] CN 1 13 140 528 A shows a semiconductor device that functions reliably even under temperature fluctuations. A heat dissipation layer with semiconductor elements, a portion of a copper plate connected to the heat dissipation layer via a resin insulating layer, a portion of a first connection frame connected to the heat dissipation layer via a bonding material, and a portion of a second connection frame connected to the semiconductor elements via bonding materials are embedded in a resin potting compound. The portion of the copper plate exposed from the resin potting compound is welded to the heat sink. The thickness of the copper plate is a maximum of 0.3 mm and does not exceed the thickness of the heat dissipation layer. The heat dissipation element is connected to the opposite surface of the heat spreader.The heat dissipation element consists of a resin insulating layer and two metal foils that are bonded to the resin insulating layer on both sides.

[0006] JP 2011-086 889 A discloses a semiconductor device that reduces assembly effort for the customer. A single package and another single package are bonded together on a metal plate using an insulating adhesive film to form a composite package. This reduces the number of packages to be assembled when using three composite packages compared to assembling six individual packages, thus minimizing assembly effort for the customer. Summary

[0007] It is an object of the present invention to provide a technique which ensures both a miniaturization of a semiconductor device and a reduction of wiring inductance.

[0008] The problem underlying the invention is solved according to the invention, in the case of a semiconductor device, alternatively by the features of claims 1 and 2, and in the case of a power converter device, by the features of claim 11. Advantageous further developments are the subject of the respective dependent claims.

[0009] According to the present invention, a semiconductor device comprises, among other things, an insulating layer, a foil conductor, a circuit structure, a plurality of semiconductor elements, a first wiring board, and a second wiring board. The foil conductor is provided on the lower surface of the insulating layer. The circuit structure is provided on the upper surface of the insulating layer. The plurality of semiconductor elements is mounted on the upper surface of the circuit structure. The first wiring board is connected to the upper surface of the circuit structure and allows an externally supplied current to flow through the circuit structure.

[0010] The second wiring board connects the multitude of semiconductor elements and allows the current that has flowed through the circuit structure to continue flowing. The multitude of semiconductor elements is arranged along the direction of extension of the second wiring board. In a current path from the first wiring board through the second wiring board, across the circuit structure, and through the multitude of semiconductor elements, the electrical resistance of the current path through the semiconductor element located downstream is lower than the electrical resistance of the current path through the semiconductor element located upstream.

[0011] In the current path that runs from the first wiring board through the second wiring board, across the circuit structure and the numerous semiconductor elements, more current flows through the path through the semiconductor element located on the downstream side, which is positioned closer to the foil conductor, than through the path through the semiconductor element located on the upstream side. This increases the inductance cancellation effect due to the magnetic flux generated by the foil conductor. This ensures a reduction in wiring inductance.

[0012] Furthermore, it is not necessary for the first and second wiring boards to be vertically opposed, thus ensuring design freedom. This allows for both a miniaturization of the semiconductor device and a reduction in wiring inductance.

[0013] These and other tasks, features, aspects and advantages of the present invention will become clearer with reference to the following detailed description of the present invention in conjunction with the accompanying figures. Brief description of the characters Fig. Figure 1 is a cross-sectional view illustrating an example of a semiconductor device according to a first embodiment to explain the technical background of the present invention; Fig. Figure 2 is a perspective view illustrating the example of the semiconductor device according to the first embodiment to explain the technical background of the present invention; Fig. Figure 3 is a perspective view illustrating a further example of the semiconductor device according to the first embodiment to explain the technical background of the present invention; Fig. Figure 4 is a perspective view illustrating a semiconductor device according to a modification example of the invention based on the first embodiment to explain the technical background of the present invention; Fig. Figure 5 is a perspective view of a semiconductor device according to a second embodiment of the invention; Fig. 6 is a circuit diagram of the semiconductor device according to the invention; Fig. Figure 7 is a perspective view of a semiconductor device according to a third embodiment of the invention; and Fig. Figure 8 is a block diagram illustrating a configuration of a power converter system to which a power converter device according to the invention is applied. Description of preferred embodiments <Erste Ausführungsform zum technischen Hintergrund><Konfiguration der Halbleitervorrichtung>

[0014] The first embodiment, used to explain the technical background of the present invention, is described with reference to the figures. Fig. Figure 1 is a cross-sectional view illustrating an example of a semiconductor device according to the first embodiment to explain the technical background of the present invention.

[0015] As in Fig. As illustrated in Figure 1, the semiconductor device comprises an insulating layer 1, a foil conductor 2, a circuit structure 3, a plurality of semiconductor elements, a wiring board 6 serving as a first wiring board, a wiring board 7 serving as a second wiring board, a sealing material 9, and the cooler 10. First, an example is described in which a plurality of semiconductor elements is a pair of semiconductor elements 4 and 5.

[0016] The foil conductor 2 is provided on the lower surface of the insulating layer 1. The insulating layer 1 and the foil conductor 2 are formed in an elongated rectangular shape, which are the same size when viewed from above. The circuit structure 3 is composed of copper with low conductor resistance and is provided on the upper surface of the insulating layer 1. The insulating layer 3 is smaller than the insulating layer 1 and is formed in an elongated rectangular shape when viewed from above.

[0017] The pair of semiconductor elements 4 and 5 is mounted on the upper surface of the circuit structure 3, connected by the sealing materials 8c and 8f, respectively. Furthermore, the pair of semiconductor elements 4 and 5 is arranged along the direction of extension of the wiring board 7. The semiconductor material for the pair of semiconductor elements 4 and 5 is, for example, silicon (Si) or silicon carbide (SiC).

[0018] Wiring board 6 is connected to the upper surface of circuit structure 3 by means of a connecting material 8b, and it allows an externally supplied current to flow through circuit structure 3. Wiring board 7 connects the pair of semiconductor elements 4 and 5 to connecting materials 8d and 8f respectively, and allows the current flowing through circuit structure 3 and the pair of semiconductor elements 4 and 5 to flow. The current flowing through wiring board 7 may or may not be output to the outside.

[0019] The sealing material 9 is an epoxy resin or the like, and it seals a section which excludes the lower surface of the foil conductor 2, the insulating layer 1, the circuit structure 3, the pair of semiconductor elements 4 and 5, a section which excludes an end section of the wiring board 6, and a section which excludes a section of the wiring board 7.

[0020] The cooler 10 is made of copper, aluminum, or the like and is connected to the lower surface of the foil conductor 2 by means of a connecting material 8a. The connecting materials 8a to 8f are solder, silver, or the like.

[0021] Next, the current paths of the semiconductor device will be described with reference to Fig. 2 described. Fig. Figure 1 is a perspective view illustrating an example of the semiconductor device according to the first embodiment to explain the technical background of the present invention, and it is a perspective view of the semiconductor device in which an illustration of the sealing material 9 and the cooler 10 is omitted. Furthermore, the illustration of the sealing material 9 and the cooler 10 is also omitted in the subsequent perspective view.

[0022] As in Fig. As illustrated in Figure 2, the current supplied by the wiring board 6 is output by the wiring board 7 after flowing through the pair of semiconductor elements 4 and 5 and through the circuit structure 3. In a current path leading from the wiring board 6 through the wiring board 7, via the circuit structure 3 and the semiconductor elements 4 and 5, the electrical resistance of the current path passing through the downstream semiconductor element 5 is lower than the electrical resistance of the current path passing through the upstream semiconductor element 4.

[0023] This is described in detail. The current path between the pair of semiconductor elements 4 and 5 branches into two on the lower surface of semiconductor element 4. A first current path is a current path that runs through semiconductor element 5 via the circuit structure 3, without passing through semiconductor element 4. A second current path is a current path that runs through the wiring board 7 via semiconductor element 4.

[0024] The ratio of R1 <R2 ist erfüllt, wobei R1 den elektrischen Widerstand des ersten Strompfades repräsentiert und R2 den elektrischen Widerstand des zweiten Strompfades repräsentiert. Infolgedessen fließt mehr Strom durch den ersten Strompfad, welcher sich näher am Folienleiter 2 befindet, als durch den zweiten Strompfad, sodass der Induktivitätsaufhebungseffekt aufgrund des magnetischen Flusses, welcher durch den Folienleiter 2 ausgebildet wird, zunimmt. Dies stellt eine Reduzierung der Verdrahtungsinduktivität sicher.

[0025] There are several methods for establishing the ratio R1. <R2. Eine ist die Erhöhung der Dicke der Schaltungsstruktur 3. Indem die Dicke der Schaltungsstruktur 3 zum Beispiel auf 0,2 mm oder mehr festgelegt wird, reduziert sich der Leiterwiderstand der Schaltungsstruktur 3, was es einfacher macht, das Verhältnis von R1<R2 herzustellen. Darüber hinaus existiert ein Verfahren zum Ändern der Dicke der Verdrahtungsplatine 7, des Halbleiterelements 4, oder der Verbindungsmaterialien 8c und 8d, und ein Verfahren zum Ändern des Materials der Schaltungsstruktur 3, der Verdrahtungsplatine 7, des Halbleiterelements 4, oder der Verbindungsmaterialien 8c und 8d. Ferner kann als Methode zur Realisierung der Reduzierung der Verdrahtungsinduktivität zum Beispiel die Dicke der isolierenden Schicht 1 auf 0,5 mm oder weniger reduziert werden, um den Aufhebungseffekt der Induktivität aufgrund des magnetischen Flusses, welcher durch den Folienleiter 2 ausgebildet wird, zu steigern.

[0026] The pair of semiconductor elements 4 and 5 is each an insulated-gate bipolar transistor (IGBT) and a freewheeling diode (FWD). The FWD is semiconductor element 4, which is mounted on the upstream side of the current path between the pair of semiconductor elements 4 and 5. The IGBT is semiconductor element 5, which is mounted on the downstream side of the current path between the pair of semiconductor elements 4 and 5. That is, semiconductor element 4, which is the FWD, is located on the current inlet side (collector terminal), and semiconductor element 5, which is the IGBT, is located on the current outlet side (emitter terminal). The electrical resistance of semiconductor element 4, which is the FWD, is greater than the electrical resistance of semiconductor element 5, which is the IGBT; therefore, the ratio of R1 <R2 leicht hergestellt werden.

[0027] Next, a case relating to Fig. 3 described in which the multitude of semiconductor elements are three semiconductor elements 4, 5 and 16. Fig. Figure 3 is a perspective view illustrating a further example of the semiconductor device according to the first embodiment to explain the technical background of the present invention.

[0028] As in Fig. As illustrated in Figure 3, the current supplied by the wiring board 6 is output by the wiring board 7 after flowing through the semiconductor elements 4, 5, and 16 through the circuit structure 3. The current path between the semiconductor elements 4, 5, and 16 branches into three on the lower surface of semiconductor element 4. A first current path is a current path that passes through semiconductor element 16 via the circuit structure 3 without passing through semiconductor elements 4 and 5. A second current path is a current path that passes through the wiring board 7 via the circuit structure 3 and semiconductor element 5 without passing through semiconductor element 4. A third current path is a current path that passes through the wiring board 7 via semiconductor element 4.

[0029] The ratio of R1 <R2<R3 ist erfüllt, wobei R1 den elektrischen Widerstand des ersten Strompfades repräsentiert, R2 den elektrischen Widerstand des zweiten Strompfades repräsentiert, und R3 den elektrischen Widerstand des dritten Strompfades repräsentiert. Infolgedessen fließt mehr Strom durch den zweiten Strompfad, welcher sich näher an dem Folienleiter 2 befindet als der dritte Strompfad, darüber hinaus fließt mehr Strom durch den ersten Strompfad, welcher sich näher an dem Folienleiter 2 befindet als der zweite Strompfad, sodass der Induktivitätsaufhebungseffekt aufgrund des magnetischen Flusses, welcher durch den Folienleiter 2 ausgebildet wird, zunimmt. Dies stellt eine Reduzierung der Verdrahtungsinduktivität sicher.

[0030] It should be noted that although the Fig. 1 and Fig. 2. Illustrate the case in which the multitude of semiconductor elements are a pair of semiconductor elements 4 and 5, and Fig. Figure 3 illustrates the case in which the semiconductor elements are three semiconductor elements 4, 5, and 16; the number of semiconductor elements is not specifically limited as long as it is two or more. The same applies in this respect to a modification example of the first embodiment and the second and third embodiments according to the invention, which will be described later. <effekt>

[0031] As described above, the semiconductor device according to the first embodiment, for the purpose of explaining the technical background of the present invention, comprises the insulating layer 1, the foil conductor 2 which is provided on the lower surface of the insulating layer 1, the circuit structure 3 which is provided on the upper surface of the insulating layer 1, the plurality of semiconductor elements which are provided on the upper surface of the circuit structure 3, the wiring board 6 which is connected to the upper surface of the circuit structure 3 and allows an externally supplied current to flow through the circuit structure 3, and the wiring board 7 which connects the plurality of semiconductor elements and allows the current which has flowed through the plurality of semiconductor elements via the circuit structure 3 to flow.wherein the plurality of semiconductor elements are arranged along the extension direction of the wiring board 7 and wherein in the current path which leads from the wiring board 6 through the wiring board 7 via the circuit structure 3 and the plurality of semiconductor elements, the electrical resistance of the current path which leads through the semiconductor element arranged on the downstream side is lower than the electrical resistance of the current path which leads through the semiconductor element arranged on the upstream side.

[0032] Therefore, in the current path leading from the wiring board 6 through the wiring board 7, across the circuit structure 3 and the multitude of semiconductor elements, more current flows through the current path located on the downstream side, which is positioned closer to the foil conductor 2, than through the current path located on the upstream side. This increases the inductance cancellation effect due to the magnetic flux formed by the foil conductor 2. This ensures a reduction in the wiring inductance.

[0033] Furthermore, it is not necessary for the wiring board 6 and the wiring board 7 to be vertically opposed to each other; the degree of freedom regarding the design is ensured. This allows for both the miniaturization of the semiconductor device and the reduction of the wiring inductance.

[0034] For example, as in Fig. Figure 2 illustrates the multitude of semiconductor elements, a pair of semiconductor elements 4 and 5, the current path between the pair of semiconductor elements 4 and 5 branches into the first current path, which does not pass through either of the semiconductor elements 4 arranged on the upstream side and which passes through the other semiconductor element 5 arranged on the downstream side via the circuit structure 3, and into the second current path, which passes through the wiring board 7 via the semiconductor element 4, and the ratio of R1 <R2 ist erfüllt, wobei R1 den elektrischen Widerstand des ersten Strompfades und R2 den elektrischen Widerstand des zweiten Strompfades repräsentiert.

[0035] Accordingly, more current flows through the first current path, which is closer to the foil conductor 2 than the second current path, so that the inductance cancellation effect due to the magnetic flux formed by the foil conductor 2 increases. This ensures a reduction in the wiring inductance.

[0036] Furthermore, the multitude of semiconductor elements comprises an IGBT and an FWD, with the FWD mounted on the upstream side of the IGBT. Accordingly, the electrical resistance of the FWD is greater than the electrical resistance of the IGBT; this easily establishes the aforementioned ratio of the electrical resistance of the current path passing through the downstream semiconductor element to the electrical resistance of the current path passing through the upstream semiconductor element.

[0037] Furthermore, the circuit structure 3 contains copper; by using copper, which has a low conductor resistance, as the material for the circuit structure 3, the aforementioned ratio of the electrical resistance of the current path passing through the semiconductor element located on the downstream side and the electrical resistance of the current path passing through the semiconductor element located on the upstream side is easily achieved.

[0038] Furthermore, the thickness of the circuit structure 3 is 0.2 mm or more; by ensuring the thickness of the circuit structure 3, the above ratio of the electrical resistance of the current path passing through the downstream semiconductor element and the electrical resistance of the current path passing through the upstream semiconductor element can be easily achieved.

[0039] Furthermore, the thickness of the insulating layer 1 is 0.5 mm or less; thus, by reducing the thickness of the insulating layer 1, the inductance cancellation effect due to the magnetic flux generated by the foil conductor 2 increases when the current flows from the current inlet (collector terminal) to the current outlet (emitter terminal), thereby ensuring that the wiring inductance is reduced.

[0040] Furthermore, the semiconductor material of the multitude of semiconductor elements is SiC; this results in a reduction of losses in the high-frequency application area, which is an advantage of SiC and improves the lifetime of the semiconductor device. <Erfindungsgemäßes Modifikationsbeispiel auf der Grundlage der ersten Ausführungsform>

[0041] Next, a modification example according to the invention is described based on the first embodiment to explain the technical background of the present invention. Fig. Figure 4 is a perspective view of a semiconductor device according to the modification example of the invention based on the first embodiment to explain the technical background of the present invention.

[0042] As in Fig. As illustrated in Figure 4, the insulating layer 1 and the foil conductor 2 are formed in a top view as elongated rectangular shapes of the same size. The circuit structure 3 is formed in a U-shape with two straight sections in a top view. The wiring board 6 and the wiring board 7 are each arranged along two straight sections and are connected to the top surface of the two straight sections. The current inlet (collector terminal) and the current outlet (emitter terminal) protrude from the same surface of the sealing material 9 (see Figure 4). Fig. 1) stands out, and the current path from wiring board 6 to wiring board 7 is U-shaped, that is, loop-shaped in a top view. As a result, the leakage flux between wiring board 6 and wiring board 7 is reduced, thus ensuring a reduction in wiring inductance. It should be noted that the current path from wiring board 6 to wiring board 7, which is U-shaped in a top view, contributes to the reduction in wiring inductance; therefore, it is not necessary for the circuit structure 3 and wiring boards 6 and 7 to be U-shaped in a top view.

[0043] The array of semiconductor elements can include backward-conducting IGBTs. This configuration reduces the number of semiconductor elements mounted on the semiconductor device, thereby ensuring further miniaturization of the device.

[0044] The foregoing modification example is applicable to the second and third embodiments according to the invention, which will be described later. <Erfindungsgemäße zweite Ausführungsform>

[0045] Next, a semiconductor device according to the second embodiment of the invention will be described. Fig. Figure 5 is a perspective view of the semiconductor device according to the second embodiment of the invention. Fig. Figure 6 is a circuit diagram of the semiconductor device according to the second embodiment of the invention. It should be noted that in the second embodiment of the invention, the description of the same components as those described in the first embodiment to explain the technical background of the present invention is omitted here.

[0046] As in the Fig. 5 and Fig. As illustrated in Figure 6, the semiconductor device in the second embodiment according to the invention comprises a plurality of (for example, two) phases, which are composed of pairs of semiconductor elements as a plurality of semiconductor elements. Although the Fig. 5 and Fig. 6 To illustrate an example which has two phases, a high-side and a low-side, the semiconductor device can have three or more phases.

[0047] The semiconductor device comprises an insulating layer 1, a foil conductor 2, circuit structures 3a and 3b, pairs of semiconductor elements 4a and 5a, a pair of semiconductor elements 4b and 5b, a wiring board 6 as a first wiring board, wiring boards 7a and 7b as second wiring boards, a sealing material 9 (see Fig. 1), and a cooler 10 (see Fig. 1).

[0048] The foil conductor 2 is provided on the lower surface of the insulating layer 1. The insulating layer 1 and the foil conductor 2 are formed in an elongated rectangular shape, which are the same size when viewed from above. The circuit structures 3a and 3b are composed of copper with low conductor resistance and are provided on the upper surface of the insulating layer 1. The circuit structures 3a and 3b are smaller than the insulating layer 1 and are formed in an elongated rectangular shape when viewed from above.

[0049] The pair of semiconductor elements 4a and 5a is each mounted on the upper surface of the circuit structure 3a by being connected to it. The pair of semiconductor elements 4b and 5b is also each mounted on the upper surface of the circuit structure 3b by being connected to it. The semiconductor material for the pair of semiconductor elements 4a and 5a and the pair of semiconductor elements 4b and 5b is, for example, silicon (Si) or silicon carbide (SiC).

[0050] Wiring board 6 is connected to the top surface of circuit structure 3a and allows an externally supplied current to flow through circuit structure 3a. Wiring board 7a connects the pair of semiconductor elements 4a and 5a and is connected to the top surface of circuit structure 3b. It outputs the current flowing through circuit structure 3a and the pair of semiconductor elements 4a and 5a to the outside and to circuit structure 3b. Wiring board 7b connects the pair of semiconductor elements 4b and 5b and outputs the current flowing through wiring board 7a and the pair of semiconductor elements 4b and 5b to the outside.

[0051] For connecting the respective element, a connecting material is used, as in the case of the first embodiment, to illustrate the technical background of the present invention. One end section of the wiring board 6 is a C1 termination. One end section of the wiring board 7a is an E1C2 connection, and one end section of the wiring board 7b is an E2 connection.

[0052] As described above, the semiconductor device according to the second embodiment of the invention comprises a plurality of phases, which are composed of a plurality of semiconductor elements; this ensures the reduction of the wiring inductance itself in the semiconductor device, which has the plurality of phases. <Erfindungsgemäße dritte Ausführungsform>

[0053] Next, a semiconductor device according to a third embodiment of the invention will be described. Fig. Figure 7 is a perspective view of the semiconductor device according to the third embodiment of the invention. It should be noted that in the third embodiment of the invention, the description of the same components as those described in the first embodiment to explain the technical background of the present invention and in the second embodiment of the invention has been omitted here.

[0054] As in Fig. As illustrated in Figure 7, in the third embodiment of the invention, the foil conductors 12a and 12b are each laminated onto the lower surfaces of the wiring boards 6 and 7 over insulating layers 11a and 11b. As a result, the wiring boards 6 and 7 form parallel plates, with the insulating layers 11a and 11b inserted vertically between them.

[0055] As described above, in the semiconductor device according to the third embodiment of the invention, foil conductors 12a and 12b, which differ from foil conductor 2, are laminated onto the lower surfaces of the wiring board 6 and the wiring board 7, with the insulating layers 11a and 11b inserted between them. This reduces the inductance of the wiring boards 6 and 7; this ensures a further reduction of the wiring inductance. <Erfindungsgemäße vierte Ausführungsform>

[0056] In the fourth embodiment according to the invention, a semiconductor device according to the first to third embodiments described above is applied to a power converter device. Although the application of the semiconductor device according to the first to third embodiments is not limited to a specific power converter device, the fourth embodiment described below is a case in which the semiconductor device according to the first to third embodiments is applied to a three-phase inverter.

[0057] Fig. Figure 8 is a block diagram illustrating a configuration of a power converter system to which a power converter device according to the fourth embodiment is applied.

[0058] The in Fig. Figure 8 illustrates a power converter system comprising a power supply 100, a power converter device 200, and a load 300. The power supply 100 is a DC voltage supply and provides a DC voltage to the power converter device 200. The power supply 100 can be configured with various components; for example, its configuration may include a DC system, a solar cell, and a storage battery, or a rectifier circuit connected to an AC system, or it may include an AC / DC converter. Furthermore, the power supply 100 can be configured with a DC / DC converter, which converts the DC power output by the DC system into a predefined power output.

[0059] The power converter device 200 is a three-phase inverter connected between the power supply 100 and the load 300. It converts the DC power provided by the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Fig. As illustrated in Figure 8, the power converter device 200 comprises a main converter circuit 201, which converts DC power into AC power and outputs it, and a control circuit 203, which outputs a control signal to the main converter circuit 201 for controlling the main converter circuit 201.

[0060] The Last 300 is a three-phase electric motor powered by an AC voltage supplied by the power converter device 200. The Last 300 is not limited to a specific application and is an electric motor that can be mounted on various electrical devices. For example, the Last 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a rail vehicle, an elevator, or an air conditioning unit.

[0061] The following is a detailed description of the power converter device 200. The main converter circuit 201 contains a switching element (not illustrated) and a freewheeling diode (not illustrated). By switching the switching element, the DC power supplied by the power supply 150 is converted into AC power and supplied to the load 300. Different specific circuit configurations of the main converter circuit 201 exist, and the main converter circuit 201 according to the fourth embodiment is a two-level, three-phase inverter full-bridge circuit. It has six switching elements and six freewheeling diodes, each connected antiparallel to the respective switching elements.At least one of the respective switching elements and each freewheeling diode of the main converter circuit 201 is configured by a semiconductor module 202, which corresponds to any one of the embodiments 1 to 3 described above. Each of the two series-connected switching elements of the six switching elements forms an upper and a lower arm, and each upper and lower arm forms a respective phase (U phase, V phase, W phase) of the full bridge circuit. Furthermore, the output terminal of each upper and lower arm, that is, the three output terminals of the main converter circuit 201, is connected to the load 300.

[0062] Furthermore, the main converter circuit 201 includes a driver circuit (not illustrated) for controlling each switching element. This driver circuit can be integrated into the semiconductor module 202, or a configuration can be used in which the driver circuit is provided separately from the semiconductor module 202. The driver circuit generates a driver signal for controlling the switching element of the main converter circuit 201 and provides this driver signal to the control electrode of the switching element of the main converter circuit 201. Specifically, in response to the control signal, the control circuit 203, described later, outputs a driver signal to switch the switching element on and a driver signal to switch the switching element off to the control electrode of each switching element.When the switching element is held in the ON state, the driver signal is a voltage signal (ON signal) that is equal to or greater than a threshold voltage of the switching element, and when the switching element is held in the OFF state, the driver signal is a voltage signal (OFF signal) that is equal to or less than the threshold voltage of the switching element.

[0063] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (ON duration) for each switching element of the main converter circuit 201 that it remains in the ON state, based on the power to be supplied to the load 300. For example, the main converter circuit 201 is controlled by a PWM controller, which modulates the ON duration of the switching element according to the output voltage. Subsequently, a control command (control signal) is issued to the driver circuit provided in the main converter circuit 201, so that an ON signal is issued to the switching element that is to be switched on at the respective time and an OFF signal is issued to the switching element that is to be switched off.The driver circuit outputs an ON signal or an OFF signal as the driver signal to the control electrode of each switching element in accordance with the control signal.

[0064] In the power converter device according to the present embodiment, the semiconductor modules according to the first to third embodiments are used as the switching elements and the freewheeling diodes of the main converter circuit 201; this ensures both a reduction in size and a reduction in wiring inductance.

[0065] Although the present embodiment describes the semiconductor devices according to the first to third embodiments as being applied to the two-level three-phase inverter, these devices are not limited to this application and can be applied to various power converter devices. While the fourth embodiment uses a two-level power converter device, a three-level or multi-level power converter device is also applicable. Furthermore, if power is supplied to a single-phase load, the semiconductor devices according to the first to third embodiments can also be applied to a single-phase inverter. Finally, if power is supplied to a DC load or the like, the semiconductor devices according to the first to third embodiments are applicable to DC / DC converters or AC / DC converters.

[0066] Furthermore, the power converter device, to which any of the semiconductor devices according to the first to third embodiments is applied, is not limited to the case in which the aforementioned load is an electric motor; the power converter device can be applied in the case in which a load is a power supply device for an electrical discharge machine, a laser machine, an induction cooker, or a contactless power supply system, and can further be applied in the case in which a load is, for example, a power conditioner for a solar energy generation system and an energy storage system.< / effekt>

Claims

[1] Semiconductor device, exhibiting: - an insulating layer (1); - a foil conductor (2) which is provided on a lower surface of the insulating layer (1); - a circuit structure (3, 3a, 3b) which is provided on an upper surface of the insulating layer (1); - a multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) which are mounted on an upper surface of the circuit structure (3, 3a, 3b); - a first wiring board (6) which is connected to the upper surface of the circuit structure (3, 3a, 3b) and allows an externally supplied current to flow through the circuit structure (3, 3a, 3b); and - a second wiring board (7, 7a, 7b) which connects the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) and allows the current flowing through the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) via the circuit structure (3, 3a, 3b) to flow, where: - the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) are arranged along one extension direction of the second wiring board (7, 7a, 7b), - in a current path which leads from the first wiring board (6) through the second wiring board (7, 7a, 7b) via the circuit structure (3, 3a, 3b) and the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16), an electrical resistance of the current path which leads through the semiconductor element arranged on a downstream side is lower than an electrical resistance of the current path which leads through the semiconductor element arranged on an upstream side, and - the current path from the first wiring board (6) to the second wiring board (7) is U-shaped in a top view. [2] Semiconductor device, exhibiting: - an insulating layer (1); - a foil conductor (2) which is provided on a lower surface of the insulating layer (1); - a circuit structure (3, 3a, 3b) which is provided on an upper surface of the insulating layer (1); - a multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) which are mounted on an upper surface of the circuit structure (3, 3a, 3b); - a first wiring board (6) which is connected to the upper surface of the circuit structure (3, 3a, 3b) and allows an externally supplied current to flow through the circuit structure (3, 3a, 3b); and - a second wiring board (7, 7a, 7b) which connects the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) and allows the current flowing through the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) via the circuit structure (3, 3a, 3b) to flow, where: - the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) are arranged along one extension direction of the second wiring board (7, 7a, 7b), - in a current path which leads from the first wiring board (6) through the second wiring board (7, 7a, 7b) via the circuit structure (3, 3a, 3b) and the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16), an electrical resistance of the current path which leads through the semiconductor element arranged on a downstream side is lower than an electrical resistance of the current path which leads through the semiconductor element arranged on an upstream side, and - on the first wiring board (6) and the second wiring board (7, 7a, 7b) there are foil conductors (12a, 12b) which differ from the foil conductor (2) and are laminated on lower surfaces of them over insulating layers (11a, 11b). [3] Semiconductor device according to any one of the preceding claims, wherein: - the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b) is a pair of semiconductor elements (4, 4a, 4b, 5, 5a, 5b), - the current path between the pair of semiconductor elements (4, 4a, 4b, 5, 5a, 5b) into a first current path, which does not pass through one of the semiconductor elements (4, 4a, 4b) arranged on the upstream side and which passes through another of the semiconductor elements (5, 5a, 5b) arranged on the downstream side via the circuit structure (3, 3a, 3b) and branches into a second current path, which passes through the second wiring board (7, 7a, 7b) via one of the semiconductor elements (4, 4a, 4b), and - a ratio of R1 <R2 erfüllt ist, wobei R1 den elektrischen Widerstand des ersten Strompfades repräsentiert und R2 den elektrischen Widerstand des zweiten Strompfades repräsentiert. [4] Semiconductor device according to any one of the preceding claims, wherein: - the multitude of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) has an IGBT and an FWD, and - the FWD is mounted on the side further forward than the IGBT. [5] Semiconductor device according to one of the preceding claims, further comprising a plurality of phases which are composed of the plurality of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16). [6] Semiconductor device according to any of the preceding claims, wherein the circuit structure (3, 3a, 3b) contains copper. [7] Semiconductor device according to any of the preceding claims, wherein the thickness of the circuit structure (3, 3a, 3b) is 0.2 mm or more. [8] Semiconductor device according to any of the preceding claims, wherein the thickness of the insulating layer (1) is 0.5 mm or less. [9] Semiconductor device according to one of claims 1 and 2 in combination with one of claims 4 to 8, wherein the plurality of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) includes a backward conducting IGBT. [10] Semiconductor device according to any of the preceding claims, wherein a semiconductor material of the plurality of semiconductor elements (4, 4a, 4b, 5, 5a, 5b, 16) is SiC. [11] Power converter device (200) comprising: - a main converter circuit (201) comprising the semiconductor device according to any one of the preceding claims and configured to convert and output input power; and - a control circuit (203) which is configured to output a control signal to the main converter circuit (201) for controlling the main converter circuit (201).

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