Integrated circuit with an integrated resistor and current detection functionality

Abstract

Integrated circuit comprising the following: a first circuit with a first amplifier (108), a first resistor (102), a second resistor (104), a third resistor (106), a fourth resistor (110) and a fifth resistor (112); wherein the first resistor (102) has a first resistance value (Rs); wherein the second resistor (104) and the third resistor (106) each have a second resistance value (Rt); wherein the fourth resistor (110) and the fifth resistor (112) each have a third resistance value (Rb); wherein the first resistor (102) is configured to carry a first current (Isns) based on the first resistance value (Rs) and a voltage difference between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier (108) is configured to output a third voltage (Vo) based on the first current (Isns); wherein a gain of the first amplifier (108) is based on the second resistance value (Rt) and the third resistance value (Rb); wherein the first resistor (102) is formed from a first plurality of polysilicon platelets; wherein the second resistor (104) is formed from a second plurality of polysilicon platelets; wherein the third resistor (106) is formed from a third plurality of polysilicon platelets; wherein the first plurality of polysilicon platelets, the second plurality of polysilicon platelets and the third plurality of polysilicon platelets are arranged on a layer of the integrated circuit; wherein the second plurality of polysilicon platelets is arranged axially symmetrically to the third plurality of polysilicon platelets, such that a difference in mechanical stress between the second plurality of polysilicon platelets and the third plurality of polysilicon platelets is reduced.

Description

[0001] The present invention relates generally to wireless electrical power, and more particularly to current sensing.

[0002] Current sensing is a key component in wireless power systems. The measured current, along with the voltage measurement, provides a power measurement for the system. Power measurement is critical for understanding how much power is actually received by the transmitter and delivered to a load, such as a battery. More specifically, wireless power systems must measure power very accurately to support foreign object detection. A foreign object can undesirably receive power from a transmitter and begin to overheat. The receiver can include current sensing functionality to measure the received power to determine the power lost to the foreign object. Power losses due to foreign objects can be more accurately predicted by determining the received current. Thus, it is desirable to determine the received current with a certain degree of accuracy.However, the current sensing function of the Wireless Power System may include inaccuracies introduced by one or more sources.

[0003] In view of the above, one or more embodiments of the present disclosure provide an integrated circuit with an improved current sensing function.

[0004] DE 697 27 904 T2 describes a motor controller with an integrated circuit having two or more integrated resistor dividers which generate signals to be compared with each other, the circuit being designed to reduce the dependence of the comparison on the reverse bias voltage of the junctions between the diffused resistors in the integrated resistor dividers and the silicon into which they are diffused.

[0005] US 2022 / 0 026 457 A1 describes a multi-axis angular velocity sensor with a substrate part which, perpendicular to a first axis, comprises a pair of long sides parallel to a second axis and a pair of short sides parallel to a third axis. Three sensor elements for the three axes are mounted on an upper side of the support part. A piezoelectric body of each sensor element consists of a plurality of arms. These arms extend in a predetermined extension direction. The longitudinal direction of the piezoelectric body is the extension direction. Two of the three sensor elements are arranged next to one another in a direction along the short sides of the support part, with the extension directions running parallel to the long sides.A remaining element is arranged in a direction along the long sides relative to the two elements with an orientation such that the extension direction is parallel to the short sides.

[0006] In accordance with the present invention, an integrated circuit having the features of claim 1 and a system having the features of claim 10 are provided. Advantageous further developments emerge from the dependent subclaims.

[0007] Conveniently, the second plurality of polysilicon dies and the third plurality of polysilicon dies are arranged at a first distance from a die edge to reduce the difference in mechanical stress between the second plurality of polysilicon dies and the third plurality of polysilicon dies.

[0008] Conveniently, the first resistor comprises a first row and a second row of polysilicon dies; wherein the first row is arranged between the die edge and the second plurality of polysilicon dies; wherein the second row is arranged between the die edge and the third plurality of polysilicon dies.

[0009] Conveniently, the first resistor comprises a third row and a fourth row of polysilicon die, both arranged at the first distance from the die edge; wherein the third row is arranged axially symmetrically to the fourth row.

[0010] Conveniently, the second plurality of polysilicon dies and the third plurality of polysilicon dies are arranged between the third row and the fourth row.

[0011] Advantageously, the integrated circuit has a gradient of mechanical stress; the gradient of mechanical stress decreases with increasing distance from the die edge and from the axis.

[0012] Conveniently, the integrated circuit further comprises a metallization layer; wherein the first plurality of polysilicon dies are coupled by means of the metallization layer; wherein the second plurality of polysilicon dies are coupled by means of the metallization layer; wherein the third plurality of polysilicon dies are coupled by means of the metallization layer; wherein at least some of the first plurality of polysilicon dies are coupled in parallel such that the first resistance (Rs) is lower than the second resistance (Rt).

[0013] Conveniently, the first plurality of polysilicon dies are coupled to the metallization layer by means of a first plurality of vias; wherein the second plurality of polysilicon dies are coupled to the metallization layer by means of a second plurality of vias.

[0014] Conveniently, a through-hole resistance is matched between the first resistor and the second resistor.

[0015] It is advisable to adjust the via resistance by skipping one or more vias of the second resistor.

[0016] Conveniently, the first circuit further comprises a first switch (M1), a second switch (M2), a third switch (M3), and a fourth switch (M4); wherein the first switch (M1) and the fourth switch (M4) are arranged axially symmetrically to the second switch (M2) and the third switch (M3).

[0017] Advantageously, the first switch (M1) and the fourth switch (M4) are arranged on the layer in a finger-like manner in order to reduce the resistance of a channel.

[0018] Conveniently, the first switch (M1), the second switch (M2), the third switch (M3) and the fourth switch (M4) are provided for measuring an offset of the first circuit.

[0019] Conveniently, the first plurality of polysilicon dies, the second plurality of polysilicon dies and the third plurality of polysilicon dies each have a first opening.

[0020] Conveniently, the first opening is 50 x 4 micrometers in size.

[0021] Conveniently, the first resistor is coupled between a first node having the first voltage (Vrect) and a second node having the second voltage (Vmid); wherein the second resistor is coupled between the first node and a first input of the amplifier; wherein the third resistor is coupled between the second node and a second input of the amplifier; wherein the fourth resistor is coupled between a first output of the amplifier and ground; wherein the fifth resistor is coupled between a second output of the amplifier and ground.

[0022] Conveniently, the amplifier is a differential amplifier.

[0023] Conveniently, the integrated circuit further comprises one or more package pins arranged centrally around the axis.

[0024] Conveniently, the system is configurable between a receive mode and a transmit mode; wherein the first current (Isns) is provided from the rectifier to the voltage regulator via the first resistor when the system is in the receive mode; wherein the processor is configured to determine the first current (Isns) when the system is in the receive mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Implementations of the concepts disclosed in this document may be better understood by reference to the following detailed description. Such description refers to the accompanying drawings, which are not necessarily to scale and in which some features may be exaggerated, some features may be omitted, or shown schematically for clarity. Like reference numerals in the drawings may represent the same or similar elements, features, or functions. In the following: Fig. 1A to Fig. 1C is a top view of a layout of components of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 2A and Fig. 2B is a side view of a layout of components of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 3 is a top view of a layout of components of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 4 is a circuit diagram of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 5A and Fig. 5B is a circuit diagram of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 6 is a top view of a layout of components of a current sensing circuit according to one or more embodiments of the present disclosure. Fig. 7 is a simplified block diagram of an integrated circuit including a current sensing circuit in accordance with one or more embodiments of the present disclosure. Fig. 8 is a simplified schematic of a wireless power system according to one or more embodiments of the present disclosure. Fig. 9 illustrates a simplified communication device including one or more components of a wireless power system in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] As used herein, a letter following a reference number is intended to refer to an embodiment of the feature or element with the same reference number (e.g., 1, 1a, 1b), which may be similar to, but not necessarily identical to, a previously described element or feature. Such shorthand references are used for convenience only and are not to be construed as limiting the disclosure in any way, unless specifically stated otherwise.

[0027] Furthermore, unless specifically stated otherwise, "or" refers to an inclusive "or" rather than an exclusive "or." For example, a condition A or B is satisfied by any of the following situations: A is true (or present), and B is false (or absent); A is false (or absent), and B is true (or present); and both A and B are true (or present).

[0028] Additionally, "a," "an," "an," or "another" may be used to describe elements and components of embodiments disclosed herein. This is for convenience only, and "a," "another," or "another" is intended to include "at least one," "at least one," "at least one," and "at least one," and the singular includes the plural unless clearly indicated otherwise.

[0029] Finally, reference to "one embodiment" or "some embodiments" as used herein means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment disclosed in the present document.Occurrences of the phrase "in some embodiments" in various places in the specification are not necessarily references to the same embodiment, and embodiments may include one or more of the features expressly described or inherent in the present document, or any combination or subcombination of two or more such features, together with any other features not necessarily expressly described or inherent in the present disclosure.

[0030] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0031] An integrated circuit includes a current sensing circuit formed from a polysilicon material. The resistors may be subject to internal mechanical stresses, which may have been introduced during the integrated circuit's manufacture. The piezoresistive effect can cause a change in the resistivity of the resistors when a mechanical stress is applied to the resistors. This change in resistivity can undesirably cause the resistors to exhibit an error, particularly in high-precision environments. For high-precision current sensing circuits operating at currents of 1 ampere, 1 milliampere corresponds to a 0.1% error. In some cases, the current sensing circuit may be designed to achieve an accuracy in the range of 0.5%, so the 1 milliampere error due to the piezoresistive effect consumes 20% of the 0.5% error.Balancing the offset between the resistors is therefore crucial to achieve the desired level of accuracy.

[0032] Embodiments of the present disclosure are generally directed to one or more layouts of an integrated circuit to compensate for the piezoresistive nature of resistors formed from polysilicon material. During the physical implementation of the resistors in the integrated circuit, undesirable stresses may be applied to the resistors due to printing. The resistors may be arranged on the integrated circuit with respect to the stress gradient to reduce the stress and similarly reduce changes in resistance due to the piezoresistance. In particular, a pair of matched resistors (e.g., resistors each having a resistance of 1 kilohm) may be arranged at an equal distance from the chip edge and / or axisymmetrically.The pair of matched resistors may be the input to an amplifier. A second pair of matched resistors may be the output of the amplifier and may be similarly arranged to reduce the resistance changes. In this regard, the amplifier may have an offset and gain whose percentage error can be improved by reducing the error corresponding to the resistance changes due to the piezoresistance. The piezoresistive effect of the stress gradient can thus be compensated for without the need for post-manufacturing software calibration for each integrated circuit.

[0033] With general reference to Fig. 1A to Fig. 6, a current sensing circuit 100 is described. The current sensing circuit 100 may be configured to measure current over a wide range of voltages, such as 24 volts or more. The current sensing circuit 100 may be configured to measure current over a relatively wide dynamic range, such as, but not limited to, from 1 milliampere to 2.5 amperes. It is contemplated that the accuracy of the current sensing circuit 100 may be below 0.5 percent of the actual current across the dynamic range of currents by utilizing one or more layout configurations, a switching matrix to determine the offset, and a dual-channel approach to analog and digital control loops.Although current sensing circuit 100 is depicted as including the various components included in the respective assemblies, this is not intended to limit the present disclosure. It is further contemplated that current sensing circuit 100 may include various additional components not depicted. It should be noted that, for the purposes of the present disclosure, "coupled" herein may refer to one or more of the phrases "communicatively coupled to," "electrically coupled to," and / or "physically coupled to." As used herein, "coupled" may refer to a direct or indirect coupling. An indirect coupling may refer to a connection via another functional element. A direct coupling may refer to a connection without any intervening elements.It should be noted that "coupled between" is to be understood as relative to a movement or flow of the signal between two or more components and may additionally include components acting therebetween.

[0034] With reference to Fig. 1A to Fig. 1C, a top view of a layout of one or more components of a current sensing circuit 100 is described in accordance with one or more embodiments of the present disclosure.

[0035] Current sensing circuit 100 may include one or more of a resistor 102, a resistor 104, and a resistor 106. Resistor 102 may also be referred to herein as a sense resistor having a resistance (Rs). For example, resistance (Rs) may be 20 milliohms, although this is not intended to be limiting. A range of values ​​for resistor 102 is contemplated around the exemplary 20 milliohm resistor. In this regard, the resistance value may be selected to be on the order of 1 to 100 milliohms or higher. Resistor 104 and resistor 106 may be connected to the input of an amplifier 108 such that resistor 104 and resistor 106 may also be referred to herein as "step-up resistors."Resistor 104 and resistor 106 may each have a resistance (Rt), so resistor 104 and resistor 106 may also be referred to as a pair of matched resistors. For example, resistance (Rt) may be 1 kiloohm (e.g., 1 kΩ resistor), although this is not intended to be limiting. Current sensing circuit 100 may further include one or more reactances 124. Current sensing circuit 100 may further include one or more switches 122 (e.g., switch (M1), switch (M2), switch (M3), and switch (M4)). Switches (M1-M4) may be provided for measuring an offset of the current sensing circuit due to resistor 104, resistor 106, resistor 110, resistor 112, and amplifier 108, as further described herein.

[0036] As in Fig. 1A, resistor 102, resistor 104, resistor 106, and reactance 124 are shown with different hatching, which is not intended to be limiting. Rather, resistor 102, resistor 104, resistor 106, and reactance 124 are shown with hatching to illustrate the number of elements of the grouping comprised by each resistor. It is contemplated that the layout of resistor 102, resistor 104, and resistor 106 may be advantageous for any number of current sensing circuits sensing current in a range of one milliampere to one ampere.

[0037] In embodiments, resistor 102, resistor 104, and resistor 106 each comprise a polysilicon resistor formed on a substrate. The polysilicon resistor may also be referred to herein as a polyresistor or internal polyresistor. In embodiments, the polysilicon resistor is formed as an array of array elements, each of which comprises the polysilicon die. Fig. 1A depicts resistor 102 as comprising one hundred and forty of the grouping elements, resistor 104 as comprising seven of the grouping elements, resistor 106 as comprising seven of the grouping elements, and reactance 124 as comprising six grouping elements, although this is not intended to be limiting. Further, although not depicted, the grouping elements of each of resistor 102, resistor 104, and resistor 106 may be coupled in any number of series or parallel arrangements to achieve a desired resistance value. As further described in Fig. 2, each array element may include a number of polysilicon dies. For example, the array elements may also be referred to as 10x resistors, such that each array element includes 10 polysilicon dies (also referred to as fingers), although this is not intended to be limiting. Thus, resistor 102 may include 1,400 polysilicon dies, and resistor 104 and resistor 106 may each include 70 polysilicon dies.

[0038] Thus, resistor 102, resistor 104, and resistor 106 may each be formed as a plurality of polysilicon dies. The polysilicon dies may comprise any polysilicon material known in the art, such as, but not limited to, doped or undoped polysilicon foils. The polysilicon dies may be disposed on a same layer of the integrated circuit, such as beneath metallization layers. The polysilicon dies may have a resistance that changes with temperature. The use of the polysilicon dies may be advantageous for reducing the temperature coefficient compared to implementing resistor 102, resistor 104, and resistor 106 in metallization layers of the integrated circuit.For example, the polysilicon die may have a temperature coefficient of resistance (TCR) between 150 and 160 parts per million per degree Celsius (PPM / C), although this is not limiting. The polysilicon die may each have a resistance value. For example, the polysilicon die may each have a die resistance of 300 ohms per square, although this is not limiting. The polysilicon die may be arranged in parallel and / or series. The parallel and / or series arrangement of the polysilicon die may be used to form the array of resistors for the polysilicon resistor with the selected resistance value.The resistance (Rs) for the sense resistor, the resistance (Rt) for the boost resistor, and the resistance (Rb) for the buck resistor may be based on the number and arrangement of the array of polysilicon die. The number of array resistive elements used to form resistor 102 may be substantially greater than the number of resistive elements used to form the boost resistor. Providing substantially more of the resistive elements 102 as boost resistors may cause the resistance (Rs) to be substantially less than the resistance (Rt). Consider the example in which there are 140 array elements for resistor 102, with each array element comprising 10 polysilicon die. In this example, resistor 102 may be of the type shown in FIG. 1.400 parallel-coupled polysilicon die to achieve a 20 milliohm resistance value for the resistor (Rs), although this is not to be considered limiting.

[0039] It may be desirable to ensure that resistor 104 and resistor 106 have a resistance value as closely matched as possible, for example, to ensure appropriate gain for one or more amplifiers of the current sensing circuit. One challenge in implementing resistors 102, resistors 104, and resistors 106 arises from the piezoresistive nature of polysilicon. In this regard, the resistance (Rs) and resistance (Rt) may change when the polysilicon die are subjected to pressure. Each of resistor 104 and resistor 106 may be subject to stress due to the pressure. In some cases, the stress of resistor 104 may be different from the stress of resistor 106, which may also be referred to herein as a stress difference.

[0040] As in Fig. 1B, a graph 130 of a stress gradient of the integrated circuit may be attenuated with increasing distance from the axis 126 and may also be axisymmetric about the axis 126. Similarly, a graph of resistance (not shown) as a function of distance may show a change in resistance with increasing distance from the axis. As further shown in Fig. 1C, a stress gradient plot 131 of the integrated circuit may progressively move away from the die edge 128. For example, the stress gradient may be highest at the die edge 128 and decrease in a non-linear manner along the edge such that the stress gradient from the die edge 128 is non-linear across the entire integrated circuit. Similarly, a resistance vs. distance plot (not shown) may experience a change in resistance with increasing distance from the die edge 128. It should be understood that the plot 130 and the plot 131 are non-limiting. In this regard, the plot 130 and the plot 131 may exhibit lot-to-lot variation and / or device-to-device variation.

[0041] In embodiments, resistor 104 and resistor 106 may be arranged symmetrically around the stress gradient to minimize the change in resistance due to the piezoresistance.

[0042] In embodiments, resistor 104 and resistor 106 may comprise array elements with the polysilicon die arranged symmetrically about an axis 126. Axis 126 may include a central axis. In this regard, the stress difference between the polysilicon die of resistor 104 and resistor 106 may be reduced, thereby causing the matched pair of resistors to experience similar stress and, in a similar manner, a similar change in resistance due to the piezoresistance. Causing the matched pair of resistors to experience similar changes in resistance may be particularly advantageous where the resistors are each coupled to the input of a differential amplifier, thereby improving the accuracy of the differential amplifier.

[0043] In embodiments, resistor 104 and resistor 106 may comprise grouping elements with the polysilicon die arranged at the same distance from the die edge 128 of the integrated circuit. Resistor 104 and resistor 106 may be piezoresistive and change in resistance due to pressure. The change in resistance due to pressure may affect an offset and gain of a downstream amplifier. By arranging resistor 104 and resistor 106 at the same distance from the axis 126 and the die edge 128, a stress difference between the resistors may be reduced. Reducing the stress difference may cause the resistors to experience similar changes in resistance.Thus, placing the resistors at equal distances from the die edge may have minimal effect on the offset and gain of a downstream amplifier (where, for example, resistor 104 and resistor 106 are inputs to the amplifier) ​​compared to placing resistor 104 and resistor 106 at different distances from the die edge 128.

[0044] Resistor 104 and resistor 106 can also be placed at a distance from the die edge within a portion of the stress gradient that is shallower than the regions closer to the die edge. In this regard, the resistance of the matched pair of resistors can change minimally, thereby minimizing an impact on amplifier gain. For example, one or more grouping elements of resistor 102 and one or more of the switches (M1-M4) can be placed between the die edge 128 and resistor 104, 106, thereby spacing resistor 104, 106 from the die edge 128.

[0045] As shown, the layout may include a grouping of resistors. The grouping may be separated based on one or more DNW (deep n-well) regions 132 of the integrated circuit, although this is not intended to be limiting. In this regard, the resistors may be placed on a layer above the DNW regions 132. For example, Fig. 1A depicts a 2x4 grouping of DNW regions 132, where each of the DNW regions 132 includes two rows, each containing ten of the grouping elements. As further depicted, the first 1x4 grouping of DNW regions 132 is separated from the second 1x4 grouping of DNW regions 132 by switches (M1-M4). Although the DNW regions 132 are depicted as including twenty of the grouping elements, this is not intended to limit the present disclosure. The DNW regions 132 may generally include any suitable number to achieve a desired resistance. For example, the DNW regions 132 may include 22 of the grouping elements per DNW region (i.e., rows of 11 of the grouping elements each). In this example, the total number of grouping elements can be 176 (i.e., 2x4 grouping of DNW ranges with 22 elements per range).Where each element comprises 10 fingers or polysilicon die, the array may comprise 1,760 polysilicon die. To achieve the 20 milliohm resistance for resistor 102, 1,400 of the 1,760 polysilicon die may be used, resulting in a total of 140 array elements. To achieve the 1 kiloohm resistance for each of resistor 104 and resistor 106, 70 array elements may be used. The remaining layout may include twelve array elements that are unused (for example, reactance 124).

[0046] In embodiments, as shown, resistor 104 and resistor 106 are both arranged symmetrically about axis 126 and are spaced the same distance from die edge 128. The resistors may still experience mechanical stress, causing a change in resistance. Conveniently, the resistivity for resistor 104 and resistor 106 changes by a similar amount. The resistivity may change by a similar amount because the resistors are both spaced the same distance from edge 128 and are in the same orientation with respect to axis 126. The resistance (Rt) for each resistor can thus be more closely matched.For example, the grouping elements of resistor 104 and resistor 106 are shown separated from the DNW regions 132 that are closest to the axis 126 and separated from the die edge 128 by a second group of DNW regions 132.

[0047] Resistor 102 may include one or more rows of array elements with the polysilicon die. One or more rows of resistor 102 are disposed between die edge 128 and the polysilicon die of resistor 104. Similarly, one or more rows of resistor 102 are disposed between die edge 128 and the polysilicon die of resistor 104. The rows may be considered to be closer to die edge 128 and also located within a region experiencing a higher concentration of stress. Thus, resistor 102 may experience relatively more change due to the piezoresistance than resistor 104 and resistor 106. For example, resistor 102 is depicted as including fourteen rows of array elements, with each row including ten array elements.Resistor 102 is further depicted as encompassing eight of the rows between die edge 128 and resistor 104 or resistor 124.

[0048] Resistor 102 may additionally include one or more rows of array elements spaced the same distance from die edge 128 as resistor 104 or resistor 106. The co-spaced rows may also be symmetrically spaced about axis 126. The polysilicon die of resistor 104 and resistor 106 may also be interspersed between one or more rows of first resistor 102. For example, resistor 104 and resistor 106 are depicted in one arrangement as three axisymmetric rows of resistor 102, all spaced the same distance from die edge 128. Resistor 102 may thus include a layout that reduces the space between resistor 104 and resistor 106 for better matching.

[0049] Resistor 102, resistor 104, and resistor 106 may be arranged on a same layer of the circuit to reduce temperature spread. In embodiments, resistor 104 and resistor 106 may be arranged in a finger-like manner to reduce temperature spread between resistor 104 and resistor 106. Reducing the temperature spread may be valuable in minimizing error due to changes in the resistor due to temperature.

[0050] The finger-interdigitating may refer to one or more subcomponents of a first component with one or more subcomponents of a second component. For example, an array may include polysilicon die of a first component finger-interdigitated with polysilicon die of a second component. For example, in another example, a switch matrix may include a first switch arranged on a layer finger-interdigitated with a second switch to match a channel resistance. The channel resistance may refer to the resistance from the drain to the source.

[0051] The integrated circuit may further be configured to directly measure the offset. Current sensing circuit 100 may further include one or more switches. For example, the switches may include four switches (M1-M4). Switches (M1-M4) may be configured to measure an offset. Switches (M1-M4) may also be arranged symmetrically around a stress gradient. For example, switch (M2) and switch (M3) may be symmetrical about axis 126 relative to switch (M1) and switch (M4).

[0052] The switches (M1-M4) may be arranged on a same layer as resistor 102, resistor 104, and resistor 106. In embodiments, the switch (M1) may be arranged in a finger-like interdigitated manner with the switch (M4). Similarly, the switch (M2) may be arranged in a finger-like interdigitated manner with the switch (M3). The finger-like interdigitated arrangement of the switches may be advantageous in matching the channel resistance of the switches (M1) and (M4), and similarly, in matching the channel resistance of the switches (M2) and (M3). It is contemplated that there are alternative ways to arrange the switches (M1-M4). For example, the switch (M1) and (M4) may be separate and arranged in any order with the switch (M2) and (M3).The switch (M1) and the switch (M4) can also be arranged axially symmetrically with the switch (M2) and the switch (M3).

[0053] With general reference to Fig. 2A and Fig. 2B, a polysilicon resistor array element is described. The polysilicon resistor may include one or more of resistor 102, resistor 104, or resistor 106. The array element may include one or more polysilicon dies 134 and one or more metallization layers 136. The array element may further include one or more vias 138 connecting the polysilicon dies 134 to the metallization layers 136.

[0054] The array element may include any number of polysilicon dies 134. For example, the array element may include twelve of the polysilicon dies 134 (e.g., two reactances and dies 1-10), although this is not intended to be limiting. As depicted, array element 201 and array element 203 each include ten of the polysilicon dies (1-10) coupled together, as well as two dummy polysilicon dies (Dmy). There may be a range of suitable dimensions for the polysilicon dies 134. For example, the polysilicon dies 134 may be relatively wide, such as, but not limited to, 50 micrometers. The polysilicon dies 134 may further have a length, such as, but not limited to, 4 micrometers. The aspect ratio of the polysilicon die 134 may thus be 50 micrometers to 4 micrometers, although this is not to be understood as limiting.A temperature coefficient of 150 ppm / C was experimentally determined for polysilicon wafers with an aspect ratio of 50 micrometers to 4 micrometers. Sizing the polysilicon wafers to have the same aperture and approximately the same temperature coefficient can be advantageous in canceling out the temperature coefficient of resistance (Rs) and resistance (Rt).

[0055] The connections between the plurality of polysilicon dies 134 are routed between one or more of the metallization layers 136. The metallization layers 136 of the integrated circuit may include resistance in addition to the polysilicon dies 134. Thus, the resistance value of the array element may be based on the array itself, along with the metallization layers, to get current into and out of the polysilicon dies 134. The metallization layer may be formed from one or more materials, such as, but not limited to, copper. The layer may have a resistivity inversely proportional to the thickness. As depicted, the array elements may include four metallization layers. Although the array elements are depicted as including four metallization layers, this is not intended to be limiting.For example, each array element may comprise six metallization layers (m1-m6). Layers (m1-m5) are relatively thin and have a specific die resistance (for example, 300 milliohms per square). Layers (m1-m5) may be a high-density metal interconnect substrate for various digital signals. In contrast, layer (m6) may be relatively thick compared to layers (m1-m5) and have a specific die resistance that is relatively low (for example, 4 milliohms per square). Layer (m6) may be provided for analog routing with high currents. Layer (m6) may also be described as a top layer or package layer. Metallization layers (m1-m6) may be provided as one or more parallel layers. The parallel layers may be arranged on top of the polysilicon die layer.The polysilicon die layer can be arranged on top of one or more deep DNW (deep n-well) layers.

[0056] When designing a current sensing circuit, leakage resistance due to the trace running between polysilicon die 134 introduces a spurious variable. A variance between the step-up resistances of the current sensing circuit can result in a significant percentage error. For example, if resistor 104 and resistor 106 are 1 kΩ resistors, a resistance variance of 1 ohm results in a 0.1% error. Three metal squares in layers (m1-m5) can introduce such an error. In embodiments, the connections between polysilicon die 134 can be routed between metallization layers 136, which have a lower die resistivity. Routing through the lower resistivity layers can have a minimal effect on the resistance of resistor 102, resistor 104, or resistor 106.For example, layer (m6) can be used to conduct the connections between the polysilicon dies 134 due to its lower resistivity. In this regard, connecting the polysilicon dies 134 via layer (m6) can reduce the ohmic resistance caused by the metallization layer.

[0057] Layers (m1-m5) may be disposed between layer (m6) and polysilicon die 134. Vias 138 may be coupled between polysilicon die 134 and metallization layer 136. For example, vias 138 may be provided to couple polysilicon die 134 to layer (m6). Vias 138 may run perpendicularly through layers (m1-m6) to conduct current laterally through layer (m6). Vias 138 may also be referred to as stacked vias. Vias 138 may also have a resistivity. The resistance of vias 138 may introduce an additional parasitic variable. In embodiments, the resistance of vias 138 is matched between array element 201 and array element 203.Each of the grouping element 201 and the grouping element 203 can pass through the same number of vias to adjust the resistance. A current can then flow through the stacked vias to the polysilicon die, continue along the polysilicon die, and then up to layer (m6) via a second set of stacked vias that up to another part of the m6 layer.

[0058] With reference to Fig. 2A, a grouping element 201 for resistor 102 will now be described. The grouping element 201 of resistor 102 may include one or more of the polysilicon dies 134 coupled in parallel by means of the vias 138 and the metallization layers 136, such as ten of the polysilicon dies 134. As depicted, the resistance of the grouping element may be based on the resistance of the polysilicon dies (Rpoly) and the resistance of the vias (Rcontact). In some cases, each of the polysilicon dies 134 is coupled in parallel for each grouping element of resistor 102. By coupling each of the polysilicon dies 134 in parallel, a resistance (Rs) for resistor 102 may be a very low resistance. The provision of the very low resistance is advantageous for minimizing the power loss in the resistor 102. Each of the polysilicon die 1-10 can be coupled in parallel.For example, the resistance (Rs) for resistor 102 may be 20 milliohms, although this is not limiting. Resistance can be defined using the following equation: R=[Rpoly+(2*Rcontact)] / 10

[0059] The resistor 102 may further comprise any number of the grouping elements 201 to achieve a desired resistance, such as one hundred and forty of the grouping elements 201 for the Fig. 1A shown layout.

[0060] With reference to Fig. 2B, a grouping element 203 of resistor 104 and resistor 106 will now be described. The grouping element 203 may include one or more of the series-coupled polysilicon dies. As depicted, the resistance of the grouping element may be based on the resistance of the polysilicon dies (Rpoly) and the resistance of the vias (Rcontact). The grouping element 203 may include vias 138 that lead up and pass through a resistor die 9, lead up through vias, and then lead down. The resistor die 8 may then be omitted. The pattern may continue with dies 1, 3, 5, 7, and 9 coupled in series and resistor dies 2, 4, 6, and 8 omitted. In this regard, the grouping element 201 and the grouping element 203 may have a matched via resistance.For example, resistance can be defined using the following equation:. R=(5*Rpoly)+(10*Rcontact)=5*[Rpoly+(2*Rcontact)]

[0061] The resistor 104, 106 may further comprise any number of the grouping elements 203 to achieve a desired resistance, such as 7 of the grouping elements 203 for the Fig. Layout shown in 1B.

[0062] With reference to Fig. 3, the layout of the current sensing circuit 100 according to one or more embodiments of the present disclosure will now be described in more detail. The current sensing circuit 100 may additionally include a resistor 110 and a resistor 112. The resistor 110 and the resistor 112 may be connected to the output of the amplifier such that the resistor 110 and the resistor 112 may also be referred to herein as "step-down resistors." The resistor 110 and the resistor 112 may each have a resistance (Rb), so the resistor 110 and the resistor 112 may also be referred to as a pair of matched resistors. For example, the resistance (Rb) may be 17.5 kilohms (e.g., a 17.5 kΩ resistor), although this is not intended to be limiting.

[0063] Although not shown, resistor 110 and resistor 112 may each include a number of array elements formed from polysilicon die and arranged to form the resistor (Rb). The array elements may be arranged in a checkerboard pattern to improve matching. As shown, resistor 110 and resistor 112 are arranged in a symmetrical matrix.

[0064] Current sensing circuit 100 may further include one or more of a package pin 140 and a package pin 142. The package pin 140 and the package pin 142 may be centered on the axis 126 to reduce stress gradients for the array elements, thereby improving matching between the resistor 104 and the resistor 106. The package pin may be provided for coupling a package for the integrated circuit to an external component. The package pin may also be referred to as a pin or contact pin.

[0065] The current sensing circuit 100 may further include one or more resistors 144 for a secondary amplifier trace (e.g., an analog trace), as further described with respect to Fig. 5A to Fig. 6. For example, resistors 144 may comprise an integrated pair of 1 kΩ and 17 kΩ resistors arranged in a checkerboard pattern.

[0066] With reference to Fig. 4, a circuit diagram for current sensing circuit 100 will now be described in accordance with one or more embodiments of the present disclosure. Current sensing circuit 100 may provide a structure that measures a current across a resistor with a selected degree of accuracy and over a wide range of current values. Current sensing circuit 100 may be configured to output a voltage (Vo). The voltage (Vo) may be provided to an analog-to-digital converter, which generates a digital signal that is then used by a processor to determine a current (Isns). Current sensing circuit 100 may include one or more components for generating the voltage (Vo). For example, current sensing circuit 100 may include resistor 102, resistor 104, resistor 106, amplifier 108, resistor 110, resistor 112, transistor 114, and transistor 116.The current sensing circuit 100 may additionally include one or more switches 122 (i.e., switch (M1), switch (M2), switch (M3), and switch (M4)).

[0067] Resistor 102 may be coupled between a node having a first voltage (Vrect) and a node having a voltage (Vmid). "Node" may refer to a point that provides a connection between one or more elements of a circuit and / or between one or more branches of a circuit. The node may be represented by a wire that connects the various elements and / or branches together. Resistor 102 may have a resistance (Rs). Resistor (Rs) may have a relatively small resistance value. Resistor (Rs) may be relatively small to reduce the amount of power dissipated through resistor 102 due to the inversely proportional relationship between resistance and power dissipation. For example, resistor 102 may be a 20 milliohm resistor, although this is not intended to be limiting.Resistor 102 can be configured to conduct current (Isns) through the resistor based on the resistance (Rs) and a voltage difference between the voltage (Vrect) and the voltage (Vmid). Providing the low-resistance resistor presents challenges in circuit design, particularly with reductions in resistance (Rs) and when measuring currents over a wide and dynamic range (for example, in the range of one milliampere to 2.5 amperes). Several challenges exist when integrating resistor 102 into the integrated circuit (IC).

[0068] In embodiments, current sensing circuit 100 is configured to output voltage (Vo) for sensing current (Isns). In this regard, the ability to sense current (Isns) can be advantageous for measuring received or transmitted power. Due to the desire to sense the current (Isns) through resistor 102, resistor 102 may also be referred to as a sense resistor.

[0069] Resistor 104 may be coupled between the node with voltage (Vrect) and an input of amplifier 108. Similarly, resistor 106 may be coupled between the node with voltage (Vmid) and an input of amplifier 108. In this regard, resistor 104 and resistor 106 may also be referred to herein as step-up resistors or input resistors for amplifier 108. In embodiments, resistor 104 and resistor 106 each have a resistance value (Rt) that is matched. In this regard, resistor 104 and resistor 106 may also be referred to herein as a pair of matched resistors. The resistance (Rt) may increase as resistor 104 and resistor 106 age.

[0070] Resistor 110 may be coupled between an output of amplifier 108 and ground. Similarly, resistor 112 may be coupled between an output of amplifier 108 and ground. For example, resistor 110 is depicted as being coupled between a node of transistor 114 and ground, and resistor 112 is depicted as being coupled between a node of transistor 116 and ground. In this regard, resistor 110 and resistor 112 may also be referred to herein as step-down resistors for amplifier 108. In embodiments, resistor 110 and resistor 112 each include a resistance value (Rb) that is matched. In this regard, resistor 110 and resistor 112 may also be referred to herein as a pair of matched resistors.Due to the arrangement of resistor 110 and resistor 112, the voltage output (Vo) from current detection circuit 100 is proportional to the resistance (Rb).

[0071] Amplifier 108 may be configured to output the voltage (Vo). Amplifier 108 may output the voltage (Vo) by amplifying a voltage drop across resistor 102. The voltage (Vo) may thus be based on the current (Isns). Amplifier 108 may also be referred to as an operational amplifier, differential amplifier, or high-gain amplifier. Amplifier 108 may sense the input voltage across the boost resistors and drive the outputs so that the voltage on the side and right sides are equal. Providing an equal voltage on the left and right sides may provide a current proportional to the current (Isns). Amplifier 108 may have a gain based on the resistance (Rb) of the step-down resistors divided by the resistance (Rt) of the step-up resistors.For example, the resistance (Rt) of the boost resistors may be 1 kiloohm (1 kΩ resistor), although this is not intended to be limiting. Continuing the example, the resistance (Rb) of the step-down resistors may be 17.5 kiloohms (17.5 kΩ resistors), although this is not intended to be limiting. Where the boost resistors are 1 kΩ resistors and the step-down resistors are 17.5 kΩ resistors, the gain of the amplifier may be a factor of 17.5 (e.g., a gain of approximately 24.86 dB), although this is not intended to be limiting. In some cases, the gain of amplifier 108 may be selected based on the capability of a downstream analog-to-digital converter (ADC).

[0072] In embodiments, each of resistor 102, resistor 104, resistor 106, resistor 110, and resistor 112 are included in integrated circuit 700 such that the resistors may be considered "internal." Each of the resistors may be formed from one or more polysilicon elements that define the resistance (Rs), resistance (Rt), and resistance (Rb). It is further contemplated that resistor 102, resistor 104, and resistor 106 may have a substantially similar temperature coefficient and a similar aging coefficient.

[0073] In embodiments, resistor 102 is an internal resistor. The current sensing circuit can sense the current internally, without using an external component, such as an external sense resistor. Because resistor 102 is part of the integrated circuit, has a relatively low resistance, and a wide dynamic range of currents is to be measured, there may be challenges in designing current sensing circuit 100. In embodiments, resistor 102 is a precision resistor provided on-chip within the integrated circuit and combined with amplifier 108 to form current sensing circuit 100.The current measured across resistor 102 may be referred to herein as sensed current (Isns) and may be based on the resistance of the sense resistor (Rs) and the voltage drop between the directed voltage (Vrect) and the mean voltage (Vmid).

[0074] Current sensing circuit 100 includes a node 118 between resistor 102 and resistor 104. Node 118 may be configured to conduct the voltage (Vrect) to and from a rectifier, although this is not intended to be limiting. Current sensing circuit 100 may also include a node 120 between resistor 102 and resistor 104. Node 120 may be configured to conduct the voltage (Vmid) to and from a voltage regulator, although this is not intended to be limiting.

[0075] In embodiments, resistor 102 is incorporated into an integrated circuit along with amplifier 108. The boost resistors (e.g., resistor 104, resistor 106) and the step-down resistors (e.g., resistor 110, resistor 112) may also be part of the integrated circuit. By combining the amplifier components with resistor 102 on the integrated circuit, the temperature coefficient of resistor 102 and the step-up resistors may be substantially similar. In embodiments, an integrated circuit includes the boost resistors and the current sense resistors integrated into the layout.

[0076] In embodiments, one or more of resistor 102, resistor 104, resistor 106, resistor 110, or resistor 112 comprise a polysilicon resistor formed on the integrated circuit beneath a metallization layer. The polysilicon resistor may also be referred to herein as a polyresistor, an internal polyresistor. In embodiments, the polysilicon resistor is formed as an array of polysilicon elements. The polysilicon elements may also be referred to herein as polysilicon die. The polysilicon elements may comprise any polysilicon material known in the art. The polysilicon material may have a resistance that changes with temperature.The use of polysilicon material may be advantageous for reducing the temperature coefficient compared to implementing the resistors in metallization layers of the integrated circuit.

[0077] The polysilicon elements may encompass a wide range of dimensions. For example, the polysilicon elements used to form resistor 102, resistor 104, or resistor 106 may be relatively wide. For example, the polysilicon elements may be 50 micrometers wide. The polysilicon elements may further have a length such as, but not limited to, 4 micrometers. The aspect ratio of the polysilicon elements may thus be 50 micrometers to 4 micrometers. A temperature coefficient of 150 PPM / C was experimentally determined for polysilicon elements with an aspect ratio of 50 micrometers to 4 micrometers. By way of example, in another example, the polysilicon elements used to form resistor 110 or resistor 112 may be relatively narrow compared to the polysilicon elements of the boost resistors and the sense resistor.For example, the polysilicon elements of the buck resistors can be 1 micrometer wide. The polysilicon elements of the buck resistors can change over time due to aging. In embodiments, calibration is further performed using a calibration circuit (not shown) in response to a change in the resistance of the buck resistor.

[0078] One challenge in implementing resistor 102 within the integrated circuit is the temperature coefficient of resistor 102. Integrating the boost resistors into the resistor 102 array can allow for cancellation of the temperature coefficient for resistor (Rs) and resistance (Rt). Canceling the temperature coefficient can eliminate inaccuracies related to the temperature of the boost resistor and the current sense resistor. The voltage (Vo) can be proportional to the current (Isns), resistance (Rs), and resistance (Rb). The voltage can also be inversely proportional to the resistance (Rt).

[0079] Transistor 114 and transistor 116 may function as the gain stage of the amplifier. For example, if amplifier 108 initially detects a voltage difference at the inputs, the output signal from the amplifier may drive the gate of transistor 114 and transistor 116 high or low, causing transistors 126 and transistor 116 to act as current sources. It should be understood that transistor 114 and transistor 116 may generally comprise any transistor, such as, but not limited to, a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET or M). As depicted, transistor 114 and transistor 116 may be an N-channel MOS (NMOS), although this is not intended to be limiting.

[0080] The current sensing circuit 100 may also include a switch matrix. The switch matrix may include one or more switches 122, such as, but not limited to, a switch (M1), a switch (M2), a switch (M3), and a switch (M4). The switches (M1-M4) may be selectively opened and closed to configure the current sensing circuit in a receive mode, a transmit mode, and one or more offset calibration modes. The switch matrix may enable gain reversal during transmission or reception, respectively. The switch matrix may also allow for the measurement of an offset of the input voltages to the amplifier. Conveniently, the current sensing circuit 100 includes a current sensing accuracy to within 0.5 percent of an actual current flowing through the resistor 102.The switching matrix can provide direct offset measurement with minimal introduction of parasitic effects that can affect thermal performance.

[0081] Switches (M1-M4) can be arranged between resistor 102, resistor 104, and resistor 106. Switch (M1) is coupled between node 118 and resistor 104. Switch (M2) is coupled between node 120 and resistor 106. Switch (M3) is coupled between node 120 and resistor 104. Switch (M4) is coupled between node 118 and resistor 106.

[0082] Switches (M1-M4) enable measuring the current transfer from node 118 with voltage (Vrect) to node 120 with voltage (Vmid), measuring the current transfer from voltage (Vmid) to voltage (Vrect), and measuring the offset of the current sensing circuit. The processor can receive one or more digital signals of voltage (Vo) and determine the current (Isns) based on the voltage (Vo). The voltage (Vo) can also indicate the offset contributed by resistor 104, resistor 106, resistor 110, resistor 112, and amplifier 108, depending on which of the switches (M1-M4) are closed.

[0083] Current sensing circuit 100 is configured in a receive mode when switch (M1) and switch (M2) are closed and switch (M3) and switch (M4) are open. The processor can measure the current transfer from voltage (Vrect) to voltage (Vmid) in the receive mode. In the receive mode, the current sensing circuit can measure the current received by an integrated circuit of a wireless power system. The receive mode can correspond, for example, to communication received from a transmitter and / or wireless power. The wireless power system can thus be configured in the receive mode based on the configuration of the switches.

[0084] The current sensing circuit 100 is configured in a transmit mode when the switch (M3) and the switch (M4) are closed and the switch (M1) and the switch (M2) are open. The processor can measure the current from the voltage (Vmid) to the voltage (Vrect) in the transmit mode. In this regard, the switches (M1-M4) provide a possibility of reversing between transmitting (Tx) and receiving (Rx). In the transmit mode, the current sensing circuit can measure the current transmitted by an integrated circuit of a wireless power system. For example, the transmit mode can correspond to a communication transmitted by the wireless power system. The wireless power system can thus be configured in the transmit mode based on the configuration of the switches.

[0085] The current sensing circuit 100 is configured in a first offset mode to measure the offset of the current sensing circuit 100 when the switch (M1) and the switch (M4) are closed and the switch (M2) and the third switch (M3) are open. When the switch (M1) and the switch (M4) are on, the input of the current sensing circuit 100 may be shorted to node 118. The processor may be configured to measure the offset of the current sensing circuit 100 (e.g., the offset of the various resistors and the amplifier together) based on the one or more voltage (Vo) signals when the switch (M1) and the switch (M4) are closed and the switch (M2) and the switch (M3) are open.

[0086] Alternatively, in a second offset mode, the current sensing circuit 100 is configured to measure the offset of the current sensing circuit 100 when the switch (M2) and the switch (M3) are closed and the switch (M1) and the switch (M4) are open. When the switches M2 and M3 are turned on, the input of the current sensing circuit 100 may be shorted to the node 120. The processor may be configured to measure the offset of the current sensing circuit 100 based on the one or more voltage (Vo) signals when the switch (M2) and the switch (M3) are closed and the switch (M1) and the switch (M4) are open.

[0087] The processor can then use the offset to calibrate the measured current (Isns). For example, a voltage received by the ADC in offset mode, regardless of its voltage, is a zero-current reference. The zero-current reference can be subtracted from the voltage during the calibration phase. By implementing switches in the grouping of boost resistors, the current sensing circuit 100 can have both a transmit and receive mode and also perform a direct offset measurement of the resistive structures. Thus, the processor measures the offset for the current sensing circuit 100 based on the voltage (Vo) and compensates for the offset when determining the current (Isns).

[0088] The switches (M1-M4) can be controlled by one or more processors executing program instructions. The processor can include firmware that causes the processor to control the switches (M1-M4). The firmware can cause the processor to control the switches to perform an offset measurement of the current offset. The firmware can perform the offset measurement to determine what the current offset means for the structure and then use this offset information for calibration purposes.

[0089] It is understood that the switches (M1-M4) may generally comprise any switch, such as a transistor. The transistor may comprise, but is not limited to, a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET or M). As depicted, the switches (M1-M4) may be a P-channel MOS (PMOS), although this is not intended to be limiting.

[0090] With reference to Fig. 5A and Fig. 5B, the current sensing circuit 100 will now be described according to one or more embodiments of the present disclosure. In embodiments, the current sensing circuit 100 includes one or more channels. The current sensing circuit 100 may include a digital channel and an analog channel. The current sensing circuit 100 may include amplifier 108 for the digital channel coupled in parallel with an amplifier 146 for the analog channel. The amplifier 108 and the amplifier 146 may each include inputs coupled to node 118 and node 120.

[0091] The digital channel may provide one or more digital control loops using the first current (Isns). The digital channel may output the voltage (Vo) from amplifier 108 to an ADC. The ADC may then provide one or more digital signals of the voltage (Vo) to the processor. The processor may be configured to receive one or more digital signals of the third voltage (Vo) and further configured to determine the current (Isns) based on the voltage (Vo). The processor may also measure an offset contributed by resistor 104, resistor 106, resistor 110, resistor 112, and amplifier 108 to the current sensing circuit by switching one or more switches 122. The processor may then compensate for the offset when determining the current (Isns) for one or more digital control loops.When the processor switches the switches 122, the digital channel may be taken offline such that the processor does not determine the current (Isns) when one or more switches 122 are switched to determine the offset. Undesirably, the loss of the current measurement (Isns) may result in periods during which the current (Isns) may not be measured. However, it may be desirable to provide the offset measurement to improve the accuracy of the current (Isns) measurement for the digital control loops.

[0092] The analog channel may provide one or more analog control loops using the first current (Isns). The analog channel may output a voltage (Van) from the amplifier 146 to one or more circuits. The circuits may use the current (Isns) in one or more analog control loops for wireless power control. For example, the integrated circuit's analog control loop may include, but is not limited to, a load modulation circuit (ILOAD), a main voltage regulator (MVR), and the like. The voltage regulator may regulate a voltage output of the integrated circuit. Regulating the voltage output may be beneficial by allowing a battery charging system to charge a battery. The voltage regulator circuit may generally include any circuit for regulating voltage based on the analog control loop.

[0093] By providing the analog channel and the digital channel, the amplifier 146 can remain on when node 118 has the voltage (Vrect) and node 120 has the voltage (Vmid), ensuring that the analog channel continuously receives the current (Isns). The amplifier 146 can remain on regardless of the state of the switches 122, such that the switches can be switched to determine the offset without affecting the analog control loops. The analog channel can thus operate independently of the digital channel, allowing calibration of the digital channel while the analog control loops are operating. In this regard, the amplifier 108 may also be referred to herein as a switched amplifier, and the amplifier 146 may also be referred to herein as a permanently on amplifier.

[0094] Current sensing circuit 100 may additionally include any number of elements coupled to amplifier 146. Although not shown, current sensing circuit 100 may include one or more resistors coupled between node 118 or node 120 and the input of amplifier 146 (see, for example, resistor 104, resistor 106). Current sensing circuit 100 may include one or more elements coupled to the output of amplifier 146. For example, current sensing circuit 100 may include a transistor 148, a transistor 150, a resistor 152, and a resistor 154. Transistor 148 and transistor 150 may each be coupled to an output of amplifier 146. The voltage (Van) may thus be based on the input voltages of amplifier 146 and one or more resistors of the analog channel.For example, amplifier 146 may be a differential amplifier with a gain adjusted based on the resistance of the input and output.

[0095] Transistor 148 and transistor 150 may generally comprise any transistor, such as, but not limited to, a field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET or M). As depicted, transistor 148 and transistor 150 may be a P-channel MOS (PMOS), although this is not intended to be limiting.

[0096] Resistor 152 may be coupled between transistor 148 and ground. Similarly, resistor 154 may be coupled between transistor 150 and ground. Resistor 152 and resistor 154 may each have a resistance (Rt). For example, resistor 152 and resistor 154 may have a resistance of 17 kiloohms (17 kΩ), although this is not intended to be limiting. Resistor 152 and resistor 154 may also be referred to as a pair of matched step-down resistors.

[0097] Current sensing circuit 100 may include one or more elements coupled between the output and the input of amplifier 146. The one or more elements may include a resistor 156 and a resistor 158. Resistor 156 and resistor 158 may each have a matched resistance. For example, resistor 156 and resistor 158 may each have a resistance of 1 kiloohm (1 kΩ), although this is not limiting. Resistor 156 may be coupled between transistor 148 and a first input of amplifier 146. Similarly, resistor 158 may be coupled between transistor 150 and the second input of amplifier 148.

[0098] The current sensing circuit 100 may include one or more offset correction features. For example, the amplifier 146 may include chopper switches 151. The chopper switches 151 may also be called chopper clock feedback or the like. The chopper control loop may provide a chopper for offset correction of the amplifier 146. The offset correction of the amplifier 146 may improve accuracy of the analog channel. The chopper control loop may include a first chopper switch at the inputs of the amplifier 146. The first chopper switch may be configured to switch the inputs of the amplifier. For example, in another example, the chopper control loop may include a second chopper switch at the outputs of the amplifier 146. The second chopper switch may be configured to switch the outputs of the amplifier.

[0099] It is understood that the illustration of switches 122 is not limiting. For example, current sensing circuit 100 may include any number of switches for measuring the offset, such as, but not limited to, the four-switch configuration of Fig. 4 or the three-switch configuration of Fig. 5A.

[0100] With reference to Fig. 6, a layout of one or more components of current sensing circuit 100 will now be described in accordance with one or more embodiments of the present disclosure. As depicted, reactance 124, resistor 152, resistor 154, resistor 156, and resistor 158 are shown with different hatching, which is not to be interpreted as limiting. Rather, the resistors are shown with hatching to illustrate the number of grouping elements included with each resistor. It is contemplated that the layout of resistor 152, resistor 154, resistor 156, and resistor 158 may be advantageous for any number of current sensing circuits sensing current in a range of one milliampere to one ampere.

[0101] In embodiments, resistor 152, resistor 154, and resistor 156 each comprise a polysilicon resistor formed on a substrate. The polysilicon resistor may also be referred to herein as a polyresistor or internal polyresistor. In embodiments, the polysilicon resistor is formed as an array of the array elements, each of which comprises the polysilicon die. The polysilicon die may be disposed on a layer of the integrated circuit. As shown, resistor 152 and resistor 154 each comprise 17 of the array elements. Similarly, resistor 156 and resistor 158 are each shown as comprising 9 of the array elements.Furthermore, although not shown, the array elements of each of the resistors may be coupled in any number of series or parallel arrangements to achieve a desired resistance value. Each array element may comprise a number of polysilicon dies. The discussion of the polysilicon dies of . Fig. 1A to Fig. 2B is incorporated herein by reference. In this regard, the array elements may be formed from any number of polysilicon dies with any opening, resistivity, and temperature coefficient.

[0102] It may be desirable to ensure that resistor 152 and resistor 154 have a resistance value that is as closely matched as possible, for example, to ensure appropriate gain for one or more amplifiers of the current sensing circuit. In embodiments, resistor 152 and resistor 154 may comprise grouping elements with the polysilicon die arranged symmetrically about an axis 160. Similarly, resistor 156 and resistor 158 may comprise grouping elements with the polysilicon die arranged symmetrically about an axis 160. In this regard, the stress difference between the polysilicon die may be reduced. Reducing the stress difference may cause the matched pair of resistors to experience similar stress.Experiencing similar mechanical stress can cause the resistor to experience a similar change in resistance due to the piezoelectric resistivity. The polysilicon dies for resistor 152 can be arranged in a finger-like manner with resistor 154. Similarly, the polysilicon dies for resistor 156 can be arranged in a finger-like manner with resistor 158. As shown, the polysilicon dies for resistor 152 and resistor 154 are arranged in a mirror image with respect to axis 160. Additionally, the dies for resistor 156 and resistor 158 are arranged in a mirror image with respect to axis 160. Such an arrangement can also be referred to as a checkerboard pattern, although this is not intended to be limiting.

[0103] With reference to Fig. 7, an embodiment of an integrated circuit 700 will now be described in accordance with one or more embodiments of the present disclosure. The integrated circuit 700 may also be referred to herein as a transceiver unit, a mixed-signal chip, a wireless power chip, a wireless power receiver (Rx), a receiver integrated circuit (Rx), or the like. The integrated circuit 700 may be configured to receive and condition an alternating current (AC) power and output a regulated DC voltage. For example, the AC power may be received from a coil of a wireless power system, and the regulated DC voltage may be provided to a battery for charging the battery, although this is not intended to be limiting.In embodiments, the integrated circuit 700 may include one or more of a rectifier 702, a current sensing circuit 704 (e.g., the current sensing circuit 100), a processor 706, a power supply unit 708, a voltage regulator 710, an analog-to-digital converter 712, and the like. It is further contemplated that the integrated circuit 700 may include any number of additional components that are not depicted herein for clarity. For example, the integrated circuit 700 may further include various conductive traces between one or more of the rectifier 702, the current sensing circuit 704, the embedded processor 706, the power supply unit 708, the voltage regulator 710, and the analog-to-digital converter 712, which are not depicted here.

[0104] The rectifier 702 may be configured to receive an alternating current having a voltage (Vin). For example, the alternating current may be received from a coil of a wireless power system, although this is not intended to be limiting. The rectifier 702 may further be configured to generate a direct current having a voltage (Vrect). The voltage (Vrect) need not be regulated to a desired supply voltage. The rectifier 702 may generally comprise any suitable circuit for rectifying the current. For example, the rectifier 702 may comprise a bridge circuit, such as an H-bridge circuit.

[0105] Rectifier 702 may convert an input AC voltage into a rectified DC voltage when the integrated circuit is configured in a receive mode. The rectifier may also convert an input DC voltage into an output AC voltage when the integrated circuit is configured in a transmit mode. For example, in the receive mode, the integrated circuit may be configured to receive wireless power. By way of example, in another example, the integrated circuit may be configured in the receive mode and / or the transmit mode for wireless communication with a transmitter.

[0106] Regarding current sensing circuit 704, the discussion of current sensing circuit 100 is incorporated herein by reference. Current sensing circuit 704 may include a voltage (Vrect) from a node and a voltage (Vmid) from a node. The voltage (Vrect) may be higher or lower than the voltage (Vmid) depending on whether integrated circuit 700 is currently receiving or transmitting. Current sensing circuit 704 may further output a voltage (Vo) that may be used to determine the current (Isns).

[0107] The processor 706 may generally comprise any suitable processor. For example, the embedded processor 706 may be a microprocessor, although this is not intended to be limiting. The processor 706 may further comprise one or more memory blocks by which the processor 706 may be configured to perform any of the various methods described herein. The processor 706 may comprise, for example, but is not limited to, read-only memory (ROM) for performing boot operations, one-time program (OTP) memory for boot code, and / or random access memory (e.g., static RAM) for maintaining program instructions, for communication (e.g., FSK communication, ASK communication, etc.), and the like.

[0108] Processor 706 may generally be configured to perform various program functions that may be maintained in firmware. For example, processor 706 may be configured to receive various bits from analog-to-digital converter 712. Processor 706 may further be configured to determine a current (Isns) via current sensing circuit 704.

[0109] The power supply unit 708 may be configured to supply power to various components of the integrated circuit, such as, but not limited to, the embedded processor 706 or another component of the integrated circuit 700. The power supply unit 708 may generally provide any voltage level, such as, but not limited to, 1.2 volts, 1.8 volts, 3.3 volts, or 5 volts. The power supply unit 708 may draw power from any number of sources, such as, but not limited to, a main power rail of a communication device.

[0110] The voltage regulator 710 may be configured to receive the voltage (Vmid) from the current sensing circuit 704. The voltage regulator 710 may be further configured to regulate the voltage to a desired output. The regulated voltage may then be provided to a battery or a battery charging system for charging the battery. The regulated voltage may generally comprise any suitable output voltage for wireless charging, such as, but not limited to, 15 volts or 30 volts.

[0111] The analog-to-digital converter 712 may be configured to receive various voltages and / or currents from any one or more of the integrated circuit components and generate a digital signal from bits. For example, the analog-to-digital converter 712 may receive the voltage (Vo) from the current sensing circuit 704 and generate the digital signal based on the voltage (Vo). The analog-to-digital converter 712 may then provide the digital signal to the processor 706 for processing. It should be understood that the analog-to-digital converter 712 may generally comprise any analog-to-digital converter (ADC) and may further comprise a plurality of other converters for processing other signals not depicted herein.

[0112] Although current sensing circuit 704 is described as being a component of integrated circuit 700, this is not intended to be limiting. It is contemplated that current sensing circuit 100 and / or current sensing circuit 704 may be integrated into any number of integrated circuits. In this regard, reducing the pressure change due to the piezoresistive nature may be advantageous in any number of integrated circuits for providing precision current sensing over a wide dynamic range. The application may include any type of on-chip precision current sensing, whether the power is derived from wireless power or used for any type of integrated circuit power management.

[0113] In some cases, integrated circuit 700 may achieve a current sensing accuracy of 0.5% or better, which may be an improvement over the existing current sensing accuracy of 1.0%. Improving current sensing accuracy may be beneficial in enabling higher levels of power transfer while still meeting one or more safety requirements, such as, but not limited to, foreign object detection requirements.

[0114] With reference to Fig. 8, a wireless power system 800 will now be described according to one or more embodiments of the present disclosure. The wireless power system 800 may include one or more components, such as, but not limited to, a transmitter unit 802, a transmitter coil 804, a receiver coil 806, the integrated circuit 700, and a battery charger 808. The transmitter unit 802 and the integrated circuit 700 may be inductively coupled via the transmitter coil 804 and the receiver coil 806. In this regard, the integrated circuit 700 may wirelessly receive power from the transmitter unit 802 and provide the power to the battery charger 808 for charging one or more batteries. The integrated circuit 700 and the transmitter unit 802 may communicate wirelessly using any number of communication protocols.For example, integrated circuit 700 may receive transmit and receive communication to transmitter unit 802 to establish a transmission using one or more handshake protocols. The current sensing circuit may be configured to sense the current (Isns) in either the transmit or receive mode.

[0115] Providing high-accuracy current measurement from the current sensing circuitry within integrated circuit 700 is advantageous to aid in the detection of foreign objects. The more accurate the current sensing, the more accurately the power transfer can be performed within system 800. Power transfer levels for wireless power system 800 have increased over time. Accurate current sensing becomes increasingly important as power levels increase. Internally sensing current without the use of external resistors within the current sensing circuitry is also advantageous.

[0116] With reference to Fig. 9, a communication device 900 will now be described in accordance with one or more embodiments of the present disclosure. The communication device 900 may generally include one or more components of the wireless power system 800, by means of which the battery may be wirelessly charged. Peak wireless power transmission levels for the communication device 900 may range from 15 to 30 watts or more, and may continue to increase with advances in wireless power transmission protocols and hardware. Improved accuracy in the ability to sense power within the wireless power system 800 becomes increasingly important as peak wireless power transmission levels increase. The communication device 900 may generally include any type of device configured to communicate by transmitting or receiving a signal (e.g., digital, analog, etc.).) via a medium (e.g., wired, wireless, etc.) such as, but not limited to, a cellular phone, a modem, a network interface, and the like. In some cases, the communication device 900 is configured to communicate via the wireless energy system, such as for communicating between a transmitter and a receiver.

[0117] With general reference to Fig. 1A to Fig.9, for the purposes of the present disclosure, the term "processor" or "processing element" may be broadly defined to include any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processing (DSP) units). In this sense, the one or more processors may include any device for executing algorithms and / or instructions (e.g., program instructions stored in memory). Further, the memory may include any storage medium known in the art suitable for storing program instructions executable by the processor connected thereto.The storage medium may, for example, comprise a non-volatile storage medium. By way of example, in another example, the storage medium may include, but is not limited to, read-only memory (ROM), random access memory (RAM), a magnetic or optical storage device (e.g., a hard disk), a solid-state drive, and the like. It should further be noted that the storage medium may be housed together with the processor in a common controller enclosure. In embodiments, the storage medium may be housed remotely with respect to the physical location of the processor.

Claims

[1] Integrated circuit comprising: a first circuit comprising a first amplifier (108), a first resistor (102), a second resistor (104), a third resistor (106), a fourth resistor (110) and a fifth resistor (112); wherein the first resistor (102) has a first resistance value (Rs); wherein the second resistor (104) and the third resistor (106) each have a second resistance value (Rt); wherein the fourth resistor (110) and the fifth resistor (112) each have a third resistance value (Rb); wherein the first resistor (102) is configured to carry a first current (Isns) based on the first resistance value (Rs) and a voltage difference between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier (108) is configured to output a third voltage (Vo) based on the first current (Isns); wherein a gain of the first amplifier (108) is based on the second resistance value (Rt) and the third resistance value (Rb); wherein the first resistor (102) is formed from a first plurality of polysilicon dies; wherein the second resistor (104) is formed from a second plurality of polysilicon dies; wherein the third resistor (106) is formed from a third plurality of polysilicon dies; wherein the first plurality of polysilicon dies, the second plurality of polysilicon dies, and the third plurality of polysilicon dies are arranged on a layer of the integrated circuit; wherein the second plurality of polysilicon dies are arranged axially symmetrically to the third plurality of polysilicon dies such that a difference in mechanical stress between the second plurality of polysilicon dies and the third plurality of polysilicon dies is reduced. [2] The integrated circuit of claim 1, wherein the second plurality of polysilicon dies and the third plurality of polysilicon dies are arranged a first distance from a die edge to reduce the difference in stress between the second plurality of polysilicon dies and the third plurality of polysilicon dies. [3] The integrated circuit of claim 2, wherein the first resistor (102) comprises a first row and a second row of polysilicon die; wherein the first row is disposed between the die edge and the second plurality of polysilicon die; wherein the second row is disposed between the die edge and the third plurality of polysilicon die. [4] The integrated circuit of claim 3, wherein the first resistor (102) comprises a third row and a fourth row of polysilicon die, both disposed at the first distance from the die edge; wherein the third row is arranged axisymmetrically to the fourth row. [5] The integrated circuit of claim 4, wherein the second plurality of polysilicon dies and the third plurality of polysilicon dies are disposed between the third row and the fourth row. [6] The integrated circuit of claim 5, wherein the integrated circuit has a stress gradient; wherein the stress gradient decreases with increasing distance from the die edge and from the axis. [7] The integrated circuit of claim 1, further comprising a metallization layer; wherein the first plurality of polysilicon dies are coupled by means of the metallization layer; wherein the second plurality of polysilicon dies are coupled by means of the metallization layer; wherein the third plurality of polysilicon dies are coupled by means of the metallization layer; wherein at least some of the first plurality of polysilicon dies are coupled in parallel such that the first resistance value (Rs) is lower than the second resistance value (Rt). [8] The integrated circuit of claim 7, wherein the first plurality of polysilicon dies are coupled to the metallization layer by a first plurality of vias; wherein the second plurality of polysilicon dies are coupled to the metallization layer by a second plurality of vias. [9] The integrated circuit of claim 8, wherein a via resistance is matched between the first resistor and the second resistor. [10] System comprising: a coil configured to receive wireless energy; a battery charging system; and an integrated circuit according to any one of claims 1 to 9, further comprising: a rectifier configured to receive alternating current from the coil and generate the first voltage (Vrect); a voltage regulator configured to regulate the second voltage (Vmid); and a processor; wherein the processor is configured to receive one or more digital signals of the third voltage (Vo); wherein the processor is configured to determine the current (Isns) based on the third voltage (Vo).

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