METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER

Abstract

Method for manufacturing a semiconductor device comprising: Creating a silicon carbide substrate (12) having an upper surface (12a) on which an alignment mark (20, 20a) with a recessed shape is arranged, wherein a perpendicular line (12s) which is perpendicular to the upper surface of the silicon carbide substrate is inclined in respect of a [0001] direction in the direction of a [11-20] direction; Growth of an epitaxial layer (50) on the upper surface of the silicon carbide substrate to cover the alignment marker; and Forming a structure (20b, 80) on or above the upper surface of the silicon carbide substrate, wherein the structure is formed at a position at a distance P in the [11-20] direction along the upper surface of the silicon carbide substrate from the alignment mark, and the distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the vertical line with respect to the [0001] direction.

Description

[0001] The present invention relates to a method for manufacturing a semiconductor device and also relates to a semiconductor wafer.

[0002] JP 2019-56726 A discloses a silicon carbide substrate (SiC substrate) having a top surface on which an alignment mark is arranged in a recessed shape. In the SiC substrate, the top surface is inclined with respect to a (0001) plane such that one inclination direction, or off-direction, is a [11-20] direction. In other words, in the SiC substrate, a perpendicular line, which is perpendicular to the top surface of the SiC substrate, is inclined with respect to a

[0001] direction in the direction of the [11-20] direction. When an epitaxial layer grows on the upper surface of the SiC substrate to cover the alignment mark, a faceted surface inclined with respect to the upper surface of the SiC substrate is formed at a position adjacent to the alignment mark in the [11-20] direction.According to the technique disclosed in JP 2019 - 56 726 A, the formation of the faceted surface is limited by forming an alignment mark in a predetermined shape.

[0003] Even when using the technique disclosed in JP 2019-56726A, there may be cases where the formation of a faceted surface is not prevented. Due to various limitations, it may not be possible to form an alignment marker as disclosed in JP 2019-56726A and prevent the formation of a faceted surface. After an epitaxial layer has been formed to cover the alignment marker, alignment is performed using a recessed section on an upper surface of the epitaxial layer (that is, a recessed section formed subsequently after the alignment marker). If a faceted surface formed on the epitaxial layer interferes with other structures, an alignment device may not be able to properly detect the recessed section on the upper surface of the epitaxial layer, and proper alignment cannot be performed.

[0004] US Patent 2015 / 0303119A1 discloses a method for fabricating a silicon carbide semiconductor device. A silicon carbide substrate is prepared, the main surface of which is angled in a direction away from a {0001} plane. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming an epitaxial silicon carbide layer on the first alignment mark. The first alignment mark comprises a first region and a second region, the second region being in contact with the first region and extending from the first region in the direction away from it. The second alignment mark comprises a first section formed on the first region and a second section formed on the second region.An alignment step includes taking an image of the first section, excluding the second section, and identifying an edge of the first section based on the image.

[0005] The object of the invention is to provide a technique that enables correct alignment even when a faceted surface is formed in the epitaxial layer. This object is achieved by a method for manufacturing a semiconductor device with the features of claim 1 and by a semiconductor wafer with the features of claim 6. The dependent claims are directed to advantageous embodiments of the invention.

[0006] According to one aspect of the present invention, a method for fabricating a semiconductor device comprises creating a SiC substrate, growing an epitaxial layer, and forming a structure. The SiC substrate has a top surface on which an alignment marker with a recessed shape is arranged, and a perpendicular line, perpendicular to the top surface of the SiC substrate, is inclined with respect to a

[0001] direction in a [11-20] direction. The epitaxial layer grows on the top surface of the SiC substrate to cover the alignment marker. The structure is formed on or above the top surface of the SiC substrate at a position separated by a distance P in the [11-20] direction along the top surface of the SiC substrate.The distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the vertical line with respect to the

[0001] direction.

[0007] Note that creating the SiC substrate may involve bringing the SiC substrate with the alignment mark into a manufacturing facility or forming the alignment mark on the top surface of the SiC substrate.

[0008] The formation of the structure on or above the upper surface of the SiC substrate can be carried out before or after the growth of the epitaxial layer. In other words, the structure can be formed on the upper surface of the SiC substrate before the formation of the epitaxial layer, or the structure can be formed above the upper surface of the SiC substrate after the epitaxial layer has formed (that is, on an upper surface of the epitaxial layer).

[0009] According to experiments conducted by the inventors, it was found that the width of a faceted surface formed adjacent to the alignment mark as the epitaxial layer grows to cover the alignment mark can be estimated from the inclination angle θ (so-called off-angle) of the upper surface of the SiC substrate with respect to the

[0001] direction and the depth D of the alignment mark. In general, the width of the faceted surface is less than a width W calculated by the equation W = D / tan θ. By setting the distance P such that the relationship D / tan θ < P is satisfied, it is therefore possible to prevent the faceted surface from disturbing or negatively affecting the structure.If the distance P is unnecessarily widened, the area occupied by that distance becomes broader, potentially reducing the number of semiconductor devices that can be fabricated from the SiC substrate. As described above, by setting the distance P such that the relationship D / tan θ < P < 10D / tan θ (that is, W < P < 10W) ​​is satisfied, interference between the facet surface and the structure can be prevented without unnecessarily increasing the distance P. Since interference between the facet surface and the structure can be prevented, proper alignment can be achieved using the recessed section on the top surface of the epitaxial layer (that is, the recessed section formed downstream of the alignment marker).

[0010] According to another aspect of the present invention, a semiconductor wafer comprises a base substrate, an epitaxial layer, and a structure. The base substrate consists of silicon carbide and has a top surface on which an alignment marker with a recessed shape is arranged. A perpendicular line, perpendicular to the top surface of the base substrate, is inclined with respect to a

[0001] direction in a [11-20] direction. The epitaxial layer is arranged on the top surface of the base substrate and covers the alignment marker. The structure is arranged on the top surface of the base substrate or on a top surface of the epitaxial layer. The structure is arranged at a position at a distance P in the [11-20] direction along the top surface of the base substrate from the alignment marker.The distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the vertical line with respect to the

[0001] direction.

[0011] With the semiconductor wafer described above, it is possible to perform proper alignment using the recessed section on the upper surface of the epitaxial layer.

[0012] Further tasks and advantages of the present invention will become clear from the following detailed description with reference to the accompanying drawings. These show: Fig. 1 a top view of a SiC substrate; Fig. 2 a cross-sectional view of the SiC substrate; Fig. 3 a top view of alignment markings on an upper surface of the SiC substrate; Fig. 4 a cross-sectional view showing a first method for producing the alignment marks; Fig. 5 a cross-sectional view showing a process in a second procedure for forming the alignment marks; Fig. 6 a cross-sectional view showing a process in the second procedure for forming the alignment marks following the process in Fig. 5 represents; Fig. 7 a cross-sectional view showing a process in the second procedure for forming the alignment marks following the process in Fig. 6 represents; Fig. 8 a cross-sectional view showing a process in a third method for forming the alignment marks; Fig. 9 a cross-sectional view showing a process in the third procedure for forming the alignment marks following the process in Fig. 8 represents; Fig. 10 a cross-sectional view showing a process in the third procedure for forming the alignment marks following the process in Fig. 9 represents; Fig. 11 an enlarged cross-sectional view of the alignment markings; Fig. 12 a top view of alignment markings on an upper surface of a SiC layer; Fig. 13 a cross-sectional view showing a process in an epitaxial growth process; Fig. 14 a cross-sectional view showing a process in the epitaxial growth process following the process in Fig. 13 represents; Fig. 15 a cross-sectional view showing a process in the epitaxial growth process following the process in Fig. 14 represents; Fig. 16 a cross-sectional view showing a process in the epitaxial growth process following the process in Fig. 15 represents; Fig. 17 an enlarged cross-sectional view showing an alignment mark according to a second embodiment; Fig. 18 a cross-sectional view showing an epitaxial growth process according to the second embodiment; Fig. 19 a cross-sectional view showing a structure formation process according to the second embodiment; Fig. 20 a cross-sectional view showing a structural formation process according to a modification of the second embodiment; and Fig. 21 a top view showing an alignment mark formed on a top surface of a SiC substrate according to a modification. First embodiment

[0013] In a manufacturing process of a first embodiment, a semiconductor device is manufactured from a SiC substrate 12, as described in Fig. 1 and Fig. Figure 2 shows the SiC substrate 12 consisting of 4H-SiC. Hereinafter, one thickness direction of the SiC substrate 12 is referred to as the z-direction, a direction perpendicular to the z-direction is referred to as the x-direction, and a direction perpendicular to both the z-direction and the x-direction is referred to as the y-direction. The x-direction and the y-direction are parallel to an upper surface 12a of the SiC substrate 12. As shown in Fig. As shown in Figure 2, a [1-100] direction of the SiC substrate 12 coincides with the y-direction. A (0001) plane of the SiC substrate 12 is inclined at an off-angle θ about the [1-100] direction with respect to the upper surface 12a of the SiC substrate 12. In other words, the (0001) plane is inclined with respect to the upper surface 12a in a cross-section that includes an [11-20] direction and a

[0001] direction. A perpendicular line 12s in Fig. Figure 2 indicates a vertical line that is perpendicular to the upper surface 12a. Since the (0001) plane is inclined at the off-angle θ with respect to the upper surface 12a, the vertical line 12s is inclined with respect to the

[0001] direction by the off-angle θ in the direction of [11-20]. Note that the off-angle θ can be equal to or less than 10 degrees, or equal to or less than 5 degrees. For example, the off-angle θ can be approximately 4 degrees. If, as in Fig. Figure 1 shows the upper surface 12a of the SiC substrate 12 viewed from above, the x-direction extends along the [11-20]-direction.

[0014] In the manufacturing process of the first embodiment, an orientation mark formation process is first carried out. In the orientation mark formation process, orientation marks 20 are formed on the upper surface of the SiC substrate 12, as described in Fig. Figure 3 shows that each of the alignment marks 20 has a recessed shape arranged on the upper surface 12a of the SiC substrate 12. Each of the alignment marks 20 has long sides extending in the y-direction and short sides extending in the x-direction. When the upper surface 12a of the SiC substrate 12 is viewed from above, a side face 24 (i.e., an edge segment) of each of the alignment marks 20, which are aligned in the [11-20] direction, is perpendicular to the [11-20] direction. The alignment marks 20 are arranged at a distance or interval P from each other in the x-direction. Even if it is in Fig. Not shown in Figure 1, the upper surface 12a of the SiC substrate 12 has an elemental region in which a semiconductor element structure is formed and an outer region outside the elemental region. The outer region is a region that is removed when the SiC substrate 12 is divided into multiple semiconductor devices by a dicing process. Each of the alignment marks 20 is formed in the outer region of the upper surface 12a of the SiC substrate 12.

[0015] In the alignment marker training process, the alignment markers 20 can be trained using various methods. A first training method for the alignment markers 20 is described with reference to Fig. 4 described. In the first training procedure, the following is initially done as in Fig. Figure 4 shows a resist mask 30, which has opening sections 30a, formed on the upper surface 12a of the SiC substrate 12. The upper surface 12a of the SiC substrate 12 is then etched through the opening sections 30a by anisotropic etching. Accordingly, the alignment markings 20 are formed with a corresponding recessed shape in the respective opening sections 30a. After the alignment markings 20 have been formed, the resist mask 30 is removed.

[0016] A second training procedure for the alignment markers 20 is carried out with reference to the Fig. 5 to 7 described. The Fig. Figures 5 to 7 show cross-sectional views of element area 13 and the exterior area 14. In the second training procedure, as in Fig. Figure 5 shows a hard mask 32 (for example, a silicon oxide mask) formed on the upper surface 12a of the SiC substrate 12. The hard mask 32 is a mask for controlling an area of ​​ion implantation into the SiC substrate 12. Subsequently, a resist mask 34, which has opening sections 34a, is formed on the hard mask 32. As shown in Fig. As shown in Figure 6, the hard mask 32 is then etched through the opening sections 34a by anisotropic etching. Accordingly, opening sections 32a are formed in the hard mask 32. Since the opening sections 32a are formed such that they reach the SiC substrate 12, the upper surface 12a of the SiC substrate 12 is over-etched when the opening sections 32a are formed. Consequently, recessed features are formed on the upper surface 12a of the SiC substrate 12. The recessed features formed in the outer area 14 become alignment marks 20. After the formation of the opening sections 32a in the hard mask 32, the resist mask 34 is removed. Subsequently, n-type or p-type impurity ions are implanted into the upper surface 12a of the SiC substrate 12 through the hard mask 32. As described in Fig. As shown in Figure 7, a diffusion layer 40 is formed in the SiC substrate 12 below the opening sections 32a. In element area 13, the diffusion layer 40 is formed at the required positions. In the outer area 14, the diffusion layer 40 is formed below the alignment markings 20. Even if the diffusion layer 40 is formed below the alignment markings 20, no particular problem arises. As described above, in the second formation method, the alignment markings 20 are formed using the phenomenon that the upper surface 12a of the SiC substrate 12 is over-etched when the opening sections 32a are formed in the hard mask 32 for ion implantation.

[0017] A third method for forming the alignment marks 20 is described with reference to the Fig. 8 to 10 described. The Fig. Figures 8 to 10 represent cross-sections of element area 13 and the outer area 14. In the third training procedure, the process is initially carried out as in Fig. Figure 8 shows a resist mask 36, which has opening sections 36a, formed on the upper surface 12a of the SiC substrate 12. Subsequently, n-type or p-type impurity ions are implanted into the upper surface 12a of the SiC substrate 12 through the resist mask 36. As shown in Fig. As shown in Figure 9, a diffusion layer 40 is formed in the SiC substrate 12 below the opening sections 36a. In the element area 13, the diffusion layer 40 is formed at the required positions. Furthermore, in the outer area 14, the diffusion layer 40 is formed at a position where the alignment markings 20 are to be formed. Subsequently, the SiC substrate 12 is etched through the opening sections 36a by anisotropic etching. As shown in Figure 9, the diffusion layer 40 is formed at the required positions. Fig. As shown in Figure 10, corresponding recessed shapes are provided on the upper surface 12a of the SiC substrate 12. The recessed shapes provided in the outer area 14 become the alignment marks 20. After the alignment marks 20 have been formed, the resist mask 36 is removed.

[0018] Fig. Figure 11 shows a cross-sectional view along line XI-XI of the Fig. 3. In other words, Fig. Figure 11 shows a cross-sectional view of the alignment marks 20a and 20b below the alignment marks 20 along the x-direction. Although the alignment marks 20a and 20b are in Fig. The other alignment markers 20 are shown in the same form as in 11. Fig. 11 depicted trained. As it is in Fig. As shown in Figure 11, the depth D of each of the alignment marks 20 is less than the width Wa of each of the alignment marks 20 in the x-direction. A distance P exists in the x-direction between the respective alignment marks 20.

[0019] In the manufacturing process of the first embodiment, an epitaxial growth process is carried out following the alignment marker formation process. In the epitaxial growth process, a SiC layer 50 is grown on the upper surface 12a of the SiC substrate 12, as described in Fig. Figure 13 shows that the SiC layer 50 is formed to cover the respective alignment markings 20. When the respective alignment markings 20 are covered with the SiC layer 50, recessed shapes, which follow or correspond to the recessed shapes of the alignment markings 20, are formed on the upper surface of the SiC layer 50. The recessed shapes, which follow the shapes of the alignment markings 20 and are formed on the upper surface of the SiC layer 50, are referred to below as alignment markings 60. As shown in Figure 13, the SiC layer 50 is formed to cover the respective alignment markings 20. Fig. As shown in Figure 12, a faceted surface 60F is formed on a portion of the respective alignment markings 60. The formation of the faceted surface 60F is described below.

[0020] The Fig. Figures 13 to 16 illustrate how the SiC layer 50 grows epitaxially on the upper surface 12a of the SiC substrate 12 during the epitaxial growth process. In the following description, the SiC substrate 12 prior to the epitaxial growth process is referred to as the base substrate 12b, and the entirety of the base substrate 12b and the SiC layer 50 is referred to as the SiC substrate 12. As shown in Fig. As shown in Figure 13, when the SiC layer 50 grows on the base substrate 12b, the alignment markers 60 with recessed shapes that follow the recessed shapes of the alignment markers 20 are formed on the upper surface of the SiC layer 50. In the following description, the alignment marker 60 that follows the recessed shape of the alignment marker 20a can be referred to as alignment marker 60a, and the alignment marker 60 that follows the recessed shape of the alignment marker 20b can be referred to as alignment marker 60b. As shown in Figure 13, the alignment markers 60 are formed on the upper surface of the SiC layer 50. Fig. As shown in Figure 13, the SiC layer 50 grows to a substantially uniform film thickness in an area extending over the upper surface 12a of the base substrate 12b, the side surfaces 22 of the alignment marks 20 arranged in the [-1-120] direction, and the bottom surfaces 23 of the alignment marks 20. Hereinafter, the film thickness of the SiC layer 50 on the upper surface 12a of the base substrate 12b (more precisely, the film thickness of the section where the film thickness is uniform) is referred to as film thickness T. The SiC layer 50 hardly grows on the side surfaces 24 of the alignment marks 20, which are arranged in the [11-20] direction. Therefore, the SiC layer 50 on the upper surface 12a does not grow uniformly within an area adjacent to the alignment marks 20 in the [11-20] direction.In this area, the SiC layer 50 grows such that its film thickness increases with increasing distance to the alignment marks 20, and its surface is parallel to the (0001) plane. The surface of the SiC layer 50 that is parallel to the (0001) plane is the faceted surface 60f.

[0021] If the film thickness T of the SiC layer is 50% of that in Fig. The state shown in 13 is further increased, the one in Fig. The state shown in section 14 is maintained. Fig. 14 represents a virtual line 50x the surface of the SiC layer 50 in the state of Fig. 13, and a film thickness increase quantity ΔT1 indicates an increase in film thickness compared to the state of Fig. 13 on. As it is in Fig. As shown in Figure 14, even when the film thickness T increases, the SiC layer 50 does not grow on the original facet surface 60F. When the film thickness T increases, the SiC layer 50 grows such that the surface of the SiC layer 50, parallel to the (0001) plane, is located at a position adjacent to the original facet surface 60F in the [11-20] direction. That is, the facet surface 60F expands in the [11-20] direction. A width Wf in the Fig. 13 and Fig. 14 indicates the width of the faceted surface 60F in the x-direction. As stated in the Fig. 13 and Fig. As shown in Figure 14, the width Wf of the faceted surface 60F increases with an increase in the film thickness T. If the film thickness T is less than the depth D of the alignment marks 20, the width Wf of the faceted surface 60F thus increases with an increase in the film thickness T. In this case, the width Wf of the faceted surface 60F satisfies the relationship Wf = T / tan θ relatively closely.

[0022] If the film thickness T depends on the state of Fig. As the film thickness T is further increased from 14, it reaches the depth D of the alignment marks 20, as shown in Fig. Figure 15 is shown. Then the alignment marks 20 are filled with the SiC layer 50. In this state (that is, T = D), the width Wf of the facet surface 60F satisfies the relationship Wf = D / tan θ relatively closely.

[0023] If the film thickness T depends on the state of Fig. As the 15 is further increased, the SiC layer 50 grows, as shown in Fig. 16 is shown. Fig. 16 represents a virtual line 50y the surface of the SiC layer 50 in the state of Fig. 15, and a film thickness increase quantity ΔT2 indicates a film thickness increase compared to the state of Fig. 15. As is determined by the film thickness increase parameter ΔT2 in Fig. As shown in Figure 16, the SiC layer 50 grows essentially uniformly across the entire surface after the alignment marks 20 have been filled. In other words, the SiC layer 50 grows on the faceted surface 60F with a uniform film thickness similar to that on the other surfaces. When the SiC layer 50 grows in this way, even if the film thickness T of the SiC layer 50 increases, the width Wf of the faceted surface 60F hardly changes. If the film thickness T is greater than the depth D, the width Wf of the faceted surface 60F hardly changes even if the film thickness T increases. Therefore, if the film thickness T is greater than the depth D, the width Wf of the faceted surface 60F satisfies the relationship Wf = D / tan θ relatively closely.

[0024] If, as described above, the film thickness T is less than the depth D (that is, in the states of Fig. 13 and Fig. 14) is, the width Wf of the facet surface 60F can satisfy the relationship Wf = T / tan θ relatively closely. Since T < D, in this case the width Wf satisfies the relationship Wf < D / tan θ relatively closely. If the film thickness T is equal to or greater than the depth D (that is, in the states of the Fig. 15 and Fig. 16), the width Wf satisfies the relationship Wf = D / tan θ relatively closely. Therefore, the width Wf is normally no larger than the width W calculated using the equation W = D / tan θ, regardless of the film thickness T. By making the distance P in the x-direction between the orientation marks 20a and 20b larger than the width W calculated by the equation above, it is therefore possible to prevent the faceted surface 60F of the orientation mark 60a from interfering with the orientation mark 60b.

[0025] Note that due to the influence of manufacturing conditions and similar factors, the actual width Wf of the facet surface 60F may be larger than the calculated width W. Therefore, it is advantageous to specify the spacing P within a tolerance relative to the calculated width W. However, if the spacing P is increased more than necessary relative to the calculated width W, the area occupied by the alignment marks 20 becomes large, resulting in a reduction in the number of semiconductor devices that can be fabricated from the SiC substrate 12. Furthermore, if the area occupied by the alignment marks 20 becomes large, the photographic gain when the alignment marks are photographed with an alignment camera will be small, and the alignment accuracy will deteriorate.Based on various experiments conducted by the inventors, it was found that the actual width Wf of the faceted surface 60F should not exceed ten times the calculated width W. Therefore, if the distance P satisfies the relationship W < P < 10W (that is, the relationship D / tan θ < P < 10D / tan θ), it is possible to limit the adverse influence of the faceted surface 60F of the alignment mark 60 on the adjacent alignment mark 60 and the extent of the area occupied by the alignment marks 20. In the manufacturing process of the first embodiment, it is possible to limit the adverse effect of the faceted surface 60F of the alignment mark 60 on the adjacent alignment mark 60 and the extent of the area occupied by the alignment marks 20, since the distance P satisfies the relationship W < P < 10W.

[0026] In the manufacturing process of the first embodiment, an alignment process is performed using the alignment markers 60 after the epitaxy growth process. For example, alignment is performed using the alignment markers 60, and etching, ion implantation, or similar processes can be carried out on the SiC layer 50, other semiconductor layers besides the SiC layer 50, or other layers such as electrode layers, insulating layers, or the like. For example, if ions are implanted into the grown SiC layer 50, alignment can be performed using the alignment markers 60 to precisely form opening sections in an ion implantation mask, and ions can be implanted into the SiC layer 50 through the ion implantation mask.Since the faceted surface 60F of the alignment mark 60 does not interfere with another alignment mark 60, alignment can be performed correctly using the alignment marks 60. Because the distance P between the alignment marks 60 is relatively small, the gain or magnification can be increased when the alignment marks 60 are photographed with the alignment camera. Therefore, alignment can be performed with high accuracy.

[0027] The SiC substrate 12 is then divided or cut into several parts, thereby producing several semiconductor devices.

[0028] The semiconductor wafer (that is, the SiC substrate 12), which is in Fig. As shown in Figure 16, the semiconductor wafer has the following configuration. The semiconductor wafer (i.e., the SiC substrate 12) has the base substrate 12b and an epitaxial layer (i.e., the SiC layer 50). The base substrate 12b has the upper surface 12a, on which the alignment marker 20a with the recessed shape is arranged. As shown in Fig. As shown in Figure 2, the vertical line 12s, which is perpendicular to the upper surface 12a, is inclined in the direction of [11-20] with respect to the

[0001] direction. As shown in Fig. As shown in Figure 16, the epitaxial layer (i.e., the SiC layer 50) is arranged on the upper surface 12a of the base substrate 12b and covers the alignment markings 20a. The alignment marking 20b, which has a recessed shape, is arranged as a structure on the upper surface 12a of the base substrate 12b. The structure (i.e., the alignment marking 20b) is located at a position at a distance P in the [11-20] direction along the upper surface 12a of the base substrate 12b, separated from the alignment marking 20a. The distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is the depth of the alignment mark 20a and θ is the inclination angle (i.e. the off-angle) of the perpendicular line 12s, which is perpendicular to the upper surface 12a, with respect to the

[0001] direction.Therefore, in this semiconductor wafer, the faceted surface 60F of the alignment mark 60a does not interfere with the alignment mark 60b, and proper alignment can be achieved using the alignment mark 60a. This means that semiconductor devices can be suitablely manufactured using this semiconductor wafer. Second embodiment

[0029] In a manufacturing process of a second embodiment, semiconductor devices are made from the SiC substrate 12, which is in the Fig. 1 and Fig. Figure 2 is shown, as manufactured in the first embodiment. In this manufacturing process, an alignment mark 20 with a recessed shape is formed on the upper surface 12a of the SiC substrate 12 in a similar manner to the first embodiment. As is shown, for example, in Fig. As shown in Figure 17, an alignment mark 20 with a depth D smaller than the width Wa is formed. As shown in Fig. As shown in Figure 18, a SiC layer 50 is then epitaxially grown on the SiC substrate 12 (i.e., the base substrate 12b) to cover the alignment marker 20. Accordingly, an alignment marker 60, which follows the shape of the alignment marker 20, is formed on an upper surface of the SiC layer 50. In addition, a faceted surface 60F is formed at a position adjacent to the alignment marker 60 in the [11-20] direction.

[0030] As it is in Fig. As shown in Figure 19, a structure 80 having a protruding shape is subsequently formed on the upper surface of the SiC substrate 12 (i.e., the upper surface of the SiC layer 50). Note that the structure 80 can be a conductor, an insulator, or a semiconductor. The structure 80 can be part of a semiconductor device or part of a mask. In the present embodiment, the structure 80, which has a protruding shape, is formed separately from the alignment mark 20 at a position in the [11-20] direction. A distance P is present between the alignment mark 20 and the structure 80. The distance P satisfies the relationship W < P < 10D, i.e., the relationship D / tan θ < P < 10D / tan θ. Accordingly, interference or adverse influence between the structure 80 and the facet surface 60F can be limited or prevented.This can be prevented without increasing the distance between structure 80 and alignment mark 20 more than necessary.

[0031] An alignment process is then carried out using the alignment marker 60. Since the faceted surface 60F of the alignment marker 60 does not interfere with the structure 80, an alignment using the alignment marker 60 can be carried out correctly.

[0032] The SiC substrate 12 is then divided or cut into several parts, thereby producing several semiconductor devices.

[0033] The semiconductor wafer (that is, the SiC substrate 12), which is in Fig. As shown in Figure 19, the semiconductor wafer has the following configuration. The semiconductor wafer (i.e., the SiC substrate 12) has the base substrate 12b and an epitaxial layer (i.e., the SiC layer 50). The base substrate 12b has a top surface 12a on which the alignment mark 20 with the recessed shape is arranged. As shown in Fig. As shown in Figure 2, the vertical line 12s, which is perpendicular to the upper surface 12a, is inclined in the direction of [11-20] with respect to the

[0001] direction. As shown in Fig. As shown in Figure 19, the epitaxial layer (i.e., the SiC layer 50) is arranged on the upper surface 12a of the base substrate 12b and covers the alignment mark 20. The structure 80 is arranged on the upper surface of the epitaxial layer (i.e., the SiC layer 50). The structure 80 is positioned at a distance P in the [11-20] direction on the upper surface 12a of the base substrate 12b, separated from the alignment mark 20. The distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is the depth of the alignment mark 20a and θ is the angle of inclination (i.e., the off-angle) of the perpendicular line 12s, which is perpendicular to the upper surface 12a, with respect to the

[0001] direction. Therefore, the faceted surface 60F in this semiconductor wafer does not interfere with the structure 80, and proper alignment can be carried out using the alignment mark 60.

[0034] In the second embodiment described above, the structure 80 is a projecting section arranged on the upper surface of the SiC layer 50. As shown in Fig. As shown in Figure 20, the structure 80 can also be a recessed section located on the upper surface of the SiC layer 50. This configuration can also prevent interference between the structure 80 and the faceted surface 60F.

[0035] In the first and second embodiments described above, each of the alignment markings 20 has a rectangular shape on the upper surface 12a of the SiC substrate 12. Each of the alignment markings 20 can also have a different shape. In this case, a side face of the respective alignment marking 20, which is arranged in the [11-20] direction, need not be perpendicular to the [11-20] direction. As is the case, for example, in Fig.As shown in Figure 21, a side surface 24 (i.e., an edge segment) of a respective alignment mark, which is arranged in the [11-20] direction, can extend along a direction that diagonally crosses the [11-20] direction.

[0036] In the first and second embodiments described above, the SiC layer 50 grows such that its thickness T is greater than the depth D of the alignment mark 20. Alternatively, the SiC layer 50 can grow such that its thickness T is less than the depth D of the alignment mark 20. Even in this case, by setting the distance P such that the relationship D / tan θ < P < 10D / tan θ is satisfied, interference between the facet surface 60F and other structures can be limited without increasing the distance P more than necessary.

[0037] In the first and second embodiments described above, the orientation markings 20 are formed. Alternatively, the SiC substrate 12, pre-formed with the orientation markings 20 satisfying the relationship D / tan θ < P < 10D / tan θ, can be purchased and placed in a manufacturing facility. Even if the same epitaxial growth process and the same orientation process as in the first and second embodiments are performed on the SiC substrate 12 on which the orientation markings 20 were pre-formed, the same effects as in the first and second embodiments can be obtained.

[0038] The SiC layer 50 in the first and second embodiments is an example of the epitaxial layer. The alignment markings 20a, 20 in the first and second embodiments are examples of the first alignment marking. The alignment marking 20b of the first embodiment is an example of the structure having a recessed shape that is formed on the upper surface of the SiC substrate prior to the formation of the epitaxial layer. The structure 80 of the second embodiment is an example of the structure having a protruding or recessed shape that is formed on the upper surface of the epitaxial layer. The alignment markings 60a and 60 of the first and second embodiments are examples of the second alignment marking.

Claims

[1] Method for manufacturing a semiconductor device comprising: Creating a silicon carbide substrate (12) having an upper surface (12a) on which an alignment mark (20, 20a) with a recessed shape is arranged, wherein a perpendicular line (12s) which is perpendicular to the upper surface of the silicon carbide substrate is inclined with respect to a [0001] direction in the direction of a [11-20] direction; Growth of an epitaxial layer (50) on the upper surface of the silicon carbide substrate to cover the alignment marker; and Forming a structure (20b, 80) on or above the upper surface of the silicon carbide substrate, wherein the structure is formed at a position at a distance P in the [11-20] direction along the upper surface of the silicon carbide substrate from the alignment mark, and the distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the vertical line with respect to the [0001] direction. [2] Method for producing a semiconductor device according to claim 1, wherein forming the structure includes forming the structure (20b) having a recessed shape on the upper surface of the silicon carbide substrate prior to the growth of the epitaxial layer. [3] Method for manufacturing a semiconductor device according to claim 1, wherein forming the structure includes forming the structure (80) having a protruding shape or a recessed shape on an upper surface of the epitaxial layer. [4] Method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein when the upper surface of the silicon carbide substrate is viewed from above, an edge section (24) of the alignment mark which is arranged in the [11-20] direction is perpendicular to the [11-20] direction. [5] Method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the alignment marker is a first alignment marker, the growth of the epitaxial layer includes the formation of a second alignment mark (60, 60a) on an upper surface of the epitaxial layer, wherein the second alignment mark has a recessed shape that follows the recessed shape of the first alignment mark, and The manufacturing process also includes performing an alignment using the second alignment mark. [6] Semiconductor wafer which has: a base substrate (12b) consisting of silicon carbide and having an upper surface (12a) on which an alignment mark (20, 20a) with a recessed shape is arranged, wherein a perpendicular line (12s) perpendicular to the upper surface of the base substrate is inclined in a [0001] direction in the direction of a [11-20] direction; an epitaxial layer (50) arranged on the upper surface of the base substrate and covering the alignment marker; and a structure (20b, 80) arranged on the upper surface of the base substrate or an upper surface of the epitaxial layer, wherein the structure is arranged at a position at a distance P in the [11-20] direction along the upper surface of the base substrate from the alignment mark, and the distance P satisfies the relationship D / tan θ < P < 10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the vertical line with respect to the [0001] direction. [7] Semiconductor wafer according to claim 6, wherein the structure (20b) is a recessed section arranged on the upper surface of the base substrate. [8] Semiconductor wafer according to claim 6, wherein the structure (80) is a protruding section or a recessed section arranged on the upper surface of the epitaxial layer. [9] Semiconductor wafer according to any one of claims 6 to 8, wherein, when the upper surface of the base substrate is viewed from above, an edge section (24) of the alignment mark which is arranged in the [11-20] direction is perpendicular to the [11-20] direction. [10] Semiconductor wafer according to any one of claims 6 to 9, wherein the alignment marker is a first alignment marker, and the upper surface of the epitaxial layer has a second alignment mark (60, 60a) which has a recessed shape that follows the recessed shape of the first alignment mark.

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