Method for fabricating a vertical field-effect transistor structure and corresponding vertical field-effect transistor structure

Abstract

The invention relates to a method for manufacturing a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure. The vertical field-effect transistor structure is equipped with a semiconductor body (100) having a first terminal zone (12, 14) and a second terminal zone (30) of a first line type (n), a channel zone (20) of the first line type (n) or of a second line type (p) complementary to the first line type arranged between the first and second terminal zones (12, 14; 30), a plurality of grooves (60') extending into the semiconductor body (100) from the second terminal zone (30) through the channel zone (20) to the first terminal zone (12, 14) and forming fins (FI) of the channel zone (20) and the second terminal zone (30), a control electrode (40) arranged in the grooves (60'), which is adjacent to the channel zone (20) and insulated from the semiconductor body (100), and a (12, 14;30) and a breakdown current path connected in parallel to the channel zone (20), which has at least one pn junction and is configured to conduct when a breakdown voltage applied between the first and second terminal zones (12, 14; 30) is reached. The semiconductor body (100) has a doped zone (90; 90a) of the second conduction type (p) in the first terminal zone (12, 14) below a first trench of the trenches (60'), while the first terminal zone (12, 14) below a second trench of the trenches (60') does not have a doped zone (90; 90a) of the second conduction type (p). The fins (FI) have body connection areas (22'; 22") of the second conductor type (p) which electrically contact the channel zone (20) and the second connection zone (30), the body connection areas (22'; 22") of the second conductor type (p) extending into the drift zone (14).

Description

[0001] The invention relates to a method for manufacturing a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure. State of the art

[0002] For the application of wide bandgap semiconductors (e.g. silicon carbide (SiC) or gallium nitride (GaN)) in power electronics, vertical channel power MOSFETs (TMOSFETs) are typically used.

[0003] In the TMOSFET concept, the n+ source region and the p-channel region within a semiconductor material are interrupted by trenches that extend to the n-drift region. A gate electrode, separated from the semiconductor material by a gate oxide, is located within the trenches and serves to control the channel region.

[0004] By appropriately selecting the geometry, epitaxy, channel and screening doping, the on-resistance, threshold voltage, short-circuit resistance, oxide loading and breakdown voltage of such TMOSFETs can be optimized.

[0005] Fig. Figure 3 shows a partial perspective view of a vertical field-effect transistor structure according to the prior art of DE 102 24 201 B4 as the starting point of the present invention.

[0006] The in Fig. Figure 3 of the semiconductor device depicted implements an n-type vertical trench MOSFET with a shielding structure arranged along the trenches. The known structure is, of course, also applicable to p-type MOSFETs, in which case the doping configurations described below would have to be reversed.

[0007] The semiconductor device comprises a semiconductor body 100 with an n-doped first termination zone 12, 14. This first termination zone 12, 14 is more heavily n-doped on the back side of the semiconductor body 100 and forms the n+ drain zone 12 of the MOSFET there, while a less heavily n-doped n- drift zone 14 adjoins the n+ drain zone 12. The semiconductor body 100 further comprises a p channel zone or body zone 20, which adjoins the n- drift zone 14 and is located between the n- drift zone 14 and a second, heavily n-doped n+ termination zone 30 formed on the front side. The second n+ termination zone 30 forms the source zone of the MOSFET.

[0008] Starting from the front face 101 of the semiconductor body 100, several trenches 60 extend, of which in Fig. 4 two are shown, through the n+ source zone 30, the p body zone 20 to the n- drift zone 14 of the semiconductor body 100.

[0009] Control electrodes 40, which together form the gate electrode of the MOSFET, are arranged in the region of the side walls of the trenches 60. These gate electrodes 40 are insulated from the semiconductor body 100 by a gate insulating layer 50 and extend vertically along the semiconductor body from the n+ source zone 30 along the p body zone 20 to the n- drift zone 14, in order to form an electrically conductive channel in the body zone 20 along the side wall of the trench between the n+ source zone 30 and the n- drift zone 14 when a suitable drive potential is applied.

[0010] The semiconductor device comprises a multitude of identical transistor structures, so-called cells, each with n+ source zones 30, p body zones 20, and gate electrodes 40, where all cells in the example share an n-drift zone 14 and an n+ drain zone 12. The n+ source zones 30 of all cells are electrically connected to each other to form a common source zone, and the gate electrodes 40 of all cells are electrically connected to each other to form a common gate electrode.

[0011] The in Fig. The semiconductor device shown in Figure 3 comprises a shielding structure with an electrode 80, which is formed in the respective trench 60 and is insulated from the respective gate electrode 40 by means of a further insulating layer 70. This electrode 80 extends vertically over the entire length of the trench and contacts the semiconductor body 100 at the bottom of the trench 60 in the area of ​​the drift zone 14. In this contact area between the electrode 80 and the drift zone 14, a p-doped zone 90 is provided, which is contacted by the electrode 80 and completely covers the electrode in this area. The p-doped zone 90 and the drift zone 14, or the drain zone 12, form a diode, the circuit symbol of which is shown in Fig. Figure 3 shows the diode, which, in the depicted n-type MOSFET, is forward-biased in the source-drain direction and reverse-biased in the drain-source direction. The breakdown voltage of this diode in the drain-source direction can be adjusted by the doping of the p-doped zone 90. A JFET is thus formed at the p-doped zones, which serves to limit the current through the channel region in the event of a short circuit.

[0012] The electrode 80, located in the trench 60, is short-circuited with the n+ source zone 30. For this purpose, the electrode 80 connects directly to the n+ source zone 30 at the side walls of the trench 60 in the upper region. The electrode 80, which preferably consists of a metal or polysilicon, in particular n-doped or p-doped polysilicon, thus simultaneously serves as a connection contact for the n+ source zone 30. This allows the n+ source zone 30 to be contacted directly via this electrode 80 above the trench 60, thereby eliminating the need for contact connections above the semiconductor regions, the so-called mesa regions, located between the trenches.

[0013] The semiconductor device also includes heavily p-doped p+ body termination regions 22, which, as can be seen from the perspective view in Fig. As can be clearly seen, the electrode 80 extends from the p Body zone 20 between sections of the n+ Source zone 30 to the front of the semiconductor body 100 and contacts the electrode 80 in the upper part of the trench 60, so that the electrode 80 short-circuits the p Body zone 20 and the n+ Source zone 30 via the p+ Body connection areas 22 in order to avoid parasitic bipolar effects in a known manner.

[0014] Separate contacts in the semiconductor area formed between the grooves, the so-called mesa area, for short-circuiting the n+ source zone 30 and the p body zone 20 can be dispensed with in the semiconductor device.

[0015] To connect the p body zone 20 to the electrode 80 and achieve the short circuit, the narrow p+ body connection areas 22 are sufficient, so that the space required for this in the mesa region is small. The body diode between source 30 and drain 14, created by short-circuiting the n+ source zone 30 and the p body zone 20, is polarized according to the diode of the shielding structure.

[0016] The threshold voltage of the shielding structure is set to be lower than that of the body diode. When a positive voltage is applied in the source-drain direction, most of the current flows through the forward-biased diode of the shielding structure. This allows the cross-section of the p+ body connection areas 22, which short-circuit the p body zone 20 and the n+ source zone 30, to be small and therefore space-saving. The dimensions of this silicon area between the grooves 60 can thus be reduced compared to conventional semiconductor devices, which contributes to a reduction in the specific on-resistance of the semiconductor device.

[0017] The well-known semiconductor device functions like a conventional MOSFET when a positive drain-source voltage is applied and when a gate potential positive relative to the source potential is applied; its circuit symbol is shown in Fig. Figure 3 shows this. If the drain-source voltage of the MOSFET exceeds the threshold voltage of the diode formed by the p-doped zone 90 and drift zone 14 when the MOSFET is reverse-biased, a reverse current flows from a drain terminal connected to drain zone 12, through drift zone 14, the p-doped zone 90, and electrode 80 to a source terminal connected to electrode 80. When a reverse voltage is applied (i.e., a positive voltage in the source-drain direction), this breakdown structure functions like a body diode and carries most of the resulting current, allowing the terminal for the p-body zone 20 to be small and compact.

[0018] A short circuit can occur in the TMOSFET after Fig. 3. This can occur, for example, when switching on without an applied gate voltage. In this case, a high drain voltage is present at the semiconductor device, and without suitable countermeasures, a very high short-circuit current can flow, which can lead to the destruction of the device.

[0019] A limitation of the short-circuit current can be achieved by means of the JFET formed by the p-doped zones 90, whereby the space charge regions emanating from the p-doped zones 90 approach each other in such a way that a pinch-off of the short-circuit current occurs. Thus, in the event of a short circuit, the p-doped zones 90 act as p-shielding regions.

[0020] A general optimization problem with this TMOSFET is that in the design of every power MOSFET, a compromise must be found between low on-resistance (i.e., high current at low drain voltages) and low short-circuit current (i.e., low current at high drain voltages). Disclosure of the invention

[0021] The invention provides a vertical field-effect transistor structure according to claim 1 and a method for manufacturing a vertical field-effect transistor structure according to claim 7.

[0022] Preferred further training courses are the subject of the respective sub-claims. Advantages of the invention

[0023] The underlying idea of ​​the present invention is to implant p-shielding implantations in a vertical field-effect transistor structure, for example, only in every second trench, and still achieve a good compromise between low short-circuit current and low on-resistance.

[0024] A p-body connection can be made deeper than the p-body region, extending into the n-drift zone. This creates a PN junction below the channel, which reduces resistance at high drain voltages and thus helps to lower the short-circuit current. At high drain voltages, a depletion zone forms in the n-drift zone, increasing the component's resistance. In the event of a short circuit, this increased resistance helps to limit the short-circuit current.

[0025] Since the short-circuit current is additionally limited by this PN junction, in addition to the JFET formed below the fins between two p-shield implantations, it is sufficient according to the invention to implant it only in, for example, every second trench, so that a p-shield region is created only under every second trench. The gate electrode in the trenches without a p-shield region under the trench floor is not designed as a two-part device, since there is no p-shield region under the trench that would need to be contacted. The gate electrode in the trenches with a p-shield region under the trench floor can either be designed as a two-part device (especially if the pBody connection does not extend to the p-shield regions as in [reference]). Fig. 1c, to contact these) or as an undivided electrode (especially if the areas are already contacted by a deep pBody connection as in Fig. 2b).

[0026] The trenches are preferably widened by means of cyclic oxidation and oxide etching, so that the mesas located between the trenches are narrowed into fins.

[0027] According to a preferred embodiment, the reverse current path runs in the trenches, with electrodes arranged in each of the trenches which are electrically connected to the second connection zone and which are electrically insulated from the control electrode, and a first electrode of the electrodes at the bottom of the first trench of the trenches contacts the doped zone of the second conductor type.

[0028] According to a further preferred embodiment, the body termination areas of the second conductor type electrically contact the doped zones of the second conductor type, with the reverse current path running through the body termination areas and the doped zones of the second conductor type. This has the advantage that complex processing of the termination in the grooves for electrode fabrication can be avoided.

[0029] According to a further preferred embodiment, the first connection zone has a lower doped drift area and a higher doped drain area of ​​the first conductor type, the doped zones of the second conductor type are arranged in the drift area, and the body connection areas of the second conductor type extend into the drift area.

[0030] According to another preferred design, a spreading zone of the first conductor type is provided between the first connection area and the duct zone. This contributes to better power distribution.

[0031] According to a further preferred embodiment, the semiconductor body consists of silicon carbide or gallium nitride. Brief description of the drawings

[0032] Further features and advantages of the present invention are explained below with reference to embodiments and the figures.

[0033] They show: Fig. 1a) - h) Schematic cross-sectional views to illustrate a method for manufacturing a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure according to a first embodiment of the present invention; Fig. 2a), b) schematic cross-sectional views to illustrate a method for fabricating a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure according to a second embodiment of the present invention; and Fig. 3 a partial perspective view of a vertical field-effect transistor structure according to the prior art of DE 102 24 201 B4 as the starting point of the present invention. Embodiments of the invention

[0034] In the figures, identical reference symbols denote identical or functionally equivalent elements.

[0035] Fig. Figures 1a) - h) show schematic cross-sectional views to illustrate a method for manufacturing a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure according to an embodiment of the present invention.

[0036] Fig. Figure 1a) shows a semiconductor body 100 having a heavily n-doped zone 12, the later n+ drain zone, on the back side; a less heavily n-doped n- drift zone 14 adjacent to the n+ drain zone 12; a p-doped zone 20, the later body zone, adjacent to the n- drift zone 14; and a heavily n-doped zone, the later n+ source zone 30, adjacent to the body zone 20, on the front side 101. Optionally, an n-spreading zone 14a can be provided between the n- drift zone 14 and the body zone 20, which contributes to better current distribution during operation. The spreading zone 14a can optionally be located deeper within or extend further into the n- drift zone 14. Especially up to between the p-shielding areas 90.

[0037] The process state according to Fig. 1a) is achieved by providing the semiconductor body 100 in the form of a semiconductor wafer and subsequent epitaxy and implantation steps known per se. Using a hard mask M, the trenches 60 are etched into the front surface 101 by a trench etching process, and then a scattering oxide 120 is deposited on the walls of the trenches 60. Optionally (not shown), an n-implantation step can be performed to generate an n-spreading zone in the n-drift zone 14.

[0038] According to Fig. 1b) Subsequently, p-implantation I is performed to create a p-doped zone 90 (p-shielding zone) in the n-drift zone 14 below trench 60. No p-implantation takes place in the other, adjacent trench. P-implantation can occur at periodic intervals. For example, a p-shielding zone can be implanted below every second, third, or fourth trench, while no p-implantation occurs in the intervening trenches. Other patterns of p-shielding zones are also possible, e.g., two consecutive trenches with an implanted p-shielding zone followed by a trench in which no p-implantation occurs. P-implantation can also be performed only partially in a trench, partially preserving the n-drift zone 14 in that trench.

[0039] In contrast to the known structure according to Fig. 3. During p-implantation I, the p body zones 20 can also be contacted in the third dimension via p+ doped areas 22' through corresponding openings in the hard mask M, which alternate along the n+p fin FI with the n+ source zones 30.

[0040] Furthermore, the p+-doped areas 22' can be implanted significantly deeper than the p+-doped areas 22 after Fig. 3. In particular, in this embodiment the p+ doped regions 22' can extend into the n-drift zone 14, as shown in Fig. 1b) indicated by a dashed line and in Fig. 1c) illustrated in a perspective section view.

[0041] Through an anneal step, the p-doped zones 90 and / or the p+ doped areas 22' can be diffused out and activated.

[0042] Continuing with reference to Fig. 1d) The hard mask M and the scattering oxide 120 are removed.

[0043] Then, according to Fig. 1e) at least the trenches 60 widened in which an implantation step I according to Fig. 1b) has been carried out, whereby the widened trenches 60' are laterally bounded by narrowed n+ / p mesa areas, which are also called n+ / p fins FI. This is achieved by means of cyclic oxidation and oxide etching of the n+ / p mesa areas. This step removes unwanted p implantation areas from the lateral walls of the n+ / p mesa areas, which were removed by implantation step I according to Fig. 1b) may arise.

[0044] Fig. Figure 1f) shows the structure after deposition of the gate insulation layer 50 and a polysilicon layer 40', from which according to Fig. 1g) the gate electrodes 40 are made on the side walls of the widened trenches 60'.

[0045] These gate electrodes 40 can be manufactured, for example, using a so-called polyspacer process. For this purpose, the polysilicon layer 40 is etched back, for example, using an anisotropic etching process, until the polysilicon layer 40 is removed from the bottom of the trenches 60' and from the front face 101 of the semiconductor body 100, as well as partially from the side walls in the upper region of the widened trenches 60'. Likewise, the gate insulating layer 50 is removed from the front face 101.

[0046] Finally, an insulating layer 70, e.g., an oxide layer, is produced on the exposed areas of the gate electrodes 60. For this purpose, either the insulating layer 70 is deposited onto the gate electrodes 40 or the gate electrodes 40 are subjected to an oxidation process. Subsequently, the insulating layer 70 is removed from the front face 101 of the semiconductor body 100 and from the bottom area of ​​the widened grooves 60'.

[0047] The widened trenches 60' are then filled with an electrode material, for example a metal or polysilicon, to produce the electrodes 80, as in Fig. 1h) shown, in order to arrive at the vertical field-effect transistor structure according to the embodiment of the present invention.

[0048] If the electrodes consist of a metal or n-doped silicon, it is advantageous to apply a silicide to the exposed front surface 101 of the semiconductor body 100, at least in the region of the p-doped zone, before fabricating the electrodes 80. This ensures good ohmic contact between the electrode 80 and the p-doped zone 90, thus preventing the formation of a pn junction or a Schottky contact at this interface. The contacting of the gate electrodes 40 can be carried out as in known trench transistors and is not shown here.

[0049] The process sequence described above focuses exclusively on the processes within the cell array. Outside the cell array, other processes such as edge sealing and contact pad exits, etc., must be considered. Furthermore, each step may contain several sub-steps that are not explicitly listed.

[0050] Fig. Figures 2a) and 2b) are schematic cross-sectional representations to illustrate a method for manufacturing a vertical field-effect transistor structure and a corresponding vertical field-effect transistor structure according to a second embodiment of the present invention.

[0051] As already mentioned in relation to Fig. As described in 1b), a p-implantation I was performed to form a p-doped zone 90a (p-shielding zones) in the n-drift zone 14 below trench 60. The p-implantation only took place below one trench; no p-implantation took place in the other, adjacent trench. The p-implantation I can be described as follows: Fig. 1b) as described.

[0052] Fig. 2a) shows the Fig. 1f) analog process state of the completed vertical field-effect transistor structure according to the second embodiment.

[0053] Unlike Fig. 1f) are according to Fig. 2a) The p+ doped regions 22" are implanted even deeper into the n- drift zone 14. This results in the p+ doped regions 22" and the p-doped regions 90a touching and thus being electrically connected. In this way, an electrical connection of the p-doped regions 90a (p-shielding regions) via the electrodes 80 becomes unnecessary. This is advantageous because the complex processing of this connection in the trenches 60' for the production of the electrodes 80 can now be dispensed with.

[0054] Thus, the trenches are 60' according to Fig. 2a) is simply filled with an insulating layer I to obtain a planar front surface 101. Additional layers can also be applied for filling and planarizing. In particular, in the case of areas 22" implanted deep into the n-drift clays 14, which touch the p-doped zones 90a, the splitting of the electrodes 40 can be omitted. In this case (not shown), the trench is completely filled with electrode material and insulated at the surface with an insulating layer I.

[0055] Fig. 2b) shows the Fig. 1c) Analogous process state to illustrate that the p+ doped areas 22" and the p-doped zones 90a touch, in a perspective section view

[0056] Although the present invention has been described with reference to preferred embodiments, it is not limited thereto. In particular, the materials and topologies mentioned are only examples and are not limited to the examples described. Likewise, the geometries shown are only examples and can be varied as required.

[0057] Although in the embodiments described above the p+ doped areas and the p-doped zones were formed in a common implantation step, it is also possible to use two separate implantation steps for this purpose. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 102 24 201 B4 [0005, 0033]

Claims

[1] Vertical field effect transistor structure with: a semiconductor body (100) having a first connection zone (12, 14) and a second connection zone (30) of a first conduction type (n); a channel zone (20) of the first conductivity type (n) or of a second conductivity type (p) complementary to the first conductivity type, arranged between the first and second connection zones (12, 14; 30); a plurality of trenches (60') extending into the semiconductor body (100), which trenches extend from the second connection zone (30) through the channel zone (20) into the first connection zone (12, 14) and form fins (FI) of the channel zone (20) and the second connection zone (30); a control electrode (40) arranged in the trenches (60'), which is arranged adjacent to the channel zone (20) and insulated from the semiconductor body (100); a reverse current path connected between the first and second connection zones (12, 14; 30) and parallel to the channel zone (20), which has at least one pn junction and is designed to conduct when a threshold voltage applied between the first and second connection zones (12, 14; 30) is reached; wherein the semiconductor body (100) has a doped zone (90; 90a) of the second conductivity type (p) in the first connection zone (12, 14) below a first trench of the trenches (60'), while the first connection zone (12, 14) below a second trench of the trenches (60') has no doped zone (90; 90a) of the second conductivity type (p); wherein the fins (FI) have body connection regions (22'; 22") of the second conduction type (p) which electrically contact the channel zone (20) and the second connection zone (30); and wherein the body connection regions (22'; 22") of the second conduction type (p) extend into the drift zone (14). [2] Vertical field effect transistor structure according to claim 1, wherein the reverse current path runs in the trenches (60'), wherein respective electrodes (80) are arranged in the trenches (60'), which are electrically conductively connected to the second connection zone (30) and which are electrically insulated from the control electrode (40), and a first electrode of the electrodes (80) at the bottom of the first trench of the trenches (60') contacts the doped zone (90; 90a) of the second conduction type (p). [3] Vertical field effect transistor structure according to claim 1, wherein the body connection regions (22") of the second conductivity type (p) electrically contact the doped zones (90a) of the second conductivity type (p), and wherein the breakdown current path runs via the body connection regions (22") of the second conductivity type (p) and the doped zones (90a) of the second conductivity type (p). [4] Vertical field effect transistor structure according to claim 1, 2 or 3, wherein the first connection zone (12, 14) has a lower doped drift region (14) and a higher doped drain region (12) of the first conductivity type (n), the doped zones (90; 90a) of the second conductivity type (p) are arranged in the drift region (14), and wherein the body connection regions (22'; 22") of the second conductivity type (p) extend into the drift region (14). [5] Vertical field effect transistor structure according to one of claims 1 to 4, wherein a spreading zone (14a) of the first conductivity type (n) is provided between the first connection region (12, 14) and the channel zone (20). [6] Vertical field effect transistor structure according to one of claims 1 to 5, wherein the semiconductor body (100) consists of silicon carbide (SiC) or gallium nitride (GaN). [7] Method for producing a vertical field effect transistor structure comprising the steps: Providing a semiconductor body (100) with a first connection zone (12, 14) and a second connection zone (30) of a first conductivity type (n) and a channel zone (20) of the first conductivity type (n) or of a second conductivity type (p) complementary to the first conductivity type arranged between the first and second connection zones (12, 14; 30); Forming a plurality of trenches (60') extending into the semiconductor body (100), which trenches extend from the second connection zone (30) through the channel zone (20) into the first connection zone (12, 14) and form fins (FI) of the channel zone (20) and the second connection zone (30); Forming a control electrode (40) arranged in the trenches (60'), which is arranged adjacent to the channel zone (20) and insulated from the semiconductor body (100); Forming a reverse current path connected between the first and second connection zones (12, 14; 30) and parallel to the channel zone (20), which reverse current path has at least one pn junction and is designed to conduct when a threshold voltage applied between the first and second connection zones (12, 14; 30) is reached; Forming a doped zone (90; 90a) of the second conductivity type (p) in the first connection zone (12, 14) below a first trench of the trenches (60'), while the first connection zone (12, 14) below a second trench of the trenches (60') has no doped zone (90; 90a) of the second conductivity type (p); Forming body connection regions (22'; 22") of the second conduction type (p) in the fins (FI), which electrically contact the channel zone (20) and the second connection zone (30); and wherein the body connection regions (22'; 22") of the second conduction type (p) are formed such that they extend into the drift zone (14). [8] Method according to claim 7, wherein the doped zone (90; 90a) of the second conductivity type (p) and the body connection regions (22'; 22") of the second conductivity type (p) are formed in a common implantation step (I). [9] Method according to claim 7 or 8, wherein the reverse current path runs in the trenches (60'), wherein respective electrodes (80) are arranged in the trenches (60'), which are electrically conductively connected to the second connection zone (30) and which are electrically insulated from the control electrode (40), and a first electrode of the electrodes (80) at the bottom of the first trench of the trenches (60') contacts the doped zone (90; 90a) of the second conductivity type (p). [10] The method according to claim 7 or 8, wherein the body connection regions (22") of the second conductivity type (p) are formed such that they electrically contact the doped zone (90a) of the second conductivity type (p), and wherein the breakdown current path runs via the body connection regions (22") of the second conductivity type (p) and the doped zone (90a) of the second conductivity type (p). [11] Method according to one of claims 7 to 10, wherein the first connection zone (12, 14) has a lower-doped drift region (14) and a higher-doped drain region (12) of the first conductivity type (n), the doped zone (90; 90a) of the second conductivity type (p) is arranged in the drift region (14), and wherein the body connection regions (22'; 22") of the second conductivity type (p) extend into the drift region (14). [12] Method according to one of claims 7 to 11, wherein a spreading zone (14a) of the first conduction type (n) is provided between the first connection region (12, 14) and the channel zone (20).

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