CORRECTION CIRCUIT

Abstract

A correction circuit for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on the result of the comparison.

Description

[0001] The present disclosure relates to a correction circuit for correcting one or more errors in a digitized current signal. In particular, the present disclosure relates to a correction circuit that can be applied to a switching converter. BACKGROUND

[0002] Fig. Figure 1(a) is a schematic diagram of a digital buck converter 100 having a power stage 101, analog-to-digital converters (ADCs) 102, 104, 106, and a controller 108. The power stage 101 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0003] While the power stage 101 and the passive components (inductor 114 and capacitor 116) remain the same as in an analog buck converter, the ADC 102 converts the output voltage VOUT to a digital number. Optionally, the inductor current IL of the inductor 114 and the input voltage VIN can also be converted from analog to digital by the digital control method.

[0004] We distinguish: • For example, the switching frequency (FSW) of the buck converter 100 is 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the power stage frequency. • The processing frequency of the digital controller 108 (FS), for example, approximately 100 MHz. FS is equal to 1 / TS, where TS is the processing time of the controller 108. FS can optionally also be the sampling frequency of the ADC 102.

[0005] Digital systems, such as digital buck converter 100, may use a digital signal representing current flow through an energy storage element during operation. For example, a digitized current signal may be required by a controller to control the switching operation of the digital switching converter.

[0006] In the present example, the digitized current signal is a digitized inductor current DIL, as provided by the ADC 104, which converts an analog current signal indicative of the inductor current IL into a digital format. It is apparent that components and methods other than the ADC 104 may be used to generate the digitized inductor current DIL. The digitized inductor current DIL may be generated using sensor-based or sensorless techniques. The digitized inductor current DIL is provided to the controller 108, which uses the information about the inductor current IL to control the switching operation of the power switches 110, 112. The dependence of the control scheme on the inductor current means that such a system is referred to as a current-mode converter, which uses current-mode control.

[0007] For effective operation of the buck converter or any other digital system that uses a digitized current signal during operation, it is desirable that the digitized current signal DIL accurately represent the analog current signal IL. With respect to the buck converter 100, it is desirable that the digitized inductor current DIL accurately represent the inductor current IL. It should be noted that the analog current signal and the inductor current may both be denoted by the variable "IL" to indicate that the analog current signal represents the current flow through the inductor. It is obvious that the analog current signal IL may not itself be a current signal, but may, for example, be a voltage signal representing a current signal. SUMMARY

[0008] It is desirable to provide a system to improve the accuracy of a digitized current signal compared to existing methods.

[0009] According to a first aspect of the disclosure, a correction circuit is provided for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on the result of the comparison.

[0010] Optionally, the digitized current signal is provided by a current synthesizer.

[0011] Optionally, the correction circuit is configured to generate a correction signal dependent on the result of the comparison and provide the correction signal to the current synthesizer, wherein the correction signal is suitable for correcting the one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the result of the comparison.

[0012] Optionally, the correction circuit is configured to correct an offset error between the digitized current signal and the analog current signal.

[0013] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the offset error and to correct the digitized current signal using the determined offset error.

[0014] Optionally, the correction circuit is configured to determine the offset error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, calculating a first time duration between the first time step and the second time step, determining a first slope of at least one of the digitized current signal and the analog current signal, multiplying the first duration by the first slope, thereby determining the offset error.

[0015] Optionally, the first digital threshold is approximately equal to a digitized first analog threshold.

[0016] Optionally, the correction circuit comprises a comparator configured to provide an output indicating that the analog current signal crosses the first analog threshold, the output being used to determine the second time step.

[0017] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0018] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the relative slope error and to correct the digitized current signal using the determined relative slope error.

[0019] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, and detecting a second time step when the analog current signal crosses a first analog threshold, detecting a third time step when the digitized current signal crosses a second digital threshold, detecting a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter,and then subtracting one from the first delay parameter, thereby determining the relative slope error.

[0020] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0021] Optionally, the correction circuit is configured to correct the relative slope error before correcting the offset error.

[0022] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the relative slope error and the offset error, and to correct the digitized current signal using the determined relative slope error and the offset error.

[0023] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, detecting a third time step when the digitized current signal crosses a second digital threshold, detecting a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter,then subtracting one from the first delay parameter to thereby determine the relative slope error.

[0024] Optionally, the correction circuit is configured to determine the offset error by calculating a first duration between the first time step and the second time step, determining a first slope of the analog current signal by calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold, and dividing the analog threshold difference by the first analog slope delay, and multiplying the first slope of the analog current signal by the first duration, thereby determining the offset error.

[0025] Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal during operation of a switching converter including the energy storage element.

[0026] Optionally, the switching converter is one of a buck or step-down converter, a boost or step-up converter, and a buck-boost or step-down-step-up converter.

[0027] Optionally, the energy storage element includes an inductor.

[0028] Optionally, the correction circuit is configured to correct the one or more errors in the digitized current signal two or more times during operation of the switching converter, or in response to an external signal, or in response to the one or more errors exceeding a threshold, or in response to a mode change of the switching converter, or in response to a transition.

[0029] Optionally, the correction circuit is configured to correct the one or more errors in the digitized current signal periodically or non-periodically during operation of the switching converter.

[0030] According to a second aspect of the disclosure, a method is provided for correcting one or more errors in a digitized current signal using a correction circuit, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, the method comprising comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on the result of the comparison.

[0031] It will be appreciated that the method of the second aspect may include features set out in the first aspect and may incorporate other features described therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The disclosure will now be described in more detail by way of example only and with reference to the accompanying drawings, in which: Fig. Figure 1 is a schematic diagram of a digital down converter; Fig. Figure 2 is a graph of the inductor current varying with time during operation of the buck converter of Fig. 1; Fig. Figure 3 is a timing diagram showing an example of how parameters related to the operation of the buck converter vary with time during operation; Fig. 4 timing diagrams showing examples of how parameters related to the operation of the buck converter vary with time during operation and for different inductor current values; Fig. 5 is a timing diagram showing representative waveforms of the digital inductor current and the inductor current IL as a result of a load transient during operation of the buck converter; Fig. 6(a) is a schematic diagram of a correction circuit according to a first embodiment of the present disclosure, Fig. 6(b) is a schematic diagram of the correction circuit and an energy storage element according to a second embodiment of the present disclosure; Fig. 7 is a timing diagram showing the digitized current signal and the analog current signal during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. Device shown in Figure 6(a); Fig. 8 is a timing diagram showing the digitized current signal and the analog current signal during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. Device shown in Figure 6(a); Fig. 9(a) is a timing diagram of the digitized inductor current during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a) shown device, Fig. 9(b) is a timing diagram of the digitized inductor current during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. Device shown in Figure 6(a); Fig. 10 is a timing diagram showing the digitized current signal and the analog current signal during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. Device shown in Figure 6(a); Fig. 11 is a schematic diagram of a specific embodiment of the correction circuit and the switching converter according to a third embodiment of the present disclosure; Fig. 12 is a timing diagram showing the digitized current signal and the analog current signal during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 11 shown device; Fig. 13 is a timing diagram showing simulation results of a practical implementation of a known system using a low-bandwidth correction mechanism; Fig. 14(a) is a timing diagram showing simulation results of a practical implementation of the Fig. 11 system shows, Fig. 14(b) the timing diagram of Fig. 14(a) for a shorter period; and Fig. 15 is a schematic representation of a comparator unit suitable for one or both of the two comparator units of Fig. 11 can be used. DETAILED DESCRIPTION

[0033] Fig. Figure 2 is a diagram of the inductor current IL flowing during operation of the buck converter 100 from Fig. 1 varies with time. During operation, the inductor 114 switches between coupling to the input voltage VIN via switch 110 (the magnetization phase, designated by numeral 202) and coupling to ground PGND via switch 112 (the demagnetization phase, designated by numeral 204).

[0034] The diagram shows a first curve 206, which represents an idealized inductor current. The inductor current IL can have an idealized shape consisting of straight lines, as used in US9419627B2 and US9667260B2. The diagram also shows a second curve 208, which represents a more realistic current profile, in which the slope or edge of each phase has a nonlinear shape (exponential decay for the falling slope or edge).

[0035] It should be noted that the timing diagrams are continuous time and continuous data to facilitate clarity of explanation.

[0036] For some switching converters, a linear approximation of the inductor current IL may be sufficient for an effective control scheme. However, a more accurate, nonlinear, digitized waveform of the inductor current DIL is desirable, as it can ensure more precise current control. Furthermore, a digitized inductor current DIL with improved accuracy can be used for applications beyond pure regulation, such as overcurrent protection.

[0037] There are several suitable methods for generating the digitized inductor current DIL, as known to those skilled in the art. For example, the digitized inductor current DIL can be generated using the ADC 104 as described with respect to Fig. 1 or can be generated using a current synthesizer. The following description refers to the generation of the digitized inductor current DIL using a current synthesizer.

[0038] In the discrete time domain (clocked at TS, which is the processing time of the control device 108), the digitized inductor current DIL during the magnetization phase can be represented as follows: DIL[n]=DIL[n−1]−TSL×RMAG⋅DIL[n−1]+TSL×(DIN−DOUT)

[0039] The digitized inductor current DIL during the demagnetization phase can be represented as follows: DIL[n]=DIL[n−1]−TSL×RDEMAG⋅DIL[n−1]−TSL×(DOUT)

[0040] The variable terms R MAG and R DEMAGare thus the nonlinear corrections of ideal slopes for the magnetization phase and the demagnetization phase, respectively. L is the inductance of inductor 114, DIN is a digital input voltage signal, DOUT is a digital output voltage signal, and n is an integer. RMAG=DCR+RHS RDEMAG=DCR+RLS where RHS is the on-resistance of transistor 110, RLS is the on-resistance of transistor 112, and DCR is the series resistance of inductor 114.

[0041] It is obvious that the digitized inductor current DIL can have the profile shown by curve 206 by using a straight-line approximation by setting R MAG = R DEMAG = 0 for equations (1) and (2).

[0042] A current synthesizer can be used to generate the digitized inductor current DIL using equations (1) to (4).

[0043] For example, and referring to equations (1)-(4), it is obvious that achieving an accurate digitized inductor current DIL depends on accurate values ​​for the parameters used in the equations (e.g., L, RHS, RLS, DCR, DIN, DOUT). Other sources of error may include, but are not limited to: • Driver speed • Dead times between LS and HV switch line • Temperature fluctuations of resistors • Aging of the inductor

[0044] Temperature-related errors tend to vary slowly. Errors in the digitized inductor current DIL with respect to a driver speed vary with a time constant of L / R, where R is as follows: R=D.(RHS+DCR)+(1−D).(RLS+DCR) where D is the duty cycle of buck converter 100. Deadband errors can occur within a single clock cycle. Accumulating these errors can lead to large discrepancies between the digitized inductor current DIL and IL (up to 1.3 A is observed in simulations).

[0045] Fig. Figure 3 is a timing diagram showing an example of how parameters related to the operation of buck converter 100 vary over time during operation. A curve 300 shows the inductor current IL as it varies over time; a curve 302 shows the pulse width modulation (PWM) signal varying over time; and a curve 304 shows a voltage at the switching node SW. The PWM signal is used to control the switching operation of buck converter 100, and the use of PWM in this context is known to those skilled in the art.

[0046] The time diagram in Fig. Figure 3 shows a simplified and exaggerated view of the driver delay (Tdly1, Tdly2) and dead zones (Tdz1, Tdz2) for a given inductor current IL.

[0047] In this case, there is a delay between the rising edge of the PWM signal and the response of the power switches to this change (Tdly1). A similar (but not the same) delay occurs at the falling edge of the PWM signal (Tdly2).

[0048] From an analog perspective, we consider MAG, which denotes the magnetization phase, as the period during which the inductor current IL increases. The inductor current IL is close to zero.

[0049] From equations (1) and (2), it can be seen that the expressions during the magnetization phase differ from those during the demagnetization phase, so it is desirable to accurately know the time of the transition between the phases. Using the PWM signal to identify the time of the transition will obviously lead to errors due to Tdly1 and Tdly2.

[0050] Furthermore, the different slope of the inductor current IL during the dead zones Tdz1 and Tdz2 compared to the slope during the remaining magnetization phase (where SW=VIN) is not taken into account in equations (1) and (2). The above errors are strongly dependent on IL, VIN, VOUT, and temperature.

[0051] Fig. 4 shows timing diagrams showing examples of how parameters related to the operation of the buck converter 100 vary with time during operation and for different values ​​of the inductor current IL.

[0052] Fig. Figure 4 shows how the effective MAG duration varies with the inductor current IL (for a fixed required PWM duration). More specifically, the effective MAG duration varies depending on the valley current (IL_valley) and the peak current (IL_peak) of the inductor current IL at the end of the MAG and DEMAG stages. This is due to the current conduction through the freewheeling diode, which depends on the polarity of the inductor current IL. The change in the voltage SW at the switching node depends on the polarity of the inductor current IL at the end of DEMAG and MAG.

[0053] It is possible to correct these (and other) errors in a feed-forward manner, which can reduce the magnitude of the (DIL-IL) error. However, small residual errors can also be integrated and ultimately lead to increasing deviations over time.

[0054] Fig. 5 is a timing diagram showing representative waveforms of the digital inductor current DIL (a curve 500) and the inductor current IL (a curve 502) as a result of a load transient during operation of the buck converter 100.

[0055] After the transition, a mismatch exists between the waveforms. In single-phase converters, the errors between DIL and IL may still allow the system to function, but are nevertheless undesirable due to degraded performance at transient loads and unsuitability of the digitized inductor current DIL for use in applications such as overcurrent protection. In multi-phase converters, a mismatch between the phase currents is highly undesirable, as it can degrade transient performance and efficiency. Because the DIL-to-IL errors are independent of each other, the effective mismatch between the inductor current IL of two different converter phases can be doubled with respect to a DIL-to-IL mismatch of a single-phase converter.

[0056] It is desirable that the digitized inductor current DIL has the following properties: • Accurate average value compared to IL • Exact ripple or waviness size compared to IL • Quick correction of introduced errors • No deviation over time with respect to IL • Similar nonlinear form as IL

[0057] Fig. 6(a) is a schematic diagram of a correction circuit 600 for correcting one or more errors in a digitized current signal DIL according to a first embodiment of the present disclosure. The digitized current signal DIL is a digital representation of an analog current signal IL of a current flow through an energy storage element 602.

[0058] It should be noted that the variables "IL" and "DIL" are used for consistency with the previous description, where the energy storage element comprises an inductor that is part of a buck converter. In the present embodiment, the energy storage element 602 is considered general. In specific embodiments, the energy storage element 602 may comprise an inductor or other circuit component, as understood by those skilled in the art.

[0059] During operation, the correction circuit 600 corrects the one or more errors in the digitized current signal DIL by comparing the digitized current signal DIL with the analog current signal IL and then correcting the digitized current signal DIL based on the result of the comparison.

[0060] The digitized current signal DIL may be provided by a current synthesizer 612. The correction circuit 600 may be configured to generate a correction signal 601 dependent on the result of the comparison and provide the correction signal 601 to the current synthesizer 612.

[0061] The correction signal 601 is a signal suitable for correcting the one or more errors in the digitized current signal DIL when received by the current synthesizer 612. Therefore, during operation, the current synthesizer 612 uses the correction signal 601 to correct the digitized current signal DIL based on the result of the comparison.

[0062] The correction signal 601 may include information regarding a mismatch between the two signals IL, DIL, such as when the digitized current signal DIL is not an accurate digital representation of the analog current signal IL. The current synthesizer 612 may then use the information provided by the comparison signal 601 to adjust or otherwise correct the digitized current signal DIL to reduce the mismatch and ensure that it more accurately digitally represents the analog current signal IL.

[0063] If the digitized current signal DIL is already a sufficiently accurate representation of the analog current signal IL, as may be defined by a threshold value, the mismatch indicated by the correction signal 601 may be sufficiently small so that it is not necessary for a correction to be applied by the current synthesizer 612.

[0064] Fig. Figure 6(b) is a schematic diagram of the correction circuit 600 and the energy storage element 602 according to a second embodiment of the present disclosure. In the present embodiment, the energy storage element 602 is a component of a switching converter 604 that includes at least one power switch 606.

[0065] In the present embodiment, the correction circuit 600 corrects the one or more errors in the digitized current signal DIL during operation of the switching converter 604. The switching converter 604 may be a buck converter, a boost converter, or a buck-boost converter.

[0066] The correction circuit 600 may correct the one or more errors in the digitized current signal DIL at one or more events. In a specific embodiment, the correction may be made periodically or non-periodically. In another embodiment, the correction may be performed in response to an external signal; in response to at least one of the errors exceeding a threshold; in response to a transition; or in response to a mode change of the switching converter. In other embodiments, the correction may be applied based on one or more of the above conditions.

[0067] It is obvious that the correction process may be applied more than once during the operation of the overall system including the energy storage element 602. This may be necessary when an event occurs that leads to an increase in the mismatch between the digitized current signal DIL and the analog current signal IL, for example, a transition.

[0068] In a specific embodiment, the correction circuit 600 may be configured to correct an offset error between the digitized current signal DIL and the analog current signal IL.

[0069] Fig. 7 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a). In the present example, there is an offset error (denoted by ΔI) between the digitized current signal DIL (a curve 700) and the analog current signal IL (a curve 702).

[0070] As discussed above, continuous time and value representations are used for the digitized current signal DIL to improve clarity of explanation. However, in reality, the digitized current signal DIL contains values ​​that vary with discrete time steps.

[0071] The following description assumes that the energy storage element 602 is an inductor used as part of a buck converter. However, it will be appreciated that the concept is applicable to other switching converter topologies, including, but not limited to, boost converters, buck-boost converters, and multiple switching converters, as understood by those skilled in the art.

[0072] In relation to Fig. 7, the waveforms IL and DIL are phase-aligned because the digitized inductor current DIL is a digital representation of the analog inductor current IL. Furthermore, the slew rates of the digitized inductor current DIL and the analog inductor current IL are the same during the demagnetization phase (denoted by "DEMAG"), which is also true during the magnetization phase (denoted by "MAG"). The slew rates are denoted by "SR" and have units of amperes per unit time (e.g., A / s, where "A" denotes amperes and "s" denotes seconds). The slew rates can also be referred to as "slopes."

[0073] The offset error ΔI indicates a mismatch between the average levels of the digitized current signal DIL and the analog current signal IL, which can be referred to as their direct current (DC) levels. For an accurate representation of the analog current signal IL by the digitized current signal DIL, the offset error ΔI should be approximately zero.

[0074] With respect to a specific embodiment of the present disclosure, to correct the offset error ΔI, the correction circuit 600 compares the digitized current signal DIL with the analog current signal IL to determine the offset error ΔI. Using this information, the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the offset error ΔI to approximately zero, thereby correcting the digitized current signal DIL.

[0075] In the present example, a digital threshold DISET1 receives its analog representation ISET1 via a DAC 704, which receives the threshold DISET1 to convert the analog threshold ISET1 into Fig. 7. The digital threshold DISET1 is approximately equal to the analog threshold I-SET1, since the two signals represent the same quantity in different ranges. Therefore, the thresholds DISET1, ISET1 in Fig. 7 aligned.

[0076] The digital threshold DISET1 can be any threshold between the peak of the digitized inductor current DIL and the valley of the digitized inductor current DIL, with the analog threshold ISET1 being similarly defined with respect to the analog inductor current IL.

[0077] A point P1 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET1. It is obvious that this is a digital comparison.

[0078] A point P2 is obtained by the analog inductor current IL (a real analog signal) crossing a real threshold ISET1. This analog comparison results in a real event (e.g., a comparator output).

[0079] In a specific embodiment, the correction circuit 600 may include a comparator (not shown) configured to provide an output indicating that the analog current signal IL crosses the threshold I-SET1, the output being used to determine the time step t2.

[0080] Using the two comparison points P1, P2, the offset ΔI between the DIL and IL waveforms can be determined.

[0081] In a specific embodiment, the offset error ΔI is determined by the correction circuit 600 by first detecting a time step t1 at the point P1 when the digitized current signal DIL crosses a digital threshold DISET1; detecting a time step t2 at the point P2 when the analog current signal IL crosses an analog threshold ISET1; and then calculating a duration ΔT between the two time steps. ΔT can be calculated by subtracting the time step t2 from the time step t1.

[0082] Furthermore, the correction circuit 600 is configured to determine a slope SR of one of the signals IL, DIL. In the present embodiment, the slopes are equal, and therefore the slope SR can be determined from each of the signals DIL, IL.

[0083] In operation, the correction circuit 600 then determines the offset error ΔI using the following relationship between the slope SR and the duration ΔT. ΔI=SR.ΔT

[0084] If SR and ΔT can be measured (or are otherwise known), the offset between the waveforms can be corrected. If ΔI = 0, the two waveforms DIL and IL are aligned, meaning the DIL representation of IL is accurate.

[0085] If the waveforms IL, DIL are spaced apart so that the analog inductor current IL does not cross the threshold ISET1, an accurate value for the offset can be determined by first applying a coarse correction in an attempt to bring the two waveforms DIL, IL close to each other to make a measurement.

[0086] In another specific embodiment, the correction circuit 600 may be configured to correct a relative slope error between the digitized current signal DIL and the analog current signal IL.

[0087] Fig. 8 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a). In the present example, there is a relative slope error between the digitized current signal DIL (a curve 800) and the analog current signal IL (a curve 802).

[0088] As in Fig. 7 shows Fig. 8 the digitized current signal DIL with a continuous time representation, and the following example is described with respect to a buck converter.

[0089] In this example, the slopes are unequal. The slope of the digitized inductor current DIL is labeled "SR_DIL," and the slope of the analog inductor current IL is labeled "SR_IL."

[0090] With respect to a specific embodiment of the present disclosure, the relative slope error correction circuit compares the signals IL and DIL to determine the relative slope error SR_ERR. Using this information, the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the relative slope error SR_ERR to approximately zero, thereby correcting the digitized current signal DIL.

[0091] In the present example, the thresholds ISET1 and DISET1 are as in relation to Fig. 7. In the present example, a digital threshold ISET2 receives its analog representations ISET2 via a DAC 804, which receives the threshold DISET2 to convert the analog threshold ISET2 into Fig. 8. The digital threshold DISET2 is approximately equal to the analog threshold ISET2, since the two signals represent the same quantity in different ranges. Therefore, the thresholds DISET2, ISET2 in Fig. 8 aligned.

[0092] A point P3 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET2. It is obvious that this is a digital comparison.

[0093] A point P4 is obtained by the analog inductor current IL (a real analog signal) crossing a real threshold ISET2. This analog comparison results in a real event (such as a comparator output).

[0094] In a specific embodiment, the relative slope error SR_ERR is determined by the correction circuit 600 by detecting the time steps t1 and t2, as described with respect to Fig. 7; detecting a time step t3 at point P3 when the digitized current signal DIL crosses the digital threshold DISET2; detecting a time step t4 at point P4 when the analog current signal IL crosses the analog threshold ISET2; calculating a digital slope delay ΔT_DIL between time steps t1, t3; calculating an analog slope delay ΔT_IL between time steps t2, t4; and dividing the slope delays ΔT_DIL, ΔT_IL to calculate the relative slope error SR_ERR.

[0095] We can define the following equations in terms of thresholds: ΔISET=ISET1−ISET2 ΔDISET=DISET1−DISET2

[0096] As previously described, the three delay measurements ΔT, ΔT_DIL, ΔT_DIL can be derived from the results of the digital comparisons of the digitized inductor current DIL with the digital thresholds DISET1, DISET and the analog comparisons of the analog inductor current IL with the analog thresholds ISET1, ISET2.

[0097] The relative slope error SR_ERR can be calculated as follows: SR_ERR=SR_DIL−SR_ILSR_IL=ΔT_ILΔT_DIL−1 where SR_DIL is the slope of the digitized inductor current DIL and SR_IL is the slope of the analog inductor current IL.

[0098] The value of the relative slew rates of the analog inductor current IL and the digitized inductor current DIL is provided by the relative slope error SR_ERR and can be used to apply a correction to the digitized inductor current DIL signal to align its slope SR_DIL with the slope of the analog inductor current SR_IL.

[0099] Several methods are available to adjust the SR_DIL slope, as will be apparent to those skilled in the art. For example, one option, with reference to equations (1) and (2), is to change the L parameter value used in the expression used to calculate DIL[n]. L denotes the inductance of the inductor of energy storage element 602.

[0100] In another embodiment, correction circuit 600 may be configured to correct the relative slope error and the offset error. For example, correction circuit 600 may be configured to compare the digitized current signal DIL with the analog current signal IL to determine the offset and relative slope errors, and then correct the digitized current signal DIL based on the determined errors.

[0101] In a specific embodiment, expressions (1) and (2) may be modified as follows to allow the corrections for error and slope to be taken into account when generating the digitized inductor current DIL[n]: DIL[n]=DIL[n−1]+TSL×SR_ERR×(DIN−DOUT)−ΔI−TSL×SR_ERR×RMAG.DIL[n−1] DIL[n]=DIL[n−1]+TSL×SR_ERR×(DOUT)−ΔI−TSL×SR_ERR×RDEMAG.DIL[n−1]

[0102] Since the expressions provided by equations (10) and (11) are recursive (depending on the previous value), the offset correction needs to be performed only once after the calculation (to avoid integration of this correction).

[0103] Once the offset error is corrected, all future DIL[n] values ​​will be corrected. The relative slope error term SR_ERR can (and should) be used for each subsequent DIL[n] value calculation.

[0104] The offset error can be calculated as in relation to Fig. 7 or Fig. 8. The relative slope error can be determined as described in relation to Fig. 8 described.

[0105] It is desirable that the slopes of the waveforms DIL and IL be equal during the demagnetization phase (DEMAG) and the magnetization phase (MAG) and before the offset error is corrected. Therefore, in a specific embodiment, the relative slope error can be corrected before the offset error is corrected.

[0106] With reference to the Fig. 8, the offset error can be determined using the following equation: ΔI=SR_IL.ΔT where: SR_lL=ΔlSETΔT_lL

[0107] Equations (12) and (13) can be used to correct the offset error ΔI after the relative slope error has been corrected.

[0108] If there is a relative pitch error, it is preferable to apply the relative pitch error correction before the offset error correction.

[0109] However, embodiments of the present disclosure may apply offset error correction before relative slope error correction. Another embodiment may apply only offset error correction.

[0110] Fig. Figure 9(a) is a timing diagram of the digitized inductor current DIL during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a). In the present example, the offset error was corrected by aligning the digitized inductor current DIL (a curve 900) with the analog inductor current IL (a curve 902). In the present example, the digitized inductor current DIL was aligned with the analog inductor current IL at the threshold values ​​DISET1, ISET1.

[0111] Fig. Figure 9(b) is a timing diagram of the digitized inductor current DIL during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a). In the present example, the offset error was corrected by aligning the digitized inductor current DIL (a curve 904) with the analog inductor current IL (a curve 906). In the present example, the digitized inductor current DIL was aligned with the analog inductor current IL at the threshold values ​​DISET2, ISET2.

[0112] If the slopes of DIL (SR_DIL) and IL (SR_IL) are not identical and the offset is corrected, the two waveforms can be aligned at the I-SET1, DISET1 threshold (as in Fig. 9(a)) or can be aligned to the ISET2, DISET2 threshold (as in Fig. 9(b)). However, the average digitized inductor current (which is <dil>can be called) and the average analog inductor current (which is <il>can be described) are unequal.

[0113] Fig. 10 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 6(a), wherein the energy storage element 602 is an inductor that is part of a buck converter. The present example may use the offset error correction and relative slope error correction method as described with respect to Fig. 8 described.

[0114] In the present example, during operation, the relative slope error and then the offset error are corrected by the correction circuit 600. A curve 1000 of the digitized inductor current DIL and a curve 1002 of the analog inductor current are shown. In the present example, the correction circuit 600 applies a relative slope error correction and an offset error correction at the end of two consecutive demagnetization phases at a time 1006 and a time 1008. After time 1008, the signals DIL, IL are seen to be aligned and therefore the correction circuit 600 has corrected the digitized current signal DIL. It is obvious that in another embodiment, the correction may be applied at the end of the magnetization phase and not at the end of the demagnetization phase.It is obvious that in further embodiments the correction can be applied at any time during the switching cycle.

[0115] In further embodiments, the correction method provided by the correction circuit 600 may be applied based on one or more of the following conditions: • at each switching cycle • every N switching cycles, where N is an integer • non-periodic • if necessary, as determined either from measured errors or from an external source • if calculated errors exceed a predefined threshold • when changing modes (e.g. when changing from single-phase operation to multi-phase operation) • when transitions are detected (for example, load transitions, supply transitions or temperature changes)

[0116] These corrections can thus prevent residual errors from accumulating. Although they may still contain some residual errors themselves, the corrections can be enforced if necessary, thus limiting the (DIL-IL) error.

[0117] Fig. 11 is a schematic diagram of a specific embodiment of the correction circuit 600 and the switching converter 604, wherein the switching converter 604 is a buck converter, and according to a third embodiment of the present disclosure. In the present embodiment, the buck converter 604 includes a capacitor 1100, the power switch 606 is a high-side switch and a low-side switch 1101; the correction circuit 600 includes a logic block 1102 and two comparator units 1104; an analog-to-digital converter (which may function as a current synthesizer 612 as previously described, with DIL generated based on equations (1) and (2)); the comparison circuit 608 includes a timing extraction unit 1106, a timing extraction unit 1108, an offset and relative slope error extraction unit 1110, and optionally a filter unit 1112.The timing extraction unit 1108 includes time-to-digital converters 1108a, 1108b.

[0118] It is understood that the ADC 612 illustrates one method for generating the digitized inductor current DIL, and further embodiments may use alternative methods for generating the digitized inductor current DIL, as understood by those skilled in the art. The digitized inductor current DIL method may, for example, be sensor-based or sensorless.

[0119] Each of the comparator units 1104 comprises a comparator in the present embodiment. It is obvious that alternative implementations are possible in further embodiments, consistent with the understanding of those skilled in the art.

[0120] In the present example, the current flow IL is detected by measuring the voltage drop across the low-side switch LS 1101 and is described in more detail below. In another embodiment, the current flow IL can be detected using the HS switch 606, and the alignment of IL and DIL can then occur during MAG instead of DEMAG. As previously discussed, the analog current signal IL (used for comparison with the digitized current signal DIL) and the current flow through the inductor 602 are both denoted by the variable "IL" to indicate that the analog current signal IL is representative of the current flow through the inductor. Logic block 1102 is used to generate DISET1 and DISET2 so that they are between the peak of DIL and the valley of DIL.

[0121] In the present embodiment, the offset error signal (denoted by I_ERR) and the relative slope error (denoted by SR_ERR) are examples of the correction signal 601, as previously described. Using the information provided by these signals, the current synthesizer 612 corrects the offset error and the relative slope error when generating the digitized inductor current DIL.

[0122] Fig. 12 is a timing diagram of the digitized current signal DIL (a curve 1200) and the analog current signal IL (1202) during operation of an exemplary embodiment of the present disclosure, for example, with respect to the Fig. 11. Also shown is a first comparator output signal COMP1 (a curve 1204), which is an output from one of the comparators of one of the comparator units 1104; a second comparator output signal COMP2 (a curve 1206), which is an output of the comparator of the other comparator unit 1104; and a clock signal CLKS (a curve 1208).

[0123] In previous timing diagrams, the digitized inductor current DIL was represented as continuous time. As discussed, in practice, the digitized inductor current DIL is a discrete-time, discrete-value digital signal. The analog current signal IL represents the real inductor current and is continuous in time and value.

[0124] It is obvious that there are several possible methods to determine the timing of the points, as discussed above. The following discussion refers to one such example method, as described in relation to the Fig. 11 and Fig. 12 described.

[0125] Points C and D in Fig. 12 refer to the real current flow IL(t) through the inductor 602. In the present example, the comparator units 1104 are used to detect the analog inductor current IL and compare the analog inductor current IL with the threshold value ISET1, ISET2. Each of the two comparator units 1104 is configured to compare the analog inductor current IL with one of the threshold values ​​ISET1, ISET2.

[0126] In the present embodiment, the comparators would detect the digitized inductor current IL as a voltage drop across the device resistor 1101 of the low-side switch. The threshold values ​​ISET1, ISET2 are voltage references obtained from the digital threshold values ​​DISET1, DISET2 via a DAC 1114.

[0127] Assuming zero offset and zero delays for the comparators of comparator units 1104, the outputs COMP1 and COMP2 are generated. The rising edge of COMP1 represents point C, and the rising edge of COMP2 represents point D. The delay between these signals can then be measured and converted into a digital number via the timing extraction unit 1108, which includes the time-to-digital converters 1108a, 1108b. It is apparent that alternative methods for extracting the time delay may be used in further embodiments, consistent with the understanding of those skilled in the art.

[0128] Points A and B refer to the digitized inductor current DIL[n], which is a discrete-time, discrete-value signal. A simple way to calculate the T_AB delay is to monitor the digitized inductor current DIL values ​​at each clock cycle and determine whether the DISET1 (or DISET2) level has been exceeded.

[0129] By knowing the values ​​of the digitized inductor current DIL before and after the crossing, an interpolation (e.g., linear interpolation) can be performed to determine the time at which the digitized inductor current DIL has exceeded DISET1 or DISET2. By knowing the integer number of clock cycles between A and B and the fraction of a processing period TS, the time step T_A, and the time step T_B, the total T_AB can be calculated. T_AB can be equal to ΔT_DIL, as with respect to Fig. 8 described.

[0130] Determining the delay T_AC uses two reference points on two different signals DIL, IL, located in different domains (digital and analog). One possible solution is to measure the time T_C instead of measuring T_CD directly. This allows T_AC to be calculated as follows: T_AC=T_A+N.TS−T_C where N is the integer number of clock periods that have elapsed between the end of the T_A measurement and the end of the T_C measurement, and N=2 in Fig. 12.

[0131] It is obvious that the method used to determine T_AC can also be applied to determine T_BC or T_BD.

[0132] It is obvious that the digitized inductor current DIL and the analog inductor current IL, as in Fig. 12, have linear gradients because their values ​​both increase and decrease.

[0133] It is obvious that the method for extracting the time delays T_AB, T_CD, T_AC, T_BD as described with respect to Fig. 12 can also be applied to nonlinear slopes, for example, including exponentially decaying waveform sections for both IL and DIL. However, the accuracy may be compromised compared to the linear examples because the previously described method uses an approximation of the linear slope. It is obvious that for nonlinear slopes, other methods for determining the delays can be performed, consistent with the understanding of those skilled in the art.

[0134] Fig. Figure 13 is a timing diagram showing simulation results of a practical implementation of a known system using a narrow-bandwidth correction mechanism. It shows the output voltage of a buck converter (curve 1300); the analog inductor current IL (curve 1302); the digitized inductor current DIL (curve 1303); and the current error I_ERR, which is equal to DIL-IL after filtering (curve 1304). Curves 1302 and 1303 appear to overlap in the diagram.

[0135] The error I_ERR before the transition, as it occurs at time TA, is small due to a long settling time (more than 500 µs). After the load transition, a large error I_ERR quickly accumulates. The error I_ERR decreases very slowly over time to a minimum value of -740 mA.

[0136] Fig. 14(a) is a timing diagram showing simulation results of a practical implementation of the Fig. 11, and using a cycle-by-cycle correction. The present simulation results show the same load transition as in Fig. 13, and in the present example the system reaches a stable state faster than in the example shown in Fig. 13. Shown are the output voltage of the buck converter (a curve 1400); an analog inductor current IL (a curve 1402); a digitized inductor current DIL (a curve 1403); a current error I_ERR, which after filtering is equal to DIL-IL (a curve 1404); a digitized inductor current slope SR_DIL (a curve 1406); and an analog inductor current slope SR_IL (a curve 1408).

[0137] The I_ERR error starts at a similar value (45 mA) and reaches -290 mA due to the errors caused by load transients. The I_ERR error is then quickly corrected. SR_IL and SR_DIL are also shown before and after the load transient. SR_IL and SR_DIL converge quickly, even though filtering is applied to the slope correction. In another embodiment, the relative slope error can be fully corrected in one cycle.

[0138] Fig. 14(b) is the timing diagram of Fig. 14(a) over a shorter timescale. The offset correction is applied at the end of MAG (t = 251 µs).

[0139] Fig. Figure 15 is a schematic diagram of a comparator unit 1500 that may be used for one or both of the two comparator units 1104 of Fig. 11 can be used. The comparator unit 1500 includes switches 1502, 1504, 1506, 1508, 1510, 1512; capacitors 1514, 1516, 1518; an operational amplifier 1520, and a comparator 1522.

[0140] In the examples above, it was mentioned that a zero-delay, zero-offset comparator is desirable for determining points C and D. For the purposes of the present disclosure, some approximations can be made that allow a zero-delay, zero-offset comparator to be effectively emulated. The present example can achieve zero offset and zero delays when used in the embodiments disclosed herein by clarifying that the nature of the buck converter (or other switching converter) allows some assumptions to be made regarding the inputs of these comparators.

[0141] When determining T_CD, the absolute comparator delay is not important as long as the delays between the two comparators match. However, the absolute comparator delay is important for offset correction (based on point C or D).

[0142] When considering Fig. 15, one of the inputs of comparator 1522 is constant (VN), and the other input has a relatively predictable slope defined by SR_IL. The current sources 1114 are dimensioned so that comparator 1522 switches when IL=ISET1 or IL=ISET2.

[0143] This system 1500 can achieve near-zero offset and, taking into account the IL slope constant, near-zero delay. The system 1500 samples the residual voltage VOFFS at the time the comparator 1522 switches and, based on this, adjusts an additional offset (VOFFS_COMP) at the input of the comparator 1522 such that VP = (VSW_SNS + VOFFS_COMP).

[0144] The stable state is achieved when comparator 1522, COMP, switches exactly when the residual offset, VOFFS, is zero. This results in a comparator with no delay and no offset.

[0145] This works when the slope of the inductor current SR_IL remains constant. If the slope changes (due to VIN / VOUT, load transients, or temperature effects), the system introduces an error until it returns to the new steady state.

[0146] In summary, embodiments of the present disclosure can be used to correct the DIL-IL error with respect to both offset and ripple (via slope adjustments). Specific embodiments described herein perform offset correction in a digitized inductor current DIL in a switch-mode power converter by aligning it with one or more measured points of the real inductor current (or a signal derived from the real inductor current) labeled "IL." Embodiments of the present disclosure perform slope (slew rate) correction of a digitized inductor current DIL in a switch-mode power converter by aligning it with two or more measured points of the real inductor current (or a signal derived from the real inductor current) labeled "IL."Embodiments of the present disclosure correct offset and slope (slew rate) errors of a digitized inductor current DIL in a switch-mode power converter by aligning it with two or more measured points of the real inductor current (or a signal derived from the real inductor current) labeled "IL." Embodiments of the present disclosure use delay measurements (in the analog domain) and direct delay calculations (in the digital domain) in calculating an offset and slope (slew rate) correction.

[0147] Various improvements and modifications may be made to the above without departing from the scope of the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 9419627B2

[0034] US 9667260B2

[0034] < / il> < / dil>

Claims

[1] A correction circuit for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, the correction circuit being configured to correct the one or more errors in the digitized current signal by: Comparing the digitized current signal with the analog current signal; and Correct the digitized current signal based on the comparison result. [2] The correction circuit according to claim 1, wherein the digitized current signal is provided by a current synthesizer. [3] The correction circuit according to claim 2, wherein the correction circuit is configured to: Generating a correction signal that depends on the result of the comparison; and Providing the correction signal to the current synthesizer, wherein the correction signal is suitable for correcting the one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the result of the comparison. [4] The correction circuit according to any preceding claim, configured to: Correcting an offset error between the digitized current signal and the analog current signal; and / or Correcting a relative slope error between the digitized current signal and the analog current signal. [5] The correction circuit according to claim 4, which is configured to: Comparing the digitized current signal with the analog current signal to determine the offset error; and Correcting the digitized current signal using the determined offset error. [6] The correction circuit according to claim 5, which is configured to: Determine the offset error by: Detecting a first time step when the digitized current signal crosses a first digital threshold; detecting a second time step when the analog current signal crosses a first analog threshold; Calculating a first duration between the first time step and the second time step; Determining a first slope of at least one of the digitized current signal and the analog current signal; Multiply the first duration by the first slope to determine the offset error. [7] The correction circuit according to claim 4, which is configured to: Comparing the digitized current signal with the analog current signal to determine the relative slope error; and Correcting the digitized current signal using the determined relative slope error. [8] The correction circuit according to claim 7, which is configured to: Determine the relative slope error by: Detecting a first time step when the digitized current signal crosses a first digital threshold; detecting a second time step when the analog current signal crosses a first analog threshold; Detecting a third time step when the digitized current signal crosses a second digital threshold; Detecting a fourth time step when the analog current signal crosses a second analog threshold; Calculating a first digital slope delay between the first time step and the third time step; Calculating a first analog slope delay between the second time step and the fourth time step; Dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtracting one from the first delay parameter to thereby determine the relative slope error. [9] The correction circuit of claim 4, configured to correct the relative slope error before correcting the offset error. [10] The correction circuit according to claim 9, which is configured to: Comparing the digitized current signal with the analog current signal to determine the relative slope error and the offset error; and Correct the digitized current signal using the relative slope error and offset error as determined. [11] The correction circuit according to claim 10, which is configured to: Determine the relative slope error by: Detecting a first time step when the digitized current signal crosses a first digital threshold; detecting a second time step when the analog current signal crosses a first analog threshold; Detecting a third time step when the digitized current signal crosses a second digital threshold; Detecting a fourth time step when the analog current signal crosses a second analog threshold; Calculating a first digital slope delay between the first time step and the third time step; Calculating a first analog slope delay between the second time step and the fourth time step; Dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtracting one from the first delay parameter to thereby determine the relative slope error. [12] The correction circuit according to claim 11, configured to: Determine the offset error by: Calculating a first duration between the first time step and the second time step; Determining a first slope of the analog current signal by: Calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold; and Dividing the analog threshold difference by the first analog slope delay; and Multiply the first slope of the analog current signal by the first duration to determine the offset error. [13] A method for correcting one or more errors in a digitized current signal using a correction circuit, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, the method comprising: Comparing the digitized current signal with the analog current signal; and correcting the digitized current signal based on the result of the comparison.

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