PACKAGES WITH IMPLANTATION

Abstract

One method involves bonding a device die to a package component. The device die has a semiconductor substrate and a via extending into the semiconductor substrate. The method further includes: depositing a dielectric coating covering the sidewalls of the device die; depositing a dielectric layer on the dielectric coating; and planarizing the dielectric layer and the device die. Remaining portions of the dielectric coating and dielectric layer form a gap-filling region, and the top of the via is exposed. An implantation process is performed to introduce a voltage-modulating dot into the dielectric coating and / or the dielectric layer. A redistribution line is fabricated across and in electrical connection with the via.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 532,452, filed August 14, 2023, and entitled "Semiconductor Device and Method of Manufacturing the Same," which is incorporated by reference into the present application. BACKGROUND

[0002] Integrated circuit packages may include a plurality of package components, such as device dies and package substrates, bonded together to increase functionality and raise the level of integration. Due to differences between the various materials of the plurality of package components, deflection may occur. This deflection can cause non-bonding issues, and some conductive structural elements intended to be bonded together are therefore not bonded, leading to circuit failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1-13 show cross-sectional views of intermediate stages in the fabrication of a multilevel package according to some embodiments. The Fig. 14-19 show sectional views of intermediate stages in the manufacture of a multilevel package according to alternative embodiments. The Fig. 20-23 show the structures and positions of mechanical stress modulation regions in wafers according to some embodiments. The Fig. 24A and Fig. 24B show a vertical mechanical stress dopant distribution profile and a horizontal mechanical stress dopant distribution profile, respectively, according to some embodiments. Fig. 25 shows a process flow for fabricating a package with a mechanical stress modulation dopant according to some embodiments. DETAILED DESCRIPTION

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A method is provided for implanting stress modulation dopants into dielectric layers to create stress modulation regions. The deflection profile of the implanted wafer may be improved, and the deflection may be reduced. Embodiments discussed in this disclosure are intended to provide examples to enable manufacture or use of the subject matter of the present disclosure, and one of ordinary skill in the art should readily recognize modifications that may be made without departing from the intended scope of other embodiments. Throughout illustrations and illustrative embodiments, similar reference numerals are used to refer to similar components.Although method embodiments may be discussed as embodiments performed in a particular order, other method embodiments may be performed in any logical order.

[0007] The Fig. 1 to 13 show sectional views of intermediate stages in the manufacture of a package according to some embodiments of the present disclosure. The corresponding processes are described in the process flow in Fig. 25 is also shown schematically.

[0008] Fig. 1 shows the fabrication of a release film 22 on a carrier 20. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, or the like. The release film 22 may be made of a polymer-based material and / or a heat-removable epoxy-based material (such as an LTHC (Light-To-Heat Conversion) material) that dissolves upon irradiation by, for example, a laser beam, so that the carrier 20 can be debonded from the overlying structures fabricated in later processes. According to some embodiments, the release film 22 is applied to the carrier 20 by coating.

[0009] Fig. Figure 1 shows the creation of a redistribution structure with redistribution lines (RDLs) by an RDL-first process. The respective process is designated as process 202 in the process flow 200, which is shown in Fig. 25. According to alternative embodiments, the redistribution structure may be formed by an RDL-last process. A redistribution structure 24, including a plurality of dielectric layers 26 and a plurality of RDLs 28, is formed over the release film 22.

[0010] According to some embodiments, the dielectric layers 26 may be made of or comprise inorganic dielectric materials, such as silicon-containing dielectric materials such as SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. According to alternative embodiments, the dielectric layers 26 may be made of or comprise organic dielectric materials, which may be polymers. For example, the dielectric layers 26 may be made of or comprise polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.

[0011] In an exemplary embodiment, the formation of a lower layer of RDLs 28 may include forming a metal seed layer (not shown) over the underlying dielectric layer 26, forming a patterned mask (not shown), such as a photoresist, over the metal seed layer, and then performing a metal plating process to deposit a metallic material on the exposed metal seed layer. The patterned mask and the portions of the metal seed layer covered by the patterned mask are then removed, thereby forming the lower RDLs 28 formed in Fig. 1. According to some embodiments, the metal seed layer comprises a titanium layer and a copper layer over the titanium layer. The metal seed layer can be formed, for example, using physical vapor deposition (PVD) or a similar process. The plating can be performed, for example, using an electrochemical plating process.

[0012] Fabrication of the overlying RDLs 28 may include depositing a dielectric layer 26 over the lower RDLs 28, patterning the dielectric layer 26 to create via openings and expose the underlying RDLs 28, depositing an unpatterned metal seed layer extending into the via openings, and fabricating and patterning a plating mask (such as a photoresist) with openings formed in the plating mask and directly over the via openings. A plating process is then performed to plate a metallic material that fills the via openings and has some portions higher than the top of the dielectric layer 26.The plating mask is then removed, followed by an etching process to remove the exposed portions of the metal seed layer previously covered by the plating mask. The remaining portions of the metal seed layer and the plated metallic material are the RDLs 28. The RDLs 28 include RDL lines (also called traces or trace portions) and via portions (also called vias). The trace portions are above the respective dielectric layer 26, and the via portions are within the respective dielectric layer 26.

[0013] A bond layer 32 and bond pads 30 are formed as an upper portion of the redistribution structure 24. The bond layer 32 may be formed from a silicon-containing dielectric material, wherein the silicon-containing dielectric material may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. The bond pads 30 may comprise copper and may be formed using a damascene process. The bond layer 32 and the bond pads 30 are planarized so that their upper surfaces are coplanar, which may be achieved by a chemical mechanical polish (CMP) process performed during the formation of the bond pads 30.

[0014] With reference to Fig. 2, device dies 36 are bonded to a wafer 2. The respective process is described as process 204 in the process flow 200, which is shown in Fig. 25. According to some embodiments, each of the device dies 36 may be a logic die, e.g., a central processing unit (CPU) die, a microcontroller (MCU) die, an input / output (I / O) die, a BaseBand die, or the like. The device dies 36 may also include memory dies.

[0015] The device dies 36 may include semiconductor substrates 38, which may be silicon substrates. TSVs (TSV: Through-Silicon Via) 40, sometimes referred to as "through-substrate vias," "through-semiconductor vias," or through-vias, are fabricated to extend into the semiconductor substrates 38. The TSVs 40 are used to connect the devices and metal lines fabricated on the front side (the bottom side shown) of the semiconductor substrates 38 to the back side. The device dies 36 also include interconnect structures 42 for connecting the active devices and passive devices in the device dies 36. The interconnect structures 42 include metal lines and vias.

[0016] Each of the device die 36 includes bond pads 44 and a bond layer 46 (also referred to as a bond film) on the illustrated bottom surface of the device die 36. The bottom surfaces of the bond pads 44 may be coplanar with the bottom surface of the bond layer 46. According to some embodiments, the bond layer 46 may be formed from a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. The bond pads 44 may comprise copper and may be formed using a damascene process. The bond layer 46 and the bond pads 44 are planarized so that their surfaces are coplanar, which may be achieved by a CMP process performed during the formation of the bond pads 44.

[0017] Bonding can be achieved by stacking without bumps, wafer-to-wafer, die-to-wafer, or die-to-die bonding processes. For example, bond pads 44 are bonded to bond pads 30 by metal-to-metal direct bonding. According to some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. Furthermore, bond layers 46 are bonded to bond layer 32 by fusion bonding, creating, for example, Si-O-Si bonds. Fig. 2 is hereinafter referred to as a reconstructed wafer 50, and further structural elements are fabricated to augment the reconstructed wafer 50 in later processes.

[0018] Fig. 2 shows an implantation process 48 for forming voltage modulation regions in the bond layer 32 according to some embodiments. The respective process is described as process 205 in the process flow 200 shown in Fig. 25. A plurality of implantation processes are discussed throughout the description. This does not imply that all discussed implantation processes are performed. Rather, fabrication of the package may include one or more of the discussed implantation processes, while other discussed implantation processes may be omitted. At least one or more, or all, of the discussed implantation processes are performed in any combination.

[0019] Before performing the implantation process 48, the parts of the bond layer 32 to be implanted are determined. Either the entirety of the structure shown at the wafer level or some parts of it can be implanted. For example, the Fig. 20 to 23 illustrate the parts to be implanted in the discussed implantation processes (which are discussed in the following paragraphs). To determine which parts of the reconstructed wafer 50 are to be implanted, according to some embodiments, a reconstructed sample wafer may be produced, the structure of which, for example, corresponds to the structure shown in Fig. 7 or Fig. 19. The deflection of the reconstructed sample wafer is measured. The measurement results include the deflection profile of the sample structure, for example, which parts exhibit deflection and the degree of deflection.

[0020] Based on the deflection profile, the portions of the reconstructed wafer 50 to be implanted are determined. According to some embodiments, an unstructured implantation is performed. According to alternative embodiments, a selective implantation process is performed on a portion, but not all, of the reconstructed wafer 50. When the selective implantation process is performed, an implantation mask, such as a patterned photoresist, may be fabricated to mask the portions of the reconstructed wafer 50 that are not to be implanted.

[0021] According to some embodiments, the implanted ions (hereinafter also referred to as voltage modulation dopants) may include Ge, B, P, As, Ga, or the like, or combinations thereof. The implanted ions may also include H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, or a combination thereof and / or the combination with Ge, B, P, As, and / or Ga.

[0022] According to some embodiments, the implantation process 48 is controlled such that the peak concentration of the implanted voltage modulation dopant is within the bonding layer 32. Whenever the description discusses implanting a layer with a voltage modulation dopant, the implantation process is controlled such that the peak concentration of the voltage modulation dopant is within the implanted layer and the concentration decreases as it transitions into adjacent layers. According to some embodiments, the peak concentration of the voltage modulation dopant in the implanted layer may be greater than about 10 16 / cm 3 and, according to some embodiments, can be between about 10 16 / cm 3 and about 10 22 / cm 3 lay.

[0023] Throughout the specification, the regions to be implanted with the voltage modulation dopant are designated using the letter "I" (to represent "implanted"), and the implanted portions of the bonding layer 32 are referred to as implanted portions (or regions) 32-I. The regions that are not implanted with the voltage modulation dopant are designated by the symbol "UI" (to represent "un-implanted"), and the non-implanted portions of the bonding layer 32 are thus referred to as portions (or regions) 32-UI. The non-implanted portions may have a lower concentration of the voltage modulation dopant than the implanted portions or may be free of the voltage modulation dopant.

[0024] As in Fig. As shown in Figure 2, the device dies 36 may serve as an implantation mask to mask the underlying portions of the bond layer 32, such that these portions are unimplanted portions 32-UI. Some other portions are not covered by the device dies 36 and are implanted to form implanted portions 32-I.

[0025] The implantation process 48 modifies the material of the bond layer 32. Furthermore, the density of the implanted parts is increased. Consequently, the deflection of the reconstructed wafer 50 is reduced, and the deflection profile is also modified. For example, the implantation process 48 and / or the subsequently performed implantation processes can individually or collectively lead to a modification of the deflection profile and a reduction in the deflection.

[0026] According to some embodiments, a backside grinding process may be performed to thin the device dies 36. By thinning the device dies 36, the aspect ratio of the gaps between the adjacent device dies 36 is reduced to perform gap filling. Otherwise, gap filling may be difficult due to the otherwise high aspect ratio of the gaps. After backside grinding, the TSVs 40 may be exposed. Alternatively, the TSVs 40 are not exposed at this time, and the backside grinding is stopped when the TSVs 40 are still covered by a thin layer of the substrate. According to these embodiments, the TSVs 40 may be in the Fig. 5 shown step.

[0027] The Fig. 3 and Fig. 4 illustrate the fabrication of a plurality of gap-filling layers. According to some embodiments, the gap-filling layers include a dielectric coating 54 and a dielectric layer 56 over and in contact with the dielectric coating 54.

[0028] With reference to Fig. 3, the dielectric coating 54 is deposited. The respective process is referred to as process 206 in the process flow 200, which is shown in Fig. 25. The dielectric layer 54 may be deposited using conformal deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The dielectric layer 54 is formed from a dielectric material that has good adhesion to the sidewalls of the device dies 36 and the top surfaces of the bond layer 32 and the bond pads 30. According to some embodiments, the dielectric layer 54 is formed from a nitride-containing material such as silicon nitride, SiON, SiCN, or the like. The dielectric layer 54 extends onto the sidewalls of the device dies 36 and is in contact with the sidewalls of the device dies 36.

[0029] According to some embodiments, an implantation process 58 is performed to implant a voltage modulation dopant into the dielectric layer 54. The respective process is referred to as process 208 in the process flow 200 shown in Fig. 25. According to alternative embodiments, the implantation process 58 is omitted. According to some embodiments, the implantation process 58 includes tilted implants so that the voltage modulation dopant can be implanted into sidewall portions 54-SW of the dielectric layer 54, where the sidewall portions are on the sidewalls of the device dies 36. The sidewall portions 54-SW are thus referred to as 54-I according to some embodiments. The implantation process conditions, such as the tilt angle and implantation energy, are controlled such that the peak concentration of the voltage modulation dopant is present in the sidewall portions of the dielectric layer 54.The peak concentrations of the voltage modulation dopant may also be present in the horizontal portions of the dielectric layer 54, or may be present in the underlying bond layer 32, depending on the implantation energy and tilt angle, according to some embodiments.

[0030] The implantation process 58 may also include a vertical implantation process, which may be performed in addition to the tilted implantation or without performing the tilted implantation. The vertical implantation process is controlled such that the peak concentration of the voltage modulation dopant is present in the horizontal portions of the dielectric layer 54.

[0031] If the implantation process 58 includes the vertical implantation process but not a tilted implantation, the lower portions of the sidewall portions 54-SW may be free of the voltage modulation dopants and are also referred to as 54-UI according to alternative embodiments, while the horizontal portions and some upper portions of the sidewall portions are doped and are referred to as 54-I.

[0032] The voltage modulation dopant introduced by the implantation process 58 may be selected from the same group of candidate dopants of the implantation process 48 ( Fig. 2) and may be the same as or different from the voltage modulation dopant introduced by the implantation process 48.

[0033] Fig. 4 shows the production of the dielectric layer 56 over and in contact with the dielectric coating 54. The respective process is referred to as process 210 in the process flow 200 shown in Fig. 25. The dielectric layer 56 is formed from a material different from the material of the dielectric coating 54. According to some embodiments, the dielectric layer 56 is formed from silicon oxide, although other dielectric materials, such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, or the like, may be used if there is an appropriate etch selectivity (e.g., greater than about 50) between the dielectric layer 56 and the dielectric coating 54. The etch selectivity is the ratio of the etch rate of the dielectric layer 56 to the etch rate of the dielectric coating 54 when the dielectric layer 56 is etched in a later process.The dielectric layer 56 may be deposited as a conformal layer, with the thickness of the horizontal portions and the thickness of the vertical portions being substantially equal to each other, or it may be deposited as a non-conformal dielectric layer.

[0034] With reference to Fig. 5, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the dielectric layer 56 and the dielectric coating 54, thereby exposing the device dies 36. The respective process is referred to as process 212 in the process flow 200 shown in Fig. 25. The vias 40 are also exposed. The remaining portions of the dielectric coating 54 and the dielectric layer 56 are collectively referred to as (gap-filling) insulation regions 62.

[0035] According to some embodiments, the implantation process 64 is performed to implant a voltage modulation dopant into the isolation regions 62. The respective process is referred to as process 214 in the process flow 200 shown in Fig. 25. According to alternative embodiments, the implantation process 64 is omitted. According to further alternative embodiments, the implantation process 64 is performed after the formation of vias 66, as shown in Fig. 6. The peak concentrations of the voltage modulation dopant may be within the isolation regions 62 and may also be within the semiconductor substrate 38.

[0036] In the implantation process 64, the semiconductor substrates 38 and some upper portions of the vias 40 are also implanted. Since the density of the vias 40 (which include metal) is high, the voltage modulation dopant is concentrated at the upper portions of the vias 40. Fig. For example, Figure 5 schematically shows the upper portions 40-I containing the voltage modulation dopant and the lower portions 40-UI free of the voltage modulation dopant. Due to the blocking of the vias 40, the voltage modulation dopant is abundant at the upper portions 40-I of the vias 40, with a concentration of the voltage modulation dopant in the upper portions 40-I being higher than in the dielectric coating 54 and the dielectric region 56.

[0037] According to some embodiments, the peak concentration of the voltage modulation dopant is present at a middle level of the isolation regions 62 or a higher level, with the middle level being between the top and bottom of the isolation regions 62. The voltage modulation dopant introduced by the implantation process 64 may extend to the bottom of the isolation regions 62 or may be confined to an upper portion of the isolation regions 62, with the lower portions of the isolation regions 62 being free of the voltage modulation dopant.

[0038] The voltage modulation dopant introduced by the implantation process 64 may be selected from the same group of candidate dopants of the implantation process 48 and / or the implantation process 58 and may be the same as or different from the voltage modulation dopant introduced by the implantation process 48 and / or the implantation process 58.

[0039] Fig. 6 shows the production of vias 66 that penetrate the isolation regions 62. The respective process is referred to as process 216 in the process flow 200 shown in Fig. 25. According to some embodiments, a patterned etch mask (not shown), such as a photoresist, is formed, and the dielectric layer 56 is etched using the patterned photoresist as an etch mask. Openings (occupied by the vias 66) are thus formed and extend downward to the dielectric coating 54, which acts as an etch stop layer. Another etch process is then performed to etch through the dielectric coating 54, exposing the underlying metal pads, also indicated by the reference numeral 30.

[0040] Next, a dielectric coating (not shown) is formed to cover the sidewalls of the opening, insulating the semiconductor substrates 38 from the subsequently formed vias 66. In a later process, a conductive material is filled into the openings, followed by a planarization process to remove excess conductive material and create the vias 66.

[0041] According to alternative embodiments, the vias 66 are not formed. Accordingly, the vias 66 are depicted with dashed lines to indicate that the vias 66 may or may not be formed.

[0042] With reference to Fig. 7, a (back) interconnect structure 72 is fabricated on the back of the device dies 36. The respective process is referred to as process 218 in the process flow 200 shown in Fig. 25. The interconnect structure 72 includes redistribution lines (RDLs) 70 (which also include bond pads) and one or more dielectric layers 68 (which also include a bond layer). According to some embodiments, the dielectric layer 68 is formed from an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like. The RDLs 70 may be formed using a damascene process, which includes etching the dielectric layer 68 to create openings, depositing a conductive barrier layer in the openings, plating a metallic material, such as copper or a copper alloy, and performing a planarization process to remove excess portions of the RDLs 70.

[0043] According to some embodiments, an implantation process 74 is performed to implant a voltage modulation dopant into the dielectric layer 68. The respective process is referred to as process 220 in the process flow 200 shown in Fig. 25. According to alternative embodiments, the implantation process 74 is omitted. The peak concentrations of the voltage modulation dopant may be present within the dielectric layer 68. The voltage modulation dopant introduced by the implantation process 74 may be selected from the same group of candidate dopants of the implantation processes 48 ( Fig. 2), the implantation process 58 ( Fig. 3) and / or the implantation process 64 ( Fig. 5) can be chosen.

[0044] According to some embodiments, the packaging process includes a multi-level packaging process, wherein the device dies 36 are Level 1 dies. In later processes, Level 2 dies are bonded. The processes for fabricating the Level 2 dies may be similar to the processes for the Level 1 dies and are briefly discussed below.

[0045] With reference to Fig. 8, device dies 76 (level 2 dies) are bonded to the bond pads in the interconnect structure 72. The respective process is referred to as process 222 in the process flow 200 shown in Fig. 25. The device dies 76 may include semiconductor substrates 78, vias 80, interconnect structures 82, bond pads 84, and bond layers 86. In some embodiments, the bond pads 84 are bonded to the bond pads in the RDLs 70 by direct metal-to-metal bonding, and the bond layer 86 is bonded to the bond layer in the dielectric layers 68 by melt bonding.

[0046] According to some embodiments, an implantation process 88 is performed to implant a voltage modulation dopant into selected portions of the dielectric layer 68, which portions are not covered by the device dies 76 and are referred to as voltage modulation regions 68-I. The respective process is referred to as process 224 in the process flow 200 shown in Fig. 25. According to alternative embodiments, the implantation process 88 is omitted. The portions of the dielectric layer 68 located directly beneath the device dies 76 are unimplanted and are referred to as unimplanted portions 68-UI. The peak concentrations of the voltage modulation dopant may be present within the dielectric layer 68. The voltage modulation dopant introduced by the implantation process 88 may be selected from the same group of candidate dopants of the implantation processes 48, 58, 64, and / or 74 and may be the same as or different from the voltage modulation dopant introduced by the implantation processes 48, 58, 64, and / or 74.

[0047] Fig. 9 shows the fabrication of a dielectric coating 94 and the optional implantation process 98 according to some embodiments. The respective process is referred to as process 226 in the process flow 200 shown in Fig. 25. The details of the dielectric coating 94 and the implantation process 98 may be substantially similar to those of the dielectric coating 54 and the implantation process 58 shown in Fig. 3, and the details are not repeated here.

[0048] Fig. 10 shows the formation of a dielectric layer 96, the planarization process for forming isolation regions 102, and the optional formation of vias 106. The respective process is referred to as processes 228, 230, 232, and 234 in the process flow 200 shown in Fig. 25. An optional implantation process 104 may (or may not) be performed. The details of the dielectric layer 96, the vias 106, and the implantation process 104 may be substantially similar to those of the dielectric layer 56, the vias 66, and the implantation process 64 shown in the Fig. 4-6, and the details are not repeated here.

[0049] Fig. 11 illustrates the fabrication of a redistribution structure 112 comprising one or more dielectric layers 108 and RDLs 110, and the optional implantation process 114 according to some embodiments. The respective processes are referred to as processes 236 and 238 in the process flow 200 shown in Fig. 25. The details of the dielectric layers 108, the RDLs 110, and the implantation process 114 may be substantially similar to those of the dielectric layers 68, the RDLs 70, and the implantation process 74 shown in Fig. 7, and the details are not repeated here. The fabrication of the reconstructed wafer 50 is thus completed.

[0050] In a later trial, which took place in Fig. 12, a wafer 120 is bonded to the reconstructed wafer 50 by a wafer-to-wafer bonding process. The respective process is referred to as process 240 in the process flow 200 shown in Fig. 25. According to alternative embodiments, more levels of device dies may be further bonded to the level 2 device dies 76 to further expand the reconstructed wafer 50 prior to bonding the wafer 120. As a result of the implantation processes performed during the fabrication of the reconstructed wafer 50, the deflection profile of the reconstructed wafer 50 is improved and / or the deflection of the reconstructed wafer 50 is reduced. Accordingly, the bonding of the wafer 120 and the reconstructed wafer 50 may be free of non-bonding issues.

[0051] According to some embodiments, wafer 120 is a device wafer including a semiconductor substrate 122, integrated circuit devices 124, an interconnect structure 126, bond pads 130, and a bond layer 132.

[0052] Then, the reconstructed wafer 50 is debonded from the carrier 20, for example, by projecting a laser beam onto the LTHC coating material 22, so that the LTHC coating material 22 decomposes, whereby the reconstructed wafer 50 detaches from the carrier 20. The respective process is referred to as process 242 in the process flow 200, which is shown in Fig. 25. The resulting structure is shown in Fig. 13. In later processes, electrical connection elements 134, which may be, for example, solder regions, are formed to connect to the front-side redistribution structure 24, thereby producing a reconstructed wafer 136. The respective process is referred to as process 244 in the process flow 200 shown in Fig. 25. According to alternative embodiments in which the redistribution structure 24 is not used in the process shown in Fig. 1, the redistribution structure 24 can be manufactured after the debonding of the carrier 20.

[0053] In later processes, the reconstructed wafer 136 is singulated in a sawing process to form discrete packages 136'. The discrete packages 136' include device dies 120' that have been sawn from the device wafer 120, and also include device dies 36 and device dies 76. The respective process is referred to as process 246 in the process flow 200 shown in Fig. 25 is shown.

[0054] The process discussed above illustrates a front-to-back bonding process in which the front of the device die 120' faces the back of the device die 76. The front of the device die 76 also faces the back of the device die 36. The Fig. 14 to 19 illustrate the fabrication of a package according to alternative embodiments in which front-to-front bonding is performed. Unless otherwise noted, the materials, structures, and fabrication processes of the components in these embodiments are substantially the same as those for similar components designated with similar reference numerals in the previous embodiments. The details regarding the materials, structures, and fabrication processes provided in each embodiment throughout the specification may be applied to any other embodiment, wherever applicable.

[0055] With reference to Fig. 14, the device wafer 120 is manufactured. According to some embodiments, the wafer 120 is a device wafer including the semiconductor substrate 122, integrated circuit devices 124, and the interconnect structure 126. The interconnect structure 126 also includes bond pads 130 and the bond layer 132. The device wafer 120 further includes device dies 120' therein.

[0056] With reference to Fig. 15, the device dies 36 are bonded to the device wafer 120 using a die-to-wafer bonding process. Then, according to some embodiments, the implantation process 48 may or may not be performed. This then results in the implanted regions 132-I and the unimplanted regions 132-UI.

[0057] The details of the implantation processes according to the processes in the Fig. 16 to 18 may be substantially the same as those described with reference to the embodiments in the Fig. 3 to 7. The processes are briefly mentioned below, and the details can be found in the above embodiments.

[0058] With reference to Fig. 16, the dielectric coating 54 is deposited as a conformal layer through a conformal deposition process. According to some embodiments, the implantation process 58 may or may not be performed.

[0059] Fig. 17 illustrates the formation of dielectric layer 56, isolation regions 62, and optional vias 66 according to some embodiments. The implantation process 64 may be performed or omitted. If performed, the implantation process 64 is performed after the formation of isolation regions 62, and it may be performed before or after the formation of vias 66.

[0060] Fig. 18 shows the production of a lower part of the redistribution structure 112 ( Fig. 19) having the dielectric layer 108 and the redistribution lines 110 therein. The implantation process 114 may be performed or omitted.

[0061] Fig. 19 shows the further fabrication of the redistribution structure 112, which also includes the dielectric layer 108 and the redistribution lines 110 therein. Electrical connection elements 121 are then fabricated on the redistribution lines 110. The electrical connection elements 121 may include solder regions according to some embodiments. The reconstructed wafer 136 is thus fabricated. In a later process, a dicing process is performed to saw the reconstructed wafer 136 into a plurality of discrete packages 136'.

[0062] In the discrete packages 136', which are Fig. 13 or Fig. 19, the regions implanted with the voltage modulation dopant may have a concentration DC-I of the one or more voltage modulation dopant(s) that is higher than the concentration DC-UI of the voltage modulation dopant(s) of undoped portions of the package. For example, the implanted regions may include regions 32-I, dielectric coating 54, dielectric region 56, dielectric layer 68-I, dielectric coating 94, and / or dielectric layer 108. Depending on which of the implantation processes is performed or omitted, at least one, more, or all (in any combination) of these regions / layers may be implanted and have the concentration DC-I of the voltage modulation dopant.The unimplanted regions may include the bond layer 46 of the device dies 36, the bond layer 86 of the device dies 76, the bond layer 132 of the device die 120', the unimplanted regions 32-UI and / or 68-I (if the implantation process 74 is omitted), and the like. According to some embodiments, the DC-I / DC-UI ratio may be greater than about 10, greater than about 100, or even greater. The DC-UI concentration may be equal to 0 (no voltage modulation dopant) or greater than 0 / cm. 3 be.

[0063] The Fig. 20-23 show the implanted parts in the wafer 120 and the reconstructed wafer 50 (hereinafter referred to as wafer 120 / 50) according to some embodiments. The corresponding implantation processes are discussed with reference to the previous embodiments and may include one, several, or all of the implantation processes 48, 58, 64, 74, 88, 98, 104, and 114 in any combination. As shown in Fig. As shown in Figure 20, the entire wafer is implanted 50 / 120, with the implanted portions being referred to as 50-I / 120-I.

[0064] In Fig. 21, some portions of the 50-I / 120-I strips of the 50 / 120 wafer are implanted, and the remaining portions of the 50 / 120 wafer are not implanted. The overlapped regions of the implanted 50-I / 120-I strips whose longitudinal directions run in the x-direction and the implanted strips whose longitudinal directions run in the y-direction may overlap the regions where the deflection value is highest in the 50 / 120 carrier wafer. Fig. 22 shows an embodiment in which the implanted region 50-I / 120-I is a circular region or may have a plurality of circular regions. Fig. Figure 23 shows an embodiment in which selected and isolated regions 50-I / 120-I are implanted.

[0065] In addition, the implanted portions of one of the implantation processes 48, 58, 64, 74, 88, 98, 104 and 114 may be the same as or different from the implanted areas of the other implantation processes to achieve better results.

[0066] Fig. Figure 24A shows a distribution profile of the voltage modulation dopant in a voltage modulation region / layer 140, which represents the voltage modulation layer / regions 32-I, 56, 68 / 68-I, 96, 108, and the like discussed above. The y-direction in the Fig. 24A and Fig. 24B represents the direction perpendicular to the main surfaces of the implanted regions / layers. Accordingly, the y-direction in the Fig. 24A and Fig. 24B for all implanted areas / layers, except for the sidewall parts of the dielectric coating 54 and the dielectric coating 94, the vertical directions in the Fig. 19 and Fig. 19. For the implanted sidewall portions of the dielectric coating 54 and the dielectric coating 94, the y-direction in the Fig. 24A and Fig. 24B the horizontal directions in the Fig. 19 and Fig. 19.

[0067] In Fig. In Figure 24A, layer 142 and layer 144 represent the dielectric layers located above (if present) and below the voltage modulation region / layer 140. The voltage modulation dopant concentrations are shown on the right side of the figure. According to some embodiments, the peak concentration of the voltage modulation dopant is present in the voltage modulation region / layer 140 (and may be present at or near the mid-level of the voltage modulation region / layer 140). In the directions away from where the peak concentration occurs, the voltage modulation dopant concentrations may gradually decrease.

[0068] Fig.24B shows a distribution profile of the voltage modulation dopant in an implanted region 140-I (which may be implanted region 32-I, 68-I, and / or 132-I) and an unimplanted region 140-UI (which may be unimplanted region 32-UI, 68-UI, and / or 132-UI) in a dielectric layer 140. The dielectric layer 140 may represent one of the selectively implanted voltage modulation layer(s) discussed above. According to some embodiments, the peak concentration of the voltage modulation dopant is present in the implanted region 140-I (and may be present at or near the center of the implanted region). The concentrations of the voltage modulation dopant may gradually decrease upon transitioning into the adjacent unimplanted region 140-UI. Some parts of the non-implanted 140-UI regions may be free of the voltage modulation dopant.

[0069] In the embodiments shown above, some processes and structural elements are discussed according to some embodiments of the present disclosure for fabricating a three-dimensional (3D) package. They may also include other structural elements and processes. For example, they may include test structures to support verification testing of the 3D packaging or 3DIC devices. The test structures may, for example, include test pads fabricated in a redistribution layer or on a substrate, enabling testing of the 3D packaging or 3DIC devices, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures.In addition, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of proven good dies to increase yield and reduce cost.

[0070] The embodiments of the present disclosure have several advantageous features. By fabricating voltage modulation regions in dies and / or wafers through ion implantation processes, the deflection of the device dies and / or wafers can be reduced, and the deflection profiles can be modified. This can improve bonding and mitigate non-bonding issues. For example, if a top wafer and a bottom wafer have reduced deflection and / or their deflection profiles are similar, the wafers can be better matched, and bonding can be improved.

[0071] According to some embodiments, a method comprises the steps of: bonding a first device die to a package component, the first device die comprising a semiconductor substrate and a via extending into the semiconductor substrate; depositing a dielectric coating lining sidewalls of the first device die; depositing a dielectric layer on the dielectric coating; planarizing the dielectric layer and the first device die, wherein remaining portions of the dielectric coating and the dielectric layer form a gap-filling region and a top end of the via is exposed; performing a first implantation process to introduce a voltage modulation dopant into at least one of the dielectric coating and the dielectric layer; and forming a redistribution line over and in electrical communication with the via.

[0072] In one embodiment, the first implantation process is performed on the dielectric overlay and is performed before deposition of the dielectric layer. In one embodiment, the first implantation process comprises a tilted implantation process. In one embodiment, the first implantation process comprises a vertical implantation process. In one embodiment, the first implantation process is performed after planarizing the dielectric layer and the first device die. In one embodiment, the method further comprises: after bonding the first device die to the package component and before deposition of the dielectric overlay, performing a second implantation process to implant a top dielectric layer of the package component.

[0073] In one embodiment, the method further comprises: bonding a second device die over the first device die; depositing a further dielectric coating lining sidewalls of the second device die; depositing a further dielectric layer on the further dielectric coating; planarizing the further dielectric layer and the second device die, wherein remaining portions of the further dielectric coating and the further dielectric layer form a further gap-filling region; and performing a second implantation process to introduce a further voltage modulation dopant into the further dielectric coating and / or the further dielectric layer.

[0074] In one embodiment, the stress modulation dopant is equal to the further stress modulation dopant. In one embodiment, the first implantation process comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In one embodiment, implanting the stress modulation dopant comprises implanting the element selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In one embodiment, a peak concentration of the stress modulation dopant is present in the dielectric layer.

[0075] According to some embodiments, a structure comprises a package component having a top dielectric layer, the top dielectric layer comprising: a first portion; and a second portion; a device die over and bonded to the second portion of the top dielectric layer; and a gap-filling dielectric region comprising: a dielectric pad having vertical portions occupying sidewalls of the device die; and a horizontal portion over and in contact with the first portion of the top dielectric layer, the horizontal portion comprising a voltage modulation dopant having a first concentration, and wherein a second concentration of the voltage modulation dopant in the second portion of the top dielectric layer of the package component is less than the first concentration; and a dielectric region on the dielectric pad.

[0076] In one embodiment, the device die comprises a lower dielectric layer bonded to the second portion of the upper dielectric layer, the lower dielectric layer being free of the voltage modulation dopant therein. In one embodiment, the device die comprises: a semiconductor substrate; and a via penetrating the semiconductor substrate, wherein a third concentration of the voltage modulation dopant in an upper portion of the via is higher than both the first concentration and the second concentration. In one embodiment, the voltage modulation dopant comprises an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In one embodiment, the element is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof.

[0077] According to some embodiments, a structure comprises: a first device die; a second device die over and bonded to the first device die, the first device die extending laterally beyond sidewalls of the second device die; and a gap-filling dielectric region comprising: a dielectric pad having vertical portions on the sidewalls of the second device die; and a horizontal portion over and in contact with the first device die to form a horizontal interface, the horizontal portion having a voltage modulation dopant therein, and the voltage modulation dopant having a first peak concentration in the horizontal portion.

[0078] In one embodiment, concentrations of the voltage modulation dopant gradually decrease from a location of the first peak concentration in an upward direction and a downward direction. In one embodiment, the vertical portions have the voltage modulation dopant therein, and the voltage modulation dopant has a second peak concentration in the vertical portions. In one embodiment, concentrations of the voltage modulation dopant gradually decrease from a location of the second peak concentration in opposite horizontal directions.

[0079] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 532,452

[0001]

Claims

[1] Procedure with the following steps: Bonding a first device die to a package component, the first device die comprising a semiconductor substrate; depositing a dielectric coating covering sidewalls of the first device die; depositing a dielectric layer on the dielectric coating; Planarizing the dielectric layer and the first device die, wherein remaining portions of the dielectric coating and the dielectric layer form a gap-filling region; Performing a first implantation process to introduce a voltage modulation dopant into the dielectric coating and / or the dielectric layer; and Forming a redistribution line over and in electrical communication with the first device die. [2] The method of claim 1, wherein the first implantation process is performed on the dielectric coating and is performed before the deposition of the dielectric layer. [3] The method of claim 1 or 2, wherein the first implantation process comprises an inclined implantation process. [4] The method of claim 1 or 2, wherein the first implantation process comprises a vertical implantation process. [5] The method of any preceding claim, wherein the first device die includes a via extending into the semiconductor substrate, and wherein an upper end of the via is exposed after planarizing the dielectric layer. [6] A method according to any one of the preceding claims, further comprising: after bonding the first device die to the package component and before depositing the dielectric coating, performing a second implantation process to implant an upper dielectric layer of the package component. [7] A method according to any one of the preceding claims, further comprising: bonding a second device die over the first device die; depositing another dielectric coating covering sidewalls of the second device die; depositing a further dielectric layer on the further dielectric coating; Planarizing the further dielectric layer and the second device die, wherein remaining parts of the further dielectric coating and the further dielectric layer form a further gap-filling region; and Performing a second implantation process to introduce a further voltage modulation dopant into the further dielectric coating and / or the further dielectric layer. [8] The method of claim 7, wherein the voltage modulation dopant is equal to the further voltage modulation dopant. [9] A method according to any one of the preceding claims, wherein the first implantation process comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb and combinations thereof. [10] The method of claim 9, wherein implanting the voltage modulation dopant comprises implanting the element selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. [11] The method of claim 9 or 10, wherein a peak concentration of the voltage modulation dopant is present in the dielectric coating. [12] Structure with: a package component having an upper dielectric layer, the upper dielectric layer comprising: a first part; and a second part; a device die over and bonded to the second portion of the upper dielectric layer; and a gap-filling dielectric region comprising: a dielectric coating with: first parts that occupy the side walls of the device die; and a second portion over and in contact with the first portion of the upper dielectric layer, wherein the second portion of the dielectric coating comprises a dopant having a first concentration, and wherein a second concentration of the dopant in the second portion of the upper dielectric layer of the package component is less than the first concentration. [13] The structure of claim 12, wherein the device die comprises: a lower dielectric layer bonded to the second portion of the upper dielectric layer, the lower dielectric layer being free of the dopant therein. [14] The structure of claim 12 or 13, wherein the device die comprises: a semiconductor substrate; and a via penetrating the semiconductor substrate, wherein a third concentration of the dopant in an upper portion of the via is higher than both the first concentration and the second concentration. [15] The structure of any one of claims 12 to 14, wherein the dopant comprises an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. [16] The structure of claim 15, wherein the element is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. [17] Structure with: a first device die; a second device die over and bonded to the first device die, the first device die extending laterally beyond sidewalls of the second device die; and a gap-filling dielectric region comprising: a dielectric coating with: first parts on the side walls of the second device die; and a second portion over and in contact with the first device die to form a horizontal interface, the second portion having a dopant therein, the dopant having a first peak concentration in the second portion. [18] The structure of claim 17, wherein concentrations of the dopant gradually decrease from a location of the first peak concentration in an upward direction and a downward direction. [19] The structure of claim 17 or 18, wherein the first portions have the dopant therein, and the dopant has a second peak concentration in the first portions. [20] The structure of claim 19, wherein concentrations of the dopant gradually decrease from a location of the second peak concentration in opposite horizontal directions.

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