Safety device

Abstract

According to various embodiments, a security device is provided, comprising a modular reducer configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word, each binary number consisting of n bits, by one or more first iterations, comprising, in response to a first detector of the security device detecting that the most significant bit (MSB) of the binary number is set, modifying the binary number by deleting its MSB and adding the difference between 2 n-1 and the modulus to the binary number, followed by one or more second iterations, comprising, in response to a second detector of the security device detecting that the MSB of the sum of the binary number with the difference between 2 n-1and the modulus, setting the binary number to this sum, deleting the MSB of the sum.

Description

[0001] The present disclosure relates to safety devices.

[0002] With the development of quantum computers, alternatives to classical asymmetric cryptosystems such as RSA (Rivest Shamir Adleman) and ECC (Elliptic Curve Cryptography), which cannot be attacked by quantum computers, are being investigated. Currently, sufficiently powerful quantum computers are unavailable due to their technical complexity and engineering challenges, but once built, they will be able to break RSA and ECC in polynomial time. Therefore, standards bodies such as NIST (National Institute of Standards and Technology) are now actively investigating alternative cryptosystems. Schemes designed to resist attacks by quantum computers include lattice-based public key encryption, key exchange, and signature schemes. The digital signature algorithm Dilithium was selected by NIST as the primary quantum-secure signature scheme and is standardized in FIPS 204 under the name ML-DSA.

[0003] Key generation in Dilithium requires a uniform sampling of an integer from the range [-η, η], with η ∈ {2, 4}, depending on the parameter set. The discard method is applied to a random bit string (output of an XOF (Extendable Output Function)). The individual nibbles (i.e., bit strings of 4 bits) of this random bit string are tested and accepted if they fall within a specified range. Depending on the parameter set, the accepted values ​​are subject to modular reduction. These two steps (discard sampling and modular reduction) must be computed in a protected manner, i.e., with the masking countermeasure applied, to protect against side-channel attacks.

[0004] Therefore, efficient approaches for generating random integers from a given range are desirable, allowing protection against side-channel attacks.

[0005] The document NIST Computer Security Division. FIPS 204 (Draft): Module-Lattice-Based Digital Signature Standard, 2023, https: / / csrc.nist.zov / pubs / fips / 204 / ipd, hereinafter referred to as Reference 1, describes ML-DSA.

[0006] The publication Hannes Groß, Stefan Mangard and Thomas Korak, “Domain-oriented masking: Compact masked hardware implementations with arbitrary protection order”, in TIS@CCS, page 3. ACM, 2016, hereinafter referred to as Reference 2, describes masked operations, in particular masked AND operations.

[0007] The publication by Jean-Sebastien Coron, Johann Großschädl, Mehdi Tibouchi, and Praveen Kumar Vadnala, "Conversion from arithmetic to boolean masking with logarithmic complexity," in FSE, volume 9054 of Lecture Notes in Computer Science, pages 130–149. Springer, 2015, hereinafter referred to as Reference 3, describes masked addition.

[0008] The standard defined in “FIPS 204 (Draft) 2023-08-24. Module-lattice-based digital signature standard” specifies ML-DSA, a set of algorithms that can be used to generate and verify digital signatures.

[0009] The document US2010 / 0332578A1 describes time-invariant methods and apparatus for performing modular reduction that is protected against cache- and jump-based attacks. The modular reduction technique does not result in any performance degradation and is side-channel robust. Side-channel robustness is ensured by the delayed evaluation of transfer bits, the elimination of data-dependent branches, and the use of uniform cache accesses for all memory references.

[0010] The paper "DUPAQUIS, V. [et al.]: Redundant Modular Reduction Algorithms. In: CARDIS 2011, LNCS 7079. Berlin, Heidelberg : Springer, 2011, pp. 102-114. DOI: 10.1007 / 978-3-642-27257- 8_7" presents modular reduction algorithms over finite fields with large characteristic that enable the use of redundant modular arithmetic.

[0011] The paper "CAO, Z. [et al.]: A Fast Modular Reduction Method. In: Cryptology ePrint Archive, Paper 2014 / 040, 2014. URL: https: / / eprint.iacr.org / 2014 / 040.pdf [accessed January 28, 2025]" presents a lookup table-based modular reduction method that divides the binary string of a number to be reduced into blocks according to its bit sequences. Its complexity depends on the number of bit sequences in the binary string.

[0012] According to various embodiments, a security device is provided, comprising a modular reducer configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word, wherein each binary number consists of n bits and the modulus is less than 2 n-1 is, by processing each binary number of the sequence by one or more first iterations, comprising, in response to a first detector of the security device detecting that the most significant bit of the binary number is set, changing the binary number by clearing its most significant bit and further changing the binary number by adding the difference between 2 n-1and the modulus to the binary number, followed by one or more second iterations, comprising, in response to a second detector of the security device detecting that the most significant bit of the sum of the binary number is equal to the difference between 2 n-1 and the modulus, setting the binary number to the sum of the binary number and the difference between 2n-1 and the modulus, clearing the most significant bit of the sum.

[0013] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects are described with reference to the following drawings, in which: Fig. 1 shows an example of a safety device according to an embodiment. Fig. 2 shows an illustration of processing illustrating a parallel implementation of a rejection algorithm according to one embodiment. Fig. 3 shows a safety device according to an embodiment. Fig. 4 shows a safety device according to another embodiment. Fig. 5 shows a flowchart illustrating a method for generating a random number below a given limit according to one embodiment. Fig. 6 shows a flowchart illustrating a method for performing modulo reduction according to one embodiment.

[0014] The following detailed description refers to the accompanying drawings, which, by way of illustration, show specific details and aspects of this disclosure in which the invention may be practiced. Other aspects may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, as some aspects of this disclosure may be combined with one or more other aspects of this disclosure to form new aspects.

[0015] The examples described herein may be implemented as instructions executed by a processor of a security device such as a personal computer (with security measures), a smart card, a secure microcontroller, a hardware root of trust (ROT), an embedded secure element (ESE), a trusted platform module (TPM), or a shared device.

[0016] Trusted Platform Module (TPM) or a Hardware Security Module (HSM).

[0017] Fig. 1 shows an example of a security device 100 that includes a CPU 101, a RAM 102, a non-volatile memory (NVM) 103, a crypto module 104, an analog module 106, an input / output interface 107, and a hardware random number generator 112.

[0018] In this example, the CPU 101 (which may be, for example, an application processor) has access to at least one crypto module 104 (which may be part of a hardware security module) via a shared bus 105 to which each crypto module 104 is coupled. The shared bus is only an example, and there may be individual interfaces between the various components. In particular, each crypto module 104 may include one or more crypto cores to perform specific cryptographic operations. Example crypto cores are: - an AES core 109, - a SHA core 110, - an ECC core 111, and - a Lattice Based Cryptography (LBC) core 108.

[0019] The LBC core 108 may be provided to accelerate lattice-based cryptography.

[0020] The CPU 101, the hardware random number generator 112, the NVM 103, the crypto module 104, the RAM 102, and the input / output interface 107 are connected to the bus 105. The input / output interface 107 may include a connection 114 to other devices, which may be similar to the security device 100.

[0021] The analog module 106 is supplied with electrical energy via an electrical contact and / or via an electromagnetic field. This energy is supplied to drive the circuitry of the safety device 100 and, in particular, can enable the input / output interface to initiate and / or maintain connections to other devices via connection 114.

[0022] The bus 105 itself can be masked or unmasked. Instructions for executing the processing and algorithms described below can be stored in particular in the NVM 103 and processed by the CPU 105. The processed data can be stored in the NVM 103 or in the RAM 102. Support functions can be provided by the crypto modules 104 (e.g., pseudorandom data extension). Random numbers (e.g., for masks) are provided by the hardware random number generator 112.

[0023] The processing and algorithms described below may be performed exclusively or at least partially on the crypto module 104, e.g., on the LBC core 108 (although they may also be performed on the CPU 101 if no corresponding crypto module is present on the security device 100). A crypto module 104 may or may not be equipped with hardware-based security features. Such hardware-based security features could be circuits that implement countermeasures against side-channel analysis or fault injection (e.g., using a laser). This includes, in particular, masking, i.e., splitting secret data into multiple parts. Such countermeasures may be realized through the use of randomness, redundant hardware, or redundant processing.In general, the goal of countermeasures is to obscure the internally processed values ​​from an attacker who is able to observe the physical effect of processing such values.

[0024] To perform the procedures described below, instructions may be stored in the LBC core 108 or they may be provided by the CPU 101 via the bus 105. Data may be stored locally within the LBC core 108. It is also possible for the data to be temporarily stored in the RAM 102 or the NVM 103. The LBC core 108 may also use other crypto modules to provide support functions (e.g., pseudorandom data extension). The LBC core 108 may also include a hardware random number generator 112 or a means for generating physical and / or software random numbers (e.g., for masks).

[0025] The components of security device 100 can, for example, be implemented on a single chip. Security device 100 can be a smart card (or smart card module) powered by direct electrical contact or by an electromagnetic field. Security device 100 can be a fixed circuit or based on reconfigurable hardware (e.g., field programmable gate array, FPGA). Security device 100 can be coupled to a personal computer, a microcontroller, an FPGA, a smartphone system on a chip (SoC), or other components of a smartphone.The security device 100 may be a chip acting as a Trusted Platform Module (TPM) that provides cryptographic functionality (secure storage, secure time, signature generation and validation, attestation) according to a standardized interface to a computer, a smartphone, an Internet of Things (IoT) device, or a car.

[0026] According to various embodiments, the security device 100 performs, in particular, as a cryptographic operation (ie, cryptographic processing), the digital signature algorithm Dilithium (also referred to as ML-DSA).

[0027] Key generation in dilithium requires a uniform sampling of an integer from the range [-η, η], with η ∈ {2, 4}, depending on the parameter set. The discard method is applied to a random bit string (the output of an XOF - short for extendable-output function). The individual nibbles (4 bits) of this random bit string are tested and accepted if they fall within a specified range. Depending on the parameter set, the accepted values ​​are subject to modular reduction.

[0028] According to various embodiments, an approach is provided that allows at least one of these two steps (discard sampling and modular reduction) to be performed in a protected manner, i.e., with a masking countermeasure applied to protect against side-channel attacks. In particular, the two steps are performed using simple Boolean arithmetic, which can be performed in a masked manner, e.g., using already available masked gadgets (e.g., for performing a masked AND, a masked OR, etc.). Furthermore, due to the processing of only small values, multiple numbers (coefficients in the case of dilithium) can be processed in parallel (SIMD - Single-Instruction-Multiple-Data), which is advantageous for efficiency and side-channel security reasons.

[0029] According to various embodiments, instead of performing subtraction, the rejection test is performed by calculating a simple logical combination of the 4 bits. This can, for example, be performed on all 8 coefficients in a 32-bit word in parallel and requires only a few relatively simple logical operations (ANDs, ORs). Modular reduction is performed, for example, by trial subtraction, but the data is prepared so that, for example, an existing 32-bit masked addition can be used to perform the subtraction on 8 nibbles in parallel (inter-nibble transfers are avoided).

[0030] The key generation of ML-DSA is specified in Reference 1, Section 5. In short, the public key t is calculated as t = As1 + s2, where s1, s2 are the core components of the private key and A∈Rqk×l is a polynomial matrix, where R is the ring of polynomials with one variable over ℤ q [X] / (X 256 + 1). The secret elements s1, s2 are vectors of polynomials with n = 256 coefficients; they are generated in the ExpandS function (see Reference 1). The individual coefficients of s1 and s2 are sampled from the discrete uniform distribution over the interval [-η, η], where η = 2 for the ML-DSA-44 and ML-DSA-87 parameter sets and η = 4 for the ML-DSA-65 parameter set (see Reference 1 for details on these parameter sets). A specific implementation of the discard method is used to generate the coefficients from random bits (generated via the SHAKE XOF (extendable output function) using a secret seed as input). The concrete discard sampling procedure from Reference 1 is as follows:

[0031] The algorithm CoeffFromHalfByte(b) takes a half-byte, i.e. 4 bits (also known as a nibble), as input. It attempts to produce a uniformly distributed value c in the range [0, 2η]. If η = 2, then the input value 15 is discarded, leaving the (2η + 1) · 3 = 5 · 3 = 15 values ​​in [0, 14]. A modular reduction by (2η + 1) = 5 then yields the desired value. If η = 4, then 2η = 8, which means that values ​​greater than or equal to 9 are discarded. If accepted, the output is shifted to the target interval [-η, η] by subtracting c from η. The symbol "up tack" or "falsum" ⊥ denotes rejection.

[0032] When the key is packed in the format described in Reference 1, the subtraction of c from η is reversed, as now explained. The packing procedure for packing the key calls the BitPack algorithm, shown as follows with inputs a = b = η:

[0033] The BitPack algorithm has the inputs a = b = η (see Reference 1). In the BitPack algorithm, the input is subtracted from b. Using the (accepted) output of CoeffFromHalfByte, we get b - (c - η) = η - c + η = c. Thus, the value c ∈ [0, 2η] is packed into either 3 (η = 2) or 4 (η = 4) bits.

[0034] Thus, the generation of the packed key can also be written as shown in Algorithm 1.

[0035] The sampling procedure for the individual coefficients of s1 and s2 is very sensitive and must be protected against side-channel attacks, e.g., using masking. However, masking is not trivially applicable to the sampling algorithm. If implemented unmasked (unprotected), the test for whether b < 15 or b < 9 is typically performed by extracting the input nibble, performing a subtraction of the comparison value, and finally checking the sign bit. Directly masking this procedure requires performing a masked subtraction for each nibble, which is costly. Furthermore, this operation operates on very few bits, which could facilitate attacks.Finally, it is not trivially parallelizable using standard CPU instructions, since performing subtraction on a full CPU word containing multiple nibbles could introduce unwanted carryovers propagating across nibble boundaries. Additionally, similar reasons apply to the reduction mod 5 required in the case of η = 2. Unmasked, this reduction could be performed, e.g., by conditional subtraction of the modulus (at most 2 times) or by using another reduction technique (division, Montgomery, or Barrett reductions). In the masked setting, the input data is likely Boolean masked, meaning that performing the latter techniques requires costly masking conversions (Boolean-to-arithmetic and arithmetic-Boolean masking).Conditional subtractions can be performed directly on masked data, but cannot be easily parallelized (for the same reasons as stated above).

[0036] The following describes approaches for checking whether a nibble is in a suitable range (i.e., for discard testing) and for modular reduction, allowing parallel operations on multiple nibbles (using standard CPU instructions) and the reuse of (possibly already existing) masked operations (addition and Boolean operations, in particular (bitwise) AND, etc.).

[0037] In the following, (logical) right shifts are denoted by ». Furthermore, bitwise operations are represented in the notation of the C programming language. That is, bitwise AND is denoted by &, bitwise OR is denoted by |, bitwise XOR is denoted by ^, and bitwise negation is denoted by ~.

[0038] For discard testing (in this example, testing whether the sampled nibble is lower than 15 or 9), instead of performing a masked subtraction of either 15 or 9, the boundary is tested by logically combining the bits of b.

[0039] In the case of η = 2, the only discarded value is 15, which is the only 4-bit value with all bits set to 1. Thus, calculating the AND combination over all 4 bits reveals the discard condition.

[0040] If η = 4, then all values ​​with the most significant bit (MSB) of b equal to 0 are accepted (values ​​0 to 7). Of the values ​​with the MSB set (values ​​8 to 15), only 8 must be accepted. This is the only value where no other bit is set to 1 except the MSB. In other words, a value must be discarded if the MSB and at least one other bit are set.

[0041] The above is formalized in Algorithm 2.

[0042] Algorithm 2 can easily be computed on multiple nibbles in parallel, as shown in Algorithm 3.

[0043] Algorithm 3 requires only simple logical operations and bit shifts. The example assumes the use of a 32-bit CPU, but the approach can easily be adapted to any other common word width. The statement in line 2 can alternatively be computed using the following two operations, saving an AND operation: t=(c>>1)& c t=(t>>1)& t.

[0044] Fig. Figure 2 shows an illustration of processing 200 illustrating the parallel implementation of Algorithm 3 for the case of η = 2.

[0045] Furthermore, Algorithm 3 can easily be implemented in a masked manner. It is sufficient to compute the variable t in a masked manner, i.e., to use masked AND / OR operations to combine the (also masked) input bits, e.g., using masked AND operations as described in Reference 2 (and, e.g., replacing ORs with (masked) ANDs using de Morgan's law). The final extraction of the LSB can be performed on a share-per-share basis. The final output can be unmasked, since the discard decision is not security-critical.

[0046] The modular reduction (by 5 in the present example for the case of η = 2) is (also) designed to be computed in parallel on all nibbles of a CPU word. The function requires the computation of a masked addition, but it can reuse existing implementations (performing additions of entire CPU words). Operations preceding the addition ensure that the masked operation does not result in carry propagation across nibbles, which would corrupt the result.

[0047] Algorithm 4 is a concrete example (for the modular reduction of a single nibble). It essentially consists of two conditional subtractions of 5.

[0048] In a first step, the MSB of the input is tested and then cleared, and the result is stored in the variable b. Clearing the MSB (if it has been set) is equivalent to subtracting 8 from the numbers in the range [8, 14]. To obtain the correct result, 3 must be added after subtracting 8 (as -8 + 3 = -5). This (conditional) addition is performed by constructing a bit mask from the MSB, applying this bit mask to the constant 3, and adding the result to b. Since both operands of this addition have their MSB set to 0, it is ensured that no carryover propagates beyond the 4-bit boundary. This allows this addition to be performed on multiple nibbles in parallel using standard, e.g., 32-bit, (masked) addition. After this first conditional subtraction, the input is reduced to the range [0, 9]. The second conditional subtraction also uses the congruence 3 ≡ -5 mod 8.The constant 3 is added to the intermediate value. Since the maximum result of this addition is 9 + 3 = 12, transfer propagation across nibble boundaries is also prevented here. If the MSB is set after the addition, 8 is subtracted (i.e., the MSB is cleared again). A multiplexer is then used to select either b (MSB after addition was 0) or b + 3 - 8 (MSB after addition was 1). Algorithm 4, as written above, uses unmasked logical operations. For a masked implementation, all operations (including addition) must be replaced by their masked counterparts. Also, Algorithm 4 specifies that the input must be in [0, 14], i.e., the discard scan (e.g., as described above) is performed earlier.However, feeding 15 into the algorithm does not cause an error or affect neighboring nibbles, the only effect is that the output is not completely reduced (algorithm outputs 5 out of 5 instead of 0).

[0049] Algorithm 4 can be parallelized as shown in Algorithm 5.

[0050] For the masked variants, all operations are replaced by their masked counterparts, e.g., according to Reference 2 for AND operations and according to Reference 3 for the addition operations.

[0051] For example, the full sampling algorithm could feed the XOF output into Algorithm 3 (32 bits at a time). The accepted nibbles are then copied to another buffer. If η = 2, the buffer values ​​are fed into Algorithm 5 (again 32 bits at a time), and the output is repacked from 4 to 3 bits per coefficient. Alternatively, both Algorithm 3 and Algorithm 5 can be run on the XOF output and only then copy the accepted coefficients into the output.

[0052] As mentioned above, the algorithms given above are given in clear, i.e., unmasked, form, but can easily be converted into masked variants by replacing all operations with their masked counterparts. Masked addition (i.e., masked addition operation) can be performed using any (masked) addition functionality, such as a function that adds 32-bit words. The addition could also be optimized by exploiting the fact that no transfer can propagate across nibble boundaries. The general methods can also be applied to bit-slice representations of the data.

[0053] In summary, according to various embodiments, a safety device is provided as in Fig. 3 and / or as shown in Fig. 4 (ie in particular a safety device can be provided which combines the features of both Fig. 3 as well as Fig. 4 includes).

[0054] Fig. 3 shows a security device 300 according to one embodiment.

[0055] The security device 300 comprises a sampler 301 configured to sample a string of n bits (also referred to as a “nibble” in the examples above) in each iteration of a sequence of (random number generation) iterations.

[0056] The security device 300 further comprises a bit string discarder 302 configured to discard the string of n bits in each iteration of the sequence of iterations in response to • a first AND combiner 303 of the security device 300, which generates an AND combination (ie the result of a bitwise Boolean AND operation) of the sampled bits (ie the bits of the sampled string of n bits) which is equal to 1 if a given limit (below which a random number is to be generated) or an integer multiple of the given limit is equal to 2 n -1 is, • an AND-OR combiner 304 (i.e., a functional or functional block or processor configured to perform an AND combination and an OR combination, in this case, an AND combination having an operand that is an OR combination) of the security device 300, which generates an AND combination (i.e., the result of a bitwise Boolean AND operation) of the most significant bit of the sampled bits with an OR combination of the other bits (except the most significant bits, i.e., the least significant bits) of the sampled bits, which is equal to 1 if the given limit is equal to 2 n-1 +1 is.

[0057] The security device 300 further comprises a controller 305 configured to stop, in each iteration of the sequence of iterations, the sequence of iterations in response to a number of strings of n bits that have not been discarded being equal to or greater than a predefined (required) number of bit strings (i.e., to stop when the number of bit strings not discarded is sufficient; in other words, to continue until a sufficient number of bit strings that have not been discarded has been reached).

[0058] Fig. 4 shows a security device 400 according to one embodiment.

[0059] The security device 400 comprises a modular reducer 401 configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word (i.e., the binary numbers, when written one after the other, form the data word), each binary number consisting of n bits and the modulus being less than 2 n-1 -1 is (5 in the example above, which is less than 2 4-1 -1 = 7; this limitation allows a modular reduction by deleting the MSB (which corresponds to the value 2 n ie 8 in the example above)) by processing each binary number of the sequence by • one or more initial iterations, comprising ◯ in response to a first detector 402 of the security device 400 detecting that the most significant bit of the binary number is set, ▪ Changing the binary number by deleting its most significant bit and ▪ further changing (ie after changing the binary number by deleting the most significant bit) the binary number by adding (e.g. by a first adder 404 of the security device 400) the difference between 2 n-1and the modulus (in the example above, this difference is 8 - 5 = 3) to the binary number (and continuing with the binary number as it is modified in the next first iteration or in a second iteration (see below); in other words, the binary number resulting from processing by the first iteration is assigned to the binary number to continue with this resulting binary number). Addition is not performed if the most significant bit of the binary number has not been set and thus has not been cleared; therefore, in other words, addition is performed in response to the most significant bit being cleared. It should be noted that, according to various embodiments, any conditional operation can be performed by bit-masking an operand. For example, there is always an addition operation, but it adds either 3 or 0 (therefore, the addition of 3 is performed conditionally).Clearing the MSB before the addition ensures that there is no overflow in the addition (into a neighboring binary number in an embodiment where the data word is processed as a whole). • followed by one or more second iterations (ie the second iterations operate on the binary number resulting from the one or more first iterations), comprising ◯ in response to a second detector 403 of the security device detecting that the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus (again in the example above this difference is 8 - 5 = 3), ▪ Setting the binary number to the sum (e.g. calculated by a second adder 405 of the security device 400) of the binary number and the difference between 2 n-1 and the modulus, clearing the most significant bit of the sum (if the MSB of the sum is not set, then the binary number is kept unchanged; the one or more second iterations can then be stopped, i.e. no further second iteration needs to be performed).

[0060] Fig. 5 shows a flowchart 500 illustrating a method for generating a random number below a given limit (according to a uniform distribution over the given range) in a robust manner against side-channel attacks according to one embodiment.

[0061] The given limit or a multiple of the given limit is equal to 2 n -1 (15 in the above examples, where n = 4) or the given limit is equal to 2 n-1+1 (9 in the examples above, where n = 4). Note that n is the minimum number of bits that can be used to represent all numbers below the given limit (as binary numbers, that is, when the n bits are used to represent an n-bit binary number, the combinations of all possible values ​​of the bits include all numbers below the given limit).

[0062] The method comprises in each iteration of a sequence of (random number generation) iterations • in 501 sampling a chain of n bits (where either the given limit or a multiple of the given limit is equal to 2 n -1 is (15 in the above examples, where n = 4) or the given limit is equal to 2 n-1 +1 is (9 in the examples above, where n = 4)) • in 502 discarding the chain of n bits in response to ◯ an AND combination of the sampled bits, which is equal to 1 if the given limit or an integer multiple of the given limit is equal to 2 n -1 is, ◯ an AND combination of the most significant bit of the sampled bits with an OR combination of the other bits (except the most significant bits, ie the least significant bits) of the sampled bits, which is equal to 1 if the given limit is equal to 2 n-1 +1; and • in 503, continuing with a next iteration of the sequence of iterations in response to the bit string discarder discarding the string of n bits, and stopping the sequence of iterations in response to a number of strings of n bits that have not been discarded being equal to or greater than a predefined (required) number of bit strings (i.e., stopping when the number of bit strings not discarded is sufficient; in other words, continuing until a sufficient number of bit strings that have not been discarded has been reached).

[0063] In other words, according to various embodiments, the discard sampling is performed by Boolean combinations of the bits of sampled bit strings. This enables, in particular, efficient side-channel attack protection, since the Boolean combinations can be more easily performed in a masked manner (compared to a masked addition).

[0064] Fig. 6 shows a flowchart 600 illustrating a method for performing modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word (i.e., the binary numbers, when written one after the other, form the data word) in a manner that is robust against side-channel attacks, where each binary number consists of n bits and the modulus is less than 2 n-1 -1 is (5 in the example above, which is less than 2 n-1 -1 = 7; this limitation allows a modular reduction by deleting the MSB (which corresponds to the value 2 n-1 , ie 8 in the example above)).

[0065] Each binary number of the sequence is processed by • in 601 one or more first iterations, comprising ◯ in response to the most significant bit of the binary number being set, ▪ in 602 changing the binary number by deleting its most significant bit and ▪ in 603 further changing (ie after changing the binary number by deleting the most significant bit) the binary number by adding the difference between 2 n-1and the modulus (in the example above, this difference is 8 - 5 = 3) to the binary number (and continuing with the binary number as it is changed in the next first iteration or in a second iteration (see below); in other words, the binary number resulting from processing by the first iteration is assigned to the binary number to continue with this resulting binary number). Addition is not performed if the most significant bit of the binary number has not been set and thus has not been cleared; therefore, in other words, addition is performed in response to the most significant bit being cleared. Clearing the MSB before addition ensures that there is no overflow in the addition (into a neighboring binary number in an embodiment where the data word is processed as a whole). • followed by, in 604, one or more second iterations (ie, the second iterations operate on the binary number resulting from the one or more first iterations), comprising ◯ in response to the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus (again in the example above this difference is 8 - 5 = 3), setting the binary number to the sum of the binary number and the difference between 2 n -1 and the modulus, clearing the most significant bit of the sum (if the MSB of the sum is not set, then the binary number is kept unchanged; the one or more second iterations can then be stopped, i.e. no further second iteration needs to be performed).

[0066] In other words, according to various embodiments, modulo reduction is performed in such a way that multiple binary numbers can be reduced in parallel by processing a data word containing the binary numbers, without causing errors due to transmission bit propagation from one binary number to another. This enables the reuse of potentially existing masked adders and efficient side-channel attack protection due to a higher noise level caused by increased parallel activity compared to non-parallel processing of the binary numbers.

[0067] Different examples of the two aspects according to the Fig. (and the Fig. ) are described below.

[0068] Example 1 according to the first aspect is a safety device as described with reference to Fig. 3 is described.

[0069] Example 2 according to the first aspect is the security device of Example 1 according to the first aspect, wherein the controller is configured to proceed to a next iteration of the sequence of iterations in response to the bit string discarder discarding the string of n bits (which was sampled in the iteration). (In other words, in response to a string of n bits being discarded, a new string of n bits is resampled (and the security device continues so, i.e., possibly discarding the resampled string and resampling) until a string of n bits is found that is not discarded.)

[0070] Example 3 according to the first aspect is the security device of example 1 or 2 according to the first aspect, further comprising a modular reducer configured to perform a modular reduction of the binary number represented by the string of n bits sampled in the iteration in which the controller stops the sequence of iterations if the integer multiple of the given limit is equal to 2 n is -1.

[0071] Example 4 according to the first aspect is the security device of any one of examples 1 to 3 according to the first aspect, wherein the sampler is configured to sample, in each iteration of the sequence of iterations, a plurality of strings of n bits, wherein the bit string discarder is configured to discard, in each iteration of the sequence of iterations, for each of the sampled strings of n bits, the string of n bits in response to • the AND combiner of the security device, which generates an AND combination of the sampled bits (ie the bits of the sampled string of n bits) equal to 1 if the given limit or an integer multiple of the given limit is equal to 2 n -1 is, • the AND-OR combiner of the security device, which generates an AND combination of the most significant bit of the sampled bits with an OR combination of the other bits (except the most significant bits, ie the least significant bits) of the sampled bits, which is equal to 1 if the given limit is equal to 2 n-1 +1; andthe controller is configured to continue in each iteration of the sequence of iterations with a next iteration of the sequence of iterations until a number of strings of n bits has not been discarded that is equal to or greater than a predefined number of bit strings.

[0072] Example 5 according to the first aspect is the security device of Example 4 according to the first aspect, wherein in each iteration of the sequence of iterations, the AND combiner is configured to determine the AND combinations of the sampled bits for all of the strings of bits that were sampled simultaneously (e.g., in parallel) in the iteration.

[0073] Example 6 according to the first aspect is the security device of example 4 or 5 according to the first aspect, wherein in each iteration of the sequence of iterations, the AND-OR combiner is configured to determine the AND combination of the most significant bit of the sampled bits with the OR combination of the other bits of the sampled bits for all of the strings of bits that were sampled simultaneously (e.g., in parallel) in the iteration.

[0074] Example 7 according to the first aspect is the security device of any one of examples 1 to 6 according to the first aspect, wherein in each iteration of the sequence of iterations, the AND combiner is configured to determine the AND combination of the sampled bits by means of a masked AND operation.

[0075] Example 8 according to the first aspect is the security device of any one of examples 1 to 7 according to the first aspect, wherein in each iteration of the sequence of iterations, the AND-OR combiner is configured to determine the AND combination of the most significant bit of the sampled bits with the OR combination of the other bits of the sampled bits by means of a masked AND operation and to perform the OR combination of the other bits of the sampled bits by means of a masked OR combination.

[0076] Example 9 according to the first aspect is a method for generating a random number below a given limit in a manner robust against side-channel attacks, as described with reference to Fig. 5 is described.

[0077] Example 1 according to the second aspect is a safety device as described above with reference to Fig. 4 is described.

[0078] Example 2 according to the second aspect is the security device of Example 1 according to the second aspect, wherein the modular reducer is configured to perform the one or more first iterations concurrently (e.g., in parallel) on the binary numbers (by processing the data word as a whole).

[0079] Example 3 according to the second aspect is the security device of example 1 or 2 according to the second aspect, wherein the modular reducer is configured to perform the one or more second iterations concurrently (e.g., in parallel) on the binary numbers (by processing the data word as a whole).

[0080] Example 4 according to the second aspect is the safety device of any one of examples 1 to 3 according to the second aspect, wherein the modular reducer is configured to add the difference between 2 n -1 and the modulus to the binary number by a masked addition.

[0081] Example 5 according to the second aspect is the security device of any one of examples 1 to 4 according to the second aspect, wherein the modular reducer is configured to calculate the sum of the binary number and the difference between 2 n-1 and the modulus, with the most significant bit of the sum deleted, by a masked addition.

[0082] Example 6 according to the second aspect is the security device of any one of examples 1 to 5 according to the second aspect, wherein the first detector is configured to detect whether the most significant bit of the binary number is set by an AND operation.

[0083] Example 7 according to the second aspect is the security device of any one of examples 1 to 6 according to the second aspect, wherein the second detector is configured to detect whether the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus is set by an AND operation.

[0084] Example 8 according to the second aspect is the security device of any one of examples 1 to 7 according to the second aspect, wherein the first detector is configured to simultaneously (e.g., in parallel) detect whether the most significant bits of the binary numbers of the sequence of binary numbers are set.

[0085] Example 9 according to the second aspect is the security device of any one of examples 1 to 8 according to the second aspect, wherein the second detector is configured to simultaneously (e.g., in parallel) detect whether the most significant bits of the sums of the binary numbers with the difference between 2 n-1 and the modulus are set.

[0086] Example 10 according to the second aspect is the security device of any one of examples 1 to 9 according to the second aspect, wherein the modular reducer is configured to add the difference between 2n-1 and the modulus to the binary number in response to the first detector of the security device detecting that the most significant bit of the binary number is set, by constructing a bit mask for the difference between 2n-1 and the modulus to the binary number from the most significant bit of the binary number and adding the difference between 2n-1 and the modulus, masked by the bit mask, to the binary number.

[0087] Example 11 according to the second aspect is a method for performing modulo reduction robust against side-channel attacks by forming a modulus of each binary number of a sequence of binary numbers forming a data word, as described with reference to Fig. 6 is described.

[0088] The examples of the first aspect and the second aspect can also be combined.

[0089] The components of the safety devices 300, 400 of the Fig. 3 and Fig. 4 (e.g., the sampler, the bit string discarder, the controller, the combiners, the modular reducer, the MSB detectors and the adders) can be implemented and the methods of Fig. 5 and Fig.6 may be performed by one or more data processing devices (e.g., computers or microcontrollers) having one or more data processing units or processors and one or more memories (storing data to be processed and instructions according to which the data is processed). The terms "data processing unit" and "processor" may be understood to mean any type of unit that enables the processing of data or signals. For example, the data or signals may be handled according to at least one (i.e., one or more than one) specific function performed by the data processing unit.A computing unit or processor may include or be formed from an analog circuit, a digital circuit, a logic circuit, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or any combination thereof. Any other means for implementing the respective functions described in more detail herein may also be understood to include a computing unit, a processor, or a logic circuit. One or more of the method steps described in more detail herein may be performed (e.g., implemented) by a computing unit or processor through one or more specific functions performed by the computing unit.

[0090] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents. Reference symbol 100 safety device 101 CPU 102 RAM 103 NVM 104 Crypto module 105 Bus 106 Analog module 107 I / O interface 108 LBC core 109 AES core 110 SHA core 111 ECC core 112 HRNG 200 Illustration of a processing 300 Safety Device / Security Controller 301 scanners 302 Bit chain rejector 303 AND combiner 304 AND-OR combiners 305 Control 400 Safety Device / Security Controller 401 Modular Reducer 402 MSB detector 403 MSB detector 404 Adder 405 Adder 500 Flowchart 501-503 Processing 600 Flowchart 601-604 Processing

Claims

[1] Safety device (400) comprising: a modular reducer (401) configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers, which form a data word, where each binary number consists of n bits and the modulus is less than 2 n-1 -1, by processing each binary number of the sequence by one or more initial iterations, comprising in response to a first detector (402) of the security device detecting that the most significant bit of the binary number is set, Changing the binary number by deleting its most significant bit and further changing the binary number by adding the difference between 2 n-1 and the modulus to the binary number, followed by one or more second iterations, comprising in response to a second detector (403) of the security device detecting that the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus is set, setting the binary number to the sum of the binary number and the difference between 2 n-1 and the modulus, whereby the most significant bit of the sum is deleted. [2] The security device (400) of claim 1, wherein the modular reducer (401) is configured to perform the one or more first iterations on the binary numbers simultaneously. [3] The security device (400) of claim 1 or 2, wherein the modular reducer (401) is configured to perform the one or more second iterations on the binary numbers simultaneously. [4] Safety device (400) according to one of claims 1 to 3, wherein the modular reducer (401) is configured to add the difference between 2 n-1and the modulus to the binary number by a masked addition. [5] Security device (400) according to one of claims 1 to 4, wherein the modular reducer (401) is configured to calculate the sum of the binary number and the difference between 2 n-1 and the modulus, with the most significant bit of the sum being deleted, by a masked addition. [6] The security device (400) of any one of claims 1 to 5, wherein the first detector (402) is configured to detect whether the most significant bit of the binary number is set by an AND operation. [7] Security device (400) according to one of claims 1 to 6, wherein the second detector (403) is configured to detect whether the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus is set by an AND operation. [8] The security device (400) of any one of claims 1 to 7, wherein the first detector (402) is configured to simultaneously detect whether the most significant bits of the binary numbers of the sequence of binary numbers are set. [9] Security device (400) according to one of claims 1 to 8, wherein the second detector (403) is configured to simultaneously detect whether the most significant bits of the sums of the binary numbers with the difference between 2 n-1 and the modulus are set. [10] Safety device (400) according to one of claims 1 to 9, wherein the modular reducer (401) is configured to reduce the difference between 2 n-1 and adding the modulus to the binary number in response to the first detector (402) of the security device detecting that the most significant bit of the binary number is set, by constructing a bit mask for the difference between 2 n-1and the modulus to the binary number from the most significant bit of the binary number and adding the difference between 2 n-1 and the modulus, masked by the bit mask, to the binary number. [11] Method for performing a modulo reduction robust against side-channel attacks by a modulus of each binary number of a sequence of binary numbers forming a data word, where each binary number consists of n bits and the modulus is less than 2 n-1 -1, the method comprising: Processing each binary number of the sequence by one or more initial iterations, comprising in response to the most significant bit of the binary number being set, Changing the binary number by deleting its most significant bit and further changing the binary number by adding the difference between 2 n-1 and the modulus to the binary number, followed by one or more second iterations, comprising in response to the most significant bit of the sum of the binary number with the difference between 2 n-1 and the modulus is set, setting the binary number to the sum of the binary number and the difference between 2 n -1 and the modulus, with the most significant bit of the sum being deleted.

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