GATE DRIVER UNIT

Abstract

The Vce detection circuit (120) detects an increase in an interelectrode voltage (Vce) between a positive electrode and a negative electrode when the semiconductor switching element (10a) is switched off. The drive circuit (150) is configured to set a time for reducing the gate drive capability from a first drive capability to a second drive capability based on a detection result of the Vce detection circuit (120) during a switch-off operation of the semiconductor switching element (10a).

Description

Cross-reference to related registrations

[0001] This non-provisional application is based on Japanese patent application No. 2023-134518, which was filed with the Japanese Patent Office on August 22, 2023, and the entire contents of which are hereby incorporated by reference. Background of the invention; Field of the invention

[0002] The present invention relates to a gate driver unit for a semiconductor switching element. Description of the state of the art

[0003] As an example of a gate driver unit that drives and controls a gate control semiconductor switching element, WO 2022 / 050032 (hereinafter referred to as PTL 1) discloses a gate driver unit that switches a gate control current in two stages during a turn-off operation.

[0004] The gate driver unit disclosed in PTL 1 is configured to switch the gate-sink capability by discharging the gate with a first gate drive current from the start of a turn-off operation and discharging the gate with a second gate drive current, which is smaller than the first gate drive current, after a delay time Td has elapsed since the start of the turn-off operation. Furthermore, the delay time Td is set using a surge voltage, which is captured as a peak value of a drain voltage during each turn-off operation.

[0005] The Japanese patent application Laid-Open No. 2021-93676 (hereinafter referred to as PTL 2) discloses a semiconductor gate driver unit suitable for detecting a voltage anomaly (unsaturation state) when a semiconductor switching element is turned on, while simultaneously providing isolation. Summary of the invention

[0006] However, in the gate driver unit of PTL 1, to compensate for fluctuations in the threshold voltage of the semiconductor switching element, it is necessary to set a gate-sink capability switching time using the surge voltage in a series of turn-off cycles before a suitable gate-sink capability switching time is obtained. Therefore, the surge voltage should be kept from becoming excessively high if the initial delay time is set too short. Conversely, if the initial delay time is set too low to reduce the surge voltage, the switching loss can become significant until the delay time is adjusted accordingly.

[0007] The present invention serves to solve such a problem and an object of the present invention is to provide a gate driver unit that is able to adequately control the gate drive capability of a semiconductor switching element when it is switched off in order to suppress switching loss and surge voltage.

[0008] According to one aspect of the invention, a gate driver unit is provided for a semiconductor switching element. The gate driver unit comprises a voltage sensing circuit and a drive circuit that drives a gate of the semiconductor switching element. The voltage sensing circuit detects an increase in an inter-electrode voltage between a positive electrode and a negative electrode when the semiconductor switching element is switched off. The drive circuit is configured to set a time for reducing the gate drive capability from a first drive capability to a second drive capability based on a detection result of the voltage sensing circuit during a switch-off operation of the semiconductor switching element.

[0009] The preceding and other tasks, features, aspects and advantages of the present invention will become apparent from the following detailed description of the present invention in conjunction with the accompanying drawing. Brief description of the drawing Fig. Figure 1 shows a block diagram illustrating a configuration of a gate driver unit according to a comparative example; Fig. Figure 2 shows a conceptual waveform diagram during a switch-off process of the gate driver unit according to the comparative example; Fig. Figure 3 shows a conceptual waveform diagram during a switch-off process when the sinking capability is constant; Fig. Figure 4 shows a block diagram representing a configuration of a gate driver unit according to a first embodiment; Fig. Figure 5 shows a conceptual waveform diagram during a switch-off process of the gate driver unit according to the first embodiment; Fig. Figure 6 shows a conceptual circuit diagram representing a configuration of a gate driver unit according to a second embodiment; Fig. Figure 7 shows a first conceptual diagram illustrating the operation of the gate driver unit according to the second embodiment; Fig. Figure 8 shows a second conceptual diagram illustrating the operation of the gate driver unit according to the second embodiment; Fig. Figure 9 shows a conceptual circuit diagram representing a configuration of a gate driver unit according to a third embodiment; Fig. Figure 10 shows a first conceptual diagram illustrating the operation of the gate driver unit according to the third embodiment; Fig. Figure 11 shows a second conceptual diagram illustrating the operation of the gate driver unit according to the third embodiment; Fig. Figure 12 shows a conceptual circuit diagram representing a configuration of a gate driver unit according to a fourth embodiment; Fig. Figure 13 shows a conceptual waveform diagram during a switch-off process of the gate driver unit according to the fourth embodiment; Fig. Figure 14 shows a conceptual circuit diagram representing a configuration of a gate driver unit according to a fifth embodiment; Fig. Figure 15 shows a conceptual waveform diagram during a normal turn-on process of the gate driver unit according to the fifth embodiment; Fig. Figure 16 shows a conceptual waveform diagram during a switch-on process in which an unsaturation state occurs in the gate driver unit according to the fifth embodiment; Fig. Figure 17 shows a conceptual circuit diagram representing a configuration of a gate driver unit according to a sixth embodiment; Fig. Figure 18 shows a conceptual waveform diagram during a normal turn-on process of the gate driver unit according to the sixth embodiment; and Fig. Figure 19 shows a conceptual waveform diagram during a switch-on process in which an unsaturation state occurs in the gate driver unit according to the sixth embodiment. Description of preferred embodiments

[0010] Embodiments of the present invention are described in detail below with reference to the drawings. It should be noted that in the following description, the same or corresponding parts in the drawings are designated by the same reference numerals and their descriptions are not repeated. First embodiment (configuration and process of the comparative example)

[0011] First, a comparative example is described to explain the problem in PTL 1 in detail.

[0012] Fig. Figure 1 shows a block diagram illustrating a configuration of a Gate Driver Unit 100# according to a comparative example. The Gate Driver Unit 100# has a function for switching the "sink capability" or sinking ability of the gate (gate drive capability), which is equivalent to that described in PTL 1.

[0013] The gate driver unit 100# has, as in Fig. Figure 1 shows a function as a driver IC (integrated circuit) of a semiconductor switching element 10a. The semiconductor switching element 10a is typically equipped with an IGBT (bipolar transistor with insulated gate electrode) and comprises a negative electrode (an emitter designated E) connected to a low-potential node 22, a positive electrode (a collector designated C) connected to a high-potential node 23, and a gate (a control electrode designated G) configured to receive an output voltage VOUT from the gate driver unit 100#. The semiconductor switching element 10a can be equipped with any other gate-driving semiconductor switching element, such as a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0014] In the present embodiment, the low potential node 22 is connected to GND (earth potential / ground potential) and the potential of the high potential node 23 changes according to the on / off state of the semiconductor switching element 10a, but the low potential node 22 and the high potential node 23 can be connected to any object.

[0015] The gate driver unit 100# includes a signal input terminal 101, a reference potential terminal 102, an output terminal 103, a drive circuit 150 and a delay circuit 190.

[0016] A control signal VIN of the semiconductor switching element 10a is input into the signal input terminal 101. The control signal VIN is a binary signal and is set to a high level (hereinafter referred to as the "H level") during an ON period of the semiconductor switching element 10a and to a low level (hereinafter referred to as the "L level") during an OFF period of the semiconductor switching element 10a.

[0017] The reference potential terminal 102 is electrically connected to a negative electrode of the semiconductor switching element 10a. The output terminal 103 is electrically connected to a gate (control electrode) of the semiconductor switching element 10a. Thus, the gate voltage with respect to the negative electrode of the semiconductor switching element 10a, i.e., the gate-emitter voltage (hereinafter also simply referred to as "gate voltage") Vge, is controlled by the output voltage VOUT of the gate driver unit 100#.

[0018] The gate driver unit 100# switches on the semiconductor switching element 10a by setting the output voltage VOUT to a positive voltage Vcc during the high-level period of the control signal VIN, and switches off the semiconductor switching element 10a by setting the output voltage VOUT to a reference potential (0 V) during the low-level period of the control signal VIN.

[0019] The gate driver unit 100# switches the semiconductor switching element 10a on or off by generating a gate current through the output terminal 103 to change the gate voltage Vge via the output voltage VOUT. The delay circuit 190 outputs a signal with a delay time Td added to the control signal VIN.

[0020] The control circuit 150 comprises a sink circuit 151 and a sink circuit 152 for switching the sink capability (gate control capability) when the semiconductor switching element 10a is switched off. The sink circuits 151 and 152 are connected in parallel to the output terminal 103, and the ON / OFF state of the sink circuits 151 and 152 is controlled individually. The sink circuits 151 and 152 can, for example, be equipped with transistors connected in parallel between the output terminal 103 and the reference potential terminal 102.

[0021] Fig. Figure 2 shows a conceptual waveform diagram of a process when the semiconductor switching element 10a is switched off by the gate driver unit 100# according to the comparative example.

[0022] As in Fig. As shown in Figure 2, the switch-off process is initiated when the control signal VIN changes from a high level to a low level at time t0. Before time t0, the output voltage VOUT of the gate driver unit 100# is set to the positive voltage Vcc, which is higher than the threshold voltage Vthg of the semiconductor switching element 10a, thus placing the semiconductor switching element 10a in an ON state. In the ON state, a collector-emitter current is generated to flow from the positive electrode to the negative electrode, and a voltage VHV of the high-potential node 23, in other words a collector-emitter voltage Vce, which is an "inter-electrode voltage" between the positive and negative electrodes of the semiconductor switching element 10a, is equal to the reference potential (0 V, GND).In each of the following waveform diagrams, 0 V corresponds to the output voltage VOUT and the collector-emitter voltage Vce (voltage VHV) corresponds to the potential of the reference potential terminal 102 (the potential of the negative electrode of the semiconductor switching element 10a).

[0023] Sink circuits 151 and 152 are switched off during the ON period of semiconductor switching element 10a and switched on at time t0, when the switch-off process is started. Each of the sink circuits 151 and 152 generates a gate current to discharge the gate of semiconductor switching element 10a through the output terminal 103.

[0024] Sink circuit 151 is switched off during the OFF period of semiconductor switching element 10a, i.e., during the L-level period of the control signal VIN. Conversely, sink circuit 152 is switched off at time t2, when the output signal of delay circuit 190 changes from a high level to a low level. Time t2 is the time at which the delay time Td of delay circuit 190 has elapsed since time t0, when the switch-off process begins. Consequently, between time t0 and time t2, the sink's discharge capability is set to a gate current I1 by both sink circuits 151 and 152, and after time t2, it is reduced to a gate current I2 (I2 < 11) by sink circuit 151 alone.

[0025] When the turn-off process is initiated, the output voltage VOUT decreases from the positive voltage Vcc in response to the discharge through the sink circuits 151 and 152. Since the rate of decrease of the output voltage VOUT depends on the gate current, the rate of decrease of the output voltage VOUT between time t0 and time t2 is greater than that after time t2. In other words, in the gate driver unit 100#, the sink capability, i.e., the rate of decrease of the output voltage VOUT, is switched at time t2, which is defined by the delay time Td.

[0026] When the control signal VIN changes to a high level, the sink circuit 151 is switched off, thus reducing its sinking capability to zero. During the high-level period of the control signal VIN, the drive circuit 150 generates a gate current in one direction to charge the output terminal 103 and the gate of the semiconductor switching element 10a.

[0027] Fig. Figure 3 shows a conceptual waveform diagram during a switch-off process when the sinking capability is constant.

[0028] In relation to Fig. 3 will be at time t0, when the control signal VIN changes as in Fig. When the signal changes from the high (H) level to the low (L) level, the shutdown process is started. During the shutdown process of Fig. 3. The output voltage VOUT decreases from the positive voltage Vcc to 0 V at a constant rate during the ON period, as the control circuit 150 discharges the output terminal 103 and the gate of the semiconductor switching element 10a with a constant sinking capability (gate current).

[0029] The semiconductor switching element 10a is switched off when the gate voltage Vge drops below the positive voltage Vcc, corresponding to the output voltage VOUT. Specifically, when the gate voltage Vge falls below the threshold voltage Vthg, the collector-emitter voltage Vce begins to rise. After the output voltage VOUT (gate voltage Vge) drops to 0 V, the semiconductor switching element 10a is completely switched off, thus ceasing the collector-emitter current and allowing the collector-emitter voltage Vce to reach a steady-state value.

[0030] The rise rate of the collector-emitter voltage Vce during the turn-off process depends on the decay rate of the output voltage Vout. If the decay rate of the output voltage Vout is large, the rise rate of the collector-emitter voltage Vce will be large, and consequently, a surge voltage Vs, which is the maximum value of the collector-emitter voltage Vce generated during the turn-off process, will be high. If the surge voltage becomes too high, it can exceed the breakdown voltage of a load to which the semiconductor switching element 10a is connected, thereby damaging the load.

[0031] On the other hand, the rise rate of the collector-emitter voltage Vce is low when the fall rate of the output voltage VOUT is low, and consequently, the surge voltage Vs is also low. However, the turn-off process becomes smoother, and thus the time required to complete the turn-off process increases, resulting in greater switching losses. As described above, there is a trade-off between suppressing switching losses and surge voltage with respect to the fall rate of the output voltage VOUT.

[0032] In relation to Fig. In gate driver unit 100#, the gate current is increased immediately after the start of the turn-off process, between time t0 and time t2, to increase the slew rate of the output voltage VOUT and thereby suppress switching losses. Conversely, the slew rate of the output voltage VOUT is decreased by reducing the gate current during a turn-off process (time t2), thus suppressing the surge voltage Vs. By providing such a gate current switching function (sink capability), it is possible to suppress both switching losses and surge voltage.

[0033] On the other hand, a device variation can occur in the threshold voltage Vthg of the semiconductor switching element 10a. Fig. Figure 2 represents the waveforms HVa, HVb and HVc of the collector-emitter voltage Vce when Vthg = Va, Vb and Vc.

[0034] When Vthg = Vb, the collector-emitter voltage Vce increases from time t1b. For example, the waveform HVb at Vthg = Vb is the waveform of the collector-emitter voltage Vce when the threshold voltage of the semiconductor switching element 10a is equal to a mean value of the specification and the surge voltage and switching loss can be suppressed in a balanced manner by switching the sink capability at time t2 after the delay time Td has elapsed from the start of the turn-off process (time t0).

[0035] On the other hand, if the threshold voltage of the semiconductor switching element 10a is within a certain range but higher than the median value, Vthg = Va (Va > Vb) is satisfied, so that the collector-emitter voltage Vce rises earlier from time t1a than at time t1b, as represented by waveform HVa. Since the switching time of the sink capability at time t2 does not change in waveform HVa, the switching time of the sink capability is delayed compared to waveform HVb with respect to the rise of the collector-emitter voltage Vce. Consequently, the surge voltage in waveform HVa is higher than in waveform HVb.

[0036] On the other hand, if the threshold voltage of the semiconductor switching element 10a is within the specific range but lower than the median value, Vthg = Vc (Vc < Vb) is satisfied, so that the collector-emitter voltage Vce increases from time t1c later than time t1b, as represented by the waveform HVc.

[0037] Therefore, in waveform HVc, compared to waveform HVb, the switching point for the sinking capability occurs earlier with respect to the rise of the collector-emitter voltage Vce, which is in contrast to waveform HVa. As a result, the surge voltage in waveform HVc is lower than in waveform HVb, and it is concerning that the switching loss may increase.

[0038] In PTL 1 it is described that the delay time Td is sequentially set in response to the actual surge voltage at each turn-off operation so that the surge voltage falls into a predetermined voltage range, but the surge voltage or switching loss can become large until the delay time Td is set to a suitable value.

[0039] However, since the threshold voltage changes as the temperature of the semiconductor switching element increases, and the appropriate delay time can therefore vary, it is concerning that the switching loss or surge voltage may become large until the delay time is appropriately adjusted based on the actual surge voltage. (Configuration and operation of the first embodiment)

[0040] Therefore, in the present embodiment, the time for reducing the sinking capability (gate control capability) during a switch-off process is controlled when an increase in the collector-emitter voltage Vce is detected.

[0041] Fig. Figure 4 shows a block diagram illustrating a configuration of a Gate Driver Unit 100A according to the first embodiment.

[0042] As in Fig. As shown in Figure 4, the gate driver unit 100A comprises a signal input terminal 101, a reference potential terminal 102, an output terminal 103, and a drive circuit 150 (which are the same as those in the gate driver unit 100# according to the comparative example), a voltage sensing terminal 104, a Vce sensing circuit 120, and a delay circuit 140. The signal input terminal 101, the reference potential terminal 102, the output terminal 103, and the drive circuit 150 are configured in the same way as in the comparative example ( Fig. 1) Accordingly, the control circuit 150 is configured to switch the sinking capability in two stages using the sinking circuits 151 and 152.

[0043] The voltage sensing terminal 104 is connected to the positive electrode (the collector) of the semiconductor switching element 10a and is configured to receive a voltage VHV (hereinafter also referred to as input voltage VHV) which corresponds to the collector-emitter voltage Vce.

[0044] The Vce detection circuit 120 is configured to detect a rise in the collector-emitter voltage Vce based on the input voltage VHV. For example, when the input voltage VHV (the collector-emitter voltage Vce) becomes higher than a predetermined reference voltage Vr, the Vce detection circuit 120 changes a detection signal VHd, which represents a rise in the collector-emitter voltage Vce from the low level to the high level. The Vce detection circuit 120 corresponds to an example of a "voltage detection circuit," and the reference voltage Vr corresponds to an example of a "first reference voltage."

[0045] The delay circuit 140 generates an output signal VHdly with a delay time Tdh, which is added to the acquisition signal VHd of the Vce acquisition circuit 120. The control signal VIN and the output signal VHdly of the delay circuit 140 are input to the control circuit 150. The delay circuit 140 can, for example, be equipped with a plurality (an even number of) inverters (NOT gates) connected in series. The delay time Tdh corresponds to an example of a "first delay time".

[0046] Fig. Figure 5 shows a conceptual waveform diagram when the semiconductor switching element 10a is switched off by the gate driver unit 100A according to the first embodiment.

[0047] As in Fig. 5 shown similarly to in Fig. 2. The turn-off process is initiated when the control signal VIN changes from a high level to a low level at time t0. Accordingly, sink circuits 151 and 152 are turned on, and the output terminal 103 and the gate of the semiconductor switching element 10a are discharged by the gate current I1 (sink capability) generated by the two sink circuits 151 and 152. As a result, the output voltage VOUT decreases at a similar rate to that observed between time t0 and time t2. Fig. 2, to suppress switching loss.

[0048] At time t1, when the gate voltage Vge drops to the threshold voltage Vthg in response to a decrease in the output voltage VOUT, the collector-emitter voltage Vce begins to rise. At time t3, the collector-emitter voltage Vce rises to the set voltage Vr of the Vce detection circuit 120. This changes the detection signal VHd from a low level to a high level.

[0049] At time t4, when the delay time Tdh of the delay circuit 140 has elapsed since time t3, the sink circuit 152 is switched off if the output signal VHdly of the delay circuit 140 changes from a low level to a high level. Conversely, the sink circuit 151 remains switched on during the low-level period of the control signal VIN.

[0050] Thus, the gate current (the sinking capability) is reduced to I2 after time t4 in the same way as in Fig. 2 after time t2. As a result, the decay rate of the output voltage VOUT (the gate-emitter voltage Vce) is suppressed, so the surge voltage becomes lower. The delay time Tdh by the delay circuit 140 can be previously determined as the time difference between time t1b and time t2 in the waveform HVb of Fig. 2 will be set.

[0051] Therefore, according to the gate drive unit of the first embodiment, the sink capability (the gate drive capability) of the drive circuit 150 can be switched by online control in response to the actual rise time of the collector-emitter voltage Vce. Consequently, it is possible to switch the sink capability (the gate drive capability) of the drive circuit 150 at a suitable time (e.g., according to the waveform HVb in Fig. 2) to switch in order to suppress the surge voltage and switching loss in a balanced manner, even if the threshold voltage changes due to device variation or temperature changes of the semiconductor switching element 10a. Therefore, the effects of manufacturing variations of the semiconductor switching element can be eliminated, and therefore it is possible to stably suppress the surge voltage and switching loss during a turn-off operation. Second embodiment

[0052] The second embodiment describes a preferred example configuration of the Vce detection circuit 120. The present embodiment represents an exemplary circuit configuration that allows for the isolation of the Vce detection circuit 120 and the drive circuit 150 on the same IC.

[0053] Fig. Figure 6 shows a conceptual circuit diagram representing a configuration of a gate driver unit 100B according to the second embodiment. The gate driver unit 100B corresponds to the gate driver unit 100A ( Fig. 4), in which the internal configuration of the Vce detection circuit 120 is set up. In other words, the shutdown procedure of the gate driver unit 100B is the same as the shutdown procedure of the gate driver unit 100A ( Fig. 4).

[0054] As in Fig. As shown in Figure 6, the Vce detection circuit 120 comprises a current source 121, a current mirror circuit 122, a current mirror circuit 125, a voltage divider circuit 126 comprising resistive elements R1 and R2, and a voltage comparator 130.

[0055] The current mirror circuit 125 comprises P-type transistors T1, T2, and T4, and an N-type transistor T3. Typically, each of transistors T1, T2, and T4 is a PMOS transistor, and transistor T3 is an NMOS transistor. Transistor T1 is connected between voltage sensing terminal 104 and node N4, and transistor T2 is connected between voltage sensing terminal 104 and node N3. Thus, P-type transistors T1 and T2 have a source connected via voltage sensing terminal 104 to the positive electrode of semiconductor switching element 10a.

[0056] Transistor T3 is connected between node N4 and node N5. Transistor T4 is connected between node N3 and node N1. The gates of transistors T1 and T2 are connected to node N3, which is a connecting node for transistors T2 and T4. The gate of transistor T4 is connected to node N4, which is a connecting node for transistors T1 and T3.

[0057] The current mirror circuit 122 comprises transistors Q1 and Q2. Each of transistors Q1 and Q2 is, for example, an NPN bipolar transistor. The current source 121 outputs a constant current 1a to node N6, which is connected to the gate of transistor T3. Transistor Q1 is electrically connected between node N6 and the reference potential terminal 102, and transistor Q2 is electrically connected between node N5 and the reference potential terminal 102. The bases (control electrodes) of transistors Q1 and Q2 are connected to node N5.

[0058] The current mirror circuit 125 thus corresponds to an example of a "first current mirror circuit" and is equipped with a "power supply circuit" that generates an "output current" to the voltage divider circuit 126. The node N5 is connected to the current source 121 via the current mirror circuit 122, and the current mirror circuit 122 corresponds to an example of a "second current mirror circuit". The transistors T1 to T4 each correspond to a "first transistor" to a "fourth transistor".

[0059] The voltage comparator 130 outputs the detection signal VHd based on a comparison between a voltage V+ at the positive input terminal and a voltage V- at the negative input terminal. The detection signal VHd is set to a high level when V+ > V-, and to a low level when V+ ≤ V-.

[0060] Since the positive input terminal of the voltage comparator 130 is connected to node N2, the voltage V+ corresponds to the voltage VN2 of node N2. On the other hand, a voltage source 135 is electrically connected between the negative input terminal of the voltage comparator 130 and the reference potential terminal 102 (the negative electrode of the semiconductor switching element 10a), which outputs a defined voltage Vt (which is a DC voltage).

[0061] In the Vce detection circuit 120, transistors T3 and T4 are connected between a high-voltage circuit HVC, which includes transistors T1 and T2, and a low-voltage circuit LVC between nodes N1 and N5 and the reference potential terminal 102. Therefore, transistors T3 and T4, to which the differential voltage of the high-voltage circuit HVC and the low-voltage circuit LVC is applied between the collector and the emitter, comprise a PMOS transistor and an NMOS transistor, respectively, each of which has a high resistance voltage that can withstand the voltage of the positive electrode (collector) of the semiconductor switching element 10a.Using the high-resistance voltage PMOS transistor and the high-resistance voltage NMOS transistor to form the gate drive unit 100B according to the HVIC (Integrated High Voltage Circuit) technique (PN junction isolation technique), the gate driver unit 120 can be formed (made) with the control circuit 150 on the same IC.

[0062] The current 1a (constant current) from the current source 121 is transferred to the P-type transistors T1 and T2, which are arranged in a current mirror, via the current mirror circuit 122. The current Ib flowing through transistors T2 and T4 changes depending on the input voltage VHV (the collector-emitter voltage Vce of the semiconductor switching element 10a) of the voltage sensing terminal 104, corresponding to the current 1a (constant current) from the current source 121 as the upper limit. The current Ib corresponds to an "output current" that is supplied to the voltage divider circuit 126.

[0063] The resistors R1 and R2, which are provided in the voltage divider circuit 126, are connected in series with the current mirror circuit 125 (transistors T2 and T4) between the voltage sensing terminal 104 and the reference potential terminal 102. The resistors R1 and R2 are connected in series between node N1, to which the current Ib from the current mirror circuit 125 is supplied, and the reference potential terminal 102 via node N2. Hereinafter, the resistance values ​​of the resistors R1 and R2 will also be referred to as R1 and R2.

[0064] The Fig. 7 and Fig. Figure 8 shows conceptual diagrams illustrating the operation of the Gate Driver Unit 100B.

[0065] Fig. Figure 7 shows a characteristic curve diagram between the current Ib and the collector-emitter voltage Vce.

[0066] In relation to Fig. 2 and Fig. 7. Since the collector-emitter voltage Vce (the input voltage VHV) is equal to the source voltage of transistors T1 and T2, the current Ib is not generated in a range where Vce is lower than the threshold voltage Vpmos of transistors T1 and T2 (Ib = 0). When Vce is higher than the threshold voltage Vpmos, the current Ib is generated. The current Ib increases with the increase in Vce and saturates at the current 1a (constant current) from the current source 121.

[0067] Fig. Figure 8 shows a characteristic curve diagram between an input voltage for the voltage comparator 130 and the collector-emitter voltage Vce.

[0068] With reference to Fig. 2 and Fig. 8. A voltage VN1 is generated at node N1, which is the product of the current Ib and the voltage in Fig. The resistance value described in section 7 (R1+R2) corresponds to this. At node N2, a voltage VN2 is generated by dividing the voltage VN1 by R1 / (R1+R2). The voltage VN2 is equal to the positive input voltage of the voltage comparator 130. The voltage VN2 is proportional to the current Ib.

[0069] In the region where Vce ≤ Vpmos, VN1 = VN2 = 0; when Vce > Vpmos, voltages VN1 and VN2 are generated in response to the generation of current Ib. Voltages VN1 and VN2 increase proportionally to the current Ib with the increase in Vce and saturate at current 1a from power source 121. Voltage VN1 saturates at voltage V0, which is equal to the product of current 1a and resistance (R1+R2) (V0 = Ia·(R1+R2)), and voltage VN2 saturates at voltage equal to the product of current Ia and resistance R2.

[0070] As in Fig. 7 and Fig. As shown in figure 8, if the collector-emitter voltage Vce equals the one shown in Fig. The determining voltage Vr shown in section 5 is because the current Ib = Ir ( Fig. 7) The voltage VN1 is represented by VN1 = V1r = Ir·(R1+R2) and the voltage VN2 by VN2 = V2r = Ir·R2. In other words, the generated current Ib increases with the increase of Vce to the saturation value (Ia) when the collector-emitter voltage rises into the voltage range encompassing the defined voltage Vr.

[0071] If the detection voltage (the voltage source 135) input to the negative side of the voltage comparator 130 is designated Vt by adjusting V2r such that V2r = Vt, the voltage comparator 130 can switch the detection signal VHd to the low level when Vce ≤ Vr, and switch the detection signal VHd to the high level when Vce > Vr. The detection voltage Vr corresponds to an example of a "first detection voltage," and the detection voltage Vt corresponds to an example of a "second detection voltage."

[0072] According to the gate driver unit of the second embodiment, the same turn-off process as in the first embodiment can be carried out by detecting a rise in the collector-emitter voltage Vce during the turn-off process based on the output voltage of the voltage divider circuit 126 using the output current (Ib) of the current mirror circuit, which generates a current in accordance with the collector-emitter voltage Vce.

[0073] Thus, it is possible to reduce the resistance value of the voltage divider circuit compared to the configuration that detects an increase in Vce based on a resistance division voltage of the collector-emitter voltage Vce by simple resistance division. Consequently, since the rate at which the input voltage (positive side) of the voltage comparator 130 changes in response to the change in Vce is fast, it is possible to improve the detection accuracy of Vce = Vt (time t3). Fig. 5 to improve.

[0074] In the example configuration of Fig. The resistors R1 and R2 and the current source 121 are not external components, but internal components of the IC. Therefore, it is possible to improve the accuracy of the voltage (VN2 = V2r) of node N2 for detecting Vce > Vr by matching (pairing) the resistors R1 and R2, matching the transistors T1 and T2 (of the current mirror), and matching the transistors Q1 and Q2 (of the current mirror circuit 122). Third embodiment

[0075] Fig. Figure 9 shows a conceptual circuit diagram representing a configuration of a gate driver unit 100C according to a third embodiment.

[0076] As in Fig. As shown in Figure 9, the gate driver unit 100C differs from the gate driver unit 100B ( Fig. 6) in the configuration of the Vce detection circuit 120. In particular, the gates of the P-type transistors T1 and T2 provided in the current mirror are connected to node N4 instead of node N3, and a resistive element R3 is further arranged.

[0077] Resistor R3 is connected between node N4 and node N7, which corresponds to the drain of the high-deflection-voltage NMOS transistor T3. The gate of the high-deflection-voltage PMOS transistor T4 is connected to node N7. Node N7 is connected to a junction of resistor R3 and transistor T3. Fig. 9 the node N4 is connected to a junction of transistor T1 and resistor R3.

[0078] The other components of the gate driver unit 100C, including the Vce sensing circuit 120, are the same as in Fig. 6 (Gate driver unit 100B), and therefore the detailed description of it will not be repeated.

[0079] In the Fig. In the configuration of the second embodiment shown in Figure 6, there is a voltage difference between the input voltage VHV and the voltage of node N3 in the Vce detection circuit 120, which corresponds to the gate-source voltage of transistor T2. This results in a voltage difference between node N1 and the input voltage VHV (the collector-emitter voltage Vce).

[0080] On the other hand, in the Fig. In the configuration shown in Figure 9, since the gates of transistors T1 and T2 are connected to node N4, a current flows through nodes N4 and N5 and a current flows through nodes N3 and N1 in response to the generation of current Ia. Therefore, the ON resistance (resistance between the drain and the source) of transistor T2 becomes sufficiently low, and therefore the voltage of node N3 becomes essentially equal to the input voltage VHV (the collector-emitter voltage Vce).

[0081] Furthermore, the gate-source voltage of transistor T4 (P-type) is made possible by the voltage drop caused by the current in the resistive element R3, thus reducing the on-resistance of transistor T4. This makes the voltage of node N1, similar to node N3, essentially equal to the input voltage VHV (the collector-emitter voltage Vce).

[0082] The Fig. 10 and Fig. Figure 11 shows conceptual diagrams illustrating the operation of the Gate Driver Unit 100C.

[0083] Similar to in Fig. 7 is in Fig. 10 a characteristic curve diagram between the current Ib and the collector-emitter voltage Vce is shown.

[0084] As in Fig. As shown in 10, changes occur in the gate driver unit 100C ( Fig. 9) When the collector-emitter voltage Vce (the input voltage VHV) (Vce > 0) is present, the current Ib flowing through node N1 depends on the input voltage VHV (the collector-emitter voltage Vce of the semiconductor switching element 10a) of the voltage sensing terminal 104, but with the current Ia from the current source 121 as an upper limit. In the third embodiment, the generated current Ib also increases up to the saturation value (Ia) when the collector-emitter voltage Vce increases within the voltage range encompassing the determination voltage Vr.

[0085] In Fig. 7 (of the second embodiment) states that if the collector-emitter voltage Vce is not higher than the threshold voltage Vpmos of transistors T1 and T2, the current Ib is not generated at node N1. Since the current value Ir at Vce = Vr can deviate from the expected value due to changes in Vpmos caused by device variations or similar factors, there is a risk of an error occurring when detecting the time at which the collector-emitter voltage Vce reaches the set voltage Vt.

[0086] On the other hand, in Fig. 10 (of the third embodiment) the current value Ir of the current Ib, which corresponds to Vce = Vr, is not affected by the variation of the threshold voltage Vpmos of transistors T1 and T2.

[0087] Similar to in Fig. 8 is in Fig. Figure 11 shows a characteristic curve diagram between the input voltage of the voltage comparator 130 and the collector-emitter voltage Vce.

[0088] Since the voltages VN1 and VN2 are represented by the product of the current Ib and the resistance value (R1+R2) or the resistance value R1, the voltages VN1 and VN2 change depending on the collector-emitter voltage Vce similarly to the current Ib. By multiplying the current Ib by the in Fig. By using the characteristic curve shown in Figure 10 to generate the input voltage (the voltage VN2) of the voltage comparator 130, it is possible to accurately determine the time at which the collector-emitter voltage Vce reaches the determination voltage Vr without being influenced by the threshold voltage Vpmos of transistors T1 and T2.

[0089] The gate driver unit according to the third embodiment can therefore improve the accuracy for detecting the rise (Vce ≥ Vr) of the collector-emitter voltage Vce compared to the gate driver unit according to the second embodiment, while simultaneously suppressing the influence of device variation. Fourth embodiment

[0090] Fig. Figure 12 shows a conceptual circuit diagram representing a configuration of a gate driver unit 100D according to a fourth embodiment.

[0091] As in Fig. As shown in Figure 12, the gate driver unit 100D differs from the gate drive unit 100C ( Fig. 9) by the fact that the former additionally includes a voltage comparator 131 and an N-type transistor 123, which includes a power supply stop circuit.

[0092] The voltage comparator 131 outputs a signal based on a comparison between the output voltage VOUT of the drive circuit 150 and the target voltage Vt2 from the voltage source 136. The output signal of the voltage comparator 131 is set to a high level when VOUT < Vt2, and to a low level when VOUT ≥ Vt2.

[0093] Transistor 123 is connected in parallel with the current mirror circuit 122 (transistor Q1) between node N6 and the reference potential terminal 102. In the fourth embodiment, the output signal of the voltage comparator 131 is fed to the gate of transistor 123 as the current stop signal Vcut. The configuration of the other components of the gate driver unit 100D is the same as in Fig. 9 (the gate driver unit 100C), so that the detailed description of it will not be repeated.

[0094] The Vce detection circuit 120 must operate when the collector-emitter voltage Vce rises after the start of the turn-off process, and must not operate when the Vce rise is complete (during the OFF period after the turn-off process of the semiconductor switching element 10a has finished). Therefore, to detect the completion of the turn-off process of the semiconductor switching element 10a, the setpoint voltage Vt2, which is input to the voltage comparator 131, is set to a positive voltage close to 0 and lower than the threshold voltage of the semiconductor switching element 10a. The setpoint voltage Vt2 corresponds to an example of a "third setpoint voltage".

[0095] Thus, the current stop signal Vcut is set to a low level during the ON period (VIN = high level) of semiconductor switching element 10a, at which point the output voltage VOUT is set to the positive voltage Vcc. After the start of the turn-off process, the signal is maintained at the low level until the turn-off process is completed. Furthermore, after the turn-off process is completed, the current stop signal Vcut changes to a high level and is maintained at the high level during the next OFF period of semiconductor switching element 10a (until the next turn-on process).

[0096] Fig. Figure 13 shows a conceptual waveform diagram during a switch-off process of the gate driver unit according to the fourth embodiment.

[0097] The waveforms of the control signal VIN, the sink circuits 151 and 152, the output voltage VOUT and the input voltage VHV (collector-emitter voltage Vce) in Fig. 13 are the same as in Fig. 5. Fig. Figure 13 represents, in addition to the waveforms above, a waveform of the current stop signal Vcut.

[0098] As in Fig. As shown in Figure 13, the current stop signal Vcut is maintained at the L level at time t0 when the switch-off process is started, but after the output voltage VOUT drops after the switch-off process has started, the current stop signal Vcut changes from the L level to the H level at time t5 if VOUT < Vt2.

[0099] After time t5, when the control signal VIN changes from a low level to a high level to turn on the semiconductor switching element 10a, the output voltage VOUT rises towards the positive voltage Vcc, and as a result, the current-stop signal Vcut returns to a low level. During the ON period of the semiconductor switching element 10a, the current-stop signal Vcut remains at a low level.

[0100] During the low-level period of the current stop signal Vcut, the current Ia flows from the current source 121 through transistor Q1 and is fed into the current mirror circuit 125 (transistor T2) via the current mirror circuit 122. Therefore, the current Ib is generated in response to the rise in the collector-emitter voltage Vce, and thus the Vce detection circuit 120 performs the detection operation.

[0101] On the other hand, during the high-level period of the current stop signal Vcut, the current Ia from the current source 121 bypasses the current mirror circuit 122, flows through the switched-on transistor 132, and is not transmitted to the current mirror circuit 125. Consequently, even with a collector-emitter voltage Vce present, the current mirror circuit 125 cannot generate the current Ib at node N1. Therefore, the Vce detection circuit 120 stops the detection process.

[0102] During the OFF period, in which the control signal VIN is maintained at the L level after the turn-off process of the semiconductor switching element 10a has ended, the current Ib is continuously supplied to the voltage divider circuit 126 when the current Ia is supplied to the current mirror circuit 125, since the collector-emitter voltage Vce is present. On the other hand, it is unnecessary to detect a time for switching the sink capability during turn-off in the OFF period after the turn-off process of the semiconductor switching element 10a has ended.

[0103] Therefore, after the turn-off process of semiconductor switching element 10a is completed, transistor 132 is turned on to form a current path for the current Ia (the constant current) of the current source 121, bypassing the current mirror circuit 122 (transistor Q1), and thus the current Ib in the Vce sensing circuit 120 becomes 0 (Ib = 0). In other words, transistor 132 corresponds to an example of a "fifth transistor," and during the ON period of transistor 123, the current Ia is not supplied to the current mirror circuit 125, and thus the current Ib is not generated in the Vce sensing circuit 120.

[0104] Current Ia is generated by a low-voltage circuit with a supply voltage of a few volts up to a dozen volts. Current Ib, on the other hand, is generated by a high voltage (e.g., approximately several hundred volts) of a main circuit, which is switched on and off by the semiconductor switching element 10a. Since the power consumption of current Ib is greater than the power consumption of current Ia, after the switch-off process is complete, the supply of current Ia is stopped, thereby stopping the detection process by the Vce detection circuit 120, thus reducing power consumption.

[0105] When the semiconductor switching element 10a is switched on after time t5, the output voltage VOUT rises and VOUT > Vt2, thereby supplying the current Ia to the Vce detection circuit 120. However, since Vce = 0 during the ON period of the semiconductor switching element 10a, the current Ib is not generated. When the current Ia is supplied, the detection process of the Vce detection circuit 120 is restarted and the start of the switch-off process (time t0) is prepared, during which the control signal VIN changes from a high level to a low level.

[0106] As described above, according to the gate driver unit of the fourth embodiment, in addition to the effects of the gate driver unit of the third embodiment, it is possible to reduce power consumption when the operation of the Vce detection circuit 120 is not required (during the OFF period after the shutdown process of the semiconductor switching element 10a has ended).

[0107] In the example of Fig. 12 is the “power supply stop circuit”, which is equipped with the voltage comparator 131 and the N-type transistor 123, the gate driver unit 100C ( Fig. 9) added according to the third embodiment, but the “power supply stop circuit” can be added to the gate driver unit 100B ( Fig. 6) according to the second embodiment. In this case, the second embodiment and the fourth embodiment can be combined by connecting transistor 123, at whose gate the current-stop signal Vcut is applied, in parallel with transistor Q1 in the structure shown in the figure. Fifth embodiment

[0108] The fifth embodiment describes an example configuration in which the Vce detection circuit 120 is also used during the switch-on process of the semiconductor switching element 10a. In particular, the Vce detection circuit 120 is used to detect an unsaturation state during the switch-on process described in PTL 2.

[0109] As described in PTL 2, an unsaturation state occurs in a semiconductor switching element when an overcurrent is generated, and this can lead to a voltage anomaly where a voltage rises between the positive and negative electrodes even though the semiconductor switching element is in the ON state. Therefore, it is effective to detect a voltage anomaly (unsaturation state) to prevent the semiconductor switching element from operating continuously under overcurrent conditions.

[0110] Fig. Figure 14 shows a conceptual circuit diagram representing a configuration of a gate driver unit 100E according to the fifth embodiment.

[0111] As in Fig. As shown in Figure 14, the gate driver unit 100E differs from the gate driver unit 100D ( Fig. 12) by the fact that the gate driver unit 100E further comprises an AND gate 129 configured to safely actuate the Vce detection circuit 120 during the power-up process and a protection circuit 180 configured to actuate when an unsaturated state occurs, and that the Vce detection circuit 120 further comprises a voltage comparator 132 configured to detect the unsaturated state.

[0112] The AND gate 129 outputs an AND operation result of an output signal from the voltage comparator 131, which is the same as the one in Fig. 12 shown, and an inverted signal of the control signal VIN to the gate of transistor 132, which is the same as that shown in Fig. Figure 12 represents the current stop signal Vcut. Consequently, the current stop signal Vcut is reliably set to the low level during the high-level period of the control signal VIN (during the on-level period of the semiconductor switching element 10a). Furthermore, the output signal of the voltage comparator 131 is maintained at the low level during the low-level period of the control signal VIN until VOUT ≥ Vt2; in other words, the current stop signal Vcut is set to the low level until the turn-off process is complete. Afterward, when the turn-off process is complete, the output signal of the voltage comparator 131 changes to the high level, and the current stop signal Vcut is set to the high level.

[0113] The voltage comparator 132 generates a detection signal VFd based on a comparison result between the voltage VN2 of node N2 of the Vce detection circuit 120 and the determining voltage Vt3 from the voltage source 137. If VN2 ≤ Vt3, the detection signal VFd is set to the L level, and if VN2 > Vt3, the detection signal VFd is set to the H level.

[0114] The setpoint voltage Vt3 is adjusted according to the setpoint voltage Vrdst with respect to the collector-emitter voltage Vce to ensure that the collector-emitter voltage Vce does not drop due to the occurrence of the unsaturation state at the switch-on time. For example, in the Vce-VN2 characteristic curve of Fig. 11. The determining voltage Vt3 is set according to the value of the voltage VN2 when Vce = Vrdst. Accordingly, the voltage comparator 132 operates by setting the detection signal VFd to the L level when Vce ≤ Vrdst, and setting the detection signal VFd to the H level when Vce > Vrdst. The determining voltage Vrdst corresponds to an example of a "fourth determining voltage".

[0115] The protection circuit 180 includes a delay circuit 181, a NAND gate 182 and an AND gate 183.

[0116] The delay circuit 181 outputs a delay signal S1 with a delay time Tdp added to the control signal VIN. The NAND gate 182 outputs a signal S2 based on a NAND operation result between the detection signal VFd from the voltage comparator 132 and the delay signal S1. Similar to the delay circuit 140, the delay circuit 181 can be implemented by connecting a plurality (an even number of) inverters (NOT gates) in series.

[0117] The AND gate 183 outputs a control signal S3 to the control circuit 150 based on the result of an AND operation between the control signal VIN (which bypasses the delay circuit 181) and the signal S2. Based on the control signal S3, the control circuit 150 generates an output voltage VOUT during the power-on process, in other words, during the high-level period of the control signal VIN.

[0118] During the period from the start of the power-on process, when the control signal VIN changes from a low level to a high level, until the delay time Tdp (of the delay circuit 181) has elapsed, the delay signal S1 remains at a low level, and the signal S2 from the NAND gate 182 is fixed at a high level. Therefore, the control signal S3 is at the same signal level as the control signal VIN, regardless of the level of the sensing signal VFd.

[0119] After the delay time Tdp has elapsed from the start of the power-on process, signal S2 is set to a high level if the detection signal VFd is at a low level. Conversely, signal S2 is set to a low level if the detection signal VFd is at a high level. In this case, even though the control signal VIN is set to a high level, control signal S3 is set to a low level. Otherwise, control signal S3 is set to a high level.

[0120] When the control signal S3 is set to the low level during the power-on process, the drive circuit 150 detects that a "protection signal" is being generated and switches on the sink circuits 151 and 152 to change the output voltage VOUT to 0 V. The configuration of the other components of the gate driver unit 100E is the same as in Fig. 12 (the gate driver unit 100D), and therefore the detailed description of it will not be repeated.

[0121] Fig. Figure 15 shows a conceptual waveform diagram during a normal turn-on process of the gate driver unit according to the fifth embodiment.

[0122] As in Fig. Figure 15 shows that when the shutdown process is started by changing the control signal VIN from the H level to the L level at time t0, the output voltage VOUT, the input voltage VHV, and the current stop signal Vcut exhibit the same waveforms as in Fig. 13.

[0123] At time t6, the control signal VIN changes from a low level to a high level, thus initiating the switch-on process. Accordingly, the control circuit 150 charges the output terminal 103 and the gate of the semiconductor switching element 10a to increase the output voltage VOUT to a positive voltage Vcc, which is higher than the threshold voltage Vthg. Simultaneously, the current-stop signal Vcut changes from a high level to a low level, and the detection process is initiated by the Vce detection circuit 120.

[0124] At time t7, when the output voltage VOUT, i.e., the gate voltage Vge of the semiconductor switching element 10a, exceeds the threshold voltage Vthg, a current begins to flow between the collector and the emitter, and the input voltage VHV (the collector-emitter voltage Vce) begins to decrease. When the turn-on process normally completes, the input voltage VHV (the collector-emitter voltage Vce) becomes essentially 0 V. Therefore, at time t8, when the delay time Tdp (of the delay circuit 181) has elapsed from time t6 (the start of the turn-on process), since the control signal S3 of the protection circuit 180 is at a high level, the drive circuit 150 maintains the output voltage VOUT equal to the positive voltage Vcc.

[0125] Fig. Figure 16 shows a conceptual waveform diagram during a switch-on process in which the unsaturation state occurs.

[0126] Also in Fig. 16. The switching-off process, i.e., the waveform from time t0 to time t6, as in Fig. 15 shown.

[0127] In Fig. After the start of the switch-on process at time t6, the input voltage VHV begins to decrease from time t7 onwards. However, because an unsaturation state occurs in the semiconductor switching element 10a due to an excessive collector-emitter current (overcurrent state), a voltage anomaly occurs, so that the input voltage VHV (the collector-emitter voltage Vce) does not decrease as expected. Fig. 15 shown decreases (normal state).

[0128] Since Vce > Vrdst is satisfied due to the voltage anomaly, VN2 > Vt3 is satisfied in the voltage comparator 132, and this sets the detection signal VFd to the high level. Accordingly, at time t8, when the delay time Tdp (of the delay circuit 181) has elapsed from time t6 (the start of the switch-on process), the control signal S3 changes ( Fig. 14) from the protection circuit 180 to the L level.

[0129] In response, the control circuit 150 reduces the output voltage VOUT to 0 V, thus switching off the semiconductor switching element 10a. This enables a protective function in which the semiconductor switching element 10a is automatically switched off in response to the detection of an unsaturation state at the time of the switch-on process.

[0130] Although Fig. 14 represents the configuration which further includes the voltage comparator 132 and the protection circuit 180 (for performing the protection function by detecting an unsaturation state), which corresponds to the configuration of the gate driver unit 100D ( Fig. 12) according to the fourth embodiment, it is also possible to combine each of the first to third embodiments with the fifth embodiment by adding the voltage comparator 132 and the protection circuit 180 to each of the gate driver units 100A to 100C according to the first to third embodiments.

[0131] As described above, in the gate driver unit of the fifth embodiment, in addition to the effects of the first to fourth embodiments, the Vce detection circuit used during the switch-off process is also used during the switch-on process to enable the overcurrent protection function. Sixth embodiment

[0132] Fig. Figure 17 shows a conceptual circuit diagram representing a configuration of a gate driver unit 100F according to a sixth embodiment.

[0133] As in Fig. As shown in Figure 17, the gate driver unit 100F differs from the gate driver unit 100E ( Fig. 14) by not including the voltage comparator 132. In the sixth embodiment, the determining voltage Vr for detecting an increase in the collector-emitter voltage Vce during the switch-off process is configured to be equal to the determining voltage Vrdst for detecting an unsaturation state during the switch-on process.

[0134] In the gate driver unit 100F, the detection signal VHd output by the voltage comparator 130 is fed into the protection circuit 180. Since the voltage source 135 outputs the set voltage Vt, which is equal to Vt3 (Vt = Vt3), the detection signal VHd during the switch-on process is the same as that from the voltage comparator 132 in Fig. 14 output detection signals VFd.

[0135] The configuration of the other components of the Gate Driver Unit 100F is the same as in Fig. 14 (of the gate driver unit 100E), and therefore the detailed description of it will not be repeated.

[0136] Fig. Figure 18 shows a conceptual waveform diagram during a normal turn-on process of the gate driver unit according to the sixth embodiment.

[0137] The waveform diagram in Fig. 18 is the same as the waveform diagram in Fig. 15, except that the determining voltage Vr applied during the switching-off process and the determining voltage Vrdst applied during the switching-on process are the same.

[0138] Fig. Figure 19 shows a conceptual waveform diagram during a switch-on process in which an unsaturation state occurs in the gate driver unit according to the sixth embodiment.

[0139] The waveform diagram of Fig. 19 is the same as the waveform diagram of Fig. 16, except that the determining voltage Vr applied during the switching-off process and the determining voltage Vrdst applied during the switching-on process are the same.

[0140] Since the determining voltage Vr applied during the switch-off process and the determining voltage Vrdst applied during the switch-on process are the same, the voltage comparator 132 can be used in Fig. 14 omitted and the voltage comparator 130, which is used in the switch-off process, is used to enable the protection function against an overcurrent based on the detection of an unsaturation state during a switch-on process.

[0141] However, in the case where the determining voltage Vrdst for detecting the unsaturation state must be relatively high due to the characteristics of the semiconductor switching element 10a (e.g., Vrdst is approximately 50 V), when Vr = Vsdst, there is a concern that the detection of the rise in Vce during a turn-off process will be delayed. Therefore, in such a case, it is preferable to use the configuration of the fifth embodiment ( Fig. 14) to use, which includes both the voltage comparator 130 (the determining voltage Vr) and the voltage comparator 132 (the determining voltage Vrdst).

[0142] Although Fig. 17 represents a configuration that, in addition to the Gate driver unit 100D ( Fig. 12) according to the fourth embodiment, comprising a common voltage comparator 130 (Vr = Vrdst2) and a protection circuit 180 for performing the protection function against an unsaturation state, it is possible to combine each of the first to third embodiments and the sixth embodiment by setting Vr = Vrdst2 in the voltage comparator 130 and also providing the protection circuit 180 in each of the gate driver units 100A to 100C.

[0143] As described above, according to the gate driver unit of the sixth embodiment, it is possible to provide a protection function against overcurrent during the switch-on process in addition to the effects of the first to fourth embodiments, while reducing the number of additional circuit elements.

[0144] In the present embodiment, an exemplary circuit configuration for generating an output current (current Ib) to the voltage divider circuit 126 in the Vce detection circuit 120 is shown. Fig. 6 (of the second embodiment) and Fig. 9 (of the third embodiment) is shown, but the “power supply circuit” that supplies the current Ib can be any circuit configuration as long as the Fig. 7 and Fig. The 10 Vce-Ib characteristic curves shown are made possible.

[0145] Furthermore, in the present embodiment it is described that the gate driver units 100A to 100F are arranged on the same IC as the drive circuit 150 and the circumferential circuit as the Vce sensing circuit 120 by the HVIC technology, but the Vce sensing circuit 120 can be arranged as an external circuit of the drive circuit 150, which is configured as a drive IC.

[0146] In most of the embodiments described above, suitable combinations of the configurations of the respective embodiments are originally provided, including combinations not mentioned in the specification, provided they are not incompatible with each other.

[0147] It should be understood that the embodiments and examples disclosed herein are presented for illustrative and descriptive purposes only and are not limited in all aspects. The scope of the present invention is not intended to be limited to the above description but is defined by the scope of the claims and includes all modifications that correspond in meaning and scope to the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-134518

[0001] WO 2022 / 050032

[0003] JP 2021-93676

[0005]

Claims

[1] A gate driver unit for a semiconductor switching element (10a), the gate driver unit comprising: a voltage detection circuit (120) configured to detect an increase in an inter-electrode voltage (Vce) between a positive electrode (C) and a negative electrode (E) when the semiconductor switching element is turned off; and a drive circuit (150) configured to drive a gate (G) of the semiconductor switching element, wherein the drive circuit is configured to set a time (t4) for reducing a gate drive capability from a first drive capability (I1) to a second drive capability (I1) based on a detection result of the voltage detection circuit in a turn-off operation of the semiconductor switching element. [2] Gate driver unit according to claim 1, wherein the voltage detection circuit (120) is configured to detect an increase in the inter-electrode voltage (Vce) when the inter-electrode voltage becomes higher than a predetermined first determination voltage (Vr) after starting the turn-off operation of the semiconductor switching element (10a), and the drive circuit (150) is configured to set the gate drive capability to the first drive capability (11) at the start (t0) of the turn-off operation and to decrease the gate drive capability from the first drive capability to the second drive capability (12) at a time point at which a predetermined first delay time (Tdh) has elapsed after the voltage detection circuit detects the increase in the inter-electrode voltage. [3] Gate driver unit according to claim 2, wherein the voltage detection circuit (120) comprises: a power supply circuit (125) and a voltage divider circuit (126) connected in series between the positive electrode (C) and the negative electrode (E); and a voltage comparator (130) configured to output a detection signal (VHd) representing an increase in the inter-electrode voltage (Vce) when an output voltage (VN2) of the voltage divider circuit is higher than a second determination voltage (Vt), the power supply circuit is configured to increase an output current (Ib) to a saturation value (Ia) when the inter-electrode voltage (Vce) increases in a voltage range including the first determination voltage (Vr), the voltage divider circuit is configured to generate the output voltage proportional to the output current of the power supply circuit, and the second determination voltage (Vt) is set according to the output voltage (Vr2) generated by the voltage divider circuit based on the output current when the inter-electrode voltage is equal to the first determination voltage (Vr). [4] Gate driver unit according to claim 3, wherein the power supply circuit comprises a first current mirror circuit (125) connected between the positive electrode (C) and the voltage divider circuit (126), the first current mirror circuit is configured to generate the output current (Ib) according to a current of a node (N5) connected by means of a second current mirror circuit (122) to a current source (121) outputting a constant current (Ia), and the first current mirror circuit comprises a first p-type transistor (T1) and a second p-type transistor (T2), each comprising a source electrically connected to the positive electrode and a gate connected to each other. [5] Gate driver unit according to claim 4, wherein the first current mirror circuit (125) comprises: a third n-type transistor (T3) connected between the first transistor (T1) and the second current mirror circuit (122) and configured to allow a current supplied by the power supply circuit (125) to flow therethrough; and a fourth p-type transistor (T4) connected between the second transistor (T2) and the voltage divider circuit (126), the gate of the first transistor and the second transistor is connected to a connection node (N3) of the second transistor and the fourth transistor, and a gate of the fourth transistor is connected to a connection node (N4) of the first transistor and the third transistor. [6] Gate driver unit according to claim 4, wherein the first current mirror circuit (125) comprises: a third n-type transistor (T3) connected between the first transistor (T1) and the second current mirror circuit (122) and arranged to allow a current supplied from the power supply circuit (125) to flow therethrough; a resistance element (R3) connected between the first transistor (T1) and the third transistor (T3); and a fourth p-type transistor (T4) connected between the second transistor (T2) and the voltage divider circuit (126), the gate of the first transistor and the second transistor is connected to a connection node (N4) of the first transistor and the resistance element, and a gate of the fourth transistor is connected to a connection node (N7) of the resistance element and the third transistor. [7] The gate driving unit according to claim 4, further comprising a power supply stop circuit (123, 131) configured to stop supplying the current (Ia) from the power source (121) to the first current mirror circuit (125) via the second current mirror circuit (122) during a period from the completion of a turn-off operation of the semiconductor switching element (10a) to the start of a next turn-on operation of the semiconductor switching element. [8] Gate driver unit according to claim 5 or 6, further comprising a power supply stop circuit (121, 123) configured to stop supplying the current (Ia) from the power source (121) to the first current mirror circuit (125) by means of the second current mirror circuit (122) during a period from the completion of a turn-off operation of the semiconductor switching element (10a) to the start of a next turn-on operation of the semiconductor switching element, wherein the power supply stop circuit comprises a fifth transistor (123) connected in parallel with the second current mirror circuit to form a path that bypasses the second current mirror circuit and allows the constant current from the power source to flow through, and the fifth transistor is turned on during a period when an output voltage (VOUT) of the drive circuit (150) is lower than a third determination voltage (Vt2) which is lower than a threshold voltage of the semiconductor switching element (10a). [9] Gate driver unit according to claim 1, wherein the voltage detection circuit (120) is further configured to detect a state of unsaturation of the semiconductor switching element (10a) based on the inter-electrode voltage (Vce) when the semiconductor switching element is turned on, and the drive circuit (150) is configured to drive the gate (G) to turn off the semiconductor switching element when the unsaturation state is detected by the voltage detection circuit during the turn-on operation of the semiconductor switching element. [10] Gate driver unit according to one of claims 2 to 7, wherein the voltage detection circuit (120) is further configured to detect an unsaturation state of the semiconductor switching element (10a) when the inter-electrode voltage (Vce) is not lower than a predetermined fourth determination voltage (Vrdst) after starting the turn-on operation of the semiconductor switching element, the gate driver unit further comprises a protection circuit (180) configured to generate a protection signal (S3) when the unsaturation state is detected by the voltage detection circuit at a time (t8) at which a predetermined second delay time (Tdp) has elapsed from the start (t6) of the turn-on process, and the drive circuit is configured to drive the gate (G) to turn off the semiconductor switching element when the protection signal is generated by the protection circuit. [11] The gate driving unit according to claim 10, wherein the first determination voltage (Vr) and the fourth determination voltage (Vrdst) are equal to each other. [12] The gate driver unit according to claim 5 or 6, wherein each of the third transistor (T3) and the fourth transistor (T4) is formed using PN junction isolation technology to arrange the voltage detection circuit (120) and the drive circuit (150) in the same integrated circuit.

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