Integrated circuit structures with direct-assembled interconnect elements for a uniform grid-metal gate and trench contact cut

Abstract

Integrated circuit structures with interconnects for a uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a gate electrode above a vertical stack of horizontal nanowires or a fin. A conductive trench contact is adjacent to the gate electrode with a dielectric sidewall spacer therebetween. First and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A first conductive interconnect is located in a recess of the first dielectric cut plug structure and is in contact with one side of the gate electrode.A second conductive connecting element is located in a recess of the second dielectric cut plug structure and is in contact with one side of the conductive trench contact.

Description

BACKGROUND

[0001] In recent decades, the scaling of features in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling to ever smaller features enables increased densities of functional units within the limited real estate of semiconductor chips. For example, reducing transistor size allows for the inclusion of a larger number of memory or logic devices on a chip, which lends itself to the manufacture of products with increased capacity. However, the move toward ever larger capacities also presents challenges. The need to optimize the performance of each device is becoming increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common with the continued downscaling of device dimensions. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and because they enable less complicated tri-gate fabrication processes. In another aspect, maintaining mobility enhancement and short-channel control as microelectronic device dimensions scale below the 10-nanometer (nm) node presents a device fabrication challenge. Nanowires used to fabricate devices provide improved short-channel control.

[0003] However, the scaling of multi-gate and nanowire transistors has not been without consequences. As the dimensions of these fundamental building blocks of a microelectronic circuit assembly are reduced, and as the sheer number of fundamental building blocks fabricated in a given area increases, the constraints on the lithography processes used to pattern these building blocks have become overwhelming. In particular, there can be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing of such features. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A-1D illustrate oblique cross-sectional views representing various operations in methods for fabricating an integrated circuit structure with uniform grid metal gate and trench contact cut, according to an embodiment of the present disclosure. Fig. 1E-10 illustrate oblique cross-sectional views representing various operations in methods of fabricating an integrated circuit structure with interconnect elements for a uniform grid metal gate and trench contact cut, according to an embodiment of the present disclosure. Fig. 2A illustrates a cross-sectional view of an integrated circuit structure having a fin and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 2B illustrates a cross-sectional view of an integrated circuit structure having a fin and a cut metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 3A illustrates a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 3B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a cut metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 4A illustrates a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 4B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a cut metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 5A-5C illustrate top views of comparative integrated circuit structures according to an embodiment of the present disclosure. Fig. 6A-6C illustrate cross-sectional views of comparative integrated circuit structures according to an embodiment of the present disclosure. Fig. 7A-7J illustrate cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure according to an embodiment of the present disclosure. Fig. 8 illustrates a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure. Fig. 9 illustrates cross-sectional views through nanowires and fins for a no-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure. Fig. 10 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with gate all-around devices according to an embodiment of the present disclosure. Fig. 11A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 11B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Fig. 11A along the a-a' axis according to an embodiment of the present disclosure. Fig. Figure 11C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Fig. 11A along the b-b' axis according to an embodiment of the present disclosure. Fig. 12 illustrates a computing device according to an implementation of an embodiment of the disclosure. Fig. 13 illustrates an interposer incorporating one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0004] Integrated circuit structures having interconnects for a uniform grid metal gate and trench contact cut and methods of fabricating integrated circuit structures having interconnects for a uniform grid metal gate and trench contact cut are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be understood by one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily obscure embodiments of the present disclosure.Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0005] Certain terminology may also be used in the following description for reference purposes only and is not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or location of parts of the component within a consistent but arbitrary frame of reference made clear by reference to the text and associated drawings describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0006] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of an integrated circuit (IC) fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the final FEOL process, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0007] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of an IC fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as the metallization layer or layers. BEOL includes contacts, insulation layers (dielectrics), metal levels, and bond pads for chip-to-package connections. In the BEOL portion of the fabrication phase, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0008] Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Although an example processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be particularly applicable to BEOL processing. Likewise, although an example processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be particularly applicable to FEOL processing.

[0009] One or more embodiments described herein relate to integrated circuit structures fabricated to include a uniform grid of metal gate and trench contact cuts, which may be referred to as a pixel structure. One or more embodiments described herein relate to gate-all-around devices fabricated using multiple common and extended metal gate cut (MGC)-trench contact (TCN) cut plug structures. It should be understood that, unless otherwise stated, reference to nanowires herein may indicate nanowires or nanoribbons. One or more embodiments described herein relate to FinFET devices fabricated using multiple common and extended metal gate cut (MGC)-trench contact (TCN) cut plug structures.One or more embodiments described herein relate to interconnect elements for cut structures having plugs therein, wherein the interconnect elements are formed using directed self-assembly (DSA).

[0010] To provide some context, it may be advantageous to simplify a trench contact and polycut (gate cut) process, for example, to improve device performance and reduce process variation.

[0011] According to one or more embodiments of the present disclosure, a metal gate process is performed and a trench contact process is performed without plugs. A single "infinite" long grid is then used to create every possible trench contact plug and gate cut plug (as a unified dielectric cut plug). The resulting structure may be referred to as a pixel structure. The pixel structure may then undergo local plug removal to effectively rejoin or reconnect cut gate portions and / or rejoin cut contact portions.

[0012] As an example processing scheme, illustrate Fig. 1A-1D are oblique cross-sectional views representing various operations in methods of fabricating an integrated circuit structure with uniform grid metal gate and trench contact cut, according to an embodiment of the present disclosure.

[0013] With reference to Fig. 1A shows a starting structure 100 prior to a nanowire stripping and gate replacement process. The starting structure 100 includes subfins 104 extending from a substrate 102, such as silicon subfins extending from a silicon substrate. The subfins 104 extend through a shallow trench isolation (STI) structure 106, such as a silicon oxide or silicon dioxide trench isolation structure. One or more stacks of horizontal nanowires 108, such as stacks of horizontal silicon nanowires, are located above a corresponding subfin 104. In this stage, an intermediate sacrificial layer 110, such as an intermediate silicon germanium sacrificial layer, alternates with the horizontal nanowires 108 in the stacks of nanowires. A sacrificial gate oxide 112, such as a silicon oxide or silicon dioxide sacrificial gate oxide, is located over the stacks of horizontal silicon nanowires 108.A sacrificial gate structure 114, such as a polysilicon sacrificial gate structure, is located over the sacrificial gate oxide 112 and over channel regions of the stacks of horizontal nanowires 108. A hard mask layer 116, such as a silicon nitride hard mask layer, may be included on the sacrificial gate structure 114, as shown. A gate spacer forming material 118, such as a silicon nitride gate spacer forming material 118, is included over and along sides of the sacrificial gate structure 114.

[0014] Again with reference to Fig. 1A, epitaxial source or drain structures 120, such as epitaxial silicon or epitaxial silicon germanium source or drain structures, are located at ends of the stacks of horizontal nanowires 108 at locations between adjacent sacrificial gate structures 114. Internal gate spacers 126, such as internal silicon nitride gate spacers 126, may be formed by recessing the intermediate sacrificial layer 110 and depositing the internal gate spacer material prior to forming the epitaxial source or drain structures 120. The epitaxial source or drain structures 120 may be formed above a bottom spacer recess fill 122, such as a silicon nitride spacer fill, which may be formed simultaneously with internal gate spacers 126 and / or a gate spacer forming material 118.A contact insulator structure 128, such as a silicon oxide or silicon dioxide structure, is included over the epitaxial source or drain structures 120 and may occupy locations where conductive trench contacts are ultimately formed.

[0015] With reference to Fig. 1B, the starting structure 100 undergoes a replacement gate and nanowire stripping process flow. In particular, the structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. The planarization may remove the hard mask layer 116, may form gate spacers 118A from the gate spacer formation material 118, and may form a planarized contact insulator structure 128A. The sacrificial gate structure 114 and the sacrificial gate oxide 112 are then removed using selective etching. The intermediate sacrificial layer 110 is then removed using a selective etch. A permanent gate dielectric structure 132, such as a gate dielectric structure including a high-k dielectric layer, is then formed in the resulting trenches and cavities, including around the channel region of each of the nanowires 108.A permanent gate electrode 134, such as a gate electrode including a metal, is formed over the permanent gate dielectric structure 132, including at locations around the channel regions of the nanowires 108. A gate insulation cap layer 136, such as a silicon nitride cap layer, may be formed on the resulting permanent gate electrode structure 134, e.g., by recessing the gate structure and filling it with a dielectric.

[0016] With reference to Fig. 1C and Fig. 1D is a pixel structure 149 with an exposed trench contact cross-sectional view ( Fig. 1C) and with an exposed gate structure cross-sectional view ( Fig. 1D). The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with trench contact material. At this stage, the trench contact material is "infinite" along each contact trench, spanning all source / drain structures along a given trench contact line, effectively shorting all trench contacts along a single trench contact line. Likewise, the gate electrode material at this stage is "infinite" along each gate trench, spanning all nanowire stack channel regions along a given gate line, effectively shorting all gates along a single gate line contact line. The gate insulation cap layer 136 may have been removed at this stage.

[0017] Subsequently, non-selective cuts are made along a direction orthogonal to the gate and trench contact lines, effectively cutting and isolating all trench contacts along a single trench contact line and cutting and isolating all gate electrodes along a single gate line. The cuts are then filled with dielectric plugs 148 that extend through all trench contact lines and through all gate lines. The resulting "pixel" structure 149 includes a plurality of isolated / cut trench contact structures 140, which may include an isolation cap 142 thereon. A trench contact structure 140 may be located at a location exposed by an etch stop layer 144 in contact with a silicide layer 146 on a corresponding epitaxial source or drain structure 120. The resulting "pixel" structure 149 also includes a plurality of isolated / cut gate structures, e.g.Structures including a cut gate dielectric 132A and a cut gate electrode 134A.

[0018] Again with reference to Fig. 1C and Fig. 1D, an integrated circuit structure 149 according to an embodiment of the present disclosure includes a vertical stack of horizontal nanowires 108. A gate electrode 134A is located above the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is located between the gate electrode 134A and the conductive trench contact 140. A first dielectric cut plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric cut plug structure 148 extends through the gate electrode 140, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140.The second dielectric cut plug structure 148 is laterally spaced from and parallel to the first dielectric cut plug structure 148.

[0019] It is understood that the pixel structure 149 may then be subjected to selective reassembly / reconnection of individual ones of the isolated / cut trench contact structures 140 and / or selective reassembly / reconnection of individual ones of the isolated / cut gate structures 132A / 134A. In another aspect, for example, one or more embodiments described herein relate to integrated circuit structures fabricated using a directed self-assembly (DSA) process for trench contact (TCN) plug removal and / or metal gate cut (MGC) plug removal, e.g., as removal of a selective portion of a dielectric cut plug structure.

[0020] To provide context, complex processing schemes may be used to effectively remove metal gate cut (MGC) plugs added during trench contact (TCN) plug patterning to restore continuity in a gate metal. Such an approach may involve one lithography pass, multiple deposition of sacrificial layers, etching, and cleaning, which is expensive and may introduce more variation. According to one or more embodiments of the present disclosure, such an approach is avoided to improve robustness and simplify an MGC plug removal process. Benefits for implementing embodiments disclosed herein may include reducing process costs and increasing robustness (e.g., self-aligned plug removal may provide maximum process margin).

[0021] To provide further context, lateral interconnection can be a key aspect of a pixel architecture. It is important to establish a good lateral connection in one direction without destroying CDs in the other direction. In one embodiment, directed self-assembly (DSA) is used to enable the fabrication of such lateral interconnects.

[0022] As an example processing scheme, illustrate Fig. 1E-10 are oblique cross-sectional views representing various operations in methods of fabricating an integrated circuit structure with interconnect elements for a uniform grid metal gate and trench contact cut, according to an embodiment of the present disclosure. It should be understood that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires or nanoribbons or nanoplates. It should also be understood that a similar approach may be used to reassemble gate structures.

[0023] With reference to Fig. 1E shows a starting structure 150 after metal gate and trench contact cutting processes, e.g., as exemplary versions of the pixel structure 149 of Fig. 1C and Fig. 1D. The starting structure 150 includes a gate electrode 152, such as a metal gate electrode, and a gate dielectric layer 154, such as a high-k gate dielectric layer. A dielectric gate cap 164, such as a silicon nitride dielectric gate cap, is included on the gate electrode 152 and the gate dielectric layer 154. Dielectric sidewall spacers, which may include external spacer portions 155A and internal spacer portions 155B, such as silicon nitride or carbon-doped silicon nitride spacers, are located along sides of the gate electrodes 152, the gate dielectric layers 154, and the gate dielectric caps 164. Each gate structure 152 / 154 is located over one or more pluralities of horizontally stacked nanowires (or nanoribbons or nanosheets, or alternatively, one or more fins) 151, such as silicon nanowires.In one embodiment, a gate location may be replaced by a fin trim isolation (FTI) structure, such as FTI structure 186.

[0024] Again with reference to Fig. 1E, epitaxial source or drain structures 156, such as epitaxial silicon or silicon germanium source or drain structures, laterally adjoin the dielectric sidewall spacers 155A / 155B. In one embodiment, each of the epitaxial source or drain structures 156 is located at an end of a corresponding one of the plurality of horizontally stacked nanowires (or at an end of a corresponding fin) covered by a gate electrode 152 and a gate dielectric layer 154. An etch stop layer 160, such as a silicon nitride etch stop layer, may remain on lower portions of the epitaxial source or drain structures 156.

[0025] Again with reference to Fig. 1E, a conductive trench contact 162, such as a contact structure comprising a conductive liner and a tungsten (W) fill material, is disposed over upper portions of the epitaxial source or drain structures 156. In one embodiment, a silicide layer 151 is disposed between the conductive trench contacts 162 and the corresponding epitaxial source or drain structures 156, as illustrated. Dielectric cut plug structures 166, such as SiN, SiON, SiO, and / or SiC dielectric plugs, intersect selected locations of the gate electrode 152 (such as gate cut plug portions) and extend into and completely isolate portions of the conductive trench contact 162 (such as conductive trench contact cut plug portions), e.g., as in a pixel structure, as illustrated.In such an embodiment, one or more of the dielectric cut plug structures 166 interrupt the continuity of the trench contact 162 at a location that is to be electrically connected.

[0026] In previous approaches, a next-level interconnect could be used to electrically join two portions of a conductive trench contact 162 that are otherwise isolated by a dielectric cut plug 166 extending into the conductive trench contact 162. Alternatively, according to one or more embodiments of the present disclosure, a portion of the dielectric cut plug 166 is removed and replaced with a conductive interconnect element, such as in connection with Fig. 1E-10 described.

[0027] With reference to Fig. 1F, a grating structure 170 is formed on and along a direction of the dielectric gate caps 164 located above the gate structures 152 / 154. In one embodiment, the grating structure 170 is formed by a directed self-assembly (DSA) process that favors formation on a dielectric surface and is not formed on a conductive surface, such as the surfaces of the trench contacts 162, which remain exposed. A patterning helmet layer 172 may be formed on the grating structure 170.

[0028] With reference to Fig. 1G, a mask layer 174 with openings 176 therein is deposited over the structure of Fig. 1F. In one embodiment, each opening 176 exposes a location where a discontinuity between two conductive trench contacts is to be replaced with a conductive interconnect. Portions of the patterning helmet layer 172 and the dielectric cut plug structures 166 below the openings 176 in the mask 174 are subjected to an etch process to provide a patterned helmet layer 172A and recessed dielectric cut plug structures 166A. In one embodiment, the etch process is selective to the conductive trench contacts 162, as shown. The etch process provides for the recessed dielectric cut plug structures 166A to have an overlying recess 175 laterally adjacent to the conductive trench contacts 162 and to expose one side of each of a pair of the conductive trench contacts 162.

[0029] With reference to Fig. 1H, the mask 174 and the patterned helmet layer 172A are removed. A conductive layer 178 is formed between portions of the grating structure 170. The conductive layer 178 is formed on the conductive trench contacts 162 and in the recesses 175 of the recessed dielectric cut plug structures 166A and is ultimately used to form an interconnection element for adjacent trench contacts, as described below in connection with Fig. 1O is described.

[0030] With reference to Fig. 1I, the grid structure 170 is removed, leaving the conductive layer 178 as raised structures.

[0031] With reference to Fig. 1J represents a structure 180 the structure of Fig. 1I following the formation of a dielectric layer 182 and a helmet layer 184 over the conductive layer 178, with the cross-section now passing through the gate structures 152 / 154 (and, if present, the FTI structures 186), in contrast to the cross-sectional perspective of Fig. 1E-1I, which is shown by the epitaxial source or drain structures.

[0032] With reference to Fig. 1K, a mask layer 188 with openings 190 therein is deposited over the structure of Fig. 1J. In one embodiment, each opening 190 exposes a location where a discontinuity between two gate electrodes is to be replaced with a conductive interconnect element. Portions of the dielectric gate caps 164 and the dielectric cut plug structures 166 or 166A below the openings 190 in the mask 188 are subjected to an etch process to provide recessed dielectric cut plug structures 166B. In one embodiment, the etch process is selective to the gate electrodes 152, as shown. The etch process provides for the recessed dielectric cut plug structures 166B to have an overlying recess 191 laterally adjacent to the gate electrodes 152 and to expose one side of each of a pair of the gate electrodes 152.

[0033] With reference to Fig. 1L, the mask layer 188 is removed. A conductive layer 192 is formed between portions of the dielectric layer 182 and over the gate structures 152 / 154. The conductive layer 192 is formed on the dielectric gate caps 164 and in the recesses 191 of the recessed dielectric cut plug structures 166B, e.g., at locations 194, and is ultimately used to form an interconnect for adjacent gate electrodes, as described below in connection with Fig. 1M is described.

[0034] With reference to Fig. 1M, the conductive layer 192 is recessed to leave remaining conductive interconnects 194A in the recesses 191 of the recessed dielectric cut plug structures 166B. In one embodiment, a conductive interconnect 194A couples two adjacent gate electrodes 152, as shown.

[0035] With reference to Fig. 1N, a dielectric cap forming the material layer 196 is formed between portions of the dielectric layer 182 and over the gate structures 152 / 154.

[0036] With reference to Fig. 10 is the structure of Fig. 1N planarized to remove dielectric layer 182 and helmet layer 184, to planarize dielectric capping material layer 196 to form gate insulation cap layer 196A over gate electrodes 152 and over conductive interconnects 194A, and to planarize conductive layer 178 to form conductive interconnects 178A. In one embodiment, conductive interconnect 178A couples two adjacent conductive trench contacts 162, as shown.

[0037] Detection of the implementation of the embodiments described herein may include observing trench contact interconnects and / or gate interconnects that are self-aligned to the trench contacts and / or to the gates and to each other.

[0038] In another aspect, to reduce cell height in a future or scaled-up technology node, both the gate endcap and gate cut size must shrink. A gate cut before a gate metal fill can limit the effective endcap available for a working function and can challenge metal fill capability in a tighter space. The defect can be worse for any gate end-to-end misregistration, creating an even smaller endcap space.

[0039] According to one or more embodiments of the present disclosure, when addressing previously outlined issues, a metal gate cutting process is implemented subsequent to completing a gate dielectric and work function metal deposition and patterning. In any case, in one embodiment, gate plugs formed after metal gate formation ("plug-last") and / or gate plugs formed before metal gate formation ("plug-first"), both described below, may be used for the processes previously described in connection with Fig. 1A-10 described gate / contact plugs can be used.

[0040] Advantages for implementing approaches described herein may include a so-called "plug-last" approach, with the result that a gate dielectric layer (such as a high-k gate dielectric layer) is not deposited on a gate plug sidewall, effectively saving additional space for workfunction metal deposition. In contrast, during a so-called conventional "plug-first" approach, metal gate fill material may squeeze in between the plug and the fin. The space for metal fill may be narrower due to plug misregistration in the latter approach and may result in gaps during metal fill. In embodiments described herein, using a "plug-last" approach, workfunction metal deposition may be seamless (e.g., without gaps).

[0041] According to one or more embodiments of the present disclosure, an integrated circuit structure has a clean interface between a gate plug dielectric and a gate metal. It is understood that many embodiments may benefit from approaches described herein, such as plug-last approaches. For example, a metal gate cut on a FinFET device is described below in connection with Fig. 2B. A metal gate cutting scheme can be implemented for a Gate-All-Around (GAA) device, such as described below in connection with Fig. 3B and Fig. 4B. Furthermore, a metal gate cut and plug formation may appear differently based on the incoming structure. For example, the plug may land on a shallow trench isolation (STI) structure, such as in conjunction with Fig. 2B and Fig. 3B, or may land on a prefabricated gate wall made of a dielectric, such as in conjunction with Fig. 4B. A metal gate cut approach may be selective to a gate spacer dielectric, such as in conjunction with Fig. 5B and Fig. 6B, or may be non-selective to a gate spacer material, such as in conjunction with Fig. 5C and Fig. 6C. A non-selective metal gate cut embodiment may require an alternative contact metal scheme to accommodate a dielectric plug between the epitaxial source / drain. Plug etch selectivity to the epitaxial source / drain material is optional. However, if the epitaxial source / drain is subject to a plug etch in one embodiment (e.g., due to device dimension), the etch may anisotropically trim the source / drain, as described below in connection with Fig. 5C. Such an approach can be implemented to achieve close endcap spacing.

[0042] A dielectric gate plug can be fabricated for a FinFET device. As a comparative example, Fig. 2A is a cross-sectional view of an integrated circuit structure having a fin and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 2B illustrates a cross-sectional view of an integrated circuit structure having a fin and a cut metal gate dielectric plug according to an embodiment of the present disclosure.

[0043] With reference to Fig. 2A, an integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206, such as a high-k gate dielectric layer, is located over the protruding portion of the fin 202 and over the STI structure 204. It should be understood that, although not shown, an oxidized portion of the fin 202 may be located between the protruding portion of the fin 202 and the gate dielectric material layer 206 and may be included together with the gate dielectric material layer 206 to form a gate dielectric structure. A conductive gate layer 208, such as a work function metal layer, is located above the gate dielectric material layer 206 and may be located directly on the gate dielectric material layer 206, as shown.A conductive gate fill material 210 is disposed over the conductive gate layer 208 and may be disposed directly on the conductive gate layer 208, as shown. A dielectric gate cap 212 is disposed on the conductive gate fill material 210. A dielectric gate plug 214 is laterally spaced from the fin 202 and disposed on the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are disposed along sides of the dielectric gate plug 214.

[0044] With reference to Fig. 2B, an integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256, such as a high-k gate dielectric layer, is located over the protruding portion of the fin 252 and over the STI structure 254. It should be understood that, although not shown, an oxidized portion of the fin 252 may be located between the protruding portion of the fin 252 and the gate dielectric material layer 256 and may be included along with the gate dielectric material layer 256 to form a gate dielectric structure. A conductive gate layer 258, such as a work function metal layer, is located above the gate dielectric material layer 256 and may be located directly on the gate dielectric material layer 256, as shown.A conductive gate fill material 260 is disposed over the conductive gate layer 258 and may be disposed directly on the conductive gate layer 258, as shown. A dielectric gate cap 262 is disposed on the conductive gate fill material 260.

[0045] In one embodiment, a dielectric gate plug 264 is laterally spaced from the fin 252 and is located on, but not through, the STI structure 254. As used throughout the disclosure, a dielectric plug referred to as being "on, but not through" an STI structure may refer to a dielectric plug that has landed on a top or uppermost surface of the STI, or may refer to a plug that extends into, but does not penetrate, the STI. In other embodiments, a plug described herein may extend completely through or penetrate the STI.

[0046] In one embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 are not located along sides of the gate dielectric plug 264. Instead, the conductive gate fill material 260 is in contact with the sides of the gate dielectric plug 264. As a result, a region between the gate dielectric plug 264 and the fin 252 includes only one layer of the gate dielectric material layer 256 and only one layer of the conductive gate layer 258, alleviating space constraints in such a narrow region of the structure 250. Alleviating space constraints may improve metal filling and / or facilitate patterning of multiple VTs.

[0047] Again with reference to Fig. 2B, in one embodiment, the dielectric gate plug 264 is formed after forming the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate fill material 260. In one embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along sides of the dielectric gate plug 264. In one embodiment, the dielectric gate plug 264 has a top surface coplanar with a top surface of the dielectric gate cap 262, as shown. In another embodiment, not shown, no dielectric gate cap 262 is included, and the dielectric gate plug 264 has a top surface coplanar with a top surface of the conductive gate fill material 260, e.g., along a plane 280.

[0048] A dielectric gate plug can be fabricated for a nanowire device. As a comparative example, Fig. 3A is a cross-sectional view of an integrated circuit structure including nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 3B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a cut metal gate dielectric plug according to an embodiment of the present disclosure.

[0049] With reference to Fig. 3A, an integrated circuit structure 300 includes a subfin 302 with a portion protruding above a shallow trench isolation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are located above the subfin 302. A gate dielectric material layer 306, such as a high-k gate dielectric layer, is located above the protruding portion of the subfin 302, above the STI structure 304, and surrounding the horizontally stacked nanowires 305. It should be understood that, although not shown, an oxidized portion of the subfin 302 and horizontally stacked nanowires 305 may be located between the protruding portion of the subfin 302 and the gate dielectric material layer 306 and between the horizontally stacked nanowires 305 and the gate dielectric material layer 306 and may be included together with the gate dielectric material layer 306 to form a gate dielectric structure.A conductive gate layer 308, such as a work function metal layer, is disposed over the gate dielectric material layer 306 and may be disposed directly on the gate dielectric material layer 306, as shown. A conductive gate fill material 310 is disposed over the conductive gate layer 308 and may be disposed directly on the conductive gate layer 308, as shown. A dielectric gate cap 312 is disposed on the conductive gate fill material 310. A dielectric gate plug 314 is laterally spaced from the subfin 302 and the plurality of horizontally stacked nanowires 305 and is disposed on the STI structure 304. The gate dielectric material layer 306 and the conductive gate layer 308 are disposed along sides of the dielectric gate plug 314.

[0050] With reference to Fig. 3B, an integrated circuit structure 350 includes a subfin 352 with a portion protruding above a shallow trench isolation (STI) structure 354. A plurality of horizontally stacked nanowires 355 are located above the subfin 352. A gate dielectric material layer 356, such as a high-k gate dielectric layer, is located above the protruding portion of the subfin 352, above the STI structure 354, and surrounding the horizontally stacked nanowires 355. It should be understood that, although not shown, an oxidized portion of the subfin 352 may be located between the protruding portion of the subfin 352 and the gate dielectric material layer 356 and between the horizontally stacked nanowires 355 and the gate dielectric material layer 356 and may be included together with the gate dielectric material layer 356 to form a gate dielectric structure.A conductive gate layer 358, such as a work function metal layer, is disposed over the gate dielectric material layer 356 and may be disposed directly on the gate dielectric material layer 356, as shown. A conductive gate fill material 360 is disposed over the conductive gate layer 358 and may be disposed directly on the conductive gate layer 358, as shown. A dielectric gate cap 362 is disposed on the conductive gate fill material 360. A dielectric gate plug 364 is laterally spaced from the subfin 352 and the plurality of horizontally stacked nanowires 355 and is disposed on, but not through, the STI structure 354. However, the gate dielectric material layer 356 and the conductive gate layer 358 are not located along sides of the dielectric gate plug 364.Instead, the conductive gate fill material 360 is in contact with the sides of the dielectric gate plug 364. As a result, a region between the dielectric gate plug 364 and the combination of the subfin 352 and the plurality of horizontally stacked nanowires 355 includes only one layer of the gate dielectric material layer 356 and only one layer of the conductive gate layer 358, alleviating space constraints in such a narrow region of the structure 350.

[0051] Again with reference to Fig. 3B, in one embodiment, the dielectric gate plug 364 is formed after forming the gate dielectric material layer 356, the conductive gate layer 358, and the conductive gate fill material 360. In one embodiment, the gate dielectric material layer 356 and the conductive gate layer 358 are not formed along sides of the dielectric gate plug 364. In one embodiment, the dielectric gate plug 364 has a top surface coplanar with a top surface of the dielectric gate cap 362, as shown. In another embodiment, not shown, no dielectric gate cap 362 is included, and the dielectric gate plug 364 has a top surface coplanar with a top surface of the conductive gate fill material 360, e.g., along a plane 380.

[0052] A dielectric gate plug can be fabricated on a gate endcap wall for a nanowire device. As a comparative example, Fig. 4A is a cross-sectional view of an integrated circuit structure including nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 4B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a cut metal gate dielectric plug according to an embodiment of the present disclosure.

[0053] With reference to Fig. 4A, an integrated circuit structure 400 includes a subfin 402 with a portion protruding above a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are located above the subfin 402. A gate endcap structure 403, such as a self-aligned gate endcap structure, is located on the STI structure 404 and is laterally spaced from the subfin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is located above the protruding portion of the subfin 402, above the STI structure 404, along sides of the gate endcap structure 403, and surrounds the horizontally stacked nanowires 405.It should be understood that, although not shown, an oxidized portion of the subfin 402 and horizontally stacked nanowires 405 may be located between the protruding portion of the subfin 402 and the gate dielectric material layer 406 and between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and may be included with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408, such as a work function metal layer, is located over the gate dielectric material layer 406 and may be located directly on the gate dielectric material layer 406, as shown. A conductive gate fill material 410 is located over the conductive gate layer 408 and may be located directly on the conductive gate layer 408, as shown. A dielectric gate cap 412 is located on the conductive gate fill material 410.A dielectric gate plug 414 is located on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are located along sides of the dielectric gate plug 414.

[0054] With reference to Fig. 4B, an integrated circuit structure 450 includes a subfin 452 with a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are located above the subfin 452. A gate endcap structure 453, such as a self-aligned gate endcap structure, is located on top of, but not through, the STI structure 454 and is laterally spaced from the subfin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is located above the protruding portion of the subfin 452, above the STI structure 454, along sides of the gate endcap structure 453, and surrounds the horizontally stacked nanowires 455.It should be understood that, although not shown, an oxidized portion of the subfin 452 may be located between the protruding portion of the subfin 452 and the gate dielectric material layer 456 and between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and may be included with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a work function metal layer, is located over the gate dielectric material layer 456 and may be located directly on the gate dielectric material layer 456, as shown. A conductive gate fill material 460 is located over the conductive gate layer 458 and may be located directly on the conductive gate layer 458, as shown. A dielectric gate cap 462 is located on the conductive gate fill material 460.A dielectric gate plug 464 is located on the gate end cap structure 453. However, the gate dielectric material layer 456 and the conductive gate layer 458 are not located along sides of the dielectric gate plug 464. Instead, the conductive gate fill material 460 is in contact with the sides of the dielectric gate plug 464.

[0055] Again with reference to Fig. 4B, in one embodiment, the dielectric gate plug 464 is formed after forming the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate fill material 460. In one embodiment, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along sides of the dielectric gate plug 464. In one embodiment, the dielectric gate plug 464 has a top surface coplanar with a top surface of the dielectric gate cap 462, as shown. In another embodiment, not shown, no dielectric gate cap 462 is included, and the dielectric gate plug 464 has a top surface coplanar with a top surface of the conductive gate fill material 460, e.g., along a plane 480.

[0056] In another aspect, selective or non-selective versions of a metal gate cut may be implemented. As an example, Fig. 5A-5C are top views of comparative integrated circuit structures according to an embodiment of the present disclosure. Fig. Figure 5A represents a conventional plug-first approach illustrating two gate plugs in adjacent gates. Fig. Figure 5B represents a selective metal gate cut approach illustrating two gate plugs in adjacent gates. Fig. Figure 5C represents a non-selective metal gate cutting approach illustrating a long gate plug across multiple gates.

[0057] With reference to Fig. 5A includes an integrated circuit structure 500 including gate lines between dielectric spacers 517 and conductive source or drain contacts 518. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508, such as a work function metal layer, and a conductive gate fill material 510. The dielectric gate plugs 514 may break up portions of a corresponding gate line. The dielectric gate plugs 514 are in contact with the conductive gate layer 508, but not with the gate dielectric material layer 506 or the conductive gate fill material 510. The top view of Fig. 5A can be used to describe the structures Fig. 2A, Fig. 3A or Fig. 4A. It should be understood that, although previously referred to as conductive source or drain contacts 518, a placeholder dielectric or dielectric plug may be present in place of the conductive source or drain contacts 518 at earlier stages of the process or at other locations in an integrated circuit structure.

[0058] With reference to Fig. 5B includes an integrated circuit structure 550 including gate lines between dielectric spacers 567 and conductive source or drain contacts 568. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558, such as a work function metal layer, and a conductive gate fill material 560. The dielectric gate plugs 564 may break up portions of a corresponding gate line. The dielectric gate plugs 564 are in contact with the conductive gate fill material 560. The top view of Fig. 5B can be used to describe the structures Fig. 2B, Fig. 3B or Fig. 4B. It should be understood that, although previously referred to as conductive source or drain contacts 568, a placeholder dielectric or dielectric plug may be present in place of the conductive source or drain contacts 568 at earlier stages of the process or at other locations in an integrated circuit structure.

[0059] With reference to Fig. 5C includes an integrated circuit structure 570 gate lines between dielectric spacers 587 and conductive source or drain contacts 588. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578, such as a work function metal layer, and a conductive gate fill material 580. A single dielectric gate plug 584 may break up portions of the gate lines and may extend through dielectric spacers 587 and even partially or completely into one or more of the conductive source or drain contacts 588. The dielectric gate plug 584 is in contact with the conductive gate fill material 580. The top view of Fig. 5C can be used to describe the structures Fig. 2B, Fig. 3B or Fig. 4B.

[0060] Again with reference to Fig. 5C, it should be understood that, although previously referred to as conductive source or drain contacts 588, a placeholder dielectric or dielectric plug may be present in place of the conductive source or drain contacts 588 at earlier stages of the process or at other locations in an integrated circuit structure. In one embodiment, an etch used to form an opening in which a single dielectric gate plug 584 is ultimately formed is referred to as a non-selective etch. If conductive source or drain contacts 588 have already been formed, the non-selective etch may etch into the conductive material of the conductive source or drain contacts 588.In other embodiments, if a placeholder dielectric or a dielectric plug is present instead of the conductive source or drain contacts 588, the non-selective etch may etch into the placeholder dielectric or a dielectric plug. In both cases, the non-selective etch may etch through and possibly separate an epitaxial semiconductor material of source or drain regions formed below the location of the conductive source or drain contacts 588. If conductive source or drain contacts 588 have already been formed, the epitaxial semiconductor material of the source or drain regions may include silicided portions.

[0061] Fig. 6A-6C illustrate cross-sectional views of comparative integrated circuit structures according to an embodiment of the present disclosure. Fig. 6A represents a traditional “plug-first” approach. Fig. Figure 6B represents a selective metal gate cutting approach. Fig. Figure 6C represents a non-selective metal gate cutting approach.

[0062] With reference to Fig. 6A, an integrated circuit structure 600 includes a dielectric gate plug 614 between dielectric spacers 617 and conductive source or drain contacts 618. The cross-sectional view of Fig. 6A may be an orthogonal view corresponding to the structures of Fig. 2A, Fig. 3A, Fig. 4A or Fig. 5A.

[0063] With reference to Fig. 6B, an integrated circuit structure 650 includes a dielectric gate plug 664 between dielectric spacers 667 and conductive source or drain contacts 668. The cross-sectional view of Fig. 6B may be an orthogonal view corresponding to the structures of Fig. 2B, Fig. 3B, Fig. 4B or Fig. 5B corresponds.

[0064] With reference to Fig. 6C, an integrated circuit structure 670 includes a single dielectric gate plug 684 between conductive source or drain contacts 688. The dashed box 690 shows where a corresponding discrete gate plug, such as gate plug 664, in the case of Fig. 6B. Dashed boxes 692 show where non-recessed source or drain contacts 668 are located in the case of Fig. 6B. The areas between the dashed box 690 and the dashed boxes 692 show where dielectric spacers 667 in the case of Fig. 6B. The cross-sectional view from Fig. 6C may be an orthogonal view corresponding to the structures of Fig. 2B, Fig. 3B, Fig. 4B or Fig. 5C.

[0065] In one embodiment, a metal work function may be: (a) a same metal system in NMOS and PMOS, (b) a different metal system between NMOS and PMOS, and / or (c) single material or multi-layer metals (e.g., W, TiN, Ti x Al y C z , TaN, Mo, MoN). In one embodiment, a metal cutting etch chemistry includes chlorine-containing or fluorine-containing etchants, with possible additional carbon- or silicon-containing components providing passivation.

[0066] It is understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons with different widths, thicknesses, and / or materials, including, but not limited to, Si and SiGe. For example, Group III-V materials may be used.

[0067] It should be understood that, in a particular embodiment, nanowires or nanoribbons, or intervening sacrificial layers, may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material consisting of a very substantial amount of, if not all, silicon. However, it should be understood that virtually 100% pure Si may be difficult to form and therefore might include a tiny percentage of carbon, germanium, or tin. Such impurities may be included as an unavoidable impurity or component during the deposition of Si, or may "contaminate" the Si upon diffusion during post-deposition processing. Therefore, embodiments described herein relating to a silicon layer may include a silicon layer containing a relatively small amount, e.g., an "impurity level," of non-Si atoms or species, such as Ge, C, or Sn.It is understood that a silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus or arsenic.

[0068] It is understood that in a particular embodiment, nanowires or nanoribbons or intervening sacrificial layers may be composed of silicon germanium. As used throughout, a silicon germaninum layer may be used to describe a silicon germaninum material consisting of substantial portions of both silicon and germanium, such as at least 5% of each. In some embodiments, the amount of germanium is greater than the amount of silicon. In specific embodiments, a silicon germaninum layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60). In other embodiments, the amount of silicon is greater than the amount of germanium. In specific embodiments, a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30). It should be understood that virtually 100% pure silicon germanium (commonly referred to as SiGe) can be difficult to form and therefore might include a tiny percentage of carbon or tin. Such impurities may be included as an unavoidable impurity or component during the deposition of SiGe, or may "contaminate" the SiGe upon diffusion during post-deposition processing. Therefore, embodiments described herein relating to a silicon germanium layer may include a silicon germanium layer containing a relatively small amount, e.g., an "impurity level," of non-Ge and non-Si atoms or species, such as carbon or tin. It should be understood that a silicon germanium layer as described herein may be undoped or doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0069] Described below are various devices and processing schemes that may be used to fabricate a device that can be integrated with a slice metal gate. It should be understood that the example embodiments may not necessarily require all of the described features or may include more features than described. For example, nanowire exposure processing may be performed through a replacement gate trench. Examples of such exposure processes are described below. Furthermore, in yet another aspect, backend (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein may be implemented to enable integration of front-side and back-side interconnects for nanowire transistors.Embodiments described herein may provide an approach to achieving a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0070] One or more embodiments described herein relate to dual epitaxial (EPI) interconnects for nanowire or nanoribbon transistors using a partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors that are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. A deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0071] As an exemplary process flow for fabricating another gate-all-around device of a gate-all-around integrated circuit structure, Fig. 7A-7J are cross-sectional views of various operations in a method of fabricating a gate-all-around structure of an integrated circuit according to an embodiment of the present disclosure.

[0072] With reference to Fig. 7A includes a method of fabricating an integrated circuit structure. Forming a starting stack including alternating sacrificial layers 704 and nanowires 706 above a fin 702, such as a silicon fin. The nanowires 706 may be referred to as a vertical array of nanowires. A protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706, as shown. A relaxed buffer layer 752 and a defect modification layer 750 may be formed below the alternating sacrificial layers 704 and nanowires 706, as also shown.

[0073] With reference to Fig. 7B, a gate stack 710 is formed over the vertical array of horizontal nanowires 706. Portions of the vertical array of horizontal nanowires 706 are then exposed by removing portions of the sacrificial layers 704 to provide recessed sacrificial layers 704' and cavities 712, as shown in Fig. 7C is shown.

[0074] It is understood that the structure consists of Fig. 7C can be fully fabricated without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), a fabrication process in one embodiment involves using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial bumps, which may be vertically discrete source or drain structures.

[0075] With reference to Fig. 7D, upper gate spacers 714 are formed on sidewalls of the gate structure 710. Cavity spacers 716 are formed in the cavities 712 below the upper gate spacers 714. A deep trench contact etch is then optionally performed to form trenches 718 and recessed nanowires 706'. A patterned relaxed buffer layer 752' and a patterned defect modification layer 750' may also be present, as shown.

[0076] A sacrificial material 720 is then formed in the trenches 718, as in Fig. 7E. In other process schemes, an isolated trench bottom or silicon trench bottom may be used.

[0077] With reference to Fig. 7F, a first epitaxial source or drain structure (e.g., left features 722) is formed at a first end of the vertical array of horizontal nanowires 706'. A second epitaxial source or drain structure (e.g., right features 722) is formed at a second end of the vertical array of horizontal nanowires 706'. In one embodiment, the epitaxial source or drain structures 722, as shown, are vertically discrete source or drain structures and may be referred to as epitaxial bumps.

[0078] An interlayer dielectric (ILD) material 724 is then formed on the sides of the gate electrode 710 and adjacent to the source or drain structures 722, as shown in Fig. 7G. With reference to Fig. 7H, a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. The ILD material 724 is then removed, as in Fig. 7I. The sacrificial material 720 is then removed from one of the source-drain locations (e.g., on the right side) to form the trench 732, but is not removed from the other of the source-drain locations to form the trench 730.

[0079] With reference to Fig. 7J, a first conductive contact structure 734 is formed that is coupled to the first epitaxial source or drain structure (e.g., features 722 on the left side). A second conductive contact structure 736 is formed that is coupled to the second epitaxial source or drain structure (e.g., features 722 on the right side). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In one embodiment, although described in Fig. 7J is not shown, further forming an exposed surface of the second conductive contact structure 736 on a bottom surface of the fin 702. Conductive contacts may include a contact resistance reduction layer and a primary contact electrode layer, examples of which may include Ti, Ni, Co (for the former and W, Ru, Co for the latter).

[0080] In one embodiment, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734, as shown. In one such embodiment, the first conductive contact structure 734 is not located along the fin 702, as shown. In another such embodiment, not shown, the first conductive contact structure 734 is partially located along the fin 702.

[0081] In one embodiment, the second conductive contact structure 736 is located along an entirety of the fin 702. In one embodiment, although not shown, in the event that the bottom surface of the fin 702 is exposed by a backside substrate removal process, the second conductive contact structure 736 comprises an exposed surface at a bottom surface of the fin 702.

[0082] In one embodiment, the structure may be Fig. 7J or associated structures from Fig. 7A-7J using a staggered gate cut approach, such as previously described.

[0083] In another aspect, to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, integrated circuit structures described herein may be fabricated using a backside exposure of frontside structures manufacturing approach. In some embodiments, exposing the backside of a transistor or other device structure includes wafer-level backside processing. Unlike conventional TSV-type technology, exposing the backside of a transistor as described herein may be performed at the density of device cells and even within subregions of a device.Furthermore, such backside exposure of a transistor can be performed to remove substantially the entire donor substrate on which a device layer was deposited during frontside device processing. Therefore, a micrometer-deep TSV becomes unnecessary, with the thickness of a semiconductor in the device cells following backside exposure of a transistor potentially being only several tens or hundreds of nanometers.

[0084] The exposure techniques described here can enable a paradigm shift from bottom-up device fabrication to center-out fabrication, where the center is any layer inserted during front-side fabrication, exposed from the backside, and reinserted during backside fabrication. Processing both a front side and an exposed backside of a device structure can address many of the challenges associated with fabricating 3D ICs when primarily relying on front-side processing.

[0085] For example, one approach for exposing the backside of a transistor may be used to remove at least a portion of a support layer and an intermediate layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer may be used. For example, if the support layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor may be used. Likewise, any wet etchant or plasma etching process known to be suitable for thinning the Group IV semiconductor may also be used.

[0086] In some embodiments, the above is preceded by cleaving the support layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process can be used to remove a substantial portion of the support layer as a bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, if a support layer has a thickness of 400-900 µm, 100-700 µm can be cleaved away by applying any blanket implantation known to promote wafer-level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.Following such a cleavage process, the thickness of the support layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, if the support layer is not fractured, the grinding, polishing, and / or etching process can be used to remove a greater thickness of the support layer.

[0087] Next, exposure of an intermediate layer is detected. Detection is used to identify a point at which the backside surface of the donor substrate has nearly approached the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorbance or emission of the backside surface of the donor substrate while performing polishing or etching. In some other embodiments, the endpoint criteria are associated with a change in the optical absorbance or emission of byproducts during polishing or etching of the donor substrate backside surface.For example, the absorbance or emission wavelengths associated with the byproducts of support layer etching may change as a function of the varying compositions of the support layer and the intervening layer. In other embodiments, the endpoint criteria are associated with a change in the mass of species in byproducts of polishing or etching the backside surface of the donor substrate. For example, the processing byproducts may be sampled by a quadrupole mass analyzer, and a change in species mass may be correlated with the varying compositions of the support layer and the intervening layer. In another embodiment, the endpoint criteria are associated with a change in friction between a backside surface of the donor substrate and a polishing surface in contact with the backside surface of the donor substrate.

[0088] Detection of the interlayer may be improved if the removal process is selective toward the carrier layer relative to the interlayer, since non-uniformity of the carrier removal process can be mitigated by an etch rate delta between the carrier layer and the interlayer. Detection may even be skipped if the grinding, polishing, and / or etching process removes the interlayer at a rate sufficiently below the rate at which the carrier layer is removed. If no endpoint criterion is employed, a grinding, polishing, and / or etching process of a predetermined fixed duration may stop on the interlayer material if the interlayer thickness is sufficient for etch selectivity. In some examples, the carrier etch rate:intermediate layer etch rate ratio is 3:1-10:1 or more.

[0089] In exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be uniformly removed, for example, by polishing. Alternatively, a thickness of the intervening layer may be removed using a masked or blanket etching process. The process may employ the same polishing or etching process as that used to thin the carrier, or may be a distinct process with distinct process parameters. For example, if the intervening layer provides an etch stop for the charge carrier removal process, the latter process may employ a different polishing or etching process that promotes removal of the intervening layer over removal of the device layer.When less than a few hundred nanometers of intervening layer thickness are to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than that used to remove the support layer. For example, a CMP process employed may employ a slurry that provides very high selectivity (e.g., 100:1–300:1 or more) between semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical insulation between adjacent device regions.

[0090] For embodiments where the device layer is exposed by completely removing the intervening layer, backside processing may begin on an exposed backside of the device layer or specific device regions therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through a thickness of the device layer located between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region.

[0091] In some embodiments where the support layer, the intermediate layer, or the device layer backside is recessed with a wet and / or plasma etch, such etch may be a patterned etch or a materially selective etch that introduces significant non-planarity or topography into the device layer backside surface. As described further below, the patterning may be within a device cell (i.e., "intracell patterning") or may be across device cells (i.e., "intercell patterning"). In some embodiments with patterned etching, at least a partial thickness of the intermediate layer is employed as a hard mask for backside device layer patterning. Therefore, a masked etch process may precede a correspondingly masked device layer etch.

[0092] The processing scheme described above may result in a donor-host substrate assembly including IC devices having a backside of an intermediate layer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer and / or frontside metallization exposed. Additional backside processing of any of these exposed regions may then be performed during downstream processing.

[0093] It is understood that the structures resulting from the preceding processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of a completed device, Fig. 8 is a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure.

[0094] With reference to Fig. 8, a semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a subfin region 805) within a trench isolation region 806. In one embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires 804A and 804B) above the subfin region 805, as represented by the dashed lines. In both cases, for ease of description of the non-planar integrated circuit structure 800, a non-planar active region 804 is hereinafter referred to as a protruding fin portion. In one embodiment, the subfin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840, as shown.

[0095] A gate line 808 is disposed over the protruding portions 804 of the non-planar active region (including, if applicable, surrounding nanowires 804A and 804B) as well as over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. A gate contact 814 and the overlying gate contact via 816 are also seen from this perspective, along with an overlying metal interconnect 860, all disposed in interlayer dielectric stacks or layers 870. Also from the perspective of Fig. As seen in Figure 8, in one embodiment, the gate contact 814 is disposed over the trench isolation region 806, but not over the non-planar active regions. In another embodiment, the gate contact 814 is located over the non-planar active regions.

[0096] In one embodiment, the semiconductor structure or device 800 is a non-planar device, such as, among others, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 808 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

[0097] As in Fig. 8, in one embodiment, there is an interface 880 between a protruding fin portion 804 and a subfin region 805. The interface 880 may be a transition region between a doped subfin region 805 and a lightly or undoped upper fin portion 804. In such an embodiment, each fin is approximately 10 nanometers wide or less, and subfin dopants are optionally supplied from an adjacent solid-state doping layer at the subfin location. In one particular such embodiment, each fin is less than 10 nanometers wide.

[0098] Although this is Fig. 8, it is understood that source or drain regions may be located from or adjacent to the protruding fin portions 804 on both sides of the gate line 808, i.e., into and out of the side. In one embodiment, the material of the protruding fin portions 804 at the source or drain location is removed and replaced with another semiconductor material, e.g., by epitaxial deposition, to form epitaxial source or drain structures. The source or drain regions may extend below the level of the dielectric layer of the trench isolation region 806, i.e., into the subfin region 805. According to one embodiment of the present disclosure, the more heavily doped subfin regions, i.e., the doped portions of the fins below the interface 880, hinder source-to-drain leakage through this portion of the bulk semiconductor fins.In one embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as previously described in connection with . Fig. 7J described.

[0099] With further reference to Fig. 8, in one embodiment, the fins 804 / 805 (and possibly the nanowires 804A and 804B) are made of a crystalline silicon germanium layer doped with a charge carrier such as, but not limited to, phosphorus, arsenic, boron, gallium, or a combination thereof.

[0100] In one embodiment, the trench isolation region 806 and trench isolation regions (trench isolation structures or trench isolation layers) described throughout may be comprised of a material suitable for ultimately electrically isolating or contributing to the isolation of portions of a permanent gate structure from an underlying bulk substrate or isolating active regions formed within an underlying bulk substrate, such as isolating active fin regions. For example, in one embodiment, the trench isolation region 806 may be comprised of a dielectric material such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0101] The gate line 808 may be comprised of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate, and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, alumina, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer 852 may include a layer of native oxide formed by the top few layers of the substrate fin 804.In one embodiment, the gate dielectric 852 consists of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure that includes a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate.

[0102] In one embodiment, the gate electrode layer 850 is comprised of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode layer 850 is comprised of a non-work function adjusting fill material formed above a work function adjusting metal layer. The gate electrode layer 850 may be comprised of a p-type work function metal or an n-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.In some implementations, the gate electrode layer 850 may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, e.g., ruthenium oxide. A p-type metal layer will enable the formation of a PMOS gate electrode with a work function ranging between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.An n-type metal layer will enable the formation of an NMOS gate electrode with a work function ranging between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar non-U-shaped structures.For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0103] Spacers associated with the gate electrode stacks may be made of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of a dielectric material such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0104] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In one embodiment, one or more of the contacts or vias may be made of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (such as, for example, a silicide material).

[0105] In one embodiment (although not shown), a contact structure is formed that is substantially perfectly aligned with an existing gate structure 808 while eliminating the use of a lithographic step with an extremely tight coverage accuracy budget. In one embodiment, the contact pattern is a vertically symmetric contact pattern or an asymmetric contact pattern, such as in connection with Fig. 7J. In other embodiments, all contacts are front-connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of an intrinsically highly selective wet etch (e.g., versus conventionally implemented dry or plasma etching) to create contact openings. In one embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact plug lithography process. In one such embodiment, the approach enables the elimination of the need for an otherwise critical lithography process to create contact patterning, as used in conventional approaches. In one embodiment, a trench contact grid is not separately patterned, but is instead formed between poly (gate) lines.For example, in such an embodiment, a trench contact grid is formed subsequent to gate grid patterning but prior to gate grid cutting.

[0106] In one embodiment, providing structure 800 involves fabricating gate stack structure 808 through a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process rather than being carried over from prior processing. In one embodiment, dummy gates are removed through a dry etch or wet etch process. In one embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a dry etch process including the use of SF6.In another embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are made of silicon nitride and are removed using a wet etch including aqueous phosphoric acid.

[0107] With further reference to Fig. 8, the arrangement of a semiconductor structure or device 800 places the gate contact over isolation regions. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, a semiconductor device includes contact structures that contact portions of a gate electrode formed over an active region, e.g., over a fin 805, and in a same layer as a trench contact via.

[0108] In one embodiment, the structure may be Fig. 8 using a staggered gate cut approach, such as previously described.

[0109] It should be understood that not all aspects of the processes described herein need be implemented to fall within the spirit and scope of embodiments of the present disclosure. Furthermore, the processes described herein may be used to form one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Furthermore, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, a dual-gate independent access device, or a FIN-FET.One or more embodiments may be particularly useful for fabricating semiconductor devices with a sub-10 nanometer (10 nm) technology node.

[0110] In one embodiment, the interlayer dielectric (ILD) material, as used throughout this specification, consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0111] In one embodiment, as used throughout this specification, metal lines or an interconnect line material (and via material) consist of one or more metal structures or other conductive structures. A common example is the use of copper lines and structures, which may or may not include barrier layers between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including Ta and / or TaN and / or Ti and / or TiN), stacks of different metals or alloys, etc. Accordingly, the interconnect lines may be a single layer of material or may be formed from several layers, including conductive liner layers and fill layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form interconnect lines. In one embodiment, the interconnect lines are made of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. The interconnect lines are sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0112] In one embodiment, hard mask materials, cap layers, or plugs, as also used throughout this specification, are made of dielectric materials different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials may be used in different regions to provide different growth or etch selectivity to each other and to underlying dielectric and metal layers. In some embodiments, a hard mask layer, cap, or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials.Alternatively, depending on the particular implementation, other hard mask, cap, or plug layers known in the art may be used. The hard mask, cap, or plug layers may be formed by CVD, PVD, or other deposition techniques.

[0113] In one embodiment, as used throughout this description, lithographic processes are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular such embodiment, the topographic mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0114] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures. Certain embodiments may relate to integration of multi-width (multi-WSI) nanowires and nanoribbons in a SAGE architecture and separated by a SAGE wall. In one embodiment, nanowires / nanoribbons with multiple WSI are integrated in a SAGE architecture portion of a front-end process flow. Such a process flow may involve integration of nanowires and nanoribbons of different WSI to provide robust functionality of next-generation low-power and high-performance transistors. Associated epitaxial source or drain regions may be embedded (e.g., portions of nanowires are removed and then source-or-drain (S / D) growth is performed).

[0115] To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture may include enabling higher layout density and, in particular, scaling diffusion-to-diffusion spacing. To provide an illustrative comparison, Fig. 9 Cross-sectional views through nanowires and fins for a non-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0116] Referring to the left side (a) of Fig. 9, an integrated circuit structure 900 includes a substrate 902 having fins 904 protruding therefrom by an amount 906 above an isolation structure 908 laterally surrounding lower portions of the fins 904. Upper portions of the fins may include a relaxed buffer layer 922 and a defect modification layer 920, as shown. Corresponding nanowires 905 are located above the fins 904. A gate structure may be formed over the integrated circuit structure 900 to fabricate a device. However, discontinuities in such a gate structure may be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0117] In contrast, referring to the right-hand side (b) of Fig. 9, an integrated circuit structure 950 includes a substrate 952 having fins 954 protruding therefrom by an amount 956 above an isolation structure 958 laterally surrounding lower portions of the fins 954. Upper portions of the fins may include a relaxed buffer layer 972 and a defect modification layer 970, as shown. Respective nanowires 955 are located above the fins 954. Isolation SAGE walls 960 (which may include a hard mask thereon, as shown) are included within the isolation structure 952 and between adjacent fin 954 / nanowire 955 pairs. The distance between an isolation SAGE wall 960 and a nearest fin 954 / nanowire 955 pair defines the gate endcap spacing 962. A gate structure may be formed over the integrated circuit structure 900 between isolation SAGE walls to fabricate a device.Discontinuities in such a gate structure are imposed by the isolation SAGE walls. Because the isolation SAGE walls 960 are self-aligned, limitations of conventional approaches can be minimized to enable more aggressive diffusion-to-diffusion spacing. Furthermore, because gate structures include discontinuities at all locations, individual gate structure portions may be a layer connected by local interconnects formed over the isolation SAGE walls 960. In one embodiment, as illustrated, the SAGE walls 960 each include a bottom dielectric portion and a dielectric cap on the bottom dielectric portion. According to one embodiment of the present disclosure, a manufacturing process for structures formed with . Fig. 9, the use of a process scheme providing a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0118] In one embodiment, the structure of part (a) may be Fig. 9 using a staggered gate cut approach, such as previously described. In one embodiment, the structure of part (b) may be Fig. 9 using a staggered gate cut approach, such as previously described.

[0119] A self-aligned gate endcap (SAGE) processing scheme involves the formation of gate / trench contact endcaps that are self-aligned with fins without requiring additional length to account for mask misregistration. Accordingly, embodiments may be implemented to enable a reduction in transistor layout area. Embodiments described herein may include the fabrication of gate endcap isolation structures, which may also be referred to as gate wall isolation gate walls, or self-aligned gate endcap (SAGE) walls.

[0120] An example processing scheme for structures with SAGE walls separating adjacent devices is shown in Fig. 10 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with gate all-around devices according to an embodiment of the present disclosure.

[0121] With reference to part (a) of Fig. 10, a starting structure includes a nanowire patterning stack 1004 above a substrate 1002. A lithographic patterning stack 1006 is formed above the nanowire patterning stack 1004. The nanowire patterning stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxed buffer layer 1082 and a defect modification layer 1080, as shown. A protective mask 1014 is located between the nanowire patterning stack 1004 and the lithographic patterning stack 1006. In one embodiment, the lithographic patterning stack 1006 is a three-layer mask consisting of a topographic mask portion 1020, an anti-reflective coating (ARC) layer 1022, and a photoresist layer 1024.In one particular such embodiment, the topographical masking portion 1020 is a carbon hard mask (CHM) layer and the anti-reflective coating layer 1022 is a silicon ARC layer.

[0122] With reference to part (b) of Fig. 10, the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0123] With reference to part (c) of Fig. 10, the structure of part (b) comprises an isolation layer 1040 and a SAGE material 1042 formed in trenches 1030. The structure is then planarized to leave the patterned topographic masking layer 1020' as an exposed top layer.

[0124] With reference to part (d) of Fig. 10, the isolation layer 1040 is recessed below a top surface of the patterned substrate 1002, for example, to define a protruding fin portion and to provide a trench isolation structure 1041 below the SAGE walls 1042.

[0125] With reference to part (e) of Fig. 10, the sacrificial layers 1010 are removed at least in the channel region to expose the nanowires 1012A and 1012B. After the formation of the structure of part (e) of Fig. 10, gate stacks may be formed around nanowires 1012B or 1012A, over protruding fins of substrate 1002, and between SAGE walls 1042. In one embodiment, prior to forming the gate stacks, the remaining portion of the protective mask 1014 is removed. In another embodiment, the remaining portion of the protective mask 1014 is retained as an insulating fin hat as an artifact of the processing scheme.

[0126] Referring again to part (e) of Fig. 10, it is understood that a channel view is depicted with source or drain regions extending into and out of the side. In one embodiment, the channel region including nanowires 1012B has a width that is smaller than the channel region including nanowires 1012A. Accordingly, in one embodiment, an integrated circuit structure includes multi-width (multi-WSI) nanowires. Although the structures of 1012B and 1012A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires. It is also understood that reference to or depiction of a fin / nanowire pair throughout may refer to a structure including a fin and one or more overlying nanowires (e.g., in Fig. 10 two overlying nanowires are shown). According to one embodiment of the present disclosure, a manufacturing process for structures comprising Fig. 10, the use of a process scheme providing a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0127] In one embodiment, the structure of part (e) may be Fig. 10 using a staggered gate cut approach, such as previously described.

[0128] In one embodiment, as described herein, self-aligned gate end cap (SAGE) isolation structures may be comprised of a material or materials suitable for ultimately electrically isolating or contributing to the isolation of portions of permanent gate structures. Example materials or material combinations include a single-material structure, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other example materials or material combinations include a multilayer stack having a bottom portion comprised of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and a top portion comprised of a higher dielectric constant material, such as hafnium oxide.

[0129] To provide an exemplary integrated circuit structure with three vertically arranged nanowires, Fig. 11A is a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 11B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Fig. 11A along the a-a' axis. Fig. Figure 11C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Fig. 11A along the b-b' axis.

[0130] With reference to Fig. 11A, an integrated circuit structure 1100 includes one or more vertically stacked nanowires (set 1104) above a substrate 1102. In one embodiment, as shown, a relaxed buffer layer 1102C, a defect modification layer 1102B, and a bottom substrate portion 1102A are included in the substrate 1102, as shown. An optional fin below the bottommost nanowire and formed from the substrate 1102 is not shown to highlight the nanowire portion for illustrative purposes. Embodiments herein contemplate both single-wire devices and multi-wire devices. As an example, three nanowire-based devices with nanowires 1104A, 1104B, and 1104C are shown for illustrative purposes. For simplicity of description, nanowire 1104A is used as an example, with the description focusing on one of the nanowires.It is understood that where attributes of one nanowire are described, embodiments based on multiple nanowires may have the same or substantially the same attributes for each of the nanowires.

[0131] Each of the nanowires 1104 includes a channel region 1106 within the nanowire. The channel region 1106 has a length (L). Referring to Fig. 11C, the channel region also has a perimeter (Pc) orthogonal to the length (L). With reference to both Fig. 11A and 11C, a gate electrode stack 1108 surrounds the entire perimeter (Pc) of each of the channel regions 1106. The gate electrode stack 1108 includes a gate electrode along with a gate dielectric layer between the channel region 1106 and the gate electrode (not shown). In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 1108 without any intervening material, such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments with multiple nanowires, the channel regions 1106 of the nanowires 1104 are also discrete relative to each other.

[0132] With reference to both Fig. 11A and 11B, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are located on either side of the channel regions 1106 of the plurality of vertically stacked nanowires 1104. Furthermore, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel regions 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment, which is not shown, the pair of non-discrete source or drain regions 1110 / 1112 directly adjoins the channel regions 1106 vertically, such that epitaxial growth occurs on and between nanowire portions extending beyond the channel regions 1106, with nanowire ends shown within the source or drain structures. In another embodiment, as shown in Fig. As shown in Figure 11A, the pair of non-discrete source or drain regions 1110 / 1112 indirectly vertically adjoins the channel regions 1106 in that they are formed at the ends of the nanowires and not between the nanowires.

[0133] In one embodiment, as illustrated, the source or drain regions 1110 / 1112 are non-discrete in that there are no individual and discrete source or drain regions for each channel region 1106 of a nanowire 1104. Accordingly, in embodiments with multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions, as opposed to discrete ones for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single unified feature is used as a source or drain region for multiple (in this case, 3) nanowires 1104, and in particular, for more than one discrete channel region 1106.In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions 1106, each of the pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular with a lower tapered portion and an upper vertex portion, as shown in FIG. Fig. 11B. However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowires are relatively larger, but discrete, non-vertically joined epitaxial structures, such as nubs, which may be formed in conjunction with Fig. 7A-7J.

[0134] According to one embodiment of the present disclosure, and as shown in Fig. 11A and Fig. 11B, the integrated circuit structure 1100 further includes a pair of contacts 1114, wherein each contact 1114 is on one of the pair of non-discrete source or drain regions 1110 / 1112. In such an embodiment, in a vertical sense, each contact 1114 completely surrounds the respective non-discrete source or drain region 1110 / 1112. In another aspect, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 may not be accessible for contact with contacts 1114, and the contact 1114 accordingly only partially surrounds the non-discrete source or drain regions 1110 / 1112, as in Fig. 11B. In a contrasting embodiment (not shown), the entire perimeter of the non-discrete source or drain regions 1110 / 1112 along the a-a' axis is surrounded by the contacts 1114.

[0135] With further reference to Fig. 11A, in one embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As illustrated, outer portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112, thereby providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 beneath the pair of spacers 1116. As also illustrated, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend beneath the entirety of the pair of spacers 1116.

[0136] The substrate 1102 may be made of a material suitable for fabricating an integrated circuit structure. In one embodiment, the substrate 1102 includes a lower bulk substrate made of a single crystal of a material that may include, but is not limited to, silicon, germanium, silicon germanium, germanium-tin, silicon germanium-tin, or a Group III-V compound semiconductor material. An upper insulator layer made of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is located on the lower bulk substrate. Accordingly, the structure 1100 may be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, the structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form electrically insulating portions instead of the previously described upper insulator layer.In another alternative embodiment, structure 1100 is formed directly from a bulk substrate, and doping is used to form electrically isolated active regions, such as nanowires, thereon. In such an embodiment, the first nanowire (i.e., near the substrate) has the shape of an omega-FET-type structure.

[0137] In one embodiment, the nanowires 1104 may be sized as wires or ribbons, as described below, and may have square or rounded corners. In one embodiment, the nanowires 1104 are made of a material such as, but not limited to, silicon, germanium, or a combination thereof. In such an embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire 1104, a single-crystalline nanowire may be oriented in a global (100) orientation, e.g., with a <100> -plane in the z-direction. As described below, other orientations may also be considered. In one embodiment, the dimensions of the nanowires 1104 are in the nanoscale from a cross-sectional perspective. For example, in one particular embodiment, the smallest dimension of the nanowires 1104 is less than about 20 nanometers.In one embodiment, the nanowires 1104 are made of a material under mechanical stress, particularly in the channel regions 1106.

[0138] With reference to Fig. 11C, in one embodiment, each of the channel regions 1106 has a width (Wc) and a height (Hc), where the width (Wc) is approximately equal to the height (Hc). That is, in both cases, the channel regions 1106 are rectangular or, if with rounded corners, circular in cross-sectional profile. In another aspect, the width and height of the channel region need not be equal, as in the case of nanoribbons, as described throughout.

[0139] In one embodiment, as described herein, an integrated circuit structure includes non-planar devices, such as, but not limited to, a FinFET or a tri-gate device, with one or more corresponding overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body having one or more discrete nanowire channel portions overlying the three-dimensional body. In such an embodiment, the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body and further surround each of the one or more discrete nanowire channel portions.

[0140] In one embodiment, the structure may be Fig. 11A-11C using a staggered gate cut approach, such as previously described.

[0141] In one embodiment, as described herein, an underlying substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In one embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, gallium, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate consists of an epitaxial layer grown on a distinct crystalline substrate, e.g., an epitaxial silicon layer grown on a boron-doped monocrystalline bulk silicon substrate. A bulk substrate may alternatively be composed of a Group III-V material.In one embodiment, a bulk substrate is comprised of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is comprised of a Group III-V material, and the charge carrier dopant impurity atoms are those such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0142] Embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory may be fabricated. Furthermore, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), mobile phones, personal electronic devices, etc. The integrated circuits may be coupled to a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc.Each of the processor, memory, and chipset may potentially be manufactured using the approaches disclosed herein.

[0143] Fig. 12 illustrates a computing device 1200 according to an implementation of an embodiment of the present disclosure. Computing device 1200 houses a circuit board 1202. Circuit board 1202 may include a number of components, including, but not limited to, a processor 1204 and at least one communication chip 1206. Processor 1204 is physically and electrically coupled to circuit board 1202. In some implementations, at least one communication chip 1206 is also physically and electrically coupled to circuit board 1202. In further implementations, communication chip 1206 is part of processor 1204.

[0144] Depending on its applications, computing device 1200 may include other components that may not be physically and electrically coupled to circuit board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so on).

[0145] The communication chip 1206 enables wireless communications for transferring data to and from the computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid-state medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not. The communication chip 1206 can implement any of a number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 1200 may include multiple communication chips 1206. For example, a first communication chip 1206 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 1206 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0146] The processor 1204 of the computing device 1200 includes an integrated circuit die encapsulated within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures, such as gate-all-around integrated circuit structures with interconnect elements for a uniform grid metal gate and trench contact interface, constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0147] The communication chip 1206 also includes an integrated circuit die encapsulated within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures, such as gate-all-around integrated circuit structures with interconnect elements for a uniform grid metal gate and trench contact cut, constructed according to implementations of embodiments of the present disclosure.

[0148] In further implementations, another component housed within the computing device 1200 may include an integrated circuit die including one or more structures, such as gate-all-around integrated circuit structures with interconnect elements for a uniform grid metal gate and trench contact cut, constructed in accordance with implementations of embodiments of the present disclosure.

[0149] In various implementations, computing device 1200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1200 may be any other electronic device that processes data.

[0150] Fig.13 illustrates an interposer 1300 incorporating one or more embodiments of the present disclosure. The interposer 1300 is an intermediate substrate used as a bridge from a first substrate 1302 to a second substrate 1304. The first substrate 1302 may be, for example, an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1300 is to spread an interconnect to a wider pitch or to reroute an interconnect to another interconnect. For example, an interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to the second substrate 1304.In some embodiments, the first and second substrates 1302 / 1304 are mounted on opposite sides of the interposer 1300. In other embodiments, the first and second substrates 1302 / 1304 are mounted on the same side of the interposer 1300. And in further embodiments, three or more substrates are connected together via the interposer 1300.

[0151] The interposer 1300 may be formed from an epoxy resin, a glass-fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1300 may be formed from alternating rigid or flexible materials, which may include the same materials previously described for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.

[0152] The interposer 1300 may include metal interconnects 1308 and vias 1310, including, among others, through-silicon vias (TSVs) 1312. The interposer 1300 may further include embedded devices 1314, which may include both passive and active devices. Such devices include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and ESD (electrostatic discharge) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1300. According to embodiments of the disclosure, devices or processes disclosed herein may be used in the manufacture of the interposer 1300 or in the manufacture of components included in the interposer 1300.

[0153] Accordingly, embodiments of the present disclosure include integrated circuit structures having interconnects for a uniform grid metal gate and trench contact cut and methods of fabricating integrated circuit structures having interconnects for a uniform grid metal gate and trench contact cut.

[0154] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of the disclosure and examples thereof are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as one skilled in the art will recognize.

[0155] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the disclosure is determined entirely by the following claims, which are to be interpreted in accordance with established doctrines for claim interpretation.

[0156] Embodiment 1: An integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is located above the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The first dielectric cut plug has a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode.A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and arranged parallel to the first dielectric cut plug structure. The second dielectric cut plug has a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact. A first conductive interconnection element is located in the recess of the first dielectric cut plug structure and in contact with the gate electrode side. And a second conductive interconnection element is located in the recess of the second dielectric cut plug structure and in contact with the conductive trench contact side.

[0157] Embodiment 2: The integrated circuit structure of Embodiment 1, further including a second conductive trench contact in contact with the second conductive interconnect element, wherein the second conductive interconnect element couples the second conductive trench contact to the conductive trench contact.

[0158] Embodiment 3: The integrated circuit structure of Embodiment 1 or 2, further including a second gate electrode in contact with the first conductive interconnect element, wherein the first conductive interconnect element couples the second gate electrode to the gate electrode.

[0159] Embodiment 4: The integrated circuit structure of Embodiment 1, further including a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact.

[0160] Embodiment 5: The integrated circuit structure of Embodiment 4, further including a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode.

[0161] Embodiment 6: An integrated circuit structure includes a fin. A gate electrode is located above the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The first dielectric cut plug has a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and arranged parallel to the first dielectric cut plug structure.The second dielectric cut plug has a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact. A first conductive interconnect element is located in the recess of the first dielectric cut plug structure and is in contact with the gate electrode side. A second conductive interconnect element is located in the recess of the second dielectric cut plug structure and is in contact with the conductive trench contact side.

[0162] Embodiment 7: The integrated circuit structure of Embodiment 6, further including a second conductive trench contact in contact with the second conductive interconnect element, wherein the second conductive interconnect element couples the second conductive trench contact to the conductive trench contact.

[0163] Embodiment 8: The integrated circuit structure of Embodiment 6 or 7, further including a second gate electrode in contact with the first conductive interconnect element, wherein the first conductive interconnect element couples the second gate electrode to the gate electrode.

[0164] Embodiment 9: The integrated circuit structure of Embodiment 6, further including a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact.

[0165] Embodiment 10: The integrated circuit structure of Embodiment 9, further including a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode.

[0166] Embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure including a vertical stack of horizontal nanowires, or a fin. A gate electrode is located over the vertical stack of horizontal nanowires, or the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The first dielectric cut plug has a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode.A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and arranged parallel to the first dielectric cut plug structure. The second dielectric cut plug has a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact. A first conductive interconnection element is located in the recess of the first dielectric cut plug structure and in contact with the gate electrode side. And a second conductive interconnection element is located in the recess of the second dielectric cut plug structure and in contact with the conductive trench contact side.

[0167] Embodiment 12: The computing device of Embodiment 11, including the vertical stack of horizontal nanowires.

[0168] Embodiment 13: The computing device of Embodiment 11, which includes the fin.

[0169] Embodiment 14: The computing device of embodiment 11, 12 or 13, further including a memory coupled to the circuit board.

[0170] Embodiment 15: The computing device of embodiment 11, 12, 13 or 14, further including a communication chip coupled to the circuit board.

[0171] Embodiment 16: The computing device of Embodiment 11, 12, 13, 14, or 15, further including a battery coupled to the circuit board.

[0172] Embodiment 17: The computing device of Embodiment 11, 12, 13, 14, 15 or 16, further including a camera coupled to the circuit board.

[0173] Embodiment 18: The computing device of Embodiment 11, 12, 13, 14, 15, 16, or 17, further including a display coupled to the circuit board.

[0174] Embodiment 19: The computing device of Embodiment 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is an encapsulated integrated circuit die.

[0175] Embodiment 20: The computing device of embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

[1] Integrated circuit structure comprising: a vertical stack of horizontal nanowires; a gate electrode above the vertical stack of horizontal nanowires; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the first dielectric cut plug having a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode; a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and parallel to the first dielectric cut plug structure, and the second dielectric cut plug having a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact; a first conductive interconnection element in the recess of the first dielectric cut plug structure, the first conductive interconnection element being in contact with the side of the gate electrode; and a second conductive interconnection element in the recess of the second dielectric cut plug structure, the second conductive interconnection element being in contact with the side of the conductive trench contact. [2] The integrated circuit structure of claim 1, further comprising a second conductive trench contact in contact with the second conductive interconnect element, the second conductive interconnect element coupling the second conductive trench contact to the conductive trench contact. [3] The integrated circuit structure of claim 1 or 2, further comprising a second gate electrode in contact with the first conductive interconnect element, the first conductive interconnect element coupling the second gate electrode to the gate electrode. [4] The integrated circuit structure of claim 1, further comprising a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact. [5] The integrated circuit structure of claim 4, further comprising a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode. [6] Integrated circuit structure comprising: a fin; a gate electrode above the fin; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the first dielectric cut plug having a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode; a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and parallel to the first dielectric cut plug structure, and the second dielectric cut plug having a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact; a first conductive interconnection element in the recess of the first dielectric cut plug structure, the first conductive interconnection element being in contact with the side of the gate electrode; and a second conductive interconnection element in the recess of the second dielectric cut plug structure, the second conductive interconnection element being in contact with the side of the conductive trench contact. [7] The integrated circuit structure of claim 6, further comprising a second conductive trench contact in contact with the second conductive interconnect element, the second conductive interconnect element coupling the second conductive trench contact to the conductive trench contact. [8] The integrated circuit structure of claim 6 or 7, further comprising a second gate electrode in contact with the first conductive interconnect element, the first conductive interconnect element coupling the second gate electrode to the gate electrode. [9] The integrated circuit structure of claim 6, further comprising a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact. [10] The integrated circuit structure of claim 9, further comprising a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode. [11] Computing device comprising: a circuit board; and a component coupled to the board, the component including an integrated circuit structure comprising: a vertical stack of horizontal nanowires or a fin; a gate electrode above the vertical stack of horizontal nanowires or the fin; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the first dielectric cut plug having a recess laterally adjacent to the gate electrode and exposing one side of the gate electrode; a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure being laterally spaced from and parallel to the first dielectric cut plug structure, and the second dielectric cut plug having a recess laterally adjacent to the conductive trench contact and exposing one side of the conductive trench contact; a first conductive interconnection element in the recess of the first dielectric cut plug structure, the first conductive interconnection element being in contact with the side of the gate electrode; and a second conductive interconnection element in the recess of the second dielectric cut plug structure, the second conductive interconnection element being in contact with the side of the conductive trench contact. [12] The computing device of claim 11, comprising the vertical stack of horizontal nanowires. [13] A computing device according to claim 11, comprising the fin. [14] Computing device according to one of claims 11 to 13, further comprising: a memory that is coupled to the board. [15] Computing device according to one of claims 11 to 14, further comprising: a communication chip that is coupled to the circuit board. [16] Computing device according to one of claims 11 to 15, further comprising: a battery that is coupled to the circuit board. [17] Computing device according to one of claims 11 to 16, further comprising: a camera that is coupled to the board. [18] Computing device according to one of claims 11 to 17, further comprising: a display coupled to the circuit board. [19] A computing device according to any one of claims 11 to 18, wherein the component is an encapsulated integrated circuit die. [20] The computing device of any of claims 11 to 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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