STORAGE DEVICE AND METHOD FOR MANUFACTURING THE STORAGE DEVICE

Abstract

The present disclosure relates to a method of fabricating a memory device. A method of fabricating a memory device includes forming a stacked structure with first material layers stacked alternately with second material layers, forming a channel layer with amorphous silicon in an opening extending through the stacked structure, converting a first portion of the channel layer to single-crystal silicon, doping the first portion of the channel layer with a conductive material, doping a second portion, different from the first portion of the channel layer, with the conductive material, and converting the second portion of the channel layer to polycrystalline silicon using the conductive material.

Description

BACKGROUND1. Technical FieldVarious embodiments of the present disclosure generally relate to a memory device and a manufacturing method of the memory device, and more particularly to a memory device having a three-dimensional memory block and a method of manufacturing the memory device.2. Prior ArtA storage device may include a nonvolatile storage device in which stored data is maintained even when power supply is interrupted. The nonvolatile memory device may be classified as a two-dimensional structure or a three-dimensional structure according to a structure in which the memory cells are arranged. Memory cells of a nonvolatile memory device having a two-dimensional structure may be arranged in a single layer on a substrate, and memory cells of a nonvolatile memory device having a three-dimensional structure may be stacked in a vertical direction on the substrate. Since the integration degree of the nonvolatile memory device having the three-dimensional structure is higher than the integration degree of the nonvolatile memory device having the two-dimensional structure, electronic devices using nonvolatile memory devices having a three-dimensional structure are becoming increasingly popular recently.SUMMARYAccording to an embodiment, a method of manufacturing a memory device may include forming a stack structure having first material layers alternately stacked with second material layers, forming a channel layer having amorphous silicon in an opening extending through the stack structure, converting a first portion of the channel layer to single crystal silicon, doping the first portion of the channel layer with a conductive material, doping a second portion of the channel layer different from the first portion of the channel layer with the conductive material, and converting the second portion of the channel layer to polycrystalline silicon using the conductive material.According to an embodiment, a memory device may include a stack structure and a channel layer formed in an opening extending through the stack structure, the channel layer including a first portion including single crystal silicon and a second portion including polycrystalline silicon, the first portion being adjacent to the second portion.According to an embodiment, a method may include forming an opening extending through a stack structure; forming a channel layer including amorphous silicon in the opening; converting a first portion of the channel layer to single crystal silicon; doping the first portion of the channel layer and a second portion of the channel layer with a conductive material, the second portion adjoining the first portion; and converting the second portion of the channel layer to polycrystalline silicon using the conductive material.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure; FIG. 2 is a diagram illustrating memory blocks of a memory device according to an embodiment of the present disclosure; FIG. 3 is a plan view illustrating a layout of a storage device according to an embodiment of the present disclosure; FIG. 4 is a cross-sectional view of a memory device according to an embodiment of the present disclosure; FIGS. 5A to 5I are diagrams illustrating cross-sectional views of a memory device formed using a method of manufacturing the memory device according to an embodiment of the present disclosure; FIG. 6 is a diagram illustrating an embodiment of a memory card system including a storage device according to an embodiment of the present disclosure; and FIG. 7 is a diagram illustrating an embodiment of a solid state drive (SSD) system including a plurality of storage devices according to an embodiment of the present disclosure.DETAILED DESCRIPTIONThe specific structural or functional descriptions described in the present disclosure are examples that describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be realized in various forms and should not be construed as being limited to the specific embodiments set forth in the present disclosure.Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to sufficiently describe details for a person skilled in the art to easily realize the technical forms of the present disclosure. The cross-hatchings in the figures represent corresponding or similar areas between the figures and do not indicate the materials for these areas.Terms such as "under", "over", "above", "below", "left", "right", "down", "down" and other terms implying a spatial relationship are only for the purpose of description or reference to a drawing and are not intended to be limiting.Various embodiments relate to a memory device capable of increasing a current flowing in memory cells and a method of manufacturing the memory device.FIG. 1 is a diagram illustrating a storage device 100 according to an embodiment of the present disclosure.Referring to FIG. 1, the memory device 100 includes a memory cell array 110, a peripheral circuit 170, and a control circuit 180.The memory cell array 110 includes memory blocks BLK 1 to BLKi, where i is a positive integer. Each of the first memory block BLK 1 to the i-th memory block BLKi includes memory cells capable of storing data. Drain select lines DSL, word lines WL, source select lines SSL, and a source line SL are coupled to each of the memory blocks BLK 1 to BLKi, and bit lines BL are commonly coupled to the memory blocks BLK 1 to BLKi.The memory blocks BLK 1 to BLKi have a three-dimensional structure. Memory blocks having a three-dimensional structure may include memory cells stacked on a substrate in a vertical direction, for example.A single memory cell may store one-bit data, two-bit data, three-bit data, four-bit data, five-bit data, and so forth according to a program method. For example, a method in which one-bit data is stored in a memory cell is referred to as a single-level cell (SLC) method, and a method in which two-bit data is stored in a memory cell is referred to as a multi-level cell (MLC) method. A method in which three-bit data is stored in a memory cell is referred to as a triple-level cell method (TLC), and a method in which four-bit data is stored in a memory cell is referred to as a quad-level cell method (QLC).The peripheral circuit 170 is configured to perform a program operation storing data in the memory cell array 110, a read operation outputting data stored in the memory cell array 110, and an erase operation erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 includes a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.The voltage generator 120 generates various operating voltages Vop used during a program operation, a read operation, or an erase operation in response to an operation code OPCD. For example, the voltage generator 120 may be configured to generate program voltages, turn-on voltages, turn-off voltages, negative voltages, precharge voltages, test voltages, read voltages, pass voltages, or erase voltages in response to the operation code OPCD. The operating voltages Vop generated by the voltage generator 120 are applied to the drain selection lines DSL, the word lines WL, the source selection lines SSL, and the source line of a selected memory block by the row decoder 130.The program voltages are applied to a selected word line among the word lines WL during a program operation, and are used to increase threshold voltages of memory cells coupled to the selected word line. The turn-on voltages are applied to the drain selection lines DSL and the source selection lines SSL, and are used to turn on drain selection transistors and source selection transistors. The turn-off voltages are applied to the drain selection lines DSL and the source selection lines SSL, and are used to turn off the drain selection transistors and the source selection transistors. For example, the cut-off voltages may be set to 0V. The precharge voltages may be higher than 0V and may be applied to the bit lines BL during a read operation. The test voltages are used during a test operation to determine whether threshold voltages of selected memory cells are increased to a target level. The test voltages may be set to different levels according to the target level and may be applied to the selected word line.The read voltages are applied to the selected word line during a read operation of the selected memory cells. For example, the read voltages may be set to different levels according to a program method of the selected memory cells. The pass voltages are applied to unselected word lines among the word lines WL during a program or read operation, and are used to turn on memory cells coupled to the unselected word lines. The erase voltages are used during an erase operation for erasing the memory cells included in the selected memory block, and are applied to the source line SL.The row decoder 130 is configured to transfer the operating voltages Vop to the drain select lines DSL, the word lines WL, the source select lines SSL, and the source line SL, which are coupled to the selected memory block according to a row address RADD. For example, the row decoder 130 is coupled to the voltage generator 120 via global lines and is coupled to the memory blocks BLK 1 to BLKi via the drain select lines DSL, the word lines WL, the source select lines SSL, and the source line.The page buffer group 140 includes a plurality (i) of page buffers (not shown) coupled to the memory blocks BLK 1 to BLKi, respectively. The page buffers (not shown) are coupled to the memory blocks BLK1 to BLKi via bit lines BL. During a read operation, the page buffers (not shown) sample a current or voltage of the bit lines BL that varies according to the threshold voltages of the selected memory cells, in response to page buffer control signals PBSIG, and temporarily store the sampled data.The column decoder 150 is configured to enable transfer of data between the page buffer group 140 and the input / output circuit 160 in response to a column address CADD. For example, column decoder 150 is coupled to page buffer group 140 via column lines CL and transmits enable signals via column lines CL. The page buffers (not shown) included in the page buffer group 140 receive or output data to the input / output circuit 160 via data lines DL in response to the enable signals.The input / output circuit 160 is configured to receive or output a command CMD, an address ADD, and data via input / output lines I / O. For example, the input / output circuit 160 transmits the command CMD and the address ADD received from an external controller via the input / output lines I / O to the control circuit 180, and transmits data DATA received from the external controller via the input / output lines I / O to the page buffer group 140. In addition, the input / output circuit 160 outputs the data DATA transferred from the page buffer group 140 to the external controller via the input / output lines I / O.The control circuit 180 outputs at least one of the operation code OPCD, the row address RADD, the page buffer control signals PBSIG, and the column address CADD, in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 180 corresponds to a program operation, the control circuit 180 controls the peripheral circuit 170 to perform the program operation on a memory block selected by the address ADD. When the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 controls the peripheral circuit 170 to perform the read operation on the memory block selected by the address ADD and output read data. When the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 controls the peripheral circuit 170 to perform the erase operation on the selected memory block.FIG. 2 is a diagram illustrating memory blocks of the memory device 100 according to an embodiment of the present disclosure.Referring to FIG. 2, the memory device 100 includes the memory blocks BLK 1 to BLKi disposed on peripheral circuitry PC disposed on a substrate SUB. The memory blocks BLK 1 to BLKi at least partially overlap the peripheral circuitry PC.The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-on-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method.The peripheral circuit arrangement PC includes, for example, the peripheral circuit 170 including the row decoder 130, the column decoder 150, the page buffer group 140, and the control circuit 180 that controls the operation of the memory blocks BLK 1 to BLKi. For example, the peripheral circuitry PC may include an NMOS transistor, a PMOS transistor, a resistor, and a capacitor electrically coupled to the memory blocks BLK 1 to BLKi. The peripheral circuitry PC is arranged between the substrate SUB and the memory blocks BLK 1 to BLKi in the example of FIG. 2.Each of the memory blocks BLK 1 to BLKi includes a source structure, bit lines, cell strings electrically coupled to the source structure and the bit lines, word lines electrically coupled to the cell strings, and selection lines electrically coupled to the cell strings. Each of the cell strings includes memory cells and selection transistors connected in series by a cell plug. Each of the selection lines serves as a gate electrode of a corresponding selection transistor, and each of the word lines serves as a gate electrode of a corresponding memory cell.In another embodiment, the substrate SUB, the peripheral circuitry PC, and the memory blocks BLK 1 to BLKi may be stacked in reverse order to the order shown in FIG. 2. For example, the peripheral circuitry PC may be disposed over the memory blocks BLK 1 to BLKi.In another embodiment, unlike FIG. 2, the peripheral circuitry PC may be disposed over some areas of the substrate SUB that may not overlap with the memory blocks BLK 1 to BLKi. For example, the peripheral circuitry PC and the memory blocks BLK 1 to BLKi may be disposed in regions of the substrate SUB that do not overlap each other.FIG. 3 is a plan view illustrating a layout of a storage device according to an embodiment of the present disclosure.Referring to FIG. 3, the j-th memory block BLKjand the nearest memory blocks (memory block BLKj-1and memory block BLKj+1, partially shown in FIG. 3 ) are separated by slots SI, where j is a positive integer less than i. For example, the slots SI are arranged in the X direction of the j-th memory block BLKj or extend along this direction and adjoin two different memory blocks, for example memory block BLKj and memory block BLKj-1 or memory block BLKj and memory block BLKj+1 arranged in the Y direction. Between successive memory blocks is a slot SI.Each of the memory blocks BLK 1 to BLKi including the j-th memory block BLKj includes a plurality of cell connectors CPL. The cell connectors CPL extend in a Z direction with respect to a substrate such as the substrate SUB of FIG. 2. the cell connectors CPL may be arranged in a plurality of rows or columns. Each of the plurality of rows includes the cell connectors CPL spaced apart from each other in the X direction as shown in the example of FIG. 3. The plurality of rows are spaced apart from each other in the Y direction. The centers of the cell connectors CPL included in an odd-numbered row are offset from the centers of the cell connectors CPL included in an even-numbered row. In other words, the centers of the cell connectors CPL in successive rows are offset from each other.Each of the cell connectors CPL includes a blocking layer BX, a charge trapping layer CT, a tunnel insulation layer TX, a channel layer CH, and a core column CO. The barrier layer BX may have a cylindrical shape. The charge trap layer CT contacts an inner surface of the barrier layer BX. The tunnel insulation layer TX contacts an inner surface of the charge trap layer CT. The channel layer CH contacts an inner surface of the tunnel insulation layer TX. The core column CO fills an inner side of the channel layer CH or is surrounded by the channel layer CH. For example, the core column CO may have a cylindrical shape in a region surrounded by the channel layer CH. A capping layer (not shown) may optionally be formed over the core column CO.The barrier layer BX and the tunnel insulation layer TX may each include an oxide layer (for example, a silicon oxide layer), an oxynitride layer (for example, a silicon oxynitride layer), or a combination thereof. The charge trap layer CT may include a nitride layer or a variable resistance material. The channel layer CH may include an undoped silicon layer or a doped silicon layer. The core pillar CO may include an insulating layer or a conductive layer. Each of the barrier layer BX, the charge trap layer CT, the tunnel insulation layer TX, the channel layer CH, and the core column CO included in each of the cell connectors CPL extends in the Z direction with respect to the drawing, respectively.FIG. 4 shows a cross-sectional view of the memory device 100 according to an embodiment of the present disclosure. FIG. 4 is a cross-sectional view taken along line A--A' of FIG. 3.Referring to FIG. 4, the memory device 100 (for example, the i-th memory block BLKi) includes a stack structure STK. The stack structure STK includes a plurality of gate conductive layers CD alternately stacked with a plurality of interlayer insulating layers IIL. The gate conductive layers CD are alternately stacked with the interlayer insulating layers IIL in the Z direction, as shown in FIG. 4. The gate conductive layers CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si). The insulating intermediate layers IIL may include an oxide layer, for example a silicon oxide layer. Each of the gate conductive layers CD corresponds to one of the drain selection lines DSL, the word lines WLs, and the source selection lines SSL of FIG. 1.The memory device 100, such as the i-th memory block BLKi, includes the cell plug CPL. The cell plug CPL penetrates the stack structure STK. For example, the cell plug CPL is located within a first opening OP 1 penetrating the stack structure STK. The cell plug CPL extends in the Z direction as shown in FIG. 4. The memory cells or selection transistors described in FIGS. 1 and 2 are formed at intersections (not shown) of the cell plug CPL and the gate conductive layers CD.The cell plug CPL comprises a storage layer ML. The storage layer ML includes the barrier layer BX, the charge trap layer CT, and the tunnel insulation layer TX. The storage layer ML penetrates or extends through the stack structure STK. The storage layer ML is formed along an inner wall of the first opening OP 1. For example, the barrier layer BX contacts an inner surface of the first opening OP 1. Thus, the storage layer ML contacts an inner wall of the stack structure STK. The storage layer ML extends along an outer surface of the channel layer CH. For example, the tunnel insulation layer TX contacts the outer surface of the channel layer CH.The cell plug CPL comprises the core column CO. The core column CO fills or is surrounded by the inside of the channel layer CH. The core column CO contacts an inner surface of the channel layer CH. The core column CO is surrounded by the channel layer CH.The cell plug CPL includes the channel layer CH. The channel layer CH penetrates or extends through the stack structure STK. The channel layer CH extends in the Z direction. The channel layer CH may have a cylindrical shape. The channel layer CH includes a first part P 1 and a second part P 2 as shown in the example of FIG. 4. The second part P 2 is located below the first part P 1. A lower surface of the first part P 1 contacts an upper surface of the second part P 2. A first end, such as the top, of the second portion P2 is adjacent a first end, such as the bottom, of the first portion. In the present disclosure, for convenience of description, the first part P 1 and the second part P 2 are described as being separated or divided from each other, although the first part P 1 and the second part P 2 may not be physically separated from each other and may have a single unitary structure. For example, an interface between the first part P 1 and the second part P 2 may not be detectable.The first part P 1 of the channel layer CH includes single crystal silicon in this embodiment. In the first part P1, no grain boundary GB may be present or it is small enough to be undetectable.The second part P 2 of the channel layer CH includes polycrystalline silicon in this embodiment. The second portion P 2 of the channel layer CH includes one or more grain boundaries GB. The second part P 2 includes polycrystalline silicon having a plurality of grains in this embodiment. Accordingly, the grain boundaries GB are located in the second part P 2 of the channel layer CH. A size of the grains included in the second part P 2 is not necessarily limited to the embodiment shown in FIG. 4. FIG. 4 shows only the grain boundaries GB formed in the second part P 2, although the positions and the shapes of the grain boundaries GB are not limited to the positions and the shapes of the grain boundaries GB shown in FIG. 4.FIGS. 5A to 5I are diagrams illustrating cross-sectional views of a memory device formed using a method of manufacturing a memory device according to an embodiment of the present disclosure. FIGS. 5A to 5I each show a cross section taken along the line A-A' of FIG. 3.Referring to FIG. 5A, a preliminary stack structure pSTK is formed. The temporary stack structure pSTK includes first material layers IIL alternately stacked with second material layers SF in the Z direction. The first material layer IIL may include an insulation material. For example, the first material layer IIL may include an oxide layer (e.g., a silicon oxide layer). The second material layer SF may include a material that can be selectively removed in a subsequent process. Accordingly, the second material layer SF may include a material whose etching selectivity is different from that of the first material layer IIL. For example, the second material layer SF may include a nitride layer.The first opening OP 1 penetrating the temporary stack structure pSTK is formed. The first opening OP 1 penetrates or extends through the first material layers IIL and the second material layers SF of the preliminary stack structure pSTK. The first opening OP 1 extends in the Z direction. The first opening OP 1 may have, for example, a circular, elliptical, conical, triangular, or rectangular shape.Referring to FIG. 5B, a preliminary barrier layer pBX, a preliminary charge trap layer pCT, a preliminary tunnel isolation layer pTX, and a preliminary channel layer pCH are formed over the preliminary stack structure pSTK. For example, the preliminary barrier layer pBX, the preliminary charge trap layer pCT, the preliminary tunnel insulating layer pTX, and the preliminary channel layer pCH are sequentially formed on an upper surface of the preliminary stack structure pSTK and an inner surface of the preliminary stack structure pSTK surrounding or adjacent to the first opening OP 1. Accordingly, the preliminary channel layer pCH is formed on the inner surface of the first opening OP 1 and the upper surface of the preliminary stack structure pSTK.The preliminary barrier layer pBX, the preliminary charge trap layer pCT, the preliminary tunnel insulating layer pTX, and the preliminary channel layer pCH are arranged from an inner wall of the preliminary stack structure pSTK surrounding the first opening OP 1, sequentially or sequentially. The preliminary barrier layer pBX, the preliminary charge trap layer pCT, the preliminary tunnel insulating layer pTX, and the preliminary channel layer pCH extend through the preliminary stack structure pSTK.In FIG. 5B, the preliminary channel layer pCH includes, for example, amorphous silicon. The preliminary channel layer pCH may include through a process including depositing amorphous silicon on the top surface of the preliminary stack structure pSTK and the inner wall of the preliminary stack structure pSTK surrounding the first opening OP 1.A preliminary capping layer pCV is formed over the preliminary channel layer pCH. The preliminary capping layer pCV fills an inner side of the preliminary channel layer pCH or is disposed between the walls of the preliminary channel layer pCH. Within the first opening OP 1, the preliminary covering layer pCV covers at least a part of an inner surface of the preliminary channel layer pCH. Moreover, the preliminary covering layer pCV covers at least a part of an upper surface of the preliminary channel layer pCH formed above the preliminary stack structure pSTK. In another embodiment, the temporary capping layer pCV may fill the first opening OP 1 and may not be formed over the temporary stack structure pSTK. The preliminary capping layer pCV may include an oxide layer.Referring to FIG. 5C, a portion or region of the temporary cap layer pCV is removed to form a cap layer CV. For example, an upper portion of the temporary liner layer pCV may be etched to form a recess RC over an upper portion of the liner layer CV. A portion of the inner surface of the preliminary channel layer pCH is exposed after the region of the preliminary capping layer pCV is removed. The portion of the inner surface of the preliminary channel layer pCH is exposed by the recess RC. For example, the cover layer CV covers a lower portion of the inner surface of the preliminary channel layer pCH and does not cover an upper portion of the inner surface of the preliminary channel layer pCH. Accordingly, the upper portion of the inner surface of the preliminary channel layer pCH is exposed through the recess RC. Moreover, the top surface of the preliminary channel layer pCH formed over the preliminary stack structure pSTK is exposed. A wet etching process, a dry etching process, or the like may be performed to selectively etch or remove a part of the preliminary capping layer pCV.Over the preliminary channel layer pCH exposed by the recess RC, a conductive layer CC is formed. The conductive layer CC covers a portion of the preliminary channel layer pCH not covered by the cap layer CV. For example, the conductive layer CC is formed on the top surface of the preliminary channel layer pCH located above the preliminary stack structure pSTK. Moreover, the conductive layer CC is formed on the portion, for example, the upper portion, of the inner surface of the preliminary channel layer pCH located inside the first opening OP 1. The conductive layer CC may include a metal such as nickel (Ni).Referring to FIG. 5D, the conductive layer CC may be converted into a silicide layer SS. The conductive layer CC is converted into the silicide layer SS by a first heat treatment. The conductive layer CC contacting a surface of the preliminary channel layer pCH is converted into the silicide layer SS. The silicide layer SS may include silicide such as nickel silicide (NiSi 2).Referring to FIG. 5E, a portion of the preliminary channel layer pCH may be crystallized using the silicide layer SS. The portion of the preliminary channel layer pCH is converted into single crystal silicon using the silicide layer SS. The crystallization of the preliminary channel layer pCH using the silicide layer SS is initiated during a second heat treatment, for example. The crystallization of the preliminary channel layer pCH using the silicide layer SS is referred to as metal-induced lateral crystallization (MILC).In FIG. 5D, the silicide layer SS contacts an upper portion of the preliminary channel layer pCH. Accordingly, during metal-induced lateral recrystallization (MILC), as shown in FIG. 5E, the crystallization proceeds from the upper portion toward the lower portion of the preliminary channel layer pCH with reference to the drawing. For example, when performing the second heat treatment, the silicide layer SS moves in a downward direction with respect to the drawing, for example, in the negative Z direction. Accordingly, the upper portion of the preliminary channel layer pCH is crystallized before the lower portion of the preliminary channel layer pCH. As a result, as shown in FIG. 5E, the upper portion of the preliminary channel layer pCH includes single crystal silicon, and the lower portion of the preliminary channel layer pCH includes amorphous silicon.A portion of the preliminary channel layer pCH crystallized using the silicide layer SS is referred to as the first part P 1 or the first part P 1 of the preliminary channel layer pCH. The first part P 1 crystallized by the MILC method includes single crystal silicon. The portion of the preliminary channel layer pCH that is above or above the silicide layer SS after performing the second heat treatment is referred to as the first part P 1. Another portion of the preliminary channel layer pCH that is located below or below the silicide layer SS is referred to as the second part P 2 or the second part P 2 of the preliminary channel layer pCH with reference to the figure. The silicide layer SS is located between the first part P 1 and the second part P 2 of the preliminary channel layer pCH. In FIG. 5E, the first portion P 1 may include single crystal silicon and the second portion P 2 includes amorphous silicon. When the crystallization of the preliminary channel layer pCH is initiated using the silicide layer SS, the silicide layer SS moves in the downward direction with reference to the drawing. The lower surface of the first part P 1 may be located below an upper surface of the cap layer CV, for example, in the negative Z direction.Referring to FIG. 5E, a height of the silicide layer SS, for example, a position of the silicide layer SS in the Z direction may vary with respect to the X direction and / or the Y direction or the X-Y plane. When the second heat treatment is performed, a speed of movement of the silicide layer SS may vary depending on a position of the silicide layer SS in the X-Y plane. Accordingly, the silicide layer SS may be formed at different heights or positions in the Z direction on the preliminary channel layer pCH within one of the cell plugs CPL. For example, as shown in FIG. 5E, the silicide layer SS on the left side of the drawing is lower in the Z direction than the silicide layer SS on the right side of the drawing.Referring to FIG. 5F, the capping layer CV is removed to form a second opening OP 2. The inner surface of the preliminary channel layer pCH is exposed through the second opening OP 2. Accordingly, both the upper surface and the inner surface of the preliminary channel layer pCH are exposed.The preliminary channel layer pCH is doped with a conductive material DP. The conductive material DP is doped into the top and the inner surface of the preliminary channel layer pCH in the example of FIG. 5F. For example, the inner surface of the preliminary channel layer pCH is doped with the conductive material DP through the second opening OP 2. The conductive material DP may include a metal such as nickel (Ni).The first part P 1 of the preliminary channel layer pCH is doped with the conductive material DP. Moreover, the second part P 2 of the preliminary channel layer pCH is doped with the conductive material DP. The processes of doping the conductive material DP into the first part P 1 and the second part P 2 may be performed simultaneously.The conductive material DP is doped not only in the second part P 2 including amorphous silicon but also in the first part P 1 including single crystal silicon. Thus, the conductive material DP is doped not only in the second part P 2 to facilitate the crystallization, but also in the first part P 1 that is already crystallized. Moreover, a portion of the conductive material DP may be doped into the silicide layer SS.Referring to FIG. 5G, the preliminary channel layer pCH is crystallized using the conductive material DP. A second portion P2' of the preliminary channel layer pCH is converted into polycrystalline silicon. The crystallization of the preliminary channel layer pCH, for example, the second part P2' using the conductive material DP is initiated by a third heat treatment. The crystallization of the preliminary channel layer pCH using the conductive material DP is referred to as a Metal-Induced Recrystallization (MIC) method or process.The second part P2' of the preliminary channel layer pCH may be crystallized based on a position where the conductive material DP is doped. For example, the second part P2' may be crystallized around or near the position where the conductive material DP is doped. Accordingly, the crystallized second part P2' comprises a plurality of grains. The second part P2' of the preliminary channel layer pCH includes the grain boundaries GB.Although the conductive material DP is doped in the first part P 1 of the preliminary channel layer pCH, the crystalline state of the first part P 1 does not necessarily change because the first part P 1 includes single-crystal silicon.The silicide layer SS is diffused into the preliminary channel layer pCH when performing the third heat treatment. For example, a metal material included in the silicide layer SS may be used for crystallization using a metal-induced recrystallization (MIC) method. As a result, the silicide layer SS may not be detectable, as shown in FIG. 5G.Referring to FIG. 5H, the conductive material DP in the preliminary channel layer pCH is removed. Moreover, the remaining materials included in the conductive layer CC shown in FIG. 5C may be advantageously removed with the conductive material DP.The preliminary channel layer pCH from which the conductive material DP is removed includes the first single crystal silicon portion P 1 and the second polycrystalline silicon portion P 2'. The first part P1 is located above the second part P2' in the drawing.In the second opening OP 2, a preliminary core column pCO is formed. At least a portion of the preliminary core column pCO is surrounded by the preliminary channel layer pCH. Another portion of the preliminary core column pCO is optionally formed over the preliminary stack structure pSTK. In this example, the preliminary core column pCO contacts the top and the inner surface of the preliminary channel layer pCH.Referring to FIG. 5I, the preliminary core column pCO, the preliminary channel layer pCH, the preliminary tunnel insulating layer pTX, the preliminary charge trap layer pCT, and the preliminary barrier layer pBX, which are located above or above the preliminary stack structure pSTK in the Z direction, are removed. As a result, the top surface of the temporary stack pattern pSTK is exposed.The barrier layer BX, the charge trap layer CT, the tunnel insulation layer TX, and the channel layer CH remaining above the preliminary stack structure pSTK after the removal of the material layers form the cell plug CPL. Moreover, the channel layer CH may include a first part P1' having a cylindrical shape and the second part P2' extending below the first part P1' or downward from the first part P1'. The first part P1' comprises single crystal silicon and the second part P2' comprises polycrystalline silicon.The second material layers SF are replaced with third material layers CD to form the stack structure STK. The third material layers CD include a conductive material.When the channel layer CH is formed according to an embodiment of the present disclosure, the grain size of the silicon included in the channel layer CH may be increased. As compared with the example in which a channel layer is formed using one of the metal-induced lateral recrystallization (MILC) and metal-induced recrystallization (MIC), the silicon included in the channel layer CH according to the embodiment of the present disclosure may have a larger grain size. For example, since the channel layer CH of the present disclosure includes not only the second amorphous silicon part (P 2, P 2') but also the first single crystal silicon part (P 1, P 1'), it may have a larger average grain size than a channel layer including only amorphous silicon. As the grain size of the silicon included in the channel layer CH increases, the resistance of the grain boundary GB included in the channel layer CH decreases. According to the present disclosure, the amount of current flowing in the memory cells of the memory device 100 can be increased.FIG. 6 is a diagram illustrating an embodiment of a memory card system 3000 including a storage device 3200 according to the present disclosure.Referring to FIG. 6, the memory card system 3000 includes a controller 3100, the storage device 3200, and a connector 3300.The controller 3100 is coupled to the storage device 3200. The controller 3100 is configured to access the storage device 3200. For example, the controller 3100 is configured to control a program operation, a read operation, an erase operation, and a background operation of the memory device 3200. The controller 3100 is configured to provide an interface between the storage device 3200 and a host. The controller 3100 is configured to control firmware that controls the storage device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction device.The controller 3100 communicates with an external device via the connector 3300. The controller 3100 communicates with the external device, for example, the host, according to a specific communication protocol. For example, the controller 3100 may be configured to interface with the external device via at least one of various communication protocols such as universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), firewire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth and NVMe protocols. For example, the connector 3300 may be configured according to at least one of the above communication protocols.The memory device 3200 comprises a plurality of memory cells, which is embodied, for example, in the same manner as the memory device 100 shown in FIG. 1 and is formed according to the method for producing a memory device described above with reference to FIGS. 5A to 5I.The controller 3100 and the memory device 3200 are integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the storage device 3200 may form a memory card such as a personal computer memory card international association (PCMCIA) (PC) card), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multi-media card (MMC, RS-MMC, MMCmicro or eMMC), an miniSD, microSD or SDHC (SD) card, or a universal flash storage (UFS).FIG. 7 is a diagram illustrating an embodiment of a solid state drive (SSD) system 4000 including a plurality of storage devices 4221- 422 naccording to the present disclosure.Referring to FIG. 7, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges a signal with the host 4100 via a signal terminal 4001, and receives power via a power terminal 4002. The SSD 4200 includes a controller 4210, the plurality of storage devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.The controller 4210 controls the plurality of storage devices 4221 to 422 nin response to the signals received from the host 4100. For example, the signals may be based on an interface between the host 4100 and the SSD 4200. For example, the signals may be in accordance with at least one of a variety of interfaces, such as Universal Serial Bus (USB), Multi-Media Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnection (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe interfaces.The plurality of memory devices 4221to 422neach include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221to 422nis embodied in the same manner as the memory device 100 illustrated in FIG. 1 and formed using the method of manufacturing a memory device according to the method described above with reference to FIGS. 5A to 5I. The plurality of storage devices 4221 to 422 ncommunicates with the controller 4210 via the channels CH 1 to CHn.The auxiliary power supply 4230 is coupled to the host 4100 via a power terminal 4002. The auxiliary power supply 4230 receives power supplied from the host 4100, and can adjust the power according to the needs of the SSD. If the power supply from the host 4100 is not uniform or consistent, the auxiliary power supply 4230 supplies power to the SSD 4200. For example, the auxiliary power supply 4230 may be located inside or outside the SSD 4200. For example, auxiliary power supply 4230 may be on a motherboard (main board) and provide auxiliary power to SSD 4200.The buffer memory 4240 serves as a buffer memory for the SSD 4200. For example, the buffer memory 4240 temporarily stores data received from the host 4100 or data received from the plurality of storage devices 4221 to 422 n, or may temporarily store metadata, for example, mapping tables, of the storage devices 4221 to 422 n. The buffer memory 4240 may include volatile memories such as DRAM, SDRAM, DDR-SDRAM, and LPDDR-SDRAM, or nonvolatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.According to embodiments of the present disclosure, a current flowing in memory cells may be increased by increasing a grain size of silicon included in a channel layer of a semiconductor device. According to an embodiment, a method may include three separate heat treatment processes. According to an embodiment, a method may further include forming a conductive layer on an exposed inner surface of the channel layer; converting the conductive layer into a silicide layer using a first heat treatment; inducing the crystallization of the first portion using the silicide layer during a second heat treatment; and converting the second portion into polycrystalline silicon using a third heat treatment.Concepts associated with the various embodiments are described above. Those skilled in the art will understand that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure. Accordingly, the embodiments disclosed in the present specification should be viewed from not a limiting point of view, but rather an illustrative point of view. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments. All changes within the meaning and range of equivalence of the claims are intended to be included within the scope thereof.

Claims

A method of manufacturing a memory device, the method comprising: forming a stack structure having first material layers that are alternately stacked with second material layers; forming a channel layer having amorphous silicon in an opening extending through the stack structure; converting a first portion of the channel layer to single crystal silicon; doping the first portion of the channel layer with a conductive material; doping a second portion of the channel layer with the conductive material, wherein the second portion is different from the first portion; and converting the second portion of the channel layer to polycrystalline silicon using the conductive material.The method of claim 1, wherein forming the channel layer comprises: forming the opening extending through the stack structure; forming a storage layer on an inner surface of the stack structure surrounding the opening and an outer surface of the stack structure; and forming the channel layer on the storage layer.The method of claim 2, wherein during forming the channel layer on the storage layer, the channel layer is formed on the inner surface of the stack structure surrounding the opening and the outer surface of the stack structure, wherein the outer surface of the stack structure and the inner surface of the stack structure are on successive sides of the stack structure.The method of claim 1, wherein converting the first part to the single-crystal silicon comprises: forming a capping layer such that a portion of an inner surface of the channel layer is exposed through a recess; forming a conductive layer on the exposed inner surface of the channel layer; and converting the first part to the single-crystal silicon using the conductive layer.The method of claim 4, wherein forming the liner layer comprises: forming a temporary liner layer within the channel layer; and forming the recess by removing a portion of the temporary liner layer; wherein the portion of the inner surface of the channel layer is exposed by the recess.The method of claim 4, wherein converting the first portion to single crystal silicon using the conductive layer comprises: converting the conductive layer to a silicide layer using a first heat treatment; and initiating crystallization of the first portion using the silicide layer during a second heat treatment.The method of claim 6, wherein the silicide layer moves toward the capping layer during the second heat treatment.The method of claim 4, wherein a first surface of the capping layer abuts the recess and the first surface of the capping layer is disposed between the recess and a first end of the first portion of the channel layer as formed during converting the first portion to the single crystal silicon using the conductive layer.The method of claim 1, wherein the doping of the first portion with the conductive material and the doping of the second portion with the conductive material are performed simultaneously.The method of claim 1, wherein the converting of the second portion to polycrystalline silicon is performed using a third heat treatment.The method of claim 1, wherein a first end of the second part is formed adjacent a first end of the first part.The method of claim 1, further comprising, after converting the second portion to polycrystalline silicon, removing the conductive material from the channel layer.A memory device, comprising: a stack structure; and a channel layer formed in an opening extending through the stack structure, the channel layer comprising a first portion comprising single crystal silicon and a second portion comprising polycrystalline silicon, the first portion being adjacent to the second portion.The memory device of claim 13, further comprising a memory layer formed in the opening that extends through the stack structure and along an outer surface of the channel layer.The memory device of claim 14, wherein the memory layer comprises: a barrier layer contacting an inner surface of the stack structure; a charge trapping layer contacting an inner surface of the barrier layer; and a tunnel insulation layer contacting an inner surface of the charge trapping layer and the outer surface of the channel layer.The storage device of claim 13, further comprising a core column within the channel layer.A method comprising: forming an opening extending through a stack structure; forming a channel layer including amorphous silicon in the opening; converting a first portion of the channel layer to single crystal silicon; doping the first portion of the channel layer and a second portion of the channel layer with a conductive material, the second portion adjoining the first portion; and converting the second portion of the channel layer to polycrystalline silicon using the conductive material.The method of claim 17, further comprising three separate heat treatment processes.The method of claim 17, further comprising: forming a conductive layer on an exposed inner surface of the channel layer; converting the conductive layer to a silicide layer using a first heat treatment; initiating crystallization of the first portion using the silicide layer during a second heat treatment; and converting the second portion to polycrystalline silicon using a third heat treatment.

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