BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

Abstract

A bipolar transistor comprises an emitter region, a base region, a collector region, and a plurality of fin structures. The emitter region is arranged on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are arranged in the base region and surround the emitter region, and the plurality of fin structures extend fixedly along one direction and parallel to one another.

Description

BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION

[0001] The present disclosure relates to the field of semiconductor devices, and more particularly to a bipolar junction transistor (BJT) and a method of manufacturing the same. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] A BJT consists primarily of three sections of semiconductor materials with different doping levels. Charge flow in a BJT is primarily based on the diffusion and drift of charge carriers at the PN junction. For example, in an NPN transistor, electrons in the emitter region with a higher doping level migrate to the base region by diffusion. In the base region, holes are the majority carriers, and electrons are the minority carriers. Because the base region is very thin, these electrons thin out and enter the collector region, from which the collector current is generated. Therefore, the BJT is classified as a minority carrier device. The BJT is capable of signal amplification and has excellent power control capabilities, high-speed operation, and durability.Therefore, BJTs are often used to form amplifier circuits or to drive devices such as speakers and motors. BJTs are also widely used in aerospace products, medical devices, and robots. Therefore, improving the structure of current BJTs is a goal of relevant industries.

[0003] CN 1 06 409 890 A discloses a bipolar transistor structure comprising an emitter region, a base region surrounding the emitter, and a collector region further surrounding the base region.

[0004] US 2021 / 0 335 861 A1 discloses a BJT comprising an emitter, a base region surrounding the emitter, and a collector region surrounding the base region. SUMMARY OF THE INVENTION

[0005] According to one embodiment of the present disclosure, a BJT includes an emitter region, a base region, a collector region, and a plurality of fin structures. The emitter region is arranged on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are arranged in the base region and surround the emitter region, and the plurality of fin structures extend fixedly along one direction and parallel to each other. Furthermore, the plurality of fin structures are arranged only in the base region.

[0006] According to another embodiment of the present disclosure, a BJT comprises an emitter region, a base region, a collector region, a first insulating structure, and a second insulating structure. The emitter region is arranged on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The first insulating structure is arranged between the emitter region and the base region. The second insulating structure is arranged between the base region and the collector region, and at least one of the first insulating structure and the second insulating structure comprises a step structure. The BJT further comprises a plurality of fin structures, wherein the plurality of fin structures are arranged only in the base region.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a BJT comprises the following steps: An emitter region is formed on a substrate. A base region is formed surrounding the emitter region. A collector region is formed surrounding the base region. A plurality of fin structures arranged in the base region and surrounding the emitter region are formed, and the plurality of fin structures extend fixedly along one direction and parallel to each other, wherein the plurality of fin structures are arranged only in the base region.

[0008] These and other features of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiment shown in the various figures and drawings. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are schematic views illustrating steps for fabricating a BJT according to an embodiment of the present disclosure. Fig. Figure 7 is a schematic top view showing the Fig. 6 illustrated BJT shows. Fig. 8 is a schematic cross-sectional view illustrating a BJT according to another embodiment of the present disclosure. Fig. 9 is a schematic cross-sectional view illustrating a BJT according to another embodiment of the present disclosure. Fig. 10 is a schematic cross-sectional view illustrating a BJT according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top," "bottom," "left side," "right side," "front," "back," "bottom side," "upper side," etc., is used with reference to the orientation of the described figure(s). The components of embodiments of the present invention may be positioned in a number of different orientations. The directional terminology is, therefore, used for purposes of illustration and is in no way limiting. Also, in the following embodiments, identical or similar references will be used for identical or similar elements.

[0010] Hereinafter, the description "the first feature is formed on or above the second feature" may refer to "the first feature directly contacts the second feature" or it may refer to "another feature being present between the first feature and the second feature" such that the first feature does not directly contact the second feature.

[0011] It should be understood that although the terms first, second, and the like are used herein to describe various elements, regions, layers, and / or sections, these elements, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section. Terms such as "first," "second," and other numerical terms used herein do not imply order unless clearly indicated by the context.Thus, a first element, region, layer, and / or section discussed below could also be referred to as a second element, region, layer, and / or section without departing from the teachings of the embodiments. The terms used in the claims need not be identical to the terms used in the description, but may be used in the order of the elements claimed in the claims.

[0012] Referring to the Fig. 1 to Fig. 7 are Fig. 1 to Fig. 6 schematic cross-sectional views showing the steps for manufacturing a BJT 10 (see Fig. 6) according to an embodiment of the present disclosure, and Fig. Figure 7 is a schematic top view showing the Fig. 6. For simplification, the BJTs shown in Fig. 6 illustrated epitaxial structures 36 in Fig. 7 is omitted. In the present embodiment, the BJT 10 is a pnp transistor for explanation. In Fig. 1, a substrate 12 is first provided. The substrate 12 can be a doped silicon substrate, a doped epitaxial silicon substrate, a doped silicon carbide substrate, or a doped silicon-on-insulator (SOI) substrate. The dopants of the substrate 12 can be adjusted depending on whether the subsequently formed BJT 10 is used for a pnp transistor or an npn transistor. For example, the substrate 12 can be a p-type substrate when the BJT 10 is applied to the pnp transistor by implanting p-type dopants such as boron (B) and indium (In). When the BJT 10 is applied to the npn transistor, the substrate 12 can be an n-type substrate by implanting n-type dopants such as arsenic (As) and phosphorus (P). In the present embodiment, the BJT 10 is, for example, a PNP transistor. Therefore, the substrate 12 is, for example, a P-type substrate.

[0013] The substrate 12 may define a first region 20, a second region 22, and a third region 24, which are sequentially connected from the inside to the outside. In the top view of the BJT 10 (see Fig. 7) The second region 22 surrounds the first region 20, and the third region 24 surrounds the second region 22. The first region 20 is primarily configured to dispose an emitter region ER, the second region 22 is primarily configured to dispose a base region BR, and the third region 24 is primarily configured to dispose a collector region CR. In the present disclosure, the BJT 10 or its elements may be viewed from above, for example, when viewing the BJT 10 in a direction opposite the vertical direction D3. The vertical direction D3 may, for example, be perpendicular to the top surface 121 of the substrate 12.

[0014] Next, the emitter region ER (see Fig. 7) is formed on the substrate 12, the base region BR (see Fig. 7) surrounding the emitter region ER is formed, the collector region CR (see Fig. 7), which surrounds the base region BR, is formed, a multitude of fin structures 32 and 34 (see Fig. 7) in the base region BR and around the emitter region ER, a first insulating structure 40 is formed between the emitter region ER and the base region BR, and a second insulating structure 42 is formed between the base region BR and the collector region CR, which may comprise the following steps.

[0015] First, as in the Fig. 2 and Fig. 7 illustrates the plurality of fin structures 32 and 34 formed in the second region 22 of the substrate 12. The fin structures 32 and 34 may be formed by the following method. For example, a patterned mask (not illustrated) is formed on the substrate 12, and then an etching process is performed to transfer the pattern of the patterned mask to the substrate 12 to form the fin structures 32, 34 and a recess 13. Alternatively, the fin structures 32, 34 and the recess 13 may also be formed by a SIT (sidewall image transfer) method, which is well known to those skilled in the art and the details of which will not be further explained herein.

[0016] As in Fig. As illustrated in Figure 7, the plurality of fin structures 32 and 34 extend fixedly along a first horizontal direction D1 and parallel to each other, and the plurality of fin structures 32 and 34 are spaced apart from each other in the second horizontal direction D2. The aforementioned description "the plurality of fin structures 32 and 34 extend fixedly along a first horizontal direction D1" may refer to each of the fin structures 32 and 34 having a substantially elongated shape. In the present disclosure, when an element extends along a direction, it may refer to the element having the maximum length in that direction.

[0017] Next, as in Fig. 2, an insulating structure 50 is introduced into the substrate 12 to surround the fin structures 32 and 34. The insulating structure 50 can be formed, for example, by first applying a dielectric material to fill the recess 13 and then removing the portion of the dielectric material protruding from the recess 13 through a planarization process to obtain the insulating structure 50. At this stage, the upper surface 501 of the insulating structure 50 is aligned with the upper surface 201 of the substrate 12 in the first region 20, the upper surface 241 of the substrate 12 in the third region 24, and the upper surface 321 of the fin structure 32. Although not illustrated in the drawings, the upper surface 501 of the insulating structure 50 is also aligned with the upper surface of the fin structure 34 at this stage.

[0018] Next, as in Fig. 3 illustrates, an insulating structure 52 is introduced into the substrate 12. The insulating structure 52 is arranged at the boundary between the second region 22 and the third region 24. The insulating structure 52 can be formed, for example, by first forming the recess 15 in the substrate 12, applying a dielectric material to fill the recess 15, and then removing the portion of the dielectric material protruding from the recess 15 through a planarization process to obtain the insulating structure 52. At this stage, the upper surface 521 of the insulating structure 52 is aligned with the upper surface 201 of the substrate 12 in the first region 20, the upper surface 241 of the substrate 12 in the third region 24, and the upper surface 321 of the fin structure 32.Although not illustrated in the drawings, the upper surface 521 of the insulating structure 52 is also aligned with the upper surface of the fin structure 34 at this stage. In the embodiment, the insulating structure 50 is formed first, and then the insulating structure 52. However, the present disclosure is not limited thereto. In other embodiments, the insulating structure 52 may be formed first, and then the insulating structure 50. Alternatively, the recess 13 and the recess 15 may be formed first with different depths, then the dielectric material is deposited, and the planarization process is performed to form the insulating structures 50 and 52 simultaneously.

[0019] Next, as in Fig. 4, an etching process P1 may be performed with a patterned mask (not illustrated) to remove the exposed portions of the insulating structures 50 and 52 from the patterned mask, to convert the upper portions of the fin structures 32 and 34, to convert the insulating structure 50 located at the boundary between the first region 20 and the second region 22 into the first insulating structure 40, to convert the insulating structure 50 arranged between any two adjacent fin structures 32 and 34 into the third insulating structure 44, and to convert the insulating structure 52 arranged at the boundary between the second region 22 and the third region 24 into the second insulating structure 42. As in Fig. 4, the first insulating structure 40 comprises a step structure ST1 such that the upper surface 401 of the first insulating structure 40 comprises two horizontal surfaces instead of a single horizontal surface. Furthermore, the first structure 40 of the insulating structure has different heights in the vertical direction D3. The second insulating structure 42 comprises a step structure ST2 such that the upper surface 421 of the second insulating structure 42 comprises two horizontal surfaces instead of a single horizontal surface. Furthermore, the second insulating structure 42 has different heights in the second direction D3. The third insulating structure 44 does not comprise a step structure such that the upper surface 441 of the third insulating structure 44 is a single horizontal surface. Furthermore, the height of the third structure 44 of the insulating structure in the vertical direction D3 is substantially fixed.Each of the first insulating structure 40, the second structure 42, and the third structure 44 may, for example, be a shallow trench isolation (STI) and serve an electrical insulating function between the emitter region ER, the base region BR, and the collector region CR, which are formed later. The first insulating structure 40, the second structure 42, and the third structure 44 may comprise, but are not limited to, a dielectric material, such as silicon dioxide.

[0020] Next, as in Fig. 5, an ion implantation process P2 is performed together with an annealing process to form the first well region 14 and the second well region 16 in the substrate 12 and to form heavily doped regions (not illustrated) at the upper portions of the substrate 12 in the first region 20 and the third region 24. The dopant concentrations of the heavily doped regions are greater than the dopant concentrations of the first well region 14 and the second well region 16.

[0021] In particular, the ion implantation process P2 may include a first implantation step for implanting the dopants having a different conductivity type than that of the substrate 12 into the substrate 12 in the first region 20 and the fin structures 32 and 34 in the second region 22 to form the first well region 14. The ion implantation process P2 may further include a second implantation step for implanting the dopants having the same conductivity type as that of the substrate 12 into the substrate 12 in the third region 24 to form the second well region 16. Preferably, a patterned mask (not illustrated) is formed to cover the third region 24 during the formation of the first well region 14.By shielding the patterned mask, the dopants with a conductivity type that differs from that of the substrate 12 are implanted only into the substrate 12 in the first region 20 and into the rib structures 32 and 34 in the second region 22 during the first implantation step, but not into the substrate 12 in the third region 24. Similarly, a patterned mask (not illustrated) is formed to cover the first region 20 and the second region 22 during the formation of the second well region 16. By shielding the patterned mask, the dopants whose conductivity is identical to that of the substrate 12 are implanted only in the third region 24 during the second implantation step, but not into the substrate 12 in the first region 20 and the rib structures 32 and 34 in the second region 22.

[0022] The ion implantation process P2 may further include a third implantation step for implanting dopants having the same conductivity type as that of the substrate 12 into the upper portions of the substrate 12 in the first region 20 and the third region 24 to form the heavily doped regions (not shown). Similarly, a patterned mask (not shown) is formed to cover the second region 22 during the formation of the heavily doped regions in the first region 20 and the third region 24. By shielding the patterned mask, the dopants whose conductivity is identical to that of the substrate 12 are implanted only into the upper portions of the substrate 12 in the first region 20 and the third region 24 during the third implantation step, but not into the fin structures 32 and 34 in the second region 22.

[0023] Next, as in Fig. 6, a patterned mask (not illustrated) is used to cover the first region 20 and the third region 24, such that only the second region 22 is exposed. Subsequently, the portions of the fin structures 32 and 34 that protrude from the first insulating structure 40, the second insulating structure 42, and the third insulating structure 44 are removed, such that the upper ends of the fin structures 32 and 34 are slightly concave with respect to the first insulating structure 40, the second insulating structure 42, and the third insulating structure 44. Subsequently, a selective epitaxial growth process P3 is performed to form a plurality of epitaxial structures 36 on the plurality of fin structures 32 and 34, respectively. The plurality of epitaxial structures 36 are fused together.

[0024] In this embodiment, when forming the epitaxial structures 36, the dopants having the conductivity type different from that of the substrate 12 may be implanted into the epitaxial structures 36 in-situ through an ion implantation process and an annealing process to form the heavily doped region (not shown) in the epitaxial structures 36. In another embodiment, the ion implantation process and the annealing process may be performed after forming the epitaxial structures 36 to implant the dopants having the conductivity type different from that of the substrate 12 into the epitaxial structures 36 to form the heavily doped region (not shown) in the epitaxial structures 36.As mentioned above, it is advantageous to form a patterned mask (not illustrated) to cover the first region 20 and the third region 24 during the formation of the epitaxial structures 36 and the heavily doped region in the epitaxial structures 36. By shielding the patterned mask, the epitaxial structures 36 can be prevented from forming on the upper surface 201 of the substrate 12 in the first region 20 and the upper surface 241 of the substrate 12 in the third region 24, and the dopants with the conductivity type opposite to that of the substrate 12 are implanted only into the epitaxial structures 36, but not into the upper portions of the substrate 12 in the first region 20 and the third region 24. The dopant concentration of the aforementioned heavily doped region is greater than the dopant concentrations of the first well region 14 and the second well region 16.The production of the BJT 10 can be completed.

[0025] As mentioned above, the BJT 10 in this embodiment is a pnp transistor. Thus, the substrate 12 is an n-type substrate, the first well region 14 is an n-type well region, the second well region 16 is a p-type well region, the heavily doped region of the first region 20 is a p+ region, the heavily doped region of the epitaxial structures 36 of the second region 22 is an n+ region, and the heavily doped region of the third region 24 is a p+ region. However, the present disclosure is not limited thereto. In other embodiments, the conductivity types of the substrate 12, the first well region 14, the second well region 16, the heavily doped regions of the first region 20 and the third region 24, and the heavily doped region of the epitaxial structures 36 may be reversed, so that the BJT 10 is an npn transistor.

[0026] Furthermore, in this embodiment, the heavily doped regions of the first region 20 and the third region 24 are formed before the epitaxial structures 36 are formed. In other embodiments, the heavily doped regions of the first region 20 and the third region 24 may also be formed after the formation of the epitaxial structures 36.

[0027] The aforementioned layers, such as the insulating structures 50 and 52 and the epitaxial layer 36, can be formed using any suitable processes. These processes may include, but are not limited to, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), hydride vapor epitaxy (HVPE), and atomic layer deposition (ALD).

[0028] At the same time, attention should be paid to the Fig. 6 and Fig. 7. Fig. 6 is a schematic cross-sectional view illustrating the BJT 10 according to an embodiment of the present disclosure. Fig. Figure 7 is a schematic top view showing the Fig. 6 illustrates BJT 10. Fig. Figure 6 is a schematic view of a cross section along the line AA' in Fig. 7. For simplification, the Fig. 6 illustrated epitaxial structures 36 in Fig. 7 omitted.

[0029] The BJT 10 includes the emitter region ER, the base region BR, the collector region CR, and the plurality of fin structures 32 and 34. The emitter region ER is arranged on the substrate 12. The base region BR surrounds the emitter region ER. The collector region CR surrounds the base region BR. The plurality of fin structures 32 and 34 are arranged in the base region BR and surround the emitter region ER, and the plurality of fin structures 32 and 34 extend fixedly along the first horizontal direction D1 and parallel to each other.

[0030] The BJT 10 may further include the plurality of epitaxial structures 36 disposed on the plurality of fin structures 32 and 34, respectively, and the plurality of epitaxial structures 36 are fused together.

[0031] The plurality of fin structures 32 and 34 are arranged only in the base region BR, but not in the emitter region ER and the collector region CR. That is, the base region BR is configured as a non-planar structure, and the emitter region ER and the collector region CR are configured as planar structures. In the configuration that the fin structures are also arranged in the emitter region ER and the collector region CR, although it is advantageous to reduce the areas of the emitter region ER and the collector region in the upper viewing angle by arranging the fin structures in the emitter region ER and the collector region CR, it is unfavorable to maintain the ability of the emitter region ER and the collector region CR to withstand high voltages.Since the fin structures 32 and 34 are arranged only in the base region BR in the present disclosure, the high-voltage-withstanding capability of the emitter region ER and the collector region CR can be maintained. At the same time, the area of the base region BR at the upper viewing angle can be reduced.

[0032] In the top view of the BJT 10, the emitter region ER comprises a rectangular shape, the base region BR a rectangular ring, and the collector region CR a rectangular ring. For example, the emitter region ER may comprise a square shape, the base region BR a square ring, and the collector region CR a square ring, without limitation. The emitter region ER, the base region BR, and the collector region CR may be arranged to comprise other geometric shapes. For example, the emitter region ER may comprise a circle, and the base region BR and the collector region CR may each comprise an annulus. Fig. 7, the emitter region ER, the base region BR, and the collector region CR can be arranged concentrically. This means that in the top view of the BJT 10, the centers of the emitter region ER, the base region BR, and the collector region CR coincide.

[0033] The plurality of fin structures 32 extend fixedly along the first horizontal direction D1 and are arranged above and below the emitter region ER. The plurality of fin structures 34 extend fixedly along the first horizontal direction D1 and are arranged on the left and right sides of the emitter region ER. The fin structures 32 and the fin structures 34 surround the emitter region ER. Since the plurality of epitaxial structures 36 arranged on the fin structures 32 and 34 are fused together, the fin structures 32 and 34 surrounding the emitter region ER can be electrically connected to one another. Additional wires for electrically connecting the plurality of fin structures 32 and 34 can be omitted, which reduces the size of the BJT 10. In other embodiments, if the BJT only includes the fin structures 32 but not the fin structures 34 (ie,no fin structures 34 are arranged on the left and right sides of the emitter region ER), additional wires are required to connect the fin structures 32 arranged above the emitter region ER and the fin structures 32 arranged below the emitter region ER, which is unfavorable for reducing the size of the BJT.

[0034] In the plurality of fin structures 32 and 34, the length L1 of the fin structure 32 in the first horizontal direction D1 is greater than the length L2 of the fin structure 34 in the first horizontal direction D1. In the plan view of the BJT 10, the left end T1 of the fin structure 32 is aligned with the left end T3 of the fin structure 34 arranged on the left side of the emitter region ER, and the right end T2 of the fin structure 32 is aligned with the right end T4 of the fin structure 34 arranged on the right side of the emitter region ER.

[0035] The BJT 10 may further include the first insulating structure 40, the second insulating structure 42, and the third insulating structure 44. The first insulating structure 40 is disposed between the emitter region ER and the base region BR, the second insulating structure 42 is disposed between the base region BR and the collector region CR, and the third insulating structure 44 is disposed between two adjacent ones of the plurality of fin structures 32 and 34.

[0036] As in Fig. 6, the first insulating structure 40 comprises the step structure ST1, such that the upper surface 401 of the first insulating structure 40 comprises two horizontal surfaces instead of a single horizontal surface, and a first step difference d1 is defined between the two horizontal surfaces. Furthermore, the first structure 40 of the insulating structure has different heights in the vertical direction D3. The second insulating structure 42 comprises a step structure ST2, such that the upper surface 421 of the second insulating structure 42 comprises two horizontal surfaces instead of a single horizontal surface, and a step difference d2 is defined between the two horizontal surfaces. Furthermore, the second insulating structure 42 has different heights in the second direction D3. The third insulating structure 44 does not comprise a step structure, such that the height of the third insulating structure 44 is substantially fixed in the vertical direction D3.

[0037] The maximum height H1 of the first insulating structure 40 differs from the maximum height H2 of the second structure 42. Here, the maximum height H1 of the first insulating structure 40 is smaller than the maximum height H2 of the second insulating structure 42. The second insulating structure 42, which is arranged between the base region BR and the collector region CR, has a larger maximum height H2, which is advantageous for increasing the breakdown voltage. With the first insulating structure 40, which is arranged between the emitter region ER and the base regions BR and has a smaller maximum height H1, it is advantageous to maintain the feed-in efficiency of the emitter region ER.

[0038] The maximum height H3 of the third structure 44 is less than the maximum height H1 of the first structure 40, and the maximum height H3 of the third structure 44 is less than the maximum height H2 of the second structure 42. The maximum height H3 of the third insulating structure 44 is identical to the minimum height H5 of the first insulating structure 40 and the minimum height H6 of the second insulating structure 42. Since the height of the third insulating structure 44 is fixed in the vertical direction D3, it can also be assumed that the minimum height (unlabeled) of the third insulating structure 44 is identical to the minimum height H5 of the first insulating structure 40 and the minimum height H6 of the second structure 42.

[0039] The ratio between the maximum height H1 of the first insulating structure 40 and the maximum height H2 of the second insulating structure 42 may be between 0.4 and 0.6. The ratio of the step difference d1 to the maximum height H1 of the first insulating structure 40 may be between 0.2 and 0.3. The ratio between the step difference d2 and the maximum height H2 of the second insulating structure 42 may be between 0.1 and 0.15. According to one embodiment of the present disclosure, the step difference d1 and the step difference d2 may be 300 angstroms, the maximum height H1 of the first insulating structure 40 may be 1250 angstroms, and the maximum height H2 of the second structure 42 may be 2500 angstroms.

[0040] Referring to Fig. 8, which is a schematic cross-sectional view illustrating a BJT 10a according to another embodiment of the present disclosure. The viewing angle of Fig. 8 is the same as that of Fig. 6. The main difference between the BJT 10a and the BJT 10 is that the maximum height H2 of the second insulating structure 42 is reduced, and the maximum height H2 of the second insulating structure 42 is identical to the maximum height H1 of the first insulating structure 40. Since both the first insulating structure 40 and the second structure 42 are arranged with a lower height, the BJT 10a is advantageous in that it is suitable for a lower operating voltage and provides a higher current.

[0041] Referring to Fig. 9, which is a schematic cross-sectional view illustrating a BJT 10b according to another embodiment of the present disclosure. The viewing angle of Fig. 9 is the same as that of Fig. 6. The main difference between the BJT 10b and the BJT 10 is that the maximum height H1 of the first insulating structure 40 is increased, while the maximum height H2 of the second insulating structure 42 is reduced. In this case, it is advantageous to increase the voltages applied to the emitter region ER and the base region BR.

[0042] Referring to Fig. 10, which is a schematic cross-sectional view illustrating a BJT 10c according to another embodiment of the present disclosure. The viewing angle of Fig. 10 is the same as that of Fig.6. The main difference between the BJT 10c and the BJT 10 is that the maximum height H1 of the first insulating structure 40 is increased, and the maximum height H1 of the first insulating structure 40 is identical to the maximum height H2 of the second insulating structure 42. Since both the first insulating structure 40 and the second structure 42 are arranged with larger heights, it is advantageous to increase the voltages applied to the emitter region ER, the base region BR, and the collector region CR.

[0043] According to the above description, in the present disclosure, the heights of the first insulating structure and the second structure can be flexibly adjusted depending on the applicable voltages of the emitter region, the base region, and the collector region and the desired current supplied by the BJT.

[0044] Compared to the prior art, in the present disclosure, the fin structures are arranged only in the base region and not in the emitter region and collector region. On the one hand, it can maintain the high-voltage withstanding capability of the emitter region and collector region. On the other hand, the area of the base region in plan view can be reduced, which contributes to the downsizing of the BJT. Furthermore, in at least one of the first insulating structure arranged between the emitter region and the base region and the second insulating structure arranged between the base region and the collector region and including a step structure, it is advantageous to arrange the fin structure only in the base region and not in the emitter region and collector region.

[0045] Those skilled in the art will readily appreciate that numerous modified examples and variations of the apparatus and method can be made while retaining the teachings of the invention. Accordingly, the foregoing disclosure should be considered limited only by the scope and spirit of the appended claims.

Claims

[1] Bipolar transistor (10), comprising: an emitter region, ER, (20) arranged on a substrate (12); a base region, BR, (22) surrounding the emitter region (20); a collector region, CR, (24) surrounding the base region (22); a plurality of fin structures (32, 34) arranged in the base region (22) and surrounding the emitter region (20), the plurality of fin structures (32, 34) extending fixedly along one direction and parallel to one another; and wherein the plurality of fin structures (32, 34) are arranged only in the base region, BR, (22). [2] The bipolar transistor (10) of claim 1, wherein the plurality of fin structures (32, 34) comprises a first fin structure (32) and a second fin structure (34), and a length of the first fin structure (32) in the direction is greater than a length of the second fin structure (34) in the direction. [3] The bipolar transistor (10) of claim 2, wherein, in a plan view of the bipolar transistor (10), one end of the first fin structure (32) is aligned with one end of the second fin structure (34). [4] The bipolar transistor (10) of claim 1, further comprising: a plurality of epitaxial structures (36) each disposed on the plurality of fin structures (32, 34), the plurality of epitaxial structures (36) being fused together. [5] Bipolar transistor (10) according to claim 1, further comprising: a first insulating structure (40) arranged between the emitter region (20) and the base region (22); and a second insulating structure (42) arranged between the base region (22) and the collector region (24). [6] The bipolar transistor (10) of claim 5, wherein a maximum height of the first insulating structure (40) differs from a maximum height of the second insulating structure (42). [7] The bipolar transistor (10) of claim 5, wherein the maximum height of the first insulating structure (40) is less than the maximum height of the second insulating structure (42). [8] Bipolar transistor (10) according to claim 5, further comprising: a third insulating structure (44) arranged between two adjacent ones of the plurality of fin structures (32, 34), wherein a maximum height of the third insulating structure (44) is less than a maximum height of the first insulating structure (40), and the maximum height of the third insulating structure (44) is less than a maximum height of the second insulating structure (42). [9] Bipolar transistor (10), comprising: an emitter region, ER (20) arranged on a substrate (12); a base region, BR, (22) surrounding the emitter region (20); a collector region, CR, (24) surrounding the base region (22); a first insulating structure (40) arranged between the emitter region (20) and the base region (22); a second insulating structure (42) arranged between the base region (22) and the collector region (24), wherein at least one of the first insulating structure (40) and the second insulating structure (42) comprises a step structure; and a plurality of fin structures (32, 34), wherein the plurality of fin structures (32, 34) are arranged only in the base region (22). [10] The bipolar transistor (10) of claim 9, wherein a maximum height of the first insulating structure (40) differs from a maximum height of the second insulating structure (42). [11] The bipolar transistor (10) of claim 9, wherein a maximum height of the first insulating structure (40) is identical to a maximum height of the second insulating structure (42). [12] A method of manufacturing a bipolar transistor (10), comprising: Forming an emitter region, ER, (20) on a substrate (12); Formation of a base region, BR, (22) surrounding the emitter region (20); Forming a collector region, CR (24) surrounding the base region (22); Forming a plurality of fin structures (32, 34) arranged in the base region (22) and surrounding the emitter region (20), wherein the plurality of fin structures (32, 34) extend fixedly along one direction and parallel to one another; and wherein the plurality of fin structures (32, 34) are arranged only in the base region. [13] The method of claim 12, wherein forming the plurality of fin structures (32, 34) comprises forming a first fin structure (32) and a second fin structure (34), and a length of the first fin structure (32) in the direction is greater than a length of the second fin structure (34) in the direction. [14] The method of claim 13, wherein in a plan view of the bipolar transistor (10), an end of the first fin structure (32) is aligned with an end of the second fin structure (34). [15] The method of claim 12, further comprising: Forming a plurality of epitaxial structures (36) each disposed on the plurality of fin structures (32, 34), wherein the plurality of epitaxial structures (36) are fused together. [16] The method of claim 12, further comprising: Forming a first insulating structure (40) between the emitter region (20) and the base region (22); and Formation of a second insulating structure (42) between the base region (22) and the collector region (44). [17] The method of claim 16, wherein a maximum height of the first insulating structure (40) differs from a maximum height of the second insulating structure (42).

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