POWER SEMICONDUCTOR DEVICE

Abstract

A power semiconductor device comprising: a plurality of semiconductor modules; and a first bus bar and a second bus bar each electrically connected to a first main electrode terminal and a second main electrode terminal of each of the semiconductor modules, wherein the semiconductor modules are arranged in an array without overlap in a first direction, which is a thickness direction, and the first and second main electrode terminals protrude from a side surface of the semiconductor modules and are arranged side by side with a pitch in a second direction, which is an alignment direction of the semiconductor modules, the power semiconductor device comprising an insulating medium interposed between the first and second main electrode terminals.

Description

Background of the inventionField of the invention

[0001] The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device that ensures current handling capability of semiconductor modules and reduces heat generated in a terminal portion. Description of the state of the art

[0002] Generally, large currents flow through power semiconductor modules, such as insulated-gate bipolar transistors (IGBTs), intelligent power modules (IPMs), and transfer molded power modules (TPMs). Such a power semiconductor module includes a main electrode terminal through which a large current flows and to which a high voltage is applied, and a control terminal that controls the ON and OFF of switching devices. The control terminal is connected to an external connector and controls switching of the power semiconductor module using an external control signal.

[0003] The P terminals and N terminals of adjacent main electrode terminals are connected to respective laminated busbars. The busbars are further connected to a capacitor bank. The underside of the modules is arranged in contact with a heat sink, such as fins.

[0004] Since a large current flows through the main electrode terminals, temperature rise is a concern. Furthermore, since a high voltage is applied to the main electrode terminals, a spatial insulation distance must be maintained between the terminals for safety. Thus, increasing the terminal width is difficult.

[0005] Japanese Patent Application Laid-Open No. 2018-67990 discloses a technology for downsizing a power converter while maintaining electrical insulation between main electrode terminals by disposing insulation components between the main electrode terminals connected to bus bars and arranging the main electrode terminals to overlap with each other to narrow the distance between the main electrode terminals.

[0006] In the power converter disclosed in Japanese Patent Application Laid-Open No. 2018-67990, the alignment direction of the main electrode terminals is identical to the alignment direction of semiconductor modules. Thus, there is a limitation in arranging the insulating components between the main electrode terminals, and it has been difficult to increase the terminal width. Summary

[0007] The object of the present disclosure is to provide a power semiconductor device which ensures a current handling capacity by increasing a terminal width of a main electrode terminal of a semiconductor module and reduces heat generated in a terminal portion.

[0008] The power semiconductor device according to the present disclosure includes: a plurality of semiconductor modules; and a first bus bar and a second bus bar each electrically connected to a first main electrode terminal and a second main electrode terminal of each of the semiconductor modules, wherein the semiconductor modules are arranged without overlap in a first direction, which is a thickness direction, and the first and second main electrode terminals protrude from a side surface of the semiconductor modules and are arranged side by side with a gap in a second direction, which is an alignment direction of the semiconductor modules, wherein the power semiconductor device includes an insulating medium interposed between the first and second main electrode terminals.

[0009] In the power semiconductor device according to the present disclosure, inserting the insulating medium between the first and second main electrode terminals can shorten the spatial insulation distance and increase an electrode width, which is a length of each of the first and second main electrode terminals in the second direction.

[0010] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Brief description of the drawings Fig. 1 is a plan view illustrating a structure of a power semiconductor device according to Embodiment 1 of the present disclosure; Fig. 2 is a perspective view illustrating a structure of a connection portion between main electrode terminals of a semiconductor module and bus bars; Fig. 3 is a perspective view illustrating a structure of a connection portion between the main electrode terminals of a semiconductor module and the bus bars; Fig. 4 is a plan view of the semiconductor module; Fig. 5 is a side view of the semiconductor module in a power semiconductor device according to Embodiment 2 of the present disclosure; Fig. 6 is a plan view illustrating a structure of the power semiconductor device according to Embodiment 2 of the present disclosure; Fig. 7 is a side view of the semiconductor module in a power semiconductor device according to a modification of Embodiment 2 of the present disclosure; Fig. 8 is a plan view illustrating a structure of the power semiconductor device according to the modification of Embodiment 2 of the present disclosure; Fig. 9 is a plan view illustrating a structure of the semiconductor module in a power semiconductor device according to Embodiment 3 of the present disclosure; Fig. 10 is a side view of the semiconductor module in the power semiconductor device according to Embodiment 3 of the present disclosure; Fig. 11 is a side view of the semiconductor module in the power semiconductor device according to Embodiment 3 of the present disclosure; Fig. 12 is a side view of the semiconductor module in the power semiconductor device according to Embodiment 4 of the present disclosure; Fig. 13 is a side view of the semiconductor module in a power semiconductor device according to a modification of Embodiment 4 of the present disclosure; and Fig. 14 is a side view of the semiconductor module in the power semiconductor device according to Embodiment 4 of the present disclosure. Description of the Preferred Embodiments [Embodiment 1]

[0011] Fig. 1 is a plan view illustrating a structure of a power semiconductor device 100 according to Embodiment 1 of the present disclosure.

[0012] As in Fig. 1, the power semiconductor device 100 includes six semiconductor modules 1 mounted on an upper surface of a cooling component 4a on a cooling device 4b such as a cooling water system, and a bus bar 2a (a first bus bar) and a bus bar 2b (a second bus bar) each connected to a main electrode terminal 5a (a first main electrode terminal) and a main electrode terminal 5b (a second main electrode terminal) spaced apart from each other and protruding from the side surface of each of the semiconductor modules 1.

[0013] The bus bars 2a and 2b extend in the X direction, which is an alignment direction of the six semiconductor modules 1, and are connected to a capacitor bank, which is an array of a plurality of capacitors, at an end portion (not shown) in the Y direction orthogonal to the X direction. This capacitor bank is used, for example, as a filter capacitor of a power conversion circuit.

[0014] Each of the semiconductor modules 1 has an output terminal 10 protruding from the side surface opposite the side from which the main electrode terminals 5a and 5b protrude. The output terminals 10 of the adjacent semiconductor modules 1 are commonly connected to a terminal assembly 11. The terminal assemblies 11 are electrically connected to an outside of the power semiconductor device 100 through an external terminal assembly, which is not shown.

[0015] Fig. 2 is a perspective view illustrating a structure of a connection portion between the main electrode terminals 5a and 5b of the semiconductor module 1 and the busbars 2a and 2b. The busbars 2a and 2b are laminated in the Z direction, which is an up-and-down direction, and are electrically insulated by an insulation layer 3, called a laminator, which has an electrical resistance of approximately 100 MΩ to maintain the spatial insulation distance. In Embodiment 1, the busbar 2a is a p-potential busbar on a high-potential side, and the busbar 2b is an n-potential busbar on a low-potential side.

[0016] A composite material of a polyethylene terephthalate (PET) layer and aramid paper can be used as the insulation layer 3. The insulation layer 3 can cover not only a portion between the busbars 2a and 2b, but also the upper surfaces and the lower surfaces of the busbars 2a and 2b.

[0017] As in Fig. 2, the bus bar 2a has a structure including a plurality of bus bar terminals 21a (first bus bar terminals) extending from one edge on the side of the semiconductor module 1, and in which the upper surface of the main electrode terminal 5a of the semiconductor module 1 is connected to each of the bus bar terminals 21a.

[0018] The bus bar 2b has a structure including a plurality of bus bar terminals 21b (second bus bar terminals) extending from the edge on the side of the semiconductor module 1, and in which the upper surface of the main electrode terminal 5b of the semiconductor module 1 is connected to each of the bus bar terminals 21b.

[0019] An insulating medium 6, which is a foil-like insulating material, is interposed between the main electrode terminal 5a and the main electrode terminal 5b, which protrude from the side surface of the semiconductor module 1. The main electrode terminal 5a and the main electrode terminal 5b are connected to the bus bar 2a and the bus bar 2b, respectively. Thus, the main electrode terminal 5a has a p-type potential, and the main electrode terminal 5b has an n-type potential.Although the main electrode terminals 5a and 5b must originally be arranged with a separation distance necessary to maintain the spatial insulation distance, inserting the insulating medium 6 between the main electrode terminal 5a and the main electrode terminal 5b in the power semiconductor device 100 according to Embodiment 1 can shorten the spatial insulation distance and increase an electrode width, which is a length of each of the main electrode terminal 5a and the main electrode terminal 5b in the X direction.

[0020] The insulating medium 6 may be made of a paper material such as aramid paper and resin paper, or a resin such as a nylon layer, a polyester layer, or a polyphenylene sulfide (PPS) layer, and may have a thickness at its thinnest point of approximately 100 μm. Using the film-like insulating medium 6 can prevent an increase in manufacturing costs.

[0021] The insulating medium 6 can be thick enough to ensure the breakdown voltage. As the insulating medium 6 is thicker, the breakdown voltage increases. Thus, the insulating medium 6 can be at most as thick as the distance between the adjacent main electrode terminals 5a and 5b. Furthermore, the length of the insulating medium 6 in the Y direction can be as long as that of each of the main electrode terminals 5a and 5b in the Y direction.

[0022] Here, the semiconductor modules 1 are arranged without overlapping in the Z direction, which is a thickness direction in the power semiconductor device 100. The main electrode terminals 5a and 5b are arranged side by side in the X direction, which is an alignment direction of the semiconductor modules 1. The terminal surfaces of the main electrode terminals 5a and 5b do not overlap with each other. Since the insulating medium 6 is arranged between the main electrode terminals 5a and 5b in the X direction, which is an alignment direction of the main electrode terminals 5a and 5b, thinning the insulating medium 6 as much as possible while the insulating medium 6 can maintain the breakdown voltage can significantly increase the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction.

[0023] This allows the larger current to flow and can increase the amount of heat dissipation in a terminal portion and reduce the heat without increasing the dimensions of the semiconductor modules 1.

[0024] Instead of thickening the insulating medium 6, an insulating medium 60 which is hollow and tubular may be used. Fig. 3 is a perspective view illustrating a structure of a connection portion between the main electrode terminals 5a and 5b of the semiconductor module 1 and the busbars 2a and 2b when using the hollow and tubular insulating medium 60. Setting the width of the insulating medium 60 in the X direction to be as large as the distance between the adjacent main electrode terminals 5a and 5b and setting the length of the insulating medium 60 in the Y direction to be as large as the length of each of the main electrode terminals 5a and 5b in the Y direction can completely fill the space between the main electrode terminals 5a and 5b. Using the hollow and tubular insulating medium 60 can reduce its weight.

[0025] Fixing the insulating media 6 and 60 by bonding the insulating media 6 and 60 to at least one of the main electrode terminal 5a or 5b by an adhesive can prevent the insulating media 6 and 60 from moving due to vibration, for example.

[0026] Fig. 4 is a plan view of the semiconductor module 1 when viewed from above. As shown in Fig. As shown in Fig. 4, each of the semiconductor modules 1 has a plurality of control terminals CT projecting from the side surface from which the main electrode terminals 5a and 5b project, and from the side surface from which the output terminal 10 projects. Each of the control terminals CT receives a control signal that controls ON and OFF of switching devices included in the semiconductor module 1, is bent in the Z direction orthogonal to the projecting direction (Y direction), and is connected to an external connector, which is not shown. [Embodiment 2]

[0027] Fig. 5 is a side view of the semiconductor module 1 in a power semiconductor device 200 according to Embodiment 2 of the present disclosure when viewed from the side surface from which the main electrode terminals 5a and 5b protrude.

[0028] As in Fig. 5, the main electrode terminals 5a and 5b are arranged at different positions so that the main electrode terminals 5a and 5b have a step in the Z direction, which is a thickness direction of the semiconductor module 1. An insulating medium 61 extending in the X direction, which is an alignment direction of the main electrode terminals 5a and 5b, is inserted between the main electrode terminals 5a and 5b across the step. The insertion of the insulating medium 61 allows the bus bar terminal 21b to be connected to the upper surface of the main electrode terminal 5b and allows the bus bar terminal 21a to be connected to the lower surface of the main electrode terminal 5a.

[0029] Although Fig. 5 illustrates a structure in which the main electrode terminal 5a is arranged at a higher potential closer to a bottom surface BF of the semiconductor module 1 and the main electrode terminal 5b is arranged at a lower potential from the main electrode terminal 5a, the main electrode terminals 5a and 5b may be reversed in an up-and-down direction.

[0030] By interposing the insulating medium 61 between the main electrode terminals 5a and 5b arranged at different positions with the step, the spatial insulation distance between the main electrode terminals 5a and 5b can be maintained. Thus, the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction, can be significantly increased. For example, the terminal width can be increased to such an extent that the terminal surfaces of the main electrode terminals 5a and 5b overlap with each other when viewed from the Z direction.

[0031] Consequently, the larger current can flow, and the amount of heat dissipation in a terminal portion can be increased, and the heat can be reduced without increasing the dimensions of the semiconductor modules 1. Since the insulating medium 61 is sandwiched between the main electrode terminals 5a and 5b, this further simplifies, for example, its positioning.

[0032] Fig. 6 is a plan view illustrating a structure of the power semiconductor device 200 according to Embodiment 2 of the present disclosure. In Fig. 6, the same reference numerals are used for the same structures as those of the figures referred to in Fig. 1, and the overlapping description is omitted.

[0033] As in Fig. As shown in Fig. 6, the insulating medium 61 extending in the X direction, which is an alignment direction of the main electrode terminals 5a and 5b, is interposed between the main electrode terminals 5a and 5b of each of the semiconductor modules 1 in the power semiconductor device 200. Since the insulating media 61 covers the main electrode terminals 5a, the main electrode terminals 5a cannot be visually determined.

[0034] Although the insulating media 61 may be made of the same material as that of the insulating medium 6 described in Embodiment 1, extensions of the insulating layer 3 inserted between the bus bars 2a and 2b may be the insulating media 61. Forming the insulating media 61 by extending the insulating layer 3 can save a process of inserting the insulating media 61 and eliminate the manufacturing step. [Modifications]

[0035] Fig. 7 is a side view of the semiconductor module 1 in a power semiconductor device 201 which is a modification of Embodiment 2 of the present disclosure, when viewed from the side surface from which the main electrode terminals 5a and 5b protrude.

[0036] As in Fig. As shown in Figure 7, the main electrode terminals 5a and 5b are arranged at different positions so that the main electrode terminals 5a and 5b have a step in the Z direction, which is a thickness direction of the semiconductor module 1, and the control terminals CT are arranged closer to the bottom surface BF of the semiconductor module 1 in the Z direction so as to form the same plane as the main electrode terminal 5a. Then, an insulating medium 62 extending in the X direction is interposed between the control terminals CT and the main electrode terminals 5a and 5b arranged at the different positions in the Z direction. The insulating medium 62 is arranged to cover the main electrode terminals 5a and the control terminals CT.The insertion of the insulating medium 62 enables the bus bar terminal 21b to be connected to the upper surface of the main electrode terminal 5b and enables the bus bar terminal 21a to be connected to the lower surface of the main electrode terminal 5a.

[0037] Inserting the insulating medium 62 between the main electrode terminals 5a and 5b arranged at different positions in the Z direction can maintain the spatial insulation distance between the main electrode terminals 5a and 5b. Thus, the power semiconductor device 201 is identical to the power semiconductor device 200 according to Embodiment 2 in that the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction, can be significantly increased.

[0038] Fig. 8 is a plan view illustrating a structure of the power semiconductor device 201 according to a modification of Embodiment 2 of the present disclosure. In Fig. 8, the same reference numerals are used for the same structures as those of the figures referred to in Fig. 1 is used, and the overlapping description is omitted.

[0039] As in Fig. As shown in Fig. 8, in the power semiconductor device 201, the insulating medium 62 extending in the X direction is interposed between the control terminals CT and the main electrode terminals 5a and 5b of each of the semiconductor modules 1. Since the insulating media 62 covers the main electrode terminals 5a, the main electrode terminals 5a cannot be visually determined.

[0040] As in Fig. 8, since the insulating media 62 can be continuously arranged over the entire connection portion of the array of the semiconductor modules 1, the mountability is more improved than the power semiconductor device 200 according to Embodiment 2 in which the insulating medium 61 is arranged for each of the semiconductor modules 1.

[0041] In the semiconductor module 1 in Fig. 7, the main electrode terminal 5b at a lower potential is located closer to the control terminals CT, and the main electrode terminal 5a at a higher potential is located away from the control terminals CT at intervals in the X direction. When the main electrode terminal 5a is located closer to the control terminals CT, covering the control terminals CT with the insulating medium 62 can produce advantages of maintaining the spatial insulation distance between the main electrode terminal 5a and the control terminals CT and preventing breakdown between the main electrode terminal 5a and the control terminals CT.

[0042] Although the insulating media 62 may be made of the same material as that of the medium 6 described in Embodiment 1, extensions of the insulating layer 3 inserted between the bus bars 2a and 2b may be the insulating media 62. Forming the insulating media 62 by extending the insulating layer 3 can save a process of inserting the insulating media 62 and eliminate the manufacturing step. [Embodiment 3]

[0043] Fig. 9 is a plan view illustrating a structure of the semiconductor module 1 in a power semiconductor device 300 according to Embodiment 3 of the present disclosure when viewed from above.

[0044] Each of Fig. 10 and Fig. 11 is a side view of the semiconductor module 1 in Fig. 9 when viewed from a side surface of a long side orthogonal to side surfaces of short sides from which the main electrode terminals 5a and 5b and the output terminal 10 protrude. Fig. 10 is a side view corresponding to a cross-sectional view taken along a line AA in Fig. 9 is recorded, and Fig. 11 is a side view corresponding to a cross-sectional view taken along a line BB in Fig. 9. The illustration of an internal structure of the semiconductor module 1 is omitted for simplification.

[0045] As in Fig. As shown in FIGS. 9 to 11, an injection-molding resin MD that seals the semiconductor module 1 covers the main electrode terminal 5b except its tip, and the bus bar terminal 21b is connected to the tip. The main electrode terminal 5a is not covered with the injection-molding resin MD, and the bus bar terminal 21a is connected to an entire portion protruding from the side surface of the semiconductor module 1. The main electrode terminal 5a may be covered with the injection-molding resin MD.

[0046] As such, covering at least one of the main electrode terminals 5a or 5b with a resin can further shorten the spatial insulation distance between the main electrode terminals 5a and 5b and can increase the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction. Furthermore, extending the bus bar terminal 21a closer to the semiconductor module 1 and connecting the bus bar terminal 21a to the main electrode terminal 5a can thicken the terminal portion, further increase current carrying capacity, and further suppress temperature rise. [Embodiment 4]

[0047] Fig. 12 is a side view of the semiconductor module 1 in a power semiconductor device 400 according to Embodiment 4 of the present disclosure when viewed from the side surface from which the main electrode terminals 5a and 5b protrude.

[0048] As in Fig. As shown in Fig. 12, connection positions of the main electrode terminals 5a and 5b in the Z direction, which is a thickness direction of the semiconductor module 1, are identical in the semiconductor module 1. An insulating medium 63, which has a bend with a step in the Z direction, which is an up-and-down direction, and which extends in the X direction, is interposed between the main electrode terminals 5a and 5b in the semiconductor module 1.

[0049] The insulating medium 63 has a step such that the insulating medium 63 covers the upper surface of the main electrode terminal 5a and the lower surface of the main electrode terminal 5b. Inserting the insulating medium 63 allows the bus bar terminal 21b to be connected to the upper surface of the main electrode terminal 5b and allows the bus bar terminal 21a to be connected to the lower surface of the main electrode terminal 5a.

[0050] Inserting the insulating medium 63 between the main electrode terminals 5a and 5b with the step in the Z direction can maintain the spatial insulation distance between the main electrode terminals 5a and 5b. Thus, the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction, can be increased.

[0051] Consequently, the larger current can flow, and the amount of heat dissipation in the terminal portion can be increased, and the heat can be reduced without increasing the dimensions of the semiconductor modules 1.

[0052] Although the insulating medium 63 may be made of the same material as that of the medium 6 described in Embodiment 1, an extension of the insulating layer 3 interposed between the bus bars 2a and 2b may be the insulating medium 63. Forming the insulating medium 63 by extending the insulating layer 3 can save a process of inserting the insulating medium 63 and eliminate the manufacturing step. [Modifications]

[0053] Fig. 13 is a side view of the semiconductor module 1 in a power semiconductor device 401 which is a modification of Embodiment 4 of the present disclosure, when viewed from the side surface from which the main electrode terminals 5a and 5b protrude.

[0054] As in Fig. As shown in Fig. 13, connection positions of the main electrode terminals 5a and 5b in the Z direction, which is a thickness direction of the semiconductor module 1, are identical in the semiconductor module 1. An insulating medium 64, which has a bend with a step in the Z direction, that is, an up-and-down direction, and which extends in the X direction, is interposed between the main electrode terminals 5a and 5b in the semiconductor module 1.

[0055] The insulating medium 64 has a step such that the insulating medium 64 covers the lower surface of the main electrode terminal 5a and the upper surface of the main electrode terminal 5b. Inserting the insulating medium 64 allows the bus bar terminal 21b to be connected to the lower surface of the main electrode terminal 5b and allows the bus bar terminal 21a to be connected to the upper surface of the main electrode terminal 5a.

[0056] Inserting the insulating medium 64 between the main electrode terminals 5a and 5b with the step in the Z direction can maintain the spatial insulation distance between the main electrode terminals 5a and 5b. Thus, the terminal width, which is the length of each of the main electrode terminals 5a and 5b in the X direction, can be increased.

[0057] Consequently, the larger current can flow, and the amount of heat dissipation in the terminal portion can be increased, and the heat can be reduced without increasing the dimensions of the semiconductor modules 1.

[0058] Although the insulating medium 64 may be made of the same material as that of the medium 6 described in Embodiment 1, an extension of the insulating layer 3 interposed between the bus bars 2a and 2b may be the insulating medium 64. Forming the insulating medium 64 by extending the insulating layer 3 can save a process of inserting the insulating medium 64 and eliminate the manufacturing step. [Embodiment 5]

[0059] Fig. 14 is a side view of the semiconductor module 1 in a power semiconductor device 500 according to Embodiment 5 of the present disclosure, when viewed from the side surface from which the main electrode terminals 5a and 5b protrude.

[0060] As in Fig.As shown in FIG. 14, the connection positions of the main electrode terminals 5a and 5b in the Z direction, which is a thickness direction of the semiconductor module 1, are identical in the semiconductor module 1. The bus bar terminal 21a and the bus bar terminal 21b are respectively connected to the main electrode terminal 5a and the main electrode terminal 5b so as to surround the main electrode terminal 5a and the main electrode terminal 5b. An insulating medium 65 is disposed between the adjacent bus bar terminals 21a and 21b to maintain the spatial insulation distance between the bus bar terminals 21a and 21b.

[0061] Surrounding the main electrode terminal 5a and the main electrode terminal 5b by the bus bar terminal 21a and the bus bar terminal 21b, respectively, can increase a contact area between the main electrode terminals 5a and 5b and the bus bar terminals 21a and 21b, thicken the terminal portion, and further suppress a temperature rise.

[0062] Although a distance between the bus bar terminals 21a and 21b is shortened, the insulating medium 65 enables the spatial insulation distance to be maintained.

[0063] The busbar terminal 21a and the busbar terminal 21b are preliminarily formed into a tubular shape to surround the main electrode terminal 5a and the main electrode terminal 5b, respectively. During assembly, inserting the busbar terminal 21a and the busbar terminal 21b around the main electrode terminal 5a and the main electrode terminal 5b and applying external pressure from outside the busbar terminals 21a and 21b by crimping can connect the busbar terminal 21a and the busbar terminal 21b to the main electrode terminal 5a and the main electrode terminal 5b, respectively.

[0064] Embodiments of the present disclosure may be freely combined and appropriately modified or omitted within the scope of the disclosure.

[0065] A summary of various aspects of the present disclosure is described below as appendices. [Appendix 1]

[0066] Power semiconductor device, comprising: a plurality of semiconductor modules; and a first bus bar and a second bus bar, each electrically connected to a first main electrode terminal and a second main electrode terminal of each of the semiconductor modules, wherein the semiconductor modules are arranged in an array without overlap in a first direction, which is a thickness direction, and the first and second main electrode terminals protrude from a side surface of the semiconductor modules and are arranged side by side with a spacing in a second direction, which is an alignment direction of the semiconductor modules, wherein the power semiconductor device has an insulating medium interposed between the first and second main electrode terminals. [Appendix 2]

[0067] Power semiconductor device according to Appendix 1, wherein the insulating medium is inserted between the first and second main electrode terminals in the second direction of the first and second main electrode terminals. [Appendix 3]

[0068] Power semiconductor device according to Appendix 2, wherein the insulating medium is a layered insulating material. [Appendix 4]

[0069] Power semiconductor device according to Appendix 2, wherein the insulating medium is an insulating material which is hollow and tubular. [Appendix 5]

[0070] Power semiconductor device according to Appendix 1, wherein the first and second main electrode terminals are arranged at different positions on the one side surface so that the first and second main electrode terminals have a step in the first direction of the semiconductor modules, and the insulating medium is inserted between the first and second main electrode terminals over the step so as to extend in the second direction. [Appendix 6]

[0071] Power semiconductor device according to Appendix 5, wherein each of the semiconductor modules has a plurality of control terminals projecting from the one side surface, the control terminals are arranged at positions different from positions of the first and second main electrode terminals in the second direction, and are arranged at positions identical to a position of one of the first and second main electrode terminals in the first direction, and the insulating medium extends in the second direction so that it covers the control terminals. [Appendix 7]

[0072] Power semiconductor device according to Appendix 1, wherein the first and second main electrode terminals are arranged on the one side surface at positions which are identical in the first direction of the semiconductor modules, and the insulating medium has a bend with a step in the first direction between the first and second main electrode terminals, and is inserted in each of the semiconductor modules so as to extend in the second direction. [Appendix 8]

[0073] Power semiconductor device according to Appendix 1, wherein the first bus bar has a first bus bar terminal connected to the first main electrode terminal, the second bus bar has a second bus bar terminal connected to the second main electrode terminal, the first busbar terminal is connected to the first main electrode terminal so as to surround the first main electrode terminal, the second bus bar terminal is connected to the second main electrode terminal so as to surround the second main electrode terminal, and the insulating medium is inserted between the first main electrode terminal and the second main electrode terminal, which are respectively surrounded by the first bus bar terminal and the second bus bar terminal in the second direction of the first and second main electrode terminals. [Appendix 9]

[0074] Power semiconductor device according to one of Appendices 5 to 8, wherein the first and second bus bars are arranged to oppose each other at a distance in the first direction, an insulation layer is arranged between the first and second bus bars, and an insulating medium is formed by extending a part of the insulating layer. [Appendix 10]

[0075] Power semiconductor device, comprising: a plurality of semiconductor modules; and a first bus bar and a second bus bar, each electrically connected to a first main electrode terminal and a second main electrode terminal of each of the semiconductor modules, wherein the semiconductor modules are arranged in an array without overlap in a first direction, which is a thickness direction, the first bus bar has a first bus bar terminal connected to the first main electrode terminal, the second bus bar has a second bus bar terminal connected to the second main electrode terminal, the first and second main electrode terminals are arranged side by side with a distance in a second direction, which is an alignment direction of the semiconductor modules, the first main electrode terminal protrudes from a side surface of the semiconductor modules, the second main electrode terminal except for a tip of the second main electrode terminal is covered with a molding resin, the molding resin being contained in the semiconductor modules, the first bus bar terminal is formed into a length so as to cover a protruding portion of the first main electrode terminal and to be connected to the first main electrode terminal, and the second bus bar terminal is formed into a length so as to cover the tip of the second main electrode terminal and to be connected to the second main electrode terminal.

[0076] Although the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be devised without departing from the scope of the invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-67990 [0005, 0006]

Claims

[1] Power semiconductor device, comprising: a plurality of semiconductor modules (1); and a first bus bar (2a) and a second bus bar (2b) each electrically connected to a first main electrode terminal (5a) and a second main electrode terminal (5b) of each of the semiconductor modules (1), wherein the semiconductor modules (1) are arranged in an array without overlapping in a first direction (Z-direction), which is a thickness direction, and the first and second main electrode terminals (5a, 5b) protrude from a side surface of the semiconductor modules (1) and are arranged side by side with a distance in a second direction, which is an alignment direction of the semiconductor modules (1), wherein the power semiconductor device has an insulating medium (6, 60 to 65) inserted between the first and second main electrode terminals (5a, 5b). [2] The power semiconductor device according to claim 1, wherein the insulating medium (6, 60 to 65) is interposed between the first and second main electrode terminals (5a, 5b) in the second direction of the first and second main electrode terminals (5a, 5b). [3] A power semiconductor device according to claim 2, wherein the insulating medium (6, 60 to 65) is a layered insulating material. [4] The power semiconductor device according to claim 2, wherein the insulating medium (60) is an insulating material which is hollow and tubular. [5] Power semiconductor device according to claim 1, wherein the first and second main electrode terminals (5a, 5b) are arranged at different positions on the one side surface, so that the first and second main electrode terminals (5a, 5b) have a step in the first direction of the semiconductor modules (1), and the insulating medium (61) is inserted between the first and second main electrode terminals (5a, 5b) via the step so as to extend in the second direction. [6] Power semiconductor device according to claim 5, wherein each of the semiconductor modules (1) has a plurality of control terminals (CT) projecting from the one side surface, the control terminals (CT) are arranged at positions different from positions of the first and second main electrode terminals (5a, 5b) in the second direction, and are arranged in the first direction at positions identical to a position of one of the first and second main electrode terminals (5a, 5b), and the insulating medium (62) extends in the second direction so as to cover the control terminals (CT). [7] Power semiconductor device according to claim 1, wherein the first and second main electrode terminals (5a, 5b) are arranged on the one side surface at positions which are identical in the first direction of the semiconductor modules (1), and the insulating medium (63, 64) has a bend with a step in the first direction between the first and second main electrode terminals (5a, 5b), and is inserted in each of the semiconductor modules (1) so as to extend in the second direction. [8] Power semiconductor device according to claim 1, wherein the first bus bar (2a) has a first bus bar terminal (21a) connected to the first main electrode terminal (5a), the second bus bar (2b) has a second bus bar terminal (21b) connected to the second main electrode terminal (5b), the first bus bar terminal (21a) is connected to the first main electrode terminal (5a) so as to surround the first main electrode terminal (5a), the second bus bar terminal (21b) is connected to the second main electrode terminal (5b) so as to surround the second main electrode terminal (5b), and the insulating medium (65) is inserted between the first main electrode terminal (5a) and the second main electrode terminal (5b), which are respectively surrounded by the first bus bar terminal (21a) and the second bus bar terminal (21b) in the second direction of the first and second main electrode terminals (5a, 5b). [9] Power semiconductor device according to one of claims 5 to 8, wherein the first and second bus bars (2a, 2b) are arranged to face each other at a distance in the first direction, an insulation layer (3) is arranged between the first and second bus bars (2a, 2b), and the insulating medium (61 to 65) is formed by expanding a part of the insulating layer. [10] Power semiconductor device, comprising: a plurality of semiconductor modules (1); and a first bus bar (2a) and a second bus bar (2b) each electrically connected to a first main electrode terminal (5a) and a second main electrode terminal (5b) of each of the semiconductor modules (1), wherein the semiconductor modules (1) are arranged in an array without overlapping in a first direction (Z-direction), which is a thickness direction, the first bus bar (2a) has a first bus bar terminal (21a) connected to the first main electrode terminal (5a), the second bus bar (2b) has a second bus bar terminal (21b) connected to the second main electrode terminal (5b), the first and second main electrode terminals (5a, 5b) are arranged side by side with a distance in a second direction (X direction), which is an alignment direction of the semiconductor modules (1), the first main electrode terminal (5a) protrudes from a side surface of the semiconductor modules (1), the second main electrode terminal (5b) except for a tip of the second main electrode terminal (5b) is covered with a molding resin (MD), wherein the molding resin (MD) is contained in the semiconductor modules (1), the first bus bar terminal (21a) is formed into a length so that it covers a protruding portion of the first main electrode terminal (5a) and is connected to the first main electrode terminal (5a), and the second bus bar terminal (21b) is formed into a length so as to cover the tip of the second main electrode terminal (5b) and to be connected to the second main electrode terminal (5b).

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