Multi-die transformer power modules

Abstract

In examples, a device comprises a package substrate, a first semiconductor die, and a second semiconductor die. The package substrate has opposing first and second surfaces and includes a first coil and a second coil in a first metal layer of the package substrate, and a third coil and a fourth coil in a second metal layer of the package substrate. The first coil has a set of first terminals, the second coil has a set of second terminals, the third coil has a set of third terminals, and the fourth coil has a set of fourth terminals. The first semiconductor die is coupled to the first surface and to the sets of first and second terminals. The second semiconductor die is coupled to the second surface and to the sets of third and fourth terminals.

Description

BACKGROUNDSemiconductor wafers are circular pieces of semiconductor material such as silicon used to fabricate semiconductor chips. Generally, complex manufacturing processes are used to form numerous integrated circuits on a single wafer. The formation of such circuits on a wafer is referred to as fabrication. After wafer fabrication, the wafer is cut into multiple parts called semiconductor dies, each die including one of the circuits. Slicing or sawing the wafer into individual dies is referred to as dicing. The dies are then coupled to a leadframe and covered with a mold compound, which is subsequently sawn to produce a package.SUMMARYIn examples, a device includes a package substrate, a first semiconductor die, a second semiconductor die, conductive terminals, and a molding compound. The package substrate has opposing first and second surfaces. The package substrate includes a first coil and a second coil in a first metal layer of the package substrate, the first coil having a set of first terminals and the second coil having a set of second terminals. The package substrate also includes a third coil and a fourth coil in a second metal layer of the package substrate, the third coil having a set of third terminals and the fourth coils having a set of fourth terminals. The first semiconductor die is coupled to the first surface and to the sets of first and second terminals. The second semiconductor die is coupled to the second surface and to the sets of third and fourth terminals. The conductive terminals are coupled to the package substrate. The molding compound covers at least portions of the package substrate, the first and second semiconductor dies, and the conductive terminals.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a profile cross-sectional view of an isolation device according to various examples. FIG. 1B is a top view of an isolation device according to various examples. FIG. 1C is a perspective view of an isolation device according to various examples. FIG. 2A is a profile cross-sectional view of an isolation device according to various examples. FIG. 2B is a top view of an isolation device according to various examples. FIG. 2C is a perspective view of an isolation device according to various examples. FIG. 2D is a perspective view of an isolation device according to various examples. FIG. 2E is a top view of an isolation device according to various examples. FIG. 2F is a perspective view of an isolation device according to various examples. FIG. 2G is a top view of an isolation device according to various examples. FIG. 2H is a circuit diagram of a circuit implemented in the isolation device, according to various examples. FIG. 2I includes graphs illustrating operations of the isolation device, according to various examples. FIG. 2J is a plan view of a coil of an isolation device according to various examples. FIG. 2K is a perspective view of a coil of an isolation device according to various examples. FIG. 2L is a top view of a coil of an isolation device according to various examples. FIG. 3 is a flow diagram of a method of manufacturing an isolation device according to various examples. FIGS. 4A 1-4F 3 are a process flow for manufacturing an isolation device according to various examples. FIGS. 5A and 5B are plan views of isolation device substrate coils indicating temperature, according to various examples. FIG. 6A is a graph depicting the performance of isolation devices, according to various examples. FIGS. 6B and 6C show representative isolation devices that may behave as illustrated by the curves of the graph in FIG. 6A.DETAILED DESCRIPTIONSome isolation devices include laminate transformers and optionally semiconductor dies coupled to the transformers. Some isolation devices include multiple coplanar die pads, with a first die pad coupled to a transformer, a second die pad coupled to a semiconductor die, and a third die pad coupled to another semiconductor die. Some isolation devices include multiple coplanar semiconductor dies coupled to a top surface of the transformer. Some isolation devices include transformer coils directly wire-bonded to bond pads or leads of the isolation device. These insulation devices have numerous technical disadvantages. For example, in these configurations, the dies and transformers may not adequately dissipate the heat typically generated in power applications. Moreover, in some of the isolation devices described above, bond wires are used to couple dies to the transformer. These bond wires introduce parasitic components into the isolation device by themselves, and since the bond wires are coupled in series with the coils of the transformer, the bond wires introduce inductive asymmetry and scattering in series with the magnetic components into the isolation device, which can degrade the operation of the isolation device. Thus, engineers must consider those parasitic components from bond wires during the design phase, which presents a significant technical challenge due to the limited modeling capabilities during the design phase and the additional design clearances to be considered. In some of the isolation devices described above, the semiconductor dies must be closely spaced to one another to meet spatial design constraints. When there is a voltage potential between the dies, particularly in galvanic isolation applications, this proximity between the dies forms a high electric field region between the dies, which may interfere with the operation and capability of galvanically isolating the isolation device. Moreover, in isolation devices in which the semiconductor dies are coupled to the same side of the transformer, the transformer must be specially designed to provide coil terminals for respective semiconductor dies, which may prove to be spatially demanding if fewer transformer coil layers are desired. Isolation devices developed to solve such problems suffer from their own challenges. For example, isolation devices designed to minimize the number of transformer layers suffer from severe limitations on the number of possible transformer coil turns.This disclosure describes various examples of an isolation device that alleviate the various technical challenges described above. In examples, an isolation device includes a multilevel substrate having opposing first and second surfaces. The multilevel substrate includes a first coil in a first layer of the substrate. The first coil has a first and a second terminal. A second coil in a second layer of the substrate is vertically spaced from the first layer. A second coil has a third and a fourth terminal. The substrate also includes an insulating material covering the first and second coils. The isolation device includes a first semiconductor die coupled to the first surface and to the first and second terminals, a second semiconductor die coupled to the second surface and to the third and fourth terminals, conductive terminals coupled to the multilevel substrate, and a molding compound. The molding compound covers the multilevel substrate, the first and second semiconductor dies, and the conductive terminals. Such insulation devices are technically advantageous for several reasons. First, since the first and second semiconductor dies are positioned on opposing first and second surfaces of the substrate, they allow heat dissipation from the first and second coils, respectively. Second, the electric fields generated between semiconductor dies on the same surface of the substrate as well as their adverse impact on the operation of the isolation device are significantly reduced by positioning the first and second dies on opposing surfaces of the substrate. Third, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated by positioning the first and second dies on opposing surfaces of the substrate. Fourth, since the first and second semiconductor dies are coupled to their respective terminals by metallic (e.g., solder) bumps instead of bond wires, the disadvantages introduced by the parasitic components of the bond wires described above are mitigated. Fifthly, the isolation device achieves operational symmetry, thereby mitigating the deleterious operational effects of external disturbances acting on the isolation device. Sixth, since positioning semiconductor dies on opposing surfaces of the multilayer substrate results in less complex routing of the coils in the substrate (e.g., by eliminating any need for complex coil termination configurations), fewer layers can be used in the substrate, resulting in a thinner substrate and a thinner isolation device (e.g., up to 50% thinner). The following is a description of various examples of the insulation device with reference to the drawings.FIG. 1A is a profile cross-sectional view of an isolation device 100 (e.g., a package, a packaged integrated circuit, a power module, etc.) according to various examples. The isolation device 100 may be included in any suitable electronic device or system. For example, the isolation device 100 may be included in a personal computer, a laptop, a desktop, a notebook, a tablet, a smartphone, a device (e.g., refrigerator, television, audio player, video player, video recorder, lighting device, etc.), an automobile, an aircraft, a spacecraft, etc. The isolation device 100 may include a molding compound 102 covering various structures including portions of conductive terminals (e.g., leads) 104, a semiconductor die 108 having a device side 109 in which circuitry is formed, and a semiconductor die 110 having a device side 111 in which circuitry is formed. In examples, the semiconductor dies 108, 110 may be galvanically isolated from each other and operate in different voltage domains. In examples, the semiconductor dies 108, 110 are flip-chip coupled to the substrate 112, which means that the device sides 109, 111 face the substrate 112 and that the isolation device 100 does not have bond wires. The isolation device 100 includes and the molding compound 102 covers a multilayer substrate 112, which may be a package substrate, such as a leadframe (e.g., a routable lead frame (RLF)) having opposing surfaces 113, 115. Surface 113 is coupled to semiconductor die 108 and surface 115 is coupled to semiconductor die 110. In some examples, the semiconductor dies 108, 110 overlap vertically, meaning that a vertical line perpendicular to the surfaces 113, 115 of the substrate 112 extends through both of the semiconductor dies 108, 110. In other examples, the semiconductor dies 108, 110 do not overlap vertically, which means that a vertical line perpendicular to the surfaces 113, 115 of the substrate 112 does not extend through both of the semiconductor dies 108, 110. The semiconductor dies 108, 110 are vertically separated by a distance ranging from 100 microns to 500 microns, where a distance less than this range is detrimental because the material composition of the substrate 112 limits the dielectric strength of the isolation barrier, the mechanical stability of the substrate 112, and the parasitic barrier capacitance, and where a distance above this range is detrimental to coil sizes that can be integrated into the isolation device 100 due to reduced coupling between the coils of the transformer. However, this distance is dependent on the breakdown voltage capability of the material of which the substrate 112 is made. For example, a silicon dioxide substrate 112 may have a thickness of 15-20 micrometers depending on the working stress to be used. This spacing increases in organic substrates which have a lower dielectric strength and thus lower breakdown voltages.In examples, the multilayer substrate 112 includes a plurality of transformer coils 114, 116 positioned in different layers of the substrate 112. In examples, the coil 114 is located in a metal layer of the substrate 112 that is located between the surface 113 and the surface 115 and that is located between the surface 113 and the metal layer in which the coil 116 is positioned. Similarly, in examples, the coil 116 is located in a layer of the substrate 112 that is between the surface 113 and the surface 115 and that is between the surface 115 and the layer in which the coil 114 is positioned. The coils 114, 116 are made of any suitable type of metal or metal alloy, such as copper. Any number of coils (i.e., two or more) may be useful. Each coil 114, 116 may have any suitable number of turns. In examples where more than two coils are used, each such coil may have any suitable number of turns. In examples, the coil 114 is exposed to the surface 113 and in other examples, the coil 114 is embedded in the substrate 112 such that the coil 114 is not exposed to the surface 113. In examples, the coil 116 is exposed to the surface 115 and in other examples, the coil 116 is embedded in the substrate 112 such that the coil 116 is not exposed to the surface 115. In some examples, the coils 114, 116 vertically overlap according to the above definition of vertical overlap.The substrate 112 includes conductive traces 118 and pads 119, which may be horizontally coplanar with the coil 114. The substrate 112 includes conductive traces 120 that may be horizontally coplanar with the coil 116. The conductive traces 120 are coupled to the conductive terminals 104 by, for example, soldering or any other suitable coupling technique. The conductive traces 118 may be coupled to the conductive terminals 104 via one or more of the conductive traces 120. The conductive traces 118 may be coupled to the conductive traces 120 via vias 122. Metal interconnects (e.g., bumps, posts, pillars, etc.) 124 couple the device side 109 of the semiconductor die 108 to terminals of the coil 114 and to the conductive traces 118. Similarly, metal interconnects 126 couple the device side 111 of the semiconductor die 110 to terminals of the coil 116 and to at least some of the conductive traces 120. The substrate 112 includes a dielectric material 117 (e.g., a solid material other than air, such as a AJINOMOTO® build-up film, BT laminate, or other suitable build-up film) that contacts the metal structures of the substrate 112 such as the coils 114, 116, the conductive traces 118, 120, and the vias 122. In some examples, conductive terminals 104 are coupled to surface 115, and in other examples, conductive terminals 104 are coupled to surface 113 (via metal traces 118 and additional metal traces 118 not expressly shown in FIG. 1A ).A multilayer substrate is defined as a component of a semiconductor package, the component including a plurality of metal layers formed by plating (e.g., electroplating), and further including a dielectric, such as a molding compound or film (e.g., AJINOMOTO® build-up film (ABF)), filling spaces between and around the plurality of metal layers. A multilayer substrate is different from a printed circuit board (PCB) because the multilayer package substrate is located inside the isolation device 100, whereas the PCB is located outside the isolation device 100. The multilayer substrate includes multiple metal layers separated by a solid, tangible dielectric, whereas the PCB may include multiple circuit board layers that may not be separated by a dielectric material other than air.In operation, the semiconductor die 108 provides power and / or data to and receives power and / or data from the coil 114. The semiconductor die 110 provides power to and receives power from the coil 116. When energized by the semiconductor die 108, the coil 114 generates a fluctuating magnetic field that induces a voltage in the coil 116 through mutual inductance. Similarly, when energized by the semiconductor die 110, the coil 116 generates a varying magnetic field that induces a voltage in the coil 114 through mutual inductance. The semiconductor dies 108, 110 communicate with devices external to the isolation device 100 via the conductive terminals 104. For example, the isolation device 100 may be coupled to a printed circuit board (PCB) on which one or more other devices are mounted, and the isolation device 100 may communicate with such other devices via the conductive terminals 104 and metal traces on the PCB.Because the semiconductor dies 108, 110 are positioned on opposing surfaces 113, 115, respectively, of the multilayer substrate 112, numerous technical advantages are realized. First, the positioning of the semiconductor dies 108, 110 allows for heat dissipation from the coils 114, 116, respectively. Second, minimal or no electric fields are generated between the semiconductor dies 108, 110, and thus any adverse effects on the operation of the isolation device 100 due to such electric fields are mitigated or eliminated. Third, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated by positioning the semiconductor dies 108, 110 on opposing surfaces 113, 115 of the substrate 112. Fourth, because the semiconductor dies 108, 110 are coupled to their respective terminals by metallic (e.g., solder) bumps 124, 126 instead of (or in addition to) bond wires, the disadvantages introduced by the above-described parasitic components of the bond wires are mitigated.FIG. 1B is a top view of the isolation device 100 of FIG. 1A, according to various examples. FIG. 1C is a perspective view of the isolation device 100 of FIG. 1A, according to various examples.The size and / or position of the semiconductor dies 108, 110 may vary. Positioning the semiconductor dies 108, 110 on the opposing surfaces 113, 115 of the substrate 112 eliminates any adverse effects that would otherwise result from positioning the semiconductor dies 108, 110 in proximity to each other, such as the formation of electric fields that affect the operation of the isolation device 100. For example, the semiconductor dies 108, 110 may be centered directly above and below the substrate 112, respectively, as opposed to the configuration of FIG. 1A in which the semiconductor dies 108, 110 are horizontally offset from one another (i.e., not directly centered above and below the substrate 112, respectively). The substrate 112 should be sufficiently thick to form an isolation barrier between the semiconductor dies 108, 110 that can withstand the applied voltages. The thickness of the substrate 112 varies depending on the material used to implement the isolation barrier and its dielectric strength. The thickness of the substrate 112 also varies depending on the number of routing layers implemented in the substrate 112, which may be any suitable number (e.g., 3-6 layers). Conversely, the substrate 112 should not be excessively thick to avoid an unacceptable increase in both the vertical thickness and the area of the substrate 112 of the isolation device 100 to achieve proper coupling between the coils 114, 116. FIG. 2A shows such semiconductor dies 108, 110 centered directly above and below the substrate 112, respectively. In particular, the isolation device 100 of FIG. 2A is identical to the isolation device 100 of FIG. 1A, except that the semiconductor dies 108, 110 are larger and are centered directly above and below the substrate 112, respectively, as shown. Despite this proximity of the semiconductor dies 108, 110 to each other, the vertical spacing between the dies 108, 110 provides some voltage rating between the coils 114, 116. FIG. 2B is a top view of the isolation device 100 of FIG. 2A, according to various examples. Further, FIG. 2C is a perspective view of the isolation device 100 of FIG. 2A, according to various examples.FIG. 2D is a perspective view of another example of the isolation device 100, and FIG. 2E is a plan view of the example of the isolation device 100 of FIG. 2D. As shown in FIGS. 2D and 2E, the substrate 112 of the isolation device 100 may include multiple coils 114, including coils 114 a, 114 b, 114 c, and 114 d, and multiple coils 116, including coils 116 a, 116 b, 116 c, and 116 d. The coils 114 aand 116 amay at least partially overlap each other to form a first transformer. The coils 114 band 116 bmay at least partially overlap each other to form a second transformer. The coils 114 cand 116 cmay at least partially overlap each other to form a third transformer. The coils 114 dand 116 dmay at least partially overlap each other to form a fourth transformer.Additionally, each of the coils 114 a- 114 dmay at least partially overlap with the semiconductor die 108, where the semiconductor die 108 may be coupled to terminals of the coils 114 a- 114 dvia metal interconnects 124 (e.g., solder balls, posts, pillars, etc.). For example, the semiconductor die 108 may be coupled to the terminals of the coil 114 avia metal interconnects 124 a(e.g., 124 a_ 0, 124 a_ 1, 124 a_ 2). The semiconductor die 108 may also be coupled to terminals of the inductor 114 bvia metal interconnects 124 b(e.g., 124 b_ 0, 124 b_ 1, 124 b_ 2). The semiconductor die 108 may also be coupled to terminals of the coil 114 cvia metal interconnects 124 c(e.g., 124 c_ 0, 124 c_ 1, 124 c_ 2). The semiconductor die 108 may also be coupled to terminals of the coil 114 dvia metal interconnects 124 d(e.g., 124 d_ 0, 124 d_ 1, 124 d_ 2). Each of the coils 116 a- 116 dmay also at least partially overlap with the semiconductor die 110, where the semiconductor die 110 may be coupled to terminals of the coils 116 a- 116 dvia metal interconnects 126 (e.g., solder balls, posts, pillars, etc.). In some of the examples described herein (not shown in FIG. 2D ), the semiconductor dies may be located outside the footprint of each coil and may be coupled to the coil via, for example, bond wires or other metal interconnects that extend laterally along a surface (e.g., surfaces 113 / 115) of substrate 112.In the examples shown in FIGS. 2D and 2E, each of the coils 114 a- 114 dand the coils 116 a- 116 dmay include an 8-shaped coil. The first transformer (coils 114 aand 116 a), the second transformer (coils 114 band 116 b), the third transformer (coils 114 cand 116 c), and the fourth transformer (coils 114 dand 116 d) may each be a data transformer configured to transmit data for a particular data channel. Each coil may include a pair of differential terminals and a center tap terminal aligned along a central axis of the coil. For example, as shown in FIG. 2D, metal interconnects 124 a_ 0 and 124 a_ 2 may be coupled to differential terminals of coil 114 a, and metal interconnect 124 a_ 1 may be coupled to a center tap terminal of coil 114 a. The metal interconnects 124 a_ 0, 124 a_ 1, and 124 a_ 2 and the underlying terminals of the coil 114 amay be aligned along a central axis 150 of the coil 114 a. The differential terminals may be configured to transmit or receive a pair of differential data signals related to the potential of the center tap terminal across each half of the coil (e.g., coil portions 114 a_ 0 and 114 a_ 1 of the coil 114 a). The 8-shaped coil allows the electromagnetic emission through each coil portion to cancel or at least attenuate mutually due to the transmission / reception of the differential signals having matching amplitude and opposite polarity, whereby the common mode electromagnetic emission through the coil can be reduced / eliminated.In addition, with the arrangements of FIG. 2E, the coil portion 114 a_ 0 between the center tap terminal (under metal interconnect 124 a_ 1) and one of the differential terminals (e.g., under metal interconnect 124 a_ 2) and the coil portion 114 a_ 1 between the center tap terminal and the other of the differential terminals (e.g., under metal interconnect 124 a_ 1) may be equalized, such that the parasitic capacitance and inductances of the coil portions 114 a_ 0 and 114 a_ 1 may also be equalized / equalized. Such arrangements may reduce / eliminate the common mode noise generated when the differential signals are transmitted through the 8-shaped coil, and reduce / eliminate the common mode noise when the differential signals are received through the 8-shaped coil, and improve the common mode noise immunity of the isolation device 110.Further, as shown in FIGS. 2D and 2E, the first, second, third, and fourth data transformers are respectively located at respective corners of the semiconductor dies 108 and 110 and are equidistant from the center 108 aof the semiconductor die 108 and the center 110 bof the semiconductor die 110, while the centers 108 aand 110 bmay be aligned. Such arrangements allow for matching the transmission paths between the semiconductor die 108 and each of the coils 114 a- 114 dand the transmission paths between the semiconductor die 110 and each of the coils 116 a- 116 dand the four data channels provided by the transmission paths, and improve the operation of the isolation device 100.FIG. 2F is a perspective view of another example of the isolation device 100, and FIG. 2G is a plan view of the example of the isolation device 100 of FIG. 2F. Referring to FIGS. 2F and 2G, and compared to the examples shown in FIGS. 2D and 2E, the terminals of coils 114 a- 114 dand the terminals of coils 116 a- 116 dand metal interconnects 124 a(e.g., 124 a_ 0, 124 a_ 1, 124 a_ 2), 124 b(e.g., 124 b_ 0, 124 b_ 1, 124 b_ 2), 124 c(e.g., 124 c_ 0, 124 c_ 1, 124 c_ 2), and 124 d(e.g., 124 d_ 0, 124 d_ 1, 124 d_ 2) may be moved toward the midpoints 108 a / 110 aof the semiconductor dies 108 / 110. The terminals are not aligned along a central axis (e.g., central axis 150) of the coil. Such arrangements allow for a reduction in the footprint of the semiconductor dies 108 and 110, which in turn allows the isolation device 100 to be more compact and the lengths of the conductive traces to be reduced, at the expense of introducing minor mismatches between the two halves of the coil (e.g., between the coil portions 114 a_ 0 and 114 a_ 1).In the examples shown in FIGS. 2F and 2G, the substrate 112 may also include conductive traces 118 a, 118 b, 118 c, 118 d, and 118 ein the same metal layer as the coils 114 a- 114 d. The substrate 112 may also include conductive traces 120 a, 120 b, 120 c, 120 d, and 120 ein the same metal layer as the coils 116 a- 116 d. The conductive traces 118 aand 118 bmay be coupled to the semiconductor die 108 via metal interconnects 124 eand 124 f. The conductive traces 118 cand 118 dmay be coupled to the semiconductor die 108 via metal interconnects 124 gand 124 h. The conductive traces 118 emay be coupled to the semiconductor die 108 via metal interconnects 124 iand 124 j. In the examples shown, the conductive traces 118 aand 118 bmay extend over a first side of the semiconductor die 108 and between the coils 114 aand 114 d, the conductive traces 118 cand 118 dmay extend over a second side of the semiconductor die 108 and between the coils 114 dand 114 c. Additionally, the conductive traces 120 aand 120 bmay extend over a first side of the semiconductor die 110 (and the second side of the semiconductor die 108) and between the coils 116 cand 116 d, and may overlap with the conductive traces 118 cand 118 d. Further, the conductive traces 120 cand 120 dmay extend over a second side of the semiconductor die 110 and between the coils 116 aand 116 c. The conductive traces 118 eand 120 emay extend between the coils 114 a / 114 band between the coils 116 a / 116 b.In some examples, the conductive traces 118 aand 118 bmay be data signal conductive traces for carrying data signals to be transmitted / received by the coils 114 aand 114 b. The traces 118 cand 118 dmay be data signal traces for carrying data signals to be transmitted / received by the coils 114 cand 114 d. The conductive traces 120 aand 120 bmay be data signal conductive traces for carrying data signals to be transmitted / received by the coils 116 aand 116 b. The conductive traces 120 cand 120 dmay be data signal conductive traces for carrying data signals to be transmitted / received by the coils 116 cand 116 d. Additionally, the traces 118 emay include power / ground traces for powering the semiconductor die 108, and may be coupled to a ground plane 162 in the same metal layer. Ground plane 162 is also coupled to center tap terminals and metal interconnects 124 a_ 1, 124 b_ 1, 124 c_ 1, and 124 d_ 1.FIG. 2H illustrates a circuit diagram of a circuit implemented by the isolation device 100, in accordance with some examples. The circuit may implement a data channel. As shown in FIG. 2H, the circuit may include a transmitter circuit 170, which may be part of the semiconductor die 108. Transmitter circuit 170 may have an input 170 acoupled to conductive trace 118 aand differential outputs 170 band 170 ccoupled to terminals of coil 114 avia metal interconnects 124 a_ 0 and 124 a_ 2, respectively. The center tap terminal of the coil 114 amay be coupled to a first ground via metal interconnect 124 a_ 1. Additionally, the circuit may include a receiver circuit 172, which may be part of the semiconductor die 110. The receiver circuit 172 may have different inputs 172a and 172b and an output 172c. Differential inputs 172 aand 172 bmay be coupled to terminals of coil 116 avia metal interconnects 126 a_ 0 and 126 a_ 2, respectively, and the center tap terminal of coil 116 amay be coupled to a second ground (which may be isolated from the first ground) via metal interconnect 126 a_ 1. Output 172c may be coupled to trace 120a. In operation, transmitter circuit 170 may receive a signal 174 via trace 118 aand input 170 aand output differential signals 174 aand 174 bto coil 114 a. By magnetic coupling between coils 114 aand 116 a, coil 116 acan generate differential signals 176 aand 176 bfrom differential signals 174 aand 174 b. The coil 116 amay provide the differential signals 176 aand 176 bto the differential inputs 172 aand 172 bof the receiver circuit 172. The receiver circuit 172 may generate a signal 178 from the differential signals 176 aand 176 band provide the signal 178 via the conductive trace 120 a.FIG. 2I includes graphs illustrating example operations of isolation device 100 over different data channels. Graph 180 aillustrates an example variation over time of a voltage across coil 114 aand graph 180 billustrates an example variation over time of a voltage across coil 116 a. Additionally, graph 180 cillustrates an example variation over time of a voltage across coil 114 b, and graph 180 dillustrates an example variation over time of a voltage across coil 116 b. As shown, transmission of data signals through different data channels may be time interleaved. For example, coil 114 amay transmit data signals to coil 116 aduring interval T 1 and may be inactive during interval T 2, while coil 114 bmay be inactive during interval T 1 and may transmit data signals to coil 116 bduring interval T 2, wherein intervals T 1 and T 2 do not overlap each other. Such arrangements may reduce cross-coupling between data channels and improve data transmission through isolation device 100.FIG. 2J illustrates another example of a coil, such as coil 114 a, which may be part of substrate 112. As shown in FIG. 2J, the coil 114 amay be an O-shaped coil. The coil 114 ais coupled between a pair of terminals coupled to, for example, metal interconnects 124 a_ 0 and 124 a_ 1, and may include coil segments alternating between a first metal layer and a second metal layer, such as coil segments 114 a_ 2, 114 a_ 3, 114 a_ 4, etc., in a first metal layer and coil segments 114 a_ 5, 114 a_ 6, and 114 a_ 7 in a second metal layer. The example shown in FIG. 2J may not have a center tap terminal.FIG. 2K is a perspective view of another example of the isolation device 100, and FIG. 2L is a plan view of the example of the isolation device 100 of FIG. 2K. As shown in FIGS. 2K and 2L, the substrate 112 may include the coils 114 eand 116 ein addition to the coils 114 a- 114 dand 116 a- 116 d. The coil 114 emay be in the same metal layer as the coils 114 a- 114 d, and the coil 116 emay be in the same metal layer as the coils 116 a- 116 d. Each of the coils 114 eand 116 emay include a B-shaped coil. The B-shaped coil may have two identical half coil portions, such as 114 e_ 0 and 114 e_ 1, that allow the terminals of the coil to be shifted toward one side of the coil while maintaining the alignment between the two half coil portions.The isolation device 100 also includes a semiconductor die 182 on the surface 113 and is coupled to the terminals of the coil 114 evia metal interconnects 124 mand 114 n. The isolation device 100 also includes a semiconductor die 184 on the surface 115 and is coupled to the terminals of the coils 116 evia metal interconnects. The semiconductor die 182 may overlap the terminals of the coil 114 aand the pads 119, while the semiconductor die 184 may overlap the terminals of the coil 116 aand be spaced apart from the pads 121. As shown in FIG. 2L, the coil 114 emay be offset from the pads 119 by a distance L 1 to meet an electrical isolation distance requirement, while the semiconductor die 184 may be offset from the conductive terminals 104 at an edge of the substrate 112 by a distance L 2 to meet a thermal isolation distance requirement, which may result in the center 182 aof the semiconductor die 182 being offset from the center 184 aof the semiconductor die 184.In the examples shown in FIGS. 2K and 2L, the coils 114 eand 116 emay form a power transformer configured to receive / transmit, for example, a high voltage (or high power) signal between the semiconductor dies 182 and 184. By the semiconductor die 182 overlapping the terminals of the coils 114 e, the routing distance of the high voltage / power signal can be shortened and the power loss can be reduced. In addition, since the terminals of the coil 114 eare located on a side of the coil 114 etoward the semiconductor die 182, the footprint of the semiconductor die 182 may be reduced. In addition, since the terminals of the coil 116 eare located on a side of the coil 116 etoward the semiconductor die 184, the footprint of the semiconductor die 184 may also be reduced.FIG. 3 is a flow diagram of a method 300 for manufacturing an isolation device (e.g., an isolation device 100 of FIGS. 1-2L ) according to various examples as described herein. FIGS. 4A 1-4F 3 are a process flow for manufacturing an isolation device according to various examples. Accordingly, a parallel description of Figs. 3 and 4A1-4F3 will now be given.The method 300 includes forming a substrate, such as the substrate 112, by an iterative plating (e.g., electroplating) process and depositing a dielectric film ( 302). FIG. 4A 1 is a profile cross-sectional view of the substrate 112 formed by an iterative process of electroplating and depositing a dielectric film. For example, in a first step, a seed layer may be deposited on a metal carrier, and photolithography processes may be used to plate a portion or the entirety of a first coil (e.g., coil 116) and first conductive traces (e.g., conductive traces 120) coplanar with the first coil. In a second step, a dielectric film may be deposited (e.g., by lamination) on and around the first coil and the first conductive traces. In a third step, the dielectric film and the electroplated metal may be ground. These steps may be repeated until the first coil and the first conductive traces are completely formed. Subsequently, one or more layers of dielectric film may be deposited followed by another iterative process that uses electroplating, photolithography, and grinding to form a second coil (e.g., coil 114) and second conductive traces (e.g., conductive traces 118) coplanar with the second coil. This iterative process continues until the second coil and the second conductive traces are fully formed and sufficient dielectric film has been deposited to surround and contact the second coil and the second conductive traces (e.g., until the multilayer substrate 112 of FIG. 1A or 2A has been fully formed). FIG. 4A 2 is a top view of the structure of FIG. 4A 1, according to various examples. FIG. 4A 3 is a perspective view of the structure of FIG. 4A 1, according to various examples.The method 300 includes coupling a bottom die to a bottom surface of the substrate by reflow soldering ( 304). FIG. 4B 1 is a profile cross-sectional view of the structure of FIG. 4A 1, except for the addition of the semiconductor die 110 coupled to the surface 115 of the substrate 112 by metal interconnects 126. In particular, the device side 111 of the semiconductor die 110 is coupled to the coil 116 and the metal traces 120 via metal interconnects 126, as shown. FIG. 4B 2 is a top view of the structure of FIG. 4B 1, according to various examples. FIG. 4B 3 is a perspective view of the structure of FIG. 4B 1, according to various examples.The method 300 includes coupling the substrate to a leadframe strip by reflow soldering, with the lower semiconductor die facing down to the conductive terminals of the leadframe ( 306). FIG. 4C 1 is a profile cross-sectional view of the structure of FIG. 4B 1, except that the structure of FIG. 4B 1 has been coupled to conductive terminals 104 of a leadframe strip. As shown, the conductive terminals 104 are flat, not bent as in FIG. 1A, as the conductive terminals 104 are still coupled to the leadframe strip. FIG. 4C 2 is a top view of the structure of FIG. 4C 1, according to various examples. FIG. 4C 3 is a perspective view of the structure of FIG. 4C 1, according to various examples.The method 300 includes coupling a top die to a top surface of the substrate by reflow soldering ( 308). FIG. 4D 1 is a profile cross-sectional view of the structure of FIG. 4C 1, except that the semiconductor die 108 has been coupled to the surface 113 of the substrate 112 via solder bumps 124. FIG. 4D 2 is a top view of the structure of FIG. 4D 1, according to various examples. FIG. 4D 3 is a perspective view of the structure of FIG. 4D 1, according to various examples.The method 300 includes applying a molding compound to the structures of FIG. 4D 1 ( 310). FIG. 4E 1 is a profile cross-sectional view of the structure of FIG. 4D 1, except that the molding compound 102 has been deposited to cover the various structures of FIG. 4D 1, as shown. Any suitable technique may be useful for applying the molding compound 102, such as injection molding. FIG. 4E 2 is a top view of the structure of FIG. 4E 1, according to various examples. FIG. 4E 3 is a perspective view of the structure of FIG. 4E 1, according to various examples.The method 300 includes cutting the leads from the leadframe and bending the leads ( 312). FIG. 4F 1 is a profile cross-sectional view of the structure of FIG. 4E 1, except that the conductive terminals 104 have been cut to disengage from a leadframe strip, and the conductive terminals 104 are subsequently bent to have a buckling wing shape (or other suitable shape). FIG. 4F 2 is a top view of the structure of FIG. 4F 1, according to various examples. FIG. 4F 3 is a perspective view of the structure of FIG. 4F 1 according to various examples.The scope of this disclosure is not limited to the precise manufacturing process flow shown in FIGS. 4A 1-4F 3. For example, solder paste may be stencil printed onto a substrate 112 and the substrate 112 may be coupled to the top surfaces of the leads of a leadframe (e.g., by reflowing the stencil printed solder paste applied to the substrate 112). A semiconductor die (e.g., semiconductor die 110) may be coupled to the bottom surface of the substrate 112 (i.e., the surface of the substrate 112 facing the lines). Another semiconductor die (e.g., semiconductor die 108) may be coupled to the top surface of the substrate 112 (i.e., the surface of the substrate 112 that faces away from the leads). A molding compound may then be deposited to cover the dies 108, 110, the substrate 112, the leads, and other components of the package.As described above, an advantage of coupling the semiconductor dies 108, 110 on opposing surfaces 113, 115 of the substrate 112 is increased heat dissipation from the coils 114, 116. Efficient heat dissipation is particularly useful in power applications, such as in the isolation device 100, where a significant amount of heat is generated. Positioning the semiconductor die 108 directly above the coil 114 as shown in FIGS. 1A-1C and 2A-2C promotes heat dissipation from the coil 114 and through the semiconductor die 108. Similarly, positioning the semiconductor die 110 directly below the coil 116, as shown in FIGS. 1A-1C and 2A-2C, promotes heat dissipation from the coil 116 and through the semiconductor die 110. FIGS. 5A and 5B are top views of isolation device substrate coils 116 and 114, respectively, indicating temperatures across the coils, according to various examples. As FIG. 5A shows, the portion of the coil 116 that is in vertical alignment with the semiconductor die 110 is cooler relative to the remainder of the coil 116 due to heat dissipation from the coil 116 and through the semiconductor die 110. Similarly, as FIG. 5B shows, the portion of the coil 114 that is in vertical alignment with the semiconductor die 108 is cooler relative to the remainder of the coil 114 due to heat dissipation from the coil 114 and through the semiconductor die 108.FIG. 6A is a graph 600 illustrating the performance of isolation devices, according to various examples. Graph 600 includes three sub-graphs. The three sub-graphs share a common x-axis that indicates the frequency in gigahertz (GHz). The y-axes for the two upper subgraphs indicate the voltage gain in V / V and the y-axis for the lower subgraph indicates the transimpedance in ohms. Numeral 602 indicates an example channel operating frequency for an example isolation device (e.g., isolation device 100). The third (i.e., bottom) sub-graph illustrates the transimpedance and describes the behavior of the communication channel of an exemplary isolation device that operates as a double tuned transformer. A differential current is provided to the example isolation device and resonated at a given frequency (e.g., as indicated on the x-axis) and the magnitude of the voltage response is determined at the output of the isolation device (e.g., as indicated on the y-axis). Curve 604 indicates the typical performance of a conventional isolation device in which the semiconductor dies are on the same surface of the substrate. FIG. 6B shows such a conventional isolation device that includes a substrate 620, dies 622 and 624 on the same surface of the substrate 620, coils 626 in vertical alignment with each other, and connectors 628 connecting the die 624 to one of the coils 626. The connectors 628 distort the capacitive and inductive differential symmetry of the isolation device, resulting in the poorer performance shown in graph 600, as described below. Curve 606 indicates the performance of an isolation device according to examples herein (i.e., in which the semiconductor dies are on opposing surfaces of a multilayer substrate). FIG. 6C shows such an example isolation device including a substrate 630, dies 632 and 634 on opposing surfaces of the substrate 630, and coils 636 in vertical alignment with one another positioned within the substrate 630. In the exemplary isolation device of FIG. 6C, connectors 628 are omitted, which would otherwise result in the capacitive and inductive differential asymmetry described above, thereby improving performance as described below. As shown by curves 604 and 606, the behavior of the isolation devices of FIGS. 6B and 6C does not vary significantly with respect to transimpedance.The second (i.e., middle) subgraph illustrates the common mode voltage transfer function at the halves of the receiving transformer coil (i.e., from one end of the coil to the center tap and from the opposite end of the coil to the center tap) for the frequency sweep represented on the x-axis. Curves 608, 610 represent the voltage response for the common mode voltages typical of conventional isolation devices (e.g., the isolation device of FIG. 6B ), while curves 612, 613 represent the voltage response for the common mode voltages of an example isolation device (e.g., isolation device 100 or the isolation device of FIG. 6C ). As shown, curves 608, 610 show the operational asymmetry present in conventional isolation devices (e.g., the isolation device of FIG. 6B ), as shown by the mismatch near channel operating frequency 602 and the match present at the remaining x-axis frequencies. This asymmetry leads to the operational disadvantages described above. In contrast, curves 608, 610 show the operational symmetry of example isolation devices (e.g., isolation device 100 or isolation device of FIG. 6C ) over the entire range of frequencies represented on the x-axis, including channel operating frequency 602. This operational symmetry results in the mitigation of the technical disadvantages associated with inductive asymmetry, as described above.The first (i.e. top) subgraph represents the difference between the common mode voltages (i.e. the voltage at the receiving coil). At channel operating frequency 602, curve 616 (showing the behavior in an example isolation device, such as isolation device 100 or isolation device of FIG. 6C ) has a substantially lower (e.g., 60 times lower on logarithmic graph 600) voltage than curve 614 (showing the typical behavior for a conventional isolation device, such as in FIG. 6B ), thereby confirming the symmetry shown by curves 612, 613 compared to the asymmetry shown by curves 608, 610. The nearly eliminated operational asymmetry in example isolation devices (e.g., isolation device 100) weakens the inductive asymmetry issues described above and further protects the performance of example isolation devices (e.g., isolation device 100) from external disturbances by reducing the common mode to differential mode conversion that the asymmetry would lead to. For example, in a symmetric system, external disturbances are not reflected in the difference between common mode voltages and thus do not affect the operational integrity of the example isolation devices (e.g., isolation device 100 or isolation device of FIG. 6C ).In this specification, the term "couple" may cover connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intervening component C when the intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. Other types of coupling, such as inductive, capacitive, and optical coupling, are also contemplated and are included within the scope of this disclosure.A device "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at a time of manufacture by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuring may be through firmware and / or software programming of the device, through a construction and / or layout of hardware components and interconnections of the device, or a combination thereof.Uses of the term "mass" and its variations in the foregoing description include a chassis mass, a ground mass, a floating mass, a virtual mass, a digital mass, a common mass, and / or any other form of ground connection that are applicable or suitable for the teachings of this specification. In this specification, unless otherwise indicated, "about", "about" or "substantially" prior to a parameter means a range within + / - 10% of that parameter. Modifications of the described examples as well as other examples are possible within the scope of the claims.

Claims

An apparatus comprising: a package substrate having opposing first and second surfaces, the package substrate including: a first coil and a second coil in a first metal layer of the package substrate, the first coil having a set of first terminals and the second coil having a set of second terminals; a third coil and a fourth coil in a second metal layer of the package substrate, the third coil having a set of third terminals and the fourth coils having a set of fourth terminals; a first semiconductor die coupled to the first surface and to the sets of the first and second terminals; a second semiconductor die coupled to the second surface and to the sets of the third and fourth terminals; conductive terminals coupled to the package substrate; and a molding compound covering at least parts of the package substrate, the first and second semiconductor dies, and the conductive terminals.The apparatus of claim 1, wherein each set of the first, second, third, and fourth terminals includes a respective center tap terminal, the center tap terminals of the set of the first and second terminals are coupled to a first ground plane in the first metal layer, and the center tap terminals of the set of the third and fourth terminals are coupled to a second ground plane in the second metal layer.The apparatus of claim 1, wherein the first, second, third and fourth coils each include a respective 8-shaped coil.The apparatus of claim 3, wherein each set of the first, second, third and fourth terminals is aligned along a respective central axis of the first, second, third and fourth 8-shaped coils.The apparatus of claim 3, wherein each set of the first, second, third and fourth terminals is located on a side of a respective central axis of the first, second, third and fourth 8-shaped coils.The apparatus of claim 1, wherein the first semiconductor die overlaps at least partially with the first and second coils and the second semiconductor die overlaps at least partially with the third and fourth coils.The apparatus of claim 1, wherein the first coil at least partially overlaps with the third coil to form a first transformer and the second coil at least partially overlaps with the fourth coil to form a second transformer.The device of claim 7, wherein: the package substrate further includes first and second conductive lines in the first metal layer and third and fourth conductive lines in the second metal layer; the first semiconductor die includes: a first transmitter circuit coupled between the first conductive line and the set of first terminals of the first coil; and a second transmitter circuit coupled between the second conductive line and the set of second terminals of the second coil; and the second semiconductor die includes: a first receiver circuit coupled between the set of third terminals of the third coil and the third conductive line; and a second receiver circuit coupled between the set of fourth terminals of the fourth coil and the fourth conductive line.The apparatus of claim 8, wherein the first transmitter circuit is configured to transmit a first signal to the first receiver circuit via the first transformer within a first interval, wherein the second transmitter circuit is configured to transmit a second signal to the second receiver circuit via the second transformer within a second interval spaced from the first interval.The apparatus of claim 8, wherein: the package substrate includes: a fifth coil and a sixth coil in the first metal layer of the package substrate, the fifth coil having a set of fifth terminals and the sixth coil having a set of sixth terminals; and a seventh coil and an eighth coil in the second metal layer of the package substrate, the seventh coil having a set of seventh terminals and the eighth coil having a set of eighth terminals; the fifth coil at least partially overlaps with the seventh coil to form a third transformer; the sixth coil at least partially overlaps with the eighth coil to form a fourth transformer; the first semiconductor die is coupled to the sets of the fifth and sixth terminals; and the second semiconductor die is coupled to the sets of the seventh and eighth terminals.The apparatus of claim 10, wherein: the first, second, fifth, and sixth coils at least partially overlap with first, second, third, and fourth corners, respectively, of the first semiconductor die; and the third, fourth, seventh, and eighth coils at least partially overlap with first, second, third, and fourth corners, respectively, of the second semiconductor die.The device of claim 10, wherein: the package substrate further includes fifth and sixth conductive traces in the first metal layer and seventh and eighth conductive traces in the second metal layer; the first and second conductive traces extend over a first side of the first semiconductor die and between the first and second coils; the third and fourth conductive traces extend over a first side of the second semiconductor die and between the seventh and eighth coils; the fifth and sixth conductive traces extend over a second side of the first semiconductor die and between the second and sixth coils; and the seventh and eighth conductive traces extend over a second side of the second semiconductor die and between the fourth and eighth coils.The device of claim 12, wherein the fifth and sixth conductive lines at least partially overlap with the seventh and eighth conductive lines.The apparatus of claim 12, wherein: the first semiconductor includes: a third transmitter circuit coupled between the fifth conductive trace and the set of fifth terminals of the fifth coil; a fourth transmitter circuit coupled between the sixth conductive trace and the set of sixth terminals of the sixth coil; the second semiconductor includes: a third receiver circuit coupled between the set of seventh terminals of the seventh coil and the seventh conductive trace; and a fourth receiver circuit coupled between the set of eighth terminals of the eighth coil and the eighth conductive trace.The device of claim 1, wherein the package substrate includes a third metal layer and a fourth metal layer, the first, second, third, and fourth coils each include an O-shaped coil, the first and second O-shaped coils are located in the first and third metal layers, and the third and fourth O-shaped coils are located in the second and fourth metal layers.The device of claim 1, wherein: the package substrate includes: a fifth coil in the first metal layer of the package substrate, the fifth coil having a set of fifth terminals; and a sixth coil in the second metal layer of the package substrate, the sixth coil having a set of sixth terminals; the device further comprises: a third semiconductor die coupled to the first surface and to the set of fifth terminals; and a fourth semiconductor die coupled to the second surface and to the set of sixth terminals; and the molding compound covers at least portions of the third and fourth semiconductor dies.The apparatus of claim 16, wherein the first, second, third and fourth coils each include a respective B-shaped coil and the fifth and sixth coils each include a respective 8-shaped coil.The apparatus of claim 16, wherein the third semiconductor die partially overlaps with the fifth coil and the fourth semiconductor die partially overlaps with the sixth coil.The apparatus of claim 16, wherein centers of the first and second semiconductor dies are aligned and centers of the third and fourth semiconductor dies are offset from each other.The apparatus of claim 16, wherein the first and third coils form a first data transformer, the second and fourth coils form a second data transformer, and the fifth and sixth coils form a power transformer.

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