semiconductor circuit

Abstract

In a semiconductor circuit (1) comprising a substrate (2) and a plurality of semiconductor elements (3), wherein the semiconductor elements (3) are arranged on the substrate (2), the semiconductor circuit (1) comprises two contact tabs (4.1, 4.2, 5.1, 5.2), wherein the first contact tab (4.1, 4.2) is electrically connected to a first half of the semiconductor elements (3) and wherein the second contact tab (5.1, 5.2) is electrically connected to a second half of the semiconductor elements (3).

Claims

[1] Semiconductor circuit (1) comprising a substrate (2) and a plurality of semiconductor elements (3), wherein the semiconductor elements (3) are arranged on the substrate (2), characterized by that the semiconductor circuit (1) comprises two contact tabs (4.1, 4.2, 5.1, 5.2), wherein the first contact tab (4.1, 4.2) is electrically connected to a first half of the semiconductor elements (3) and wherein the second contact tab (5.1, 5.2) is electrically connected to a second half of the semiconductor elements (3). [2] Semiconductor circuit (1) according to claim 1, characterized byin that the contact tabs (4.1, 4.2, 5.1, 5.2) contact the semiconductor elements (3) from a side facing away from the substrate (2), wherein preferably each semiconductor element (3) has a bottom side and a top side, wherein the bottom sides are typically attached to the substrate (2) and wherein the contact tabs (4.1, 4.2, 5.1, 5.2) are typically arranged on the top sides of the semiconductor elements (3). [3] Semiconductor circuit (1) according to one of the preceding claims, characterized bythat the two contact tabs (4.1, 4.2, 5.1, 5.2) are each wave-shaped, wherein each contact tab (4.1, 4.2, 5.1, 5.2) comprises a plurality of wave troughs (6.1, 6.2, 6.3) and a plurality of wave crests (7.1, 7.2), wherein each wave trough (6.1, 6.2, 6.3) advantageously contacts a respective semiconductor element (3), wherein each wave trough (6.1, 6.2, 6.3) advantageously forms a valley contact surface, wherein a distance between the substrate (2) and the wave troughs (6.1, 6.2, 6.3) is preferably smaller than a distance between the substrate (2) and the wave crests (7.1, 7.2), wherein each wave crest (7.1, 7.2) typically comprises a preferably at least substantially rectangular crest surface, wherein preferably all valley contact surfaces and all mountain surfaces are parallel to each other. [4] Semiconductor circuit (1) according to one of the preceding claims, characterized bythat the semiconductor circuit (1) comprises a signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3), wherein the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) is arranged on the substrate (2), wherein between the substrate (2) and the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) a substrate insulation layer (10) is typically arranged, wherein the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) typically comprises a source sub-substrate (8.1, 8.2, 8.3), wherein the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) typically comprises a gate sub-substrate (9.1, 9.2, 9.3), wherein typically each semiconductor element (3) comprises a source contact, wherein typically each semiconductor element (3) comprises a gate contact, wherein the source sub-substrate (8.1, 8.2, 8.3) typically interconnects all source contacts, wherein the gate sub-substrate (9.1, 9.2, 9.3) typically interconnects all gate contacts. [5] Semiconductor circuit (1) according to one of the preceding claims, characterized by that the semiconductor circuit (1), preferably the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3), comprises a source contact pin (11.1, 11.2, 11.3) and a gate contact pin (12.1, 12.2, 12.3), wherein the source contact pin (11.1, 11.2, 11.3) is electrically connected to the source sub-substrate (8.1, 8.2, 8.3) and wherein the gate contact pin (12.1, 12.2, 12.3) is electrically connected to the gate sub-substrate (9.1, 9.2, 9.3). [6] Semiconductor circuit (1) according to claim 5 characterized by that the source contact pin (11.1, 11.2, 11.3) and the gate contact pin (12.1, 12.2, 12.3) are arranged at opposite ends of the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) or that the source contact pin (11.1, 11.2, 11.3) and the gate contact pin (12.1, 12.2, 12.3) are arranged next to one another on the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3). [7] Semiconductor circuit (1) according to claim 6, characterized by that the source contact pin (11.1, 11.2, 11.3) and the gate contact pin (12.1, 12.2, 12.3) are each pressed into a sleeve (13.1, 13.2), wherein the sleeves (13.1, 13.2) are arranged on the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) and preferably point away from the substrate (2), or that the source contact pin (11.1, 11.2, 11.3) and the gate contact pin (12.1, 12.2, 12.3) are each soldered onto the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3). [8] Semiconductor circuit (1) according to one of the preceding claims, characterized by that the semiconductor circuit (1) comprises a casing (14.1, 14.2, 14.3) which at least partially encloses the semiconductor circuit (1). [9] Semiconductor circuit (1) according to claim 8, characterized bythat the casing (14.1, 14.2) is frame-shaped, wherein the casing (14.1, 14.2) preferably has direct contact with the substrate (2) and / or wherein the casing (14.1, 14.2) preferably has no direct contact with the semiconductor elements (3) and / or wherein the casing (14.1, 14.2) preferably has no direct contact with the contact tabs (4, 5) and / or wherein the casing (14.1, 14.2) preferably has no direct contact with the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) and / or wherein the casing (14.1, 14.2) preferably has no direct contact with the source contact pin (11.1, 11.2, 11.3) and / or with the gate contact pin (12.1, 12.2, 12.3). [10] Semiconductor circuit (1) according to claim 8, characterized byin that the casing (14.3) is housing-shaped, wherein the casing (14.3) preferably has direct contact with the substrate (2) and / or wherein the casing (14.3) preferably has direct contact with the semiconductor elements (3) and / or wherein the casing (14.3) preferably has direct contact with the contact tabs (5, 6) and / or wherein the casing (14.3) preferably has direct contact with the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) and / or wherein the casing (14.3) preferably has direct contact with the source contact pin (11.1, 11.2, 11.3) and / or with the gate contact pin (12.1, 12.2, 12.3). [11] Semiconductor circuit (1) according to claim 8, characterized by that the sheathing (14.3) comprises a cast insulation or is a cast insulation. [12] Semiconductor circuit (1) according to one of claims 8 to 11, characterized bythat the sheath (14.1, 14.2, 14.3) is produced by injection molding or molding or dispensing and / or that the sheath (14.1, 14.2) is made of thermoset. [13] Semiconductor circuit (1) according to one of the preceding claims, characterized by , the semiconductor circuit (1) comprises an organic insulation, wherein the organic insulation is typically suitable for electrically isolating the signal substrate (8.1, 8.2, 8.3, 9.1, 9.2, 9.3) from the substrate (2) and / or wherein the organic insulation is typically suitable for electrically isolating the substrate (2) from a cooling element (15) on which the substrate (2) is mounted. [14] Power electronics system comprising a plurality of semiconductor circuits (1) according to one of claims 1 to 13 and a busbar system, wherein the semiconductor circuits (1) are preferably inserted into the busbar system. [15] Vehicle comprising a plurality of semiconductor circuits (1) according to one of claims 1 to 13 and / or a power electronics system according to claim 14.

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