Digital-to-analog converter system and baseband transmission circuit with one main DAC and one auxiliary DAC

Abstract

The invention relates to the field of digital-to-analog converters (DACs), for example to a DAC system (500) for converting a digital input signal from a digital system input (510) into an analog output signal at an analog system output (590). The DAC system (500) comprises a main current control DAC (100), whose input (110) is connected to the digital system input (510); an active buffer (300) whose input (310) is connected to an output (190) of the main current-controlling DAC (100), wherein an output (390) of the active buffer (300) is configured to output a first current (I1) to the analog system output (590). The DAC system (500) further comprises an auxiliary current-controlling DAC (200) whose input (210) is connected to the digital system input (510), and an output (290) of the auxiliary current-controlling DAC (200) configured to output a second current (I2) to the analog system output (590). The input (210) of the auxiliary current-controlling DAC (200) is connected only to a real subset of input lines (511) of the digital system input (510).

Description

Technical area

[0001] The invention relates to the field of digital-to-analog converters (DACs), for example, to a DAC system, for example, for broadband DACs. The invention further relates to a baseband transmission circuit, a system-on-chip (SoC), and a use. background

[0002] At least for some digital-to-analog converters (DACs), high linearity is desirable and can be considered an important quality characteristic of a DAC. Since the linearity of a DAC can depend on multiple factors, this can be a challenge for many types of DACs. In particular, any measure that can help provide high linearity for DACs operating at high frequencies can be desirable.

[0003] The document US 11 196 436 B1 discloses a circuit with a digital-to-analog converter (DAC) core and with an edge-trim DAC. Summary

[0004] One example of the present disclosure relates to a digital-to-analog converter, DAC, system for converting a digital input signal from a digital system input to an analog output signal at an analog system output. The digital system input has n input lines. The DAC system includes a main current-controlling DAC having an input connected to the digital system input, and an active buffer having an input connected to an output of the main current-controlling DAC, wherein an output of the active buffer is configured to output a first current to the analog system output. The DAC system further includes an auxiliary current-controlling DAC having an input connected to the digital system input, wherein an output of the auxiliary current-controlling DAC is configured to output a second current to the analog system output.The input of the auxiliary current-controlling DAC is connected only to a real subset of input lines of the digital system input, where the real subset of input lines has k input lines. Short description of the drawings

[0005] The drawings show: Fig. 1 schematically shows a baseband transmission circuit according to an embodiment; Fig. 2 schematically shows a digital-to-analog converter, DAC, system according to an embodiment; Fig. 3 schematically shows a DAC system according to another embodiment; Fig. 4 schematically shows a DAC system according to another embodiment; Fig. 5 schematically shows a detail of a DAC system according to an embodiment; Fig. 6 schematically shows an example diagram showing an effect of the DAC system. Detailed description of embodiments

[0006] A digital-to-analog converter, or DAC, generally converts a digital input signal, which has n numbers of input lines, into an analog output signal. A DAC system can perform the same task but may have more than one DAC. The number of input lines can specify the resolution of the DAC. The analog output signal can be a current or a voltage, for example, when a high output impedance is desired. The voltage range of the DAC may depend on its specified purpose and / or the system in which the DAC is used. An example output voltage range might be from 0 V to 5 V, or, for a differential output, from -5 V to +5 V.

[0007] The DAC system comprises a main current-controlling DAC whose input is connected to the digital system input. The digital system input may be connected to a processor, e.g., a DSP (digital signal processor). The main current-controlling DAC is connected to all input lines. The main current-controlling DAC may comprise means to provide substantially high linearity, e.g., it may comprise high-precision resistors and / or semiconductors. The output of the main DAC is connected to an input of an active buffer configured to output a first current to the analog system output. The active buffer may comprise an operational amplifier (“op-amp”) whose input—and thus the input of the active buffer—may act as a so-called “virtual ground” into which the main current-controlling DAC discharges.Virtual ground is a concept that a selected node within a circuit—for example, an input of an active buffer and / or an inverting input of an op-amp—is not connected to a real ground, but is considered to have a constant voltage with respect to the real ground. Unfortunately, this may not be the case in real circuits. For example, when operating at high frequencies, the op-amp may not be fast enough to provide feedback that fully compensates for voltage fluctuations at the virtual ground. In the case of a DAC, these voltage fluctuations at the virtual ground can degrade the DAC's linearity. This effect can be relevant for DACs operating at high sampling frequencies and / or with high resolution.

[0008] The DAC system further includes an auxiliary current-controlling DAC. The input of the auxiliary DAC is connected to the digital system input. The output of the auxiliary DAC is configured to output a second current to the analog system output. The output of the auxiliary DAC is the same node as the output of the active buffer. The current of the output of the auxiliary current-controlling DAC may have an opposite direction than the current direction of the active buffer. This second current from the output of the auxiliary DAC may help compensate for fluctuations at the output of the active buffer caused by fluctuations of or at the virtual ground. The input of the auxiliary current-controlling DAC is connected to only a real subset of input lines of the digital system input, where the real subset of input lines comprises k (out of n) input lines.To improve the linearity of the DAC system, it may not be necessary to fully compensate for the fluctuations, but partial compensation can lead to an improvement in the linearity of the DAC system. For example, the DAC system described here can also be used as a high-frequency DAC. Furthermore, this can contribute to a relaxation of the gain and / or bandwidth requirements of the operational amplifier. This, in turn, can help reduce power consumption.

[0009] In various embodiments, the real subset of the input lines is an MSB section of the input lines of the digital system input, where the MSB section consists of k most significant bits (MSBs). Using the MSB section as an embodiment of the "real subset" of the digital system input can efficiently compensate for the fluctuations.

[0010] In various embodiments, the real subset of input lines consists of less than or equal to half the input lines of the digital system input. This can, on the one hand, provide sufficient compensation for the fluctuations of interest, but, on the other hand, can also enable a fairly cost-effective implementation (e.g., in terms of chip size consumption) of the auxiliary current-steering DAC.

[0011] In some embodiments, the digital system input comprises between n = 2 and n = 16 input lines, and the real subset of input lines comprises between k = 1 and k = 7 lines. For example, for n = 2, k = 1 may be selected, for n = 16, k = 7, for n = 12, k = 6 or k = 5, and so on.

[0012] In some embodiments, the digital system input comprises between n = 5 and n = 14 input lines, and the real subset of input lines comprises between k = 2 and k = 6 lines. For example, for n = 5, k = 2 may be selected, for n = 14, k = 6, for n = 10, k = 5, and so on.

[0013] In various embodiments, a voltage at the input of the active buffer is compensated using the second current from the auxiliary current-controlling DAC. The second current from the auxiliary current-controlling DAC may be similar (or in some cases, equal) to the current from the active buffer, but may have an opposite direction. This may reduce the current provided by the active buffer and therefore (as an effect) reduce the virtual ground fluctuation, thereby improving the linearity of the DAC system.

[0014] In various embodiments, the DAC system further includes a notch filter located before the analog system output of the DAC system. The notch filter may have a center frequency equal to a sampling frequency of the DAC system. This may reduce or remove the images generated by the DACs around their sampling clock.

[0015] In various embodiments, the active buffer is an active low-pass filter. This can reduce (very high-frequency) noise at the output of the main DAC, thereby reducing the effects of such unwanted noise on the DAC system.

[0016] In various embodiments, the second current is between 90% and 99% of the first current. An example of the second current may be 97% of the first current.

[0017] In various embodiments, the input lines of the main current-controlling DAC use a unary converter principle. One example of a unary converter principle could be using a so-called thermometric converter principle for the main DAC. This converter principle provides very good linearity and can also be used for high-frequency DACs.

[0018] In various embodiments, the input lines of the auxiliary current-controlling DAC use a binary conversion principle. This can save chip space for the auxiliary DAC and can also improve the linearity of the DAC system. The effect of saving chip space can be even greater if the input of the auxiliary current-controlling DAC is only connected to a real subset of the input lines of the digital system input, thus requiring fewer "sub-DACs" in the auxiliary DAC chip area, thereby reducing the size of this part of the chip.

[0019] In various embodiments, the auxiliary current-controlling DAC further comprises a low-pass filter. The low-pass filter is arranged before the output of the auxiliary current-controlling DAC. The low-pass filter can be a passive first-order RC filter. The low-pass filter can contribute to improving image rejection at the output of the auxiliary DAC.

[0020] In various embodiments, the auxiliary current-controlling DAC further comprises an output mirror. The output mirror is arranged before the output of the auxiliary current-controlling DAC. Thus, the output current of the sub-DACs—e.g., one sub-DAC per bit—is summed and passed to the output mirror. The output mirror can comprise one or more n-MOSFETs. The output mirror can be implemented as a double mirror. The output mirror can increase the DAC output impedance. The output mirror circuit comprises the low-pass filter of the auxiliary DAC, which can be a passive first-order RC filter. This low-pass filter can improve image rejection.

[0021] In various embodiments, the DAC system supports a sampling frequency between 1 MHz and 1 GHz. In one embodiment, the DAC system supports a sampling frequency between 5 MHz and 200 MHz. This applicability to such high frequencies makes the DAC system suitable for a wide range of applications. Of course, the DAC system can also be used within systems with lower or higher frequencies.

[0022] In various embodiments, the digital system input is configured as a differential digital input and / or the analog system output is configured as a differential analog output. Differential inputs and / or outputs can be implemented in systems requiring high data rates, high noise immunity, and / or low electromagnetic interference.

[0023] In various embodiments, the input of the main current-controlling DAC is connected to all input lines of the digital system input, i.e., k = n. This can further improve the linearity of the DAC system.

[0024] One aspect relates to a baseband transmit (TX) circuit. The baseband transmit circuit includes a digital signal processor (DSP) configured to output a digital number, the digital number having an output width of n bits, and a DAC system as described above and / or below. An input of the DAC system has an input width of n bits and is connected to an output of the DSP. The baseband transmit circuit further includes a low-pass filter connected to an output of the DAC system and a modulator configured to mix an output of the low-pass filter with an output of a local oscillator. An output of the modulator is connected to an amplifier and is configured to provide an antenna signal to an antenna, the antenna configured to transmit the antenna signal.The baseband transmit circuit can be connected and / or combined with a corresponding receive (RX) circuit, thereby constructing a wireless system unit.

[0025] One aspect relates to a system-on-chip, SoC, system comprising a digital-to-analog converter, DAC, system as described above and / or below.

[0026] One aspect relates to a use of a digital-to-analog converter, DAC, system as described above and / or below for a baseband transmit circuit, for a WiFi system, for a Bluetooth-based system, for a wideband base transmit circuit with high linearity, for an ultra-wideband system, for a cellular system, for an Ethernet system and / or for a cable modem system.

[0027] It should be noted that two or more of the embodiments described above and / or below may be combined, as far as technically possible.

[0028] For further explanation, the disclosure will be described with reference to embodiments shown in the figures. These embodiments are to be considered only as examples and not as limiting.

[0029] Fig. 1 schematically shows a baseband transmit circuit 600 according to one embodiment. The baseband transmit circuit 600 comprises a processor 610, for example, a digital signal processor, DSP, or any other type of processor capable of or configured to output a digital number. The digital number has an output width of n bits. The baseband transmit circuit 600 further comprises a DAC system 500, as described above and / or below. The DAC system 500 has an input 510 with an input width of n bits. The DAC system 500 is connected to an output of the DSP 610. A low-pass filter 620 is connected to an output 590 of the DAC system 500. The output of the low-pass filter 620 is connected to a modulator or mixer 630 configured to mix the output of the low-pass filter 620 with an output of a local oscillator LO.The output of modulator 630 provides a high frequency intended to be transmitted by a suitable antenna. To this end, the output of modulator 630 is connected to an amplifier 640 configured to provide an antenna signal to an antenna 650. Antenna 650 is configured to transmit the antenna signal.

[0030] Fig. 2 schematically shows a digital-to-analog converter (DAC) system 500 according to one embodiment. The DAC system 500 is adapted and / or configured to convert a digital input signal from a digital system input 510 into an analog output signal at an analog system output 590. The digital system input 510 has n input lines and thus a resolution of n bits. The DAC system 500 comprises a main current control DAC 100, whose input 110 is connected to the digital system input 510. The main DAC 100 may have a sampling frequency CLK of, for example, between 1 MHz and 1 GHz. An output 190 of the main current control DAC 100 is connected to the input 310 of an active buffer 300. The active buffer 300 comprises an op-amp 320 and a resistor R1 in the op-amp's feedback loops. The input 310 of the active buffer 300 may be the same node as an inverting input of the op-amp 320.The input 310 of the active buffer 300 can act as a virtual ground. The active buffer 300 is configured to output, at its output 390, a first current I1 to an output 580. In some embodiments, the output 580 can be identical to an analog system output 590. In the illustrated embodiment, the analog system output 590 is configured as a differential output with terminals 591 and 592.

[0031] In the embodiment shown, a notch filter 400 is arranged before the analog system output 590 of the DAC system 500, ie here: between the output node 580 and the analog system output 590. The notch filter 400 has a center frequency equal to a sampling frequency CLK of the DAC system 500.

[0032] The DAC system 500 further comprises an auxiliary current-controlling DAC 200, whose input 210 is connected to the digital system input 510. In the embodiment shown, only a real subset of the n input lines of the digital system input 510 is routed to the digital system input 510, namely only a portion 511 consisting of k (of the n) input lines. The auxiliary DAC 200 has the same sampling frequency CLK as the main DAC 100. The portion 512 of the input lines is only routed to and used by the main current-controlling DAC 100. An output 290 of the auxiliary DAC 200 is configured to output a second current I2 to the analog system output 590 (here: 580). Since in the embodiment of Fig. 2, the input 210 of the auxiliary current-controlling DAC 200 is only connected to a real subset of input lines 511 (having k input lines) of the digital system input 510, the first current I1 may not be fully compensated by the second current I2, but only partially. For at least some DAC systems, the second current I2 may be in a range between 90% and 99%—approximately 97%—of the first current I1. The second current I2 may compensate for fluctuations in the first current I1 from the active buffer 300. These fluctuations may be caused by fluctuations in the virtual ground 310. This may improve the linearity of the DAC system 500, e.g., compared to a linearity of a DAC system using only the main current-controlling DAC 100.

[0033] Fig. Figure 3 schematically shows a DAC system 500 according to another embodiment. The DAC system 500 is similar to the DAC system 500 of Fig. 2 quite similar. The same reference numerals denote similar or identical components. One difference to Fig. 2 is that the embodiment of Fig. 3 single-ended inputs 510 and one single-ended output 590 (or 580) compared to the differential inputs and outputs of the DAC system 500 of Fig. 2.

[0034] Fig. Figure 4 schematically shows a DAC system 500 according to another embodiment. The DAC system 500 is similar to the DAC system 500 of Fig. 2 quite similar. The same reference numerals denote similar or identical components. One difference to Fig. 2 is that the active buffer 300 is designed as an active low-pass filter. The low-pass filter 300 has an op-amp 320. In the feedback loops of the op-amp 320, in addition to a resistor R1 (as in Fig. 2) a capacitor C1 is arranged.

[0035] Fig. Figure 5 schematically shows a detail of a DAC system 500 according to an embodiment. In particular, Fig. 5 schematically shows a part of the auxiliary current control DAC 200 with differential outputs. Some details of the auxiliary DAC 200 are shown in Fig. 5 is neglected, e.g., an input of the sampling clock CLK. The auxiliary DAC 200 receives a plurality of input lines at its input 210, e.g., k input lines from the DAC system input 510. The auxiliary DAC 200 may have a plurality of k sub-DACs, e.g., one sub-DAC per bit. Their current is summed at outputs 260. The outputs 260 are fed to an output mirror circuit 270. The output mirror circuit 270 is arranged before the outputs 290 of the auxiliary current-controlling DAC 200, i.e., between the outputs 260 and the outputs 290 of the auxiliary DAC 200. In the embodiment of Fig. 5, the output mirror is implemented as a double mirror. The FETs of the double mirror can be implemented as n-MOSFETs. The output mirror circuit 270 includes low-pass filters 280 of the auxiliary DAC, which can be, for example, passive first-order RC filters. In one embodiment (not shown), only low-pass filters 280 can be arranged between the outputs 260 and the outputs 290 of the auxiliary DAC 200.

[0036] Fig. 6 schematically shows an example diagram 700 illustrating an effect of a DAC system 500 (see, e.g., Fig. 2) based on a simulation of a conventional DAC system and on a simulation of a DAC system 500 according to an embodiment described above. The x-axis of Fig.6 shows an input frequency fin of the DAC system 500; its y-axis shows a spurious-free dynamic range (SFDR) of the DAC system 500. Curve 710 shows the SFDR of a conventional DAC system versus the input frequency fin. For example, curve 710 shows that an SFDR above 80 dB can only be achieved within a frequency range between about 2 MHz and about 10 MHz. Curve 730 shows the SFDR of the DAC system 500 according to an embodiment described above. It is clearly visible that the SFDR is higher than 90 dB up to about 15 MHz and even higher than 100 dB within a frequency range between about 6 MHz and about 4.5 MHz. Arrow 720 emphasizes the improvement of the DAC system 500 according to an embodiment described above compared to a conventional DAC system. Other embodiments of the DAC system 500 may be designed and / or optimized for other, for example, higher, frequency ranges.

Claims

[1] Digital-to-analog converter, DAC, system (500) for converting a digital input signal from a digital system input (510) into an analog output signal at an analog system output (590), wherein the digital system input (510) has n input lines, and wherein the DAC system (500) has: a main current controlling DAC (100) whose input (110) is connected to the digital system input (510); an active buffer (300) whose input (310) is connected to an output (190) of the main current-controlling DAC (100), wherein an output (390) of the active buffer (300) is configured to output a first current (I1) to the analog system output (590); and an auxiliary current-controlling DAC (200) whose input (210) is connected to the digital system input (510), wherein an output (290) of the auxiliary current-controlling DAC (200) is configured to output a second current (I2) to the analog system output (590), wherein the input (210) of the auxiliary current controlling DAC (200) is connected only to a real subset of input lines (511) of the digital system input (510), wherein the real subset of input lines (511) has k input lines. [2] DAC system (500) according to claim 1, wherein the real subset of the input lines (511) is an MSB section of the input lines of the digital system input (510), wherein the MSB section consists of k most significant bits, MSBs. [3] DAC system (500) according to claim 1 or 2, wherein the real subset of the input lines (511) consists of less than or equal to half of the input lines of the digital system input (510). [4] DAC system (500) according to any of the preceding claims, wherein the digital system input (510) has between n=2 and n=16 input lines and the real subset of input lines (511) has between k=1 and k=7 lines. [5] DAC system (500) according to any of the preceding claims, wherein the digital system input (510) has between n=5 and n=14 input lines and the real subset of input lines (511) has between k=2 and k=6 lines. [6] DAC system (500) according to one of the preceding claims, wherein a voltage at the input (310) of the active buffer (300) is compensated by means of the second current (I2) from the auxiliary current control DAC (200). [7] DAC system (500) according to any one of the preceding claims, further comprising: a notch filter (400) arranged in front of the analog system output (590) of the DAC system (500), wherein the notch filter (400) has a center frequency equal to a sampling frequency of the DAC system (500). [8] DAC system (500) according to one of the preceding claims, wherein the active buffer (300) is an active low-pass filter. [9] DAC system (500) according to any of the preceding claims, wherein the second current (I2) is between 90% and 99% of the first current (I1). [10] DAC system (500) according to one of the preceding claims, wherein the real subset of the input lines (511) of the main current controlling DAC (100) uses a unary converter principle. [11] DAC system (500) according to one of the preceding claims, wherein the real subset of the input lines (511) of the auxiliary current-controlling DAC (200) uses a binary converter principle. [12] DAC system (500) according to one of the preceding claims, wherein the auxiliary current controlling DAC (200) further comprises a low-pass filter (280), wherein the low-pass filter (280) is arranged upstream of the output (290) of the auxiliary current controlling DAC (200). [13] DAC system (500) according to claim 12, wherein the auxiliary current controlling DAC (200) further comprises an output mirror (270), wherein the output mirror (270) is arranged upstream of the output (290) of the auxiliary current controlling DAC (200) and comprises the low-pass filter (280). [14] DAC system (500) according to any of the preceding claims, wherein the DAC system (500) supports a sampling frequency between 1 MHz and 1 GHz. [15] DAC system (500) according to any of the preceding claims, wherein the digital system input (510) is designed as a differential digital input and / or the analog system output (590) is designed as a differential analog output. [16] DAC system (500) according to one of the preceding claims, wherein the input (110) of the main current controlling DAC (100) is connected to all input lines of the digital system input (510). [17] Baseband transmit circuit (600), comprising: a digital signal processor, DSP (610) configured to output a digital number, wherein the digital number has an output width of n bits; a DAC system (500) according to one of the preceding claims, wherein an input (510) of the DAC system (500) has an input width of n bits and is connected to an output of the DSP (610); a low-pass filter (620) connected to an output (590) of the DAC system (500); a modulator (630) configured to mix an output of the low-pass filter (620) with an output of a local oscillator (LO); an amplifier (640) connected to an output of the modulator (630) and configured to provide an antenna signal; and an antenna (650) which is connected to an output of the amplifier (640) and is configured to transmit the antenna signal. [18] System-on-Chip, SoC, system comprising a digital-to-analog converter, DAC, system (500) according to any one of claims 1 to 16. [19] Use of a digital-to-analog converter, DAC, system (500) according to any one of claims 1 to 16 for a baseband transmit circuit (600), for a WiFi system (600), for a Bluetooth-based system (600), for a high linearity broadband baseband transmit circuit, for an ultra-wideband system, for a cellular system, for an Ethernet system and / or for a cable modem system.

Images