CHANNEL INSULATION STRUCTURES IN STACK RANSISTORS

Abstract

Channel isolation structures and methods for their fabrication are provided. A device comprises a multilayer stack containing: a first plurality of nanostructures; a second plurality of nanostructures above the first plurality of nanostructures; and a first channel isolation structure. The device further comprises: first source / drain regions at opposite ends of the first plurality of nanostructures; second source / drain regions above the first source / drain regions, the second source / drain regions being located at opposite ends of the second plurality of nanostructures; a first gate structure surrounding the first plurality of nanostructures; and a second gate structure surrounding the second plurality of nanostructures. The first gate structure contacts a first side face of the first channel isolation structure.

Description

Priority claim and cross-reference

[0001] The present application claims priority over the preliminary US patent application filed on September 27, 2024, under file number 63 / 700.005, which is incorporated by reference into the present application. background

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0003] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thus enabling the integration of more components in a given area. As the semiconductor industry progresses toward higher device density, increased performance, and lower costs, manufacturing and design challenges have led to stacked device configurations, such as stacked transistors containing complementary field-effect transistors (CFETs). Reducing the minimum feature size allows for the integration of additional structural elements. Brief description of the drawings

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a perspective view of an exemplary stacked transistor according to some embodiments. The Fig. Figures 2 to 8 are representations of intermediate stages in the manufacture of stacked transistors according to some embodiments. The Fig. Figures 9 to 15 are illustrations of intermediate stages in the manufacture of stacked transistors according to some embodiments. The Fig. Figures 16 to 18 are illustrations of intermediate stages in the manufacture of stacked transistors according to some embodiments. The Fig. Figures 19 to 21 are illustrations of intermediate stages in the manufacture of stacked transistors according to some embodiments. The Fig. Figures 22 to 24 are illustrations of intermediate stages in the manufacture of stacked transistors according to some embodiments. The Fig. 25, Fig. 26, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28, Fig. 29A, Fig. 29B and Fig. 29C are representations of intermediate stages in the manufacture of stacked transistors according to some embodiments. Detailed description

[0005] The disclosure below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] A stacked transistor comprising an upper and a lower transistor vertically stacked on top of each other, and a method for its fabrication, are provided. Channel isolation structures are fabricated from lower channel regions of the lower transistor between the upper channel regions of the upper transistor, isolating the upper channel regions of the upper transistor from the lower channel regions of the lower transistor. The channel isolation structures can be fabricated separately from other isolation structures in the device, such as internal spacers, which prevent an upper and lower gate stack from directly contacting an upper and lower source / drain region. Exemplary channel isolation structures, fabricated using simplified processes that are readily implementable, enable improved electrical performance, e.g.,an improved alternating current flow (AC flux), a reduced leakage loss, or the like.

[0008] Fig. Figure 1 shows an example of a stacked transistor 10 comprising field-effect transistors (FETs) 10U and 10L, according to some embodiments. Fig. Figure 1 is a three-dimensional representation, where some structural elements of the stacked transistor have been omitted for the sake of clarity.

[0009] The stacked transistor contains several vertically stacked FETs. For example, a stacked transistor can contain a lower nanostructured FET 10L of a first device type (e.g., n / p) and an upper nanostructured FET 10U of a second device type (e.g., p / n). If the stacked transistor is a CFET, the second device type of the upper nanostructured FET 10U is opposite to the first device type of the lower nanostructured FET 10L. The nanostructured FETs 10U and 10L feature semiconductor nanostructures 26 (comprising lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U), with the semiconductor nanostructures 26 acting as channel regions for the nanostructured FETs. The lower semiconductor nanostructures 26L are intended for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26U are intended for the upper nanostructure FET 10U.In other embodiments, the stacked transistors can also be used for other types of transistors (e.g., FinFETs or the like).

[0010] The respective semiconductor nanostructures 26 are enclosed by gate dielectrics 78. Gate electrodes 80 (comprising a lower gate electrode 80L and an upper gate electrode 80U) are arranged above the gate dielectrics 78. Source / drain regions 62 (comprising lower source / drain epitaxy regions 62L and upper source / drain epitaxy regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. The source / drain regions 62 can refer to a source or a drain individually or collectively, depending on the context. Insulating elements (not shown) can be fabricated to selectively separate the source / drain regions 62 and / or the gate electrodes 80.

[0011] Fig. Figure 1 shows reference cross-sections that will be used in later figures. A cross-section A - A' is a vertical cross-section that is parallel to a longitudinal axis of the semiconductor nanostructures 26 of the stacked transistor and runs, for example, in the direction of current flow between the source / drain regions 62 of the stacked transistor. Subsequent figures show details along the cross-section A - A'.

[0012] The Fig. Figures 2 to 8 show perspective views and sectional views of intermediate stages in the production of stacked transistors (schematically represented in Fig. 1 are shown) according to some embodiments. In Fig. 2. A wafer is provided that has a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., with a p- or n-type dopant) or undoped. Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of the substrate 20 can be silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or a combination thereof.

[0013] Semiconductor strips 28 are fabricated to extend upwards from the semiconductor substrate 20. Each semiconductor strip 28 comprises a semiconductor strip 20' (structured portions of the semiconductor substrate 20, also referred to as semiconductor fins 20') and a multilayer stack 22. The stack components of the multilayer stack 22 are referred to below as nanostructures. In particular, the multilayer stack 22 includes dummy nanostructures 24A, dummy nanostructures 24B, lower semiconductor nanostructures 26L, and upper semiconductor nanostructures 26U. The dummy nanostructures 24A and the dummy nanostructures 24B can, in turn, be collectively referred to as dummy nanostructures 24. The lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U can, in turn, be collectively referred to as semiconductor nanostructures 26.

[0014] The dummy nanostructures 24A are fabricated from a first semiconductor material, and the dummy nanostructures 24B are fabricated from a second semiconductor material that differs from the first. Both the first and second semiconductor materials can be selected from those suitable for substrate 20. The first and second semiconductor materials exhibit high etch selectivity with respect to each other. This allows the dummy nanostructures 24B to be removed at a higher rate than the dummy nanostructures 24A in subsequent processes.

[0015] The semiconductor nanostructures 26 (comprising the lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U) are fabricated from one or more third semiconductor materials. These third semiconductor materials can be selected from among those suitable for the substrate 20. The lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U can be fabricated from the same semiconductor material or from different semiconductor materials. Furthermore, the first and second semiconductor materials of the dummy nanostructures 24 exhibit high etch selectivity with respect to the one or more third semiconductor materials of the semiconductor nanostructures 26. This allows the dummy nanostructures 24 to be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructures 26.In some embodiments, the dummy nanostructures 24A are made of (or contain) silicon germanium, the semiconductor nanostructures 26 are made of silicon, and the dummy nanostructures 24B can be made of germanium or silicon germanium having a higher percentage of germanium atoms than the dummy nanostructures 24A. For example, the dummy nanostructures 24A can be made of silicon germanium with a germanium concentration of about 5% to 30% or about 15% to 30%, and the dummy nanostructures 24B can be made of silicon germanium with a germanium concentration of about 30% to 60% or about 35% to about 60%.It has been observed that by modulating the germanium concentrations of the dummy nanostructures 24A / 24B to fall within the aforementioned ranges, sufficient etch selectivity can be achieved, allowing the dummy nanostructures 24B to be selectively removed in subsequent processes without significantly removing the dummy nanostructures 24A. For example, it has been observed that if the germanium concentration of the dummy nanostructures 24A is lower than 15%, these structures may not be completely removed during a gate replacement process. Furthermore, it has been observed that if the germanium concentration of the dummy nanostructures 24A is higher than 30% and that of the dummy nanostructures 24B is lower than 35%, the etch selectivity between the dummy nanostructures 24A and 24B may not be sufficiently high.This means that the dummy nanostructures 24B cannot be completely removed, while at least some of the dummy nanostructures 24A remain intact during subsequent processing.

[0016] The lower semiconductor nanostructures 26L provide channel regions for lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26U provide channel regions for upper nanostructure FETs of the CFETs. The dummy nanostructures 24B can be fabricated in direct contact with two dummy nanostructures 24A and must not contact any semiconductor nanostructures 26. In contrast to embodiments described later (see, e.g., Fig. In sections 9 to 29C, no semiconductor nanostructures 26 are used that are located directly above / below (e.g., in contact with) the dummy nanostructures 24B, and all semiconductor nanostructures 26 can provide channel regions in the resulting device. The dummy nanostructures 24B are subsequently replaced by isolation structures that define the boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0017] To fabricate the semiconductor strips 28, layers of the first, second, and third semiconductor materials (arranged as shown and described above) can be deposited onto the semiconductor substrate 20. The layers of the first, second, and third semiconductor materials can be grown using a suitable method such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using a method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. A structuring process can then be used for the layers of the first, second, and third semiconductor materials, as well as for the semiconductor substrate 20, to define the semiconductor strips 28, which include the semiconductor strips 20', the dummy nanostructures 24, and the semiconductor nanostructures 26.

[0018] The semiconductor fins and nanostructures can be structured using a suitable method. For example, the structuring process can include one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is fabricated over a substrate and then structured using a photolithography process. Spacers are fabricated along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can be used as an etching mask for the structuring process to etch the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20. The etching can be performed using a suitable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0019] As also in Fig. As shown in Figure 2, STI regions 32 (STI: shallow trench insulation) are produced over the substrate 20 and between adjacent semiconductor strips 28. The STI regions 32 can have a dielectric coating and a dielectric material overlying the dielectric coating. The dielectric coating and the dielectric material can each contain an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof. The fabrication of the STI regions 32 can involve the deposition of one or more dielectric layers and the performance of a planarization process, such as a CMP process (CMP: chemical-mechanical polishing), a machine polishing process, or the like, to remove excess portions of the dielectric materials. The deposition processes can include ALD, high-density plasma deposition (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof.In some embodiments, the STI regions 32 may contain silicon oxide produced by an FCVD process followed by an annealing process. Then, one or more dielectric layers are recessed to define the STI regions 32. The one or more dielectric layers may be recessed such that upper portions of the semiconductor strips 28 (comprising the multilayer stacks 22) extend beyond the remaining STI regions 32.

[0020] After the STI regions 32 have been created, dummy gate stacks 42 can be fabricated over and along the sidewalls of the upper portions of the semiconductor strips 28 (the portions extending beyond the STI regions 32). Fabricating the dummy gate stacks 42 can include fabricating a dielectric dummy layer 36. The dielectric dummy layer 36 can be made of, or contain, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited by suitable methods or thermally grown. A dummy gate layer 38 is fabricated over the dielectric dummy layer 36. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other methods and subsequently planarized, for example, by a CMP process.The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from a group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. A mask layer 40, which may contain, for example, silicon nitride, silicon oxide nitride, or the like, is fabricated over the planarized dummy gate layer 38. Subsequently, the mask layer 40 can be patterned by photolithography and etching processes to produce a mask that is then used for etching and patterning the dummy gate layer 38 and, optionally, the dielectric dummy layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dielectric dummy layer 36 form dummy gate stacks 42.

[0021] In Fig. 3. Gate spacers 44 and source / drain recesses 46 are fabricated. First, the gate spacers 44 are fabricated over the multilayer stacks 22 and on exposed sidewalls of the dummy gate stacks 42. The gate spacers 44 can be fabricated by conformal fabrication of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. Suitable dielectric materials can include silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbonitride, or the like, which can be deposited by a deposition process such as CVD, ALD, or the like.

[0022] Subsequently, source / drain recesses 46 are created in the semiconductor strips 28. The source / drain recesses 46 are created by etching and can extend through the multilayer stacks 22 and into the semiconductor strips 20'. The undersides of the source / drain recesses 46 can be located above, below, or at the same level as the tops of the isolation regions 32. During the etching processes, the gate spacers 44 and the dummy gate stacks 42 mask some portions of the semiconductor strips 28. The etching can comprise a single etching process or multiple etching processes. Timed etching processes can be used to stop the etching of the source / drain recesses 46 after a desired depth has been reached.

[0023] In the Fig. In steps 4 to 6, internal spacers 54 and channel insulation structures 56 are fabricated in separate steps, allowing for better control during the fabrication of the internal spacers 54 and the channel insulation structures 56. For example, the materials, thicknesses, etc., of the internal spacers 54 and the channel insulation structures 56 can be selected and controlled independently, leading to improved electrical performance (e.g., improved AC flux, reduced leakage loss, or the like), while still providing a feasible process flow that can be easily implemented. Furthermore, by fabricating the channel insulation structures 56 independently, the dummy nanostructures 24A can be fabricated directly between and in contact with the dummy nanostructures 24B without intervening semiconductor nanostructures 26. This allows dummy semiconductor nanostructures (e.g., dummy semiconductor nanostructures 26M; see Fig. 9 to 29C) can be advantageously omitted from the fabrication process and the resulting structure, further reducing leakage in the resulting device. By omitting these dummy semiconductor nanostructures (e.g., the dummy semiconductor nanostructures 26M; see Fig. 9 to 29C) leakage current through the dummy semiconductor nanostructures can also be avoided.

[0024] In Fig. 4. The fabrication of the channel insulation structures 56 can include an etching process that removes the dummy nanostructures 24B. The etching process can be isotropic and selective for the dummy nanostructure material 24B, allowing them to be etched at a higher rate than the semiconductor nanostructures 26 and the dummy nanostructures 24A. In this way, the dummy nanostructures 24B can be completely removed between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively) without removing the semiconductor nanostructures 26 or the dummy nanostructures 24A.In some embodiments, where the dummy nanostructures 24B are made of germanium or silicon germanium with a high percentage of germanium, the dummy nanostructures 24A are made of silicon germanium with a low percentage of germanium, and the semiconductor nanostructures 26 are made of silicon without germanium, the etching process can be a dry etching process using chlorine gas, with or without plasma. Alternatively, the etching process can be a wet etching process using an etchant that has an etch selectivity between the dummy nanostructures 24A and the dummy nanostructures 24B greater than 40 (e.g., in the range of 40 to 100). The wet etching process can involve distributing a liquid etchant over the apparatus or immersing the apparatus in a liquid etchant. The liquid etchant can contain one or more elements or compounds (e.g.,H2O2, O3, or the like), which oxidize germanium (e.g., the germanium in dummy nanostructures 24A and 24B), and contain one or more elements or compounds that etch away the oxidized germanium. Since the dummy nanostructures 24B have a sufficiently higher germanium concentration (e.g., in the aforementioned regions) than the dummy nanostructures 24A, etch selectivity can be achieved. Furthermore, since the dummy gate stacks 42 enclose sidewalls of the semiconductor nanostructures 26 (see . Fig. 2) The dummy gate stacks 42 can support the upper semiconductor nanostructures 26U so that they do not collapse when the dummy nanostructures 24B are removed.

[0025] In Fig. Channel insulation structures 56 are fabricated between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective). As described in more detail below, source / drain regions are subsequently created in the source / drain recesses 46. The channel insulation structures 56 can be used to insulate the upper semiconductor nanostructures 26U (collective) from the lower semiconductor nanostructures 26L (collective). The channel insulation structures 56 can be fabricated by conformal deposition of an insulating material in the source / drain recesses 46, on sidewalls of the dummy nanostructures 24, and between the upper and lower semiconductor nanostructures 26U and 26L, and by subsequent etching of the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, e.g.,Silicon oxide carbonitride, silicon oxide carbide, silicon oxide nitride, or the like. Other materials with a low dielectric constant (low-k materials) with a k-value of less than approximately 3.9 can also be used. The insulating material can be produced by a deposition process such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic or isotropic. After etching, the insulating material has regions that remain between the upper and lower semiconductor nanostructures 26U and 26L, thus forming the channel insulation structures 56.

[0026] Then in Fig. Six internal spacers 54 are fabricated on the sidewalls of dummy nanostructures 24A. Fabricating the internal spacers 54 can involve an etching process that removes material from the sidewalls of the dummy nanostructures 24A, separate from the sidewalls of the semiconductor nanostructures 26 and the channel insulation structures 56. The etching process can be isotropic and selective for the material of the dummy nanostructures 24A, allowing them to be etched at a higher rate than the semiconductor nanostructures 26 and the channel insulation structures 56. In this way, the dummy nanostructures 24A can be removed without removing the semiconductor nanostructures 26 or the channel insulation structures 56.In some embodiments, by omitting the dummy nanostructures 24A, exposed surfaces of the semiconductor nanostructures 26, including the top and / or bottom surfaces of the semiconductor nanostructures 26, can be partially etched in the outer regions of the semiconductor nanostructures 26. The etching process can include a dry etching process using chlorine gas, with or without a plasma. Although the sidewalls of the dummy nanostructures 24A after etching are shown as straight, they can also be concave or convex.

[0027] Then, internal spacers 54 are fabricated on the recessed sidewalls of the dummy nanostructures 24A. As detailed below, source / drain regions are subsequently created in the source / drain recesses 46, and the dummy nanostructures 24A are replaced by corresponding gate structures. The internal spacers 54 act as insulating elements between the subsequently fabricated source / drain regions and the subsequently fabricated gate structures. Furthermore, the internal spacers 54 can be used to prevent damage to the subsequently fabricated source / drain regions from subsequent etching processes, such as those used to fabricate the gate structures.The internal spacers 54 can be fabricated by conformal deposition of an insulating material in the source / drain recesses 46, on the sidewalls of the dummy nanostructures 24A, and between the upper and lower semiconductor nanostructures 26U and 26L, followed by etching of the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, e.g., silicon dioxide carbonitride, silicon dioxide carbide, silicon dioxide nitride, or the like. Other materials with a low dielectric constant (low-k materials) with a k-value of less than approximately 3.9 can also be used. The insulating material can be fabricated by a deposition process such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic or isotropic.After etching, the insulating material has particles that remain on the side walls of the dummy nanostructures 24A, forming the internal spacers 54. The material composition of the channel insulation structures 56 can be the same as or different from the material composition of the internal spacers 54.

[0028] As also in Fig. As shown in Figure 6, lower and upper source / drain epitaxy regions 62L and 62U are generated. The lower source / drain epitaxy regions 62L are epitaxially grown in the lower part of the source / drain recesses 46. The lower source / drain epitaxy regions 62L are in contact with the lower semiconductor nanostructures 26L, but not with the upper semiconductor nanostructures 26U. The internal spacers 54 electrically isolate the lower source / drain epitaxy regions 62L from the dummy nanostructures 24A, which are replaced by substitute gates in subsequent processes.

[0029] The lower source / drain epitaxy regions 62L are grown epitaxially and have a conductivity type suitable for the device type (p or n) of the lower nanostructure FETs. If the lower source / drain epitaxy regions 62L are n-source / drain regions, the material can contain silicon or carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. If the lower source / drain epitaxy regions 62L are p-source / drain regions, the material can contain silicon or silicon germanium doped with a p-type dopant such as boron, indium, or the like. The lower source / drain epitaxy regions 62L can be doped in situ and may or may not be implanted with the appropriate p- or n-type dopants. During the epitaxy of the lower source / drain epitaxy regions 62L, exposed surfaces of the upper semiconductor nanostructures 26U (e.g.The sidewalls are masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructures 26U. After the lower source / drain epitaxial regions 62L have been grown, the masks on the upper semiconductor nanostructures 26U can be removed.

[0030] The epitaxy processes used to generate the lower source / drain epitaxy regions 62L result in the upper surfaces of these regions having chamfers that extend laterally outward beyond the sidewalls of the multilayer stacks 22. In some embodiments, adjacent lower source / drain epitaxy regions 62L can remain separate after completion of the epitaxy process. In other embodiments, these chamfers cause adjacent lower source / drain epitaxy regions 62L of the same FET to merge.

[0031] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are fabricated over the lower source / drain epitaxy regions 62L. The first CESL 66 can be fabricated from a dielectric material with high etch selectivity for the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, using a suitable deposition method such as CVD, ALD, or the like. The first ILD 68 can be fabricated from a dielectric material that can be deposited using a suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. A suitable dielectric material for the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0032] The fabrication processes can include the deposition of a conformal CESL, the deposition of material for the first ILD 68, followed by a planarization process, and a subsequent etch-back process. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. Then, an anisotropic etching process is performed to remove the portions of the first CESL 66 that are taller than the recessed first ILD 68. After recession, the sidewalls of the upper semiconductor nanostructures 26U are exposed.

[0033] Upper source / drain epitaxy regions 62U are then generated in the upper portions of the source / drain recesses 46. These upper source / drain epitaxy regions 62U can be grown epitaxially from the exposed surfaces of the upper semiconductor nanostructures 26U. Depending on the desired conductivity type of the upper source / drain epitaxy regions 62U, the materials for these regions can be selected from the same group of materials used to generate the lower source / drain regions 62L. In embodiments where the stacked transistors are CFETs, the conductivity type of the upper source / drain epitaxy regions 62U can be opposite to that of the lower source / drain regions 62L. For example, the upper source / drain epitaxy regions can be doped with 62U in the opposite direction to the lower source / drain epitaxy regions 62L.Alternatively, the conductivity types of the upper source / drain epitaxy regions 62U and the lower source / drain epitaxy regions 62L can be the same. The upper source / drain epitaxy regions 62U can be doped in situ, and / or they can be doped with an n-type or a p-type dopant. Adjacent upper source / drain epitaxy regions 62U can remain separate or merge after the epitaxy process.

[0034] After the upper source / drain epitaxy regions 62U have been generated, a second CESL 70 and a second ILD 72 are fabricated. The materials and fabrication methods can be similar to those for the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The fabrication process can include depositing layers for the CESL 70 and the ILD 72 and performing a planarization process to remove the excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and masks 86 (if present) or dummy gates 84 (within process variations) are substantially coplanar. Accordingly, the top surfaces of masks 40 (if present) or dummy gates 38 are not covered by the second ILD 72. In the illustrated embodiment, the masks 40 remain after the removal process.In other embodiments, the masks 40 are removed so that the tops of the dummy gates 38 are not covered by the second ILD 72.

[0035] Fig. Figure 7 shows a replacement gate process for replacing the dummy gate stacks 42 and the dummy nanostructures 24A with gate stacks 90. The replacement gate process first involves removing the dummy gate stacks 42 and the remaining portions of the dummy nanostructures 24A. The dummy gate stacks 42 are removed in one or more etching processes, defining recesses between the gate spacers 44 and exposing the top portions of the semiconductor strips 28. Then, the remaining portions of the dummy nanostructures 24A are removed by etching, extending the recesses between the semiconductor nanostructures 26. In the etching process, the dummy nanostructures 24A are removed at a higher rate than the semiconductor nanostructures 26, the channel isolation structures 56, and the internal spacers 54. The etching can be isotropic.For example, if the dummy nanostructures 24A are made of silicon germanium and the semiconductor nanostructures 26 are made of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH) or the like.

[0036] Gate dielectrics 78 are then deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructures 26. The gate dielectrics 78 are conformally produced on the exposed surfaces of the recesses (the removed gate stacks 42 and the dummy nanostructures 24A) that contain the semiconductor nanostructures 26 and the gate spacers 44. In some embodiments, the gate dielectrics 78 enclose all (e.g., four) sides of the semiconductor nanostructures 26. In particular, the gate dielectrics 78 can be produced on the top surfaces of the fins 20°, on the top, side, and bottom surfaces of the semiconductor nanostructures 26, and on the side surfaces of the gate spacers 44. The gate dielectrics 78 can have an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multilayers thereof or the like.The gate dielectrics 78 can contain a material with a high dielectric constant (high-k material) having a k-value greater than approximately 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The fabrication processes for the gate dielectrics 78 can include molecular beam deposition (MBD), ALD, PECVD, and the like, followed by a planarization process (e.g., CMP) to remove portions of the gate dielectrics 78 above the second ILD 72. Although single-layer gate dielectrics 78 are shown, the gate dielectrics 78 can have multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0037] Lower gate electrodes 80L are fabricated on the gate dielectrics 78 surrounding the lower semiconductor nanostructures 26L. For example, the lower gate electrodes 80L enclose the lower semiconductor nanostructures 26. The lower gate electrodes 80L can be made of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, or the like. Although single-layer gate electrodes are shown, the lower gate electrodes 80L can contain any number of exit work layers, any number of storage layers, any number of adhesive layers, and a filler material.

[0038] The lower gate electrodes 80L are made of one or more materials suitable for the device type of lower nanostructure FETs. For example, the lower gate electrodes 80L may have one or more work function setting layers made of one or more materials suitable for the device type of lower nanostructure FETs. In some embodiments, the lower gate electrodes 80L have an n-work function setting layer, which may be made of titanium-aluminum, tantalum-aluminum carbide, tantalum-aluminum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower gate electrodes 80L have a p-work function setting layer, which may be made of titanium nitride, tantalum nitride, combinations thereof, or the like.Additionally or alternatively, the lower gate electrodes 80L can incorporate a dipole-inducing element suitable for the device type of lower nanostructure FETs. Suitable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0039] The lower gate electrodes 80L can be fabricated by conformal deposition of one or more gate electrode layers and by omitting one or more of these layers. An appropriate etching process, such as dry etching, wet etching, or a combination thereof, can be used to omit the gate electrode layers. The etching can be anisotropic. Etching the lower gate electrodes 80L exposes the upper semiconductor nanostructures 26U.

[0040] In some embodiments, insulating layers (not shown in detail) can optionally be fabricated on the lower gate electrodes 80L. The insulating layers act as insulating elements between the lower gate electrodes 80L and subsequently fabricated upper gate electrodes 80U. The insulating layers can be fabricated by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbonitride, combinations thereof, or the like) and subsequent embedding of the dielectric material to expose the upper semiconductor nanostructures 26U.

[0041] Then, upper gate electrodes 80U are fabricated on the insulation layers described above (if present) or on the lower gate electrodes 80L. The upper gate electrodes 80U are positioned between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrodes 80U enclose the upper semiconductor nanostructures 26U. The upper gate electrodes 80U can be fabricated from the same materials and using the same processes as the lower gate electrodes 80L. The upper gate electrodes 80U are fabricated from one or more materials suitable for the device type of the upper nanostructure FETs. For example, the upper gate electrodes 80U can have one or more work function setting layers (e.g.,one or more n- and / or p-function setting layers) made of one or more materials suitable for the device type of upper nanostructure FETs. Although single-layer upper gate electrodes 80U are shown, the upper gate electrodes 80U can have any number of function layers, any number of memory layers, any number of adhesive layers, and a filler material.

[0042] Furthermore, a removal process is performed to level the top surfaces of the upper gate electrodes 80U and the second ILD 72. The removal process for producing the upper gate electrodes 80U can be the same removal process used to produce the gate dielectrics 78. In some embodiments, a planarization process, such as CMP, a back-etching process, combinations thereof, or the like, can be used. After the planarization process, the top surfaces of the upper gate electrodes 80U, the gate dielectrics 78, the second ILD 72, and the gate spacers 44 are (within process variations) essentially coplanar. Each respective pair of a gate dielectric 78 and a gate electrode 80 (which has an upper gate electrode 80U and / or a lower gate electrode 80L) can be collectively referred to as a “gate structure” 90 (which has upper gate structures 90U and lower gate structures 90L).Each gate structure 90 extends along three sides (e.g. along a top, a side wall and a bottom) of a channel region of a semiconductor nanostructure 26 (see . Fig. 1) The lower gate structures 90L can also extend along side walls and / or a top surface of a semiconductor fin 20'. Furthermore, by eliminating the intermediate dummy semiconductor nanostructures on the channel insulation structures 56, the lower gate structures 90L and the upper gate structures 90U can each be in direct physical contact with the channel insulation structures 56.

[0043] As also in Fig. As shown in Figure 7, gate masks 92 are manufactured over the gate stacks 42. The manufacturing process may include: recessing the gate stacks 90; filling the resulting recesses with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxide nitride, silicon oxide carbonitride, or the like; and performing a planarization process to remove the excess parts of the dielectric material over the second ILD 72.

[0044] In Fig. 8. Metal-semiconductor alloy regions 94 and source / drain contacts 96 are produced by the second ILD 72 to electrically connect them to the upper source / drain epitaxy regions 62U and / or the lower source / drain epitaxy regions 62L. As an example of producing the source / drain contacts 96, openings are created by the second ILD 72 and the second CESL 70 using suitable photolithography and etching techniques. A coating (not shown separately), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are produced in the openings. The coating may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like. A removal process can be carried out to remove excess material from the tops of the gate spacers 44 and the second ILD 72.The remaining coating and conductive material form the source / drain contacts 96 in the openings. In some embodiments, a planarization process, such as CMP, etching, a combination thereof, or the like, is used. After the planarization process, the top surfaces of the gate spacers 44, the second ILD 72, and the source / drain contacts 96 are (within process variations) essentially coplanar.

[0045] Optionally, metal-semiconductor alloy regions 94 are produced at the interfaces between the source / drain regions 62 and the source / drain contacts 96. The metal-semiconductor alloy regions 94 can be silicide regions made from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions made from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions made from a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 94 can be produced upstream of the single or multiple materials of the source / drain contacts 96 by depositing a metal in the openings for the source / drain contacts 96 and then performing a thermal annealing process. The metal can be a metal that is compatible with semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).The source / drain regions 62 can react with a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, another precious metal, another refractory metal, a rare-earth metal, or an alloy thereof. The metal can be deposited using a deposition process such as ALD, CVD, PVD, or the like. After the thermal tempering process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the openings for the source / drain contacts 96, e.g., from the surfaces of the metal-semiconductor alloy regions 94. Then, one or more materials for the source / drain contacts 96 can be applied to the metal-semiconductor alloy regions 94.

[0046] Then, an ESL 104 and a third ILD 106 are fabricated. In some embodiments, the ESL 104 may contain a dielectric material with high etch selectivity towards the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon dioxide carbide, or the like. The third ILD 106 may be fabricated by FCVD, ALD, or the like, and the material may comprise PSG, BSG, BPSG, USG, or the like, which can be deposited by a suitable process such as CVD, PECVD, or the like.

[0047] Gate contacts 108 and source / drain vias 110 are then fabricated to connect the upper gate electrodes 80U and the source / drain contacts 96, respectively. As an example of fabricating the gate contacts 108 and the source / drain vias 110, openings for these are created through the third ILD 106 and the ESL 104. The openings can be created using suitable photolithography and etching techniques. A coating (not shown individually), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are fabricated within the openings. The coating can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like.To remove excess material from the top surface of the third ILD 106, a planarization process, such as CMP, can be performed. The remaining coating and conductive material form the gate contacts 108 and the source / drain vias 110 in the openings. The gate contacts 108 and the source / drain vias 110 can be fabricated in different processes or in the same process. Although it is shown that each of the gate contacts 108 and the source / drain vias 110 is fabricated in the same cross-section, it is understood that they can be fabricated in different cross-sections, which can prevent short-circuiting of the contacts.

[0048] A front-facing interconnect structure 114 is fabricated on a device layer 112. The front-facing interconnect structure 114 comprises dielectric layers 116 and layers of conductive structural elements 118 within the dielectric layers 116. The dielectric layers 116 may include low-k dielectric layers made of low-k dielectric materials. The dielectric layers 116 may also include passivation layers made of non-low-k and dense dielectric materials such as undoped silicate glass (USG), silicon dioxide, silicon nitride, or the like, or combinations thereof, over the low-k dielectric materials. The dielectric layers 116 may also include polymer layers.

[0049] The conductive structural elements 118 can include conductive traces and vias that can be fabricated using Damascene processes. The conductive structural elements 118 can include metal traces and metal vias that have diffusion barrier layers and a copper-containing material over the diffusion barrier layers. Aluminum pads can also be arranged over the metal traces and metal vias and electrically connected to them. In some embodiments, contacts can be established with the lower gate stacks 90L and the lower source / drain regions 80L through a rear side of the device layer 112 (e.g., a side facing the front interconnect structure 114).

[0050] The Fig. Figures 9 to 14 show sectional views of intermediate stages in the fabrication of a stacked transistor according to some further embodiments, in which the channel insulation structures 56 have a multilayer structure. In the Fig. Numbers 9 to 14 denote similar reference numbers, similar elements produced using processes similar to those described above with reference to the Fig. Items 2 to 8 have been discussed, unless otherwise stated. Fig. 9 shows a structure at a similar processing stage as in Fig. 3, as described above, in which the source / drain recesses 46 are structured by the multilayer stack 22. In Fig. 9. However, the dummy nanostructures 24B are not fabricated directly between the dummy nanostructures 24A. Instead, dummy semiconductor nanostructures 26M are arranged on the top and bottom surfaces of the dummy nanostructures 24B. The dummy semiconductor nanostructures 26M can be fabricated from the same material and using the same processes as the top semiconductor nanostructures 26U and the bottom semiconductor nanostructures 26L. For example, in some embodiments, the top semiconductor nanostructures 26U, the bottom semiconductor nanostructures 26L, and the dummy semiconductor nanostructures 26M can be fabricated from silicon, while the dummy nanostructures 24A and the dummy nanostructures 24B can be fabricated from silicon-germanium with different germanium concentrations.The dummy semiconductor nanostructures 26M can also be referred to as intermediate semiconductor nanostructures and can contribute to defining a boundary between the upper and lower transistors in the stacked transistor. The dummy semiconductor nanostructures 26M can be used to enlarge the process window for fabricating channel isolation structures, thus allowing the etch selectivity between dummy nanostructures 24A and 24B to be relaxed, since the etch selectivity between dummy nanostructures 24B (e.g., silicon germanium with a high germanium concentration) is typically higher than between dummy semiconductor nanostructures 26M (e.g., silicon) and dummy nanostructures 24A (e.g., silicon germanium with a low germanium concentration).

[0051] In Fig. 10. The dummy nanostructures 24B are removed. The removal of the dummy nanostructures 24B may involve an etching process similar to the one previously described with reference to Fig. As described in section 4. For example, the etching process can be isotropic and selective for the dummy nanostructures 24B, such that the dummy nanostructures 24B are etched at a higher rate than the upper semiconductor nanostructures 26U, the dummy semiconductor nanostructures 26M, the lower semiconductor nanostructures 26L, and the dummy nanostructures 24A. In this way, the dummy nanostructures 24B can be completely removed between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively) without removing the semiconductor nanostructures 26, the dummy semiconductor nanostructures 26M, or the dummy nanostructures 24A.In some embodiments, where the dummy nanostructures 24B are made of germanium or silicon germanium with a high percentage of germanium, the dummy nanostructures 24A are made of silicon germanium with a low percentage of germanium, and the semiconductor nanostructures 26 and the dummy semiconductor nanostructures 26M are made of silicon without germanium, the etching process can be a dry etching process using chlorine gas, with or without plasma. Alternatively, the etching process can be a wet etching process using an etchant that has an etch selectivity between the dummy nanostructures 24A and the dummy nanostructures 24B greater than 40 (e.g., in the range of 40 to 100). The wet etching process can involve distributing a liquid etchant over the apparatus or immersing the apparatus in a liquid etchant.The liquid etchant can contain one or more elements or compounds (e.g., H₂O₂, O₃, or the like) that oxidize germanium (e.g., the germanium in dummy nanostructures 24A and 24B) and one or more elements or compounds that etch away the oxidized germanium. Since dummy nanostructures 24B have a sufficiently higher germanium concentration (e.g., in the aforementioned regions) than dummy nanostructures 24A, etch selectivity can be achieved. Furthermore, since the dummy gate stacks 42 enclose sidewalls of the semiconductor nanostructures 26 (see . Fig. 2) The dummy gate stacks 42 can support the upper semiconductor nanostructures 26U so that they do not collapse when the dummy nanostructures 24B are removed.

[0052] In Fig. 11 Dielectric material layers 50A and 50B are successively deposited in the source / drain recesses 46, on sidewalls of the dummy nanostructures 24A, on sidewalls of the semiconductor nanostructures 26, on sidewalls of the dummy semiconductor nanostructures 26M, and between the upper and lower semiconductor nanostructures 26U and 26L using a conformal deposition process such as CVD, ALD, or the like. In particular, the dielectric material layer 50A can be produced in contact with side surfaces of the dummy semiconductor nanostructures 26M, and the dielectric material layer 50B can fill remaining spaces between vertically stacked nanostructures of the dummy semiconductor nanostructures 26M. The dielectric material layers 50A and 50B can have different material compositions.For example, the dielectric material layer 50A can be a relatively hard dielectric material with a relatively high k-value, such as a carbon-containing dielectric material like silicon dioxide carbonitride, silicon dioxide carbide, silicon dioxide nitride, or the like. In some embodiments, the dielectric material layer 50A can be a high-k material with a k-value of approximately 3.9 to approximately 10. In contrast, the dielectric material layer 50B can be made of a dielectric material with a relatively low k-value of less than approximately 3.9. In some embodiments, the dielectric material layer 50B has a lower k-value than the dielectric material layer 50A, and the dielectric material layer 50A is harder (e.g., has a higher etch resistance for the same etching process) than the dielectric material layer 50B.By using a combination of materials, the resulting channel insulation structure can be relatively stable and less susceptible to damage during subsequent process steps (e.g., due to the use of the hard material in dielectric layer 50A), while still maintaining a low k-value for improved insulation (e.g., due to the use of dielectric layer 50B with its low k-value). This allows the stacked transistor to have improved electrical performance (e.g., improved AC flux) and can be readily manufactured using a feasible process.

[0053] In Fig. In 12, an etching process is performed to remove the dielectric material layers 50A and 50B from the sidewalls of the source / drain recesses 46, the sidewalls of the gate spacers 44, and over the dummy gate stacks 42. Remaining portions of the dielectric material layers 50A and 50B form a channel insulation material 56A and a channel insulation material 56B, respectively. The channel insulation material 56B can be positioned between the upper and lower portions of the channel insulation material 56A. As described in more detail below, source / drain regions are then created in the source / drain recesses 46. The channel insulation material 56A and the channel insulation material 56B can be used to insulate the upper semiconductor nanostructures 26U (collectively) from the lower semiconductor nanostructures 26L (collectively). The etching of the dielectric material layers 50A and 50B can be anisotropic or isotropic.

[0054] In Fig. 13 An etching process is performed that removes the sidewalls of the dummy nanostructures 24A from the sidewalls of the semiconductor nanostructures 26 and the channel insulating materials 56A and 56B. The etching process can be isotropic and can be selective for the dummy nanostructure material 24A, allowing it to be etched at a higher rate than the semiconductor nanostructures 26 and the channel insulating materials 56A and 56B. In this way, the dummy nanostructures 24A can be removed without removing the semiconductor nanostructures 26 or the channel insulating materials 56A. In some embodiments, removing the dummy nanostructures 24A allows exposed surfaces of the semiconductor nanostructures 26, including the top and / or bottom surfaces, to be partially etched in the outer regions of the semiconductor nanostructures 26.The etching process can also partially etch away the sidewalls of the channel insulation material 56B (and optionally, to a lesser extent, the channel insulation material 56A). However, due to the relative hardness of the channel insulation material 56A, it remains relatively unetched, and the overall channel insulation structure remains intact even when the channel insulation material 56B is etched away. The etching process can involve a dry etching process using chlorine gas, with or without plasma. Although the sidewalls of the dummy nanostructures 24A after etching are shown as straight, they can also be concave or convex.

[0055] Then in Fig. 14 Internal spacers 54 are manufactured on the recessed side walls of the dummy nanostructures 24A. The internal spacers 54 can be manufactured from a similar material and using similar processes to those previously described with reference to Fig. As described in Section 6, for example, the internal spacers 54 can be fabricated by conformal deposition of an insulating material in the source / drain recesses 46, on the sidewalls of the dummy nanostructures 24A, and between the upper and lower semiconductor nanostructures 26U and 26L, and by subsequent etching of the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material like silicon dioxide carbonitride, silicon dioxide carbide, silicon dioxide nitride, or the like. Other materials with a low dielectric constant (low-k materials) with a k-value of less than about 3.9 can also be used. Portions of the insulating material on the recessed sidewalls of the channel insulating material 56B can be patterned to fabricate a channel insulating material 56C.The channel insulation material 56C has the same material composition as the internal spacers 54 and is manufactured using the same process. The resulting multilayered channel insulation structure 56 comprises the relatively hard channel insulation material 56A and the low k-value channel insulation material 56B, which is layered between the channel insulation materials 56A, and the channel insulation material 56C on the sidewalls of the channel insulation material 56B. The material composition of the channel insulation materials 56A and 56B can be the same as, or different from, the material composition of the internal spacers 54.

[0056] As also in Fig. As shown in Figure 14, upper and lower source / drain epitaxy regions 62U and 62L, CESLs 66 and 70, and ILDs 68 and 72 are fabricated in the source / drain recesses 46. To achieve the structure of Fig. To reach 15, further processing steps can be carried out, including a gate replacement process, the fabrication of gate and source / drain contacts, and the fabrication of a front-side interconnect. Fig. 15 shows a similar structure to Fig. 8, where similar reference numbers denote similar elements. The channel insulation structure 56 of Fig. However, 15 is a multilayer structure with the relatively hard channel insulation material 56A, the low k-value channel insulation material 56B layered between the channel insulation materials 56A, and the channel insulation material 56C on the sidewalls of the channel insulation material 56B. Furthermore, the dummy semiconductor nanostructures 26M can persist in the resulting device and can separate the channel insulation structure 56 from the upper and lower gate structures 90U and 90L. The dummy semiconductor nanostructures 26M cannot function as channel regions because they do not border source / drain epitaxy regions.

[0057] The Fig. Figures 16 to 18 show sectional views of intermediate stages in the fabrication of a stacked transistor according to some further embodiments, in which the channel insulation structure 56 is made of a single material and dummy semiconductor nanostructures 26M are included. In the Fig. Numbers 16 to 18 denote similar reference numbers, similar elements produced by processes similar to those described above with reference to the Fig. Items 2 to 15 have been discussed, unless otherwise stated. Fig. Figure 16 shows a structure at a similar processing stage as in Fig. 12, as described above, in which the source / drain recesses 46 are structured by the multilayer stack 22 and the channel isolation structure 56 is fabricated between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective). Fig. However, in embodiment 16, the channel insulation structure 56 does not have a multilayer structure and is made from a single material. In some embodiments, the channel insulation structure 56 is made from a hard dielectric material, such as a carbon-containing dielectric material like silicon oxide carbonitride, silicon oxide carbide, silicon oxide nitride, or the like. The channel insulation structure 56 can be fabricated in direct contact with the dummy semiconductor nanostructures 26M.

[0058] In Fig. In 17, internal spacers 54 are fabricated on the side walls of the dummy nanostructures 24A. The internal spacers 54 can be fabricated from a similar material and using similar processes to those previously described. Similar to the preceding embodiments, the internal spacers 54 and the channel insulation structures 56 can be fabricated in separate processes to allow for increased flexibility and control when fabricating different insulation structures in the stacked transistor. The internal spacers 54 can be fabricated from the same material as, or from a different material than, the channel insulation structures 56. Furthermore, upper and lower source / drain epitaxy regions 62U and 62L, CESLs 66 and 70, and ILDs 68 and 72 can also be fabricated in the source / drain recesses 46.

[0059] To get to the structure of Fig. To reach 18, further processing steps can be carried out, including a gate replacement process, the fabrication of gate and source / drain contacts, and the fabrication of a front-side interconnect. Fig. 18 shows a similar structure to Fig. 15, where similar reference numbers denote similar elements. The channel insulation structure 56 of Fig. However, 15 is not a multi-layer structure, and it is made from a single material.

[0060] In the preceding embodiments, the channel isolation structures 56 are shown as structures arranged only between and separating the upper semiconductor nanostructures 26U (collectively) and the lower semiconductor nanostructures 26L (collectively). However, the channel isolation structures 56 can also be fabricated at other positions relative to the semiconductor nanostructures 26. For example, the Fig. Figures 19 to 21 describe intermediate stages of fabrication embodiments in which the channel isolation structures 56 are also fabricated beneath the lower semiconductor nanostructures 26L, such as beneath the lower gate stack 90L. The channel isolation structures 56 can be fabricated between the lower gate stack 90L and the underlying semiconductor fin 20' or the underlying semiconductor substrate 20 to improve the isolation in the lower regions of the stack transistor and further reduce leakage loss in the resulting device. For example, the channel isolation structures 56 beneath the lower gate stack 90L can reduce leakage loss from the lower source / drain epitaxy regions 62L through the semiconductor fin 20' and the semiconductor substrate 20. The channel isolation structures 56 can be fabricated in direct contact with the lower gate stack 90L and the semiconductor fin 20'.The channel isolation structures 56 can be fabricated using similar materials and processes to those described above for the lower channel isolation structures 56 (e.g., under the lower semiconductor nanostructures 26L), which are fabricated by first fabricating dummy nanostructures 24B under the lower semiconductor nanostructures 26L (see . Fig. 19). For example, the dummy nanostructures 24B can be fabricated in direct contact with the top surfaces of the semiconductor fins 20'. The dummy nanostructures 24B can then be replaced by channel isolation structures 56, as described above with reference to Fig. 20 has been explained.

[0061] To get to the structure of Fig. To reach 21, further processing steps can be carried out, including the fabrication of internal spacers 54, the creation of upper and lower source / drain epitaxy regions 62L and 62U, the fabrication of CESLs 66 and 70, the fabrication of ILDs 68 and 72, a gate replacement process, the fabrication of gate and source / drain contacts, and the fabrication of a front-side interconnect, as described above. As further explained in Fig. As shown in Figure 21, a lower ILD 120 and a lower CESL 122 can be fabricated beneath the lower source / drain epitaxy regions 62L, such as between the lower source / drain epitaxy regions 62L and the semiconductor fins 20'. The lower ILD 120 and the lower CESL 122 can be fabricated in the source / drain recesses 46 prior to the fabrication of the lower source / drain epitaxy regions 62L using similar materials and processes to those used for the first ILD 64 and the first CESL 66, respectively. The lower ILD 120 and the lower CESL 122 can further reduce the leakage loss from the lower source / drain epitaxy regions 62L through the semiconductor fins 20'.

[0062] As another example, the Fig. 22 to 24 intermediate stages of fabrication configurations in which the channel isolation structures 56 are fabricated beneath the lower semiconductor nanostructures 26L, such as beneath the lower gate stack 90L, e.g., above the upper semiconductor nanostructures 26U. The channel isolation structures 56 can be fabricated between the lower gate stack 90L and the underlying semiconductor fin 20' or the underlying semiconductor substrate 20 to improve the isolation in lower regions of the stack transistor and further reduce leakage loss in the resulting device. For example, the channel isolation structures 56 beneath the lower gate stack 90L can reduce leakage loss from the lower source / drain epitaxy regions 62L through the semiconductor fin 20' and the semiconductor substrate 20.The channel isolation structures 56 over the upper semiconductor nanostructures 26U can be used to protect the upper semiconductor nanostructures 26U during processing for improved nanostructure profiling and nanostructure control. The channel isolation structures 56 can be fabricated using similar materials and processes to those described above. As in . Fig. As shown in Figure 22, the lower channel isolation structures 56 (e.g., beneath the lower semiconductor nanostructures 26L), which are fabricated by first fabricating dummy nanostructures 24B beneath the lower semiconductor nanostructures 26L, and the upper channel isolation structures 56 (e.g., above the upper semiconductor nanostructures 26U), can be fabricated by first fabricating dummy nanostructures 24B above the upper semiconductor nanostructures 26U. For example, the dummy nanostructures 24B can be fabricated in direct contact with the top surfaces of the semiconductor fins 20' as well as in direct contact with the uppermost surfaces of the upper semiconductor nanostructures 26U. The dummy nanostructures 24B can then be replaced by channel isolation structures 56, as described above with reference to Figure 22. Fig. 23 has been explained.

[0063] To get to the structure of Fig. To reach 24, further processing steps can be carried out, including the fabrication of internal spacers 54, the creation of upper and lower source / drain epitaxy regions 62L and 62U, the fabrication of CESLs 66 and 70, the fabrication of ILDs 68 and 72, a gate replacement process, the fabrication of gate and source / drain contacts, and the fabrication of a front-side interconnect, as described above. As further explained in Fig. As shown in Figure 24, a lower ILD 120 and a lower CESL 122 can be fabricated beneath the lower source / drain epitaxy regions 62L, such as between the lower source / drain epitaxy regions 62L and the semiconductor fins 20'. The lower ILD 120 and the lower CESL 122 can be fabricated in the source / drain recesses 46 prior to the fabrication of the lower source / drain epitaxy regions 62L using similar materials and processes to those used for the first ILD 64 and the first CESL 66, respectively. The lower ILD 120 and the lower CESL 122 can further reduce the leakage loss from the lower source / drain epitaxy regions 62L through the semiconductor fins 20'.

[0064] In the various embodiments described above, the dummy nanostructures 24A are removed after the source / drain epitaxy regions have been generated as part of the gate replacement process. In other embodiments, the dummy nanostructures 24A can be replaced by a sacrificial material before the source / drain epitaxy regions are generated. For example, the Fig. Figures 26 to 29C show sectional views during the fabrication of a stacked transistor according to further embodiments in which the dummy nanostructures 24A are replaced by a sacrificial material before the lower and upper source / drain epitaxy regions 62L and 62U are generated. Fig. 26 to 29C denote similar reference numbers, similar elements produced by similar processes to those described above with reference to the Fig. Sections 2 to 25 have been discussed, unless otherwise stated. In particular, it shows Fig. 25 a structure at the same manufacturing stage as before in Fig. 16, in which the source / drain recesses 46 are structured by the multilayer stack 22 and the dummy nanostructures 24B are replaced by channel isolation structures 56. The channel isolation structures 56 can be arranged between the upper semiconductor nanostructures 26U (collectively) and the lower semiconductor nanostructures 26L (collectively) and separate them from each other.

[0065] In the Fig. In steps 26 to 27C, the dummy nanostructures 24A are replaced by a sacrificial material 58, also referred to as an exchangeable oxide interposer (DOI) 58. Replacing the dummy nanostructures 24A can involve etching them away using a suitable etching process, such as an isotropic etching process carried out through the source / drain recesses 46, as shown in Fig. Figure 26 shows that the etching process can be selective for the material of the dummy nanostructures 24A and can remove the dummy nanostructures 24A without significantly removing the semiconductor nanostructures 26, the dummy semiconductor nanostructures 26M, or the channel insulation structures 56. In an embodiment where the dummy nanostructures 24A contain, for example, SiGe and the semiconductor nanostructures 26 or the dummy semiconductor nanostructures 26M contain, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH), or the like can be used to remove the dummy nanostructures 24A.

[0066] In the Fig. In sections 27A to 27C, the sacrificial material 58 can be produced in crevices between the semiconductor nanostructures 26. The production of the sacrificial material 58 can involve depositing a sacrificial layer in the source / drain recesses 46 and in the spaces from which the dummy nanostructures 24A have been removed. The sacrificial layer can be deposited using a conformal deposition process such as CVD, ALD, or the like. The sacrificial layer can contain an insulating material such as silicon dioxide (e.g., SiO2) or the like, which can be selectively etched out of the channel insulation structure 56, the semiconductor nanostructures 26, and the dummy semiconductor nanostructures 26M. The sacrificial layer can then be etched to produce the sacrificial material 58. The etching can be isotropic or anisotropic. For example, the sacrificial material layer can be etched using a wet etching process with diluted HF or the like as an etchant.In some embodiments, the etching is carried out until sidewalls of the sacrificial material 58 are etched beyond sidewalls of the semiconductor nanostructures 26. In the . Fig. In Figures 27A to 27C, the sidewalls of the sacrificial material 58 are shown as straight, but they can also be concave or convex. And although the sidewalls of the sacrificial material 58 are shown as oriented towards the sidewalls of the semiconductor nanostructures 26, in some embodiments the sidewalls of the sacrificial material 58 can also be recessed relative to the sidewalls of the semiconductor nanostructures 26.

[0067] Fig. 27A shows embodiments which Fig. 16 to 18 correspond in which the channel isolation structures 56 are only produced between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective). Fig. 27B shows embodiments which Fig. 19 to 21 correspond to the channel isolation structures 56 between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective) and between the lower semiconductor nanostructures 26L (collective) and the semiconductor fins 20'. Fig. 27C shows embodiments which Fig. 22 to 24 correspond in which the channel isolation structures 56 are produced between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective), between the lower semiconductor nanostructures 26L (collective) and the semiconductor fins 20' and over the upper semiconductor nanostructures 26U (collective).

[0068] Replacing the dummy nanostructures 24A with the sacrificial material 58 can offer advantages. For example, one or more high-temperature processes can be performed in subsequent source / drain fabrication steps to activate the dopants in the source / drain regions. If the dummy nanostructure material 24A (e.g., silicon germanium) is exposed to high temperatures, germanium mixing and increased roughness at the interfaces between the semiconductor nanostructures 26 and the dummy nanostructures 24A can occur. These fabrication defects can reduce the performance of the resulting transistor devices. For example, if germanium diffuses into the semiconductor nanostructures 26, a germanium residue may remain in the channel regions of the resulting stacked transistor devices, negatively impacting the performance of these channels.By replacing the dummy nanostructures 24A with an insulating material prior to high-temperature processes (e.g., source / drain tempering), manufacturing defects can be reduced, and device performance can be improved (e.g., with increased drive current, reduced capacitive resistance, and improved short-channel effect).

[0069] In Fig. In embodiment 28, internal spacers 54 are fabricated on the sidewalls of the sacrificial material 58. The internal spacers 54 can be fabricated from a similar material using similar processes to those described above. For example, fabricating the internal spacers 54 can involve recessing the sidewalls of the sacrificial material 58 relative to the sidewalls of the semiconductor nanostructures 26 and the dummy semiconductor nanostructures 26M (if these have not already been recessed). An insulating material is then deposited and back-etched to fabricate the internal spacers 54. Similar to the preceding embodiments, the internal spacers 54 and the channel insulation structures 56 can be fabricated in separate processes to allow increased flexibility and control when fabricating different insulation structures in the stacked transistor.The internal spacers 54 can be made of the same material as, or a different material than, the channel insulation structures 56. Furthermore, upper and lower source / drain epitaxy areas 62U and 62L, CESLs 66 and 70, and ILDs 68 and 72 can also be manufactured in the source / drain recesses 46.

[0070] To get to the structure of the Fig. To reach 29A to 29C, further processing steps can be carried out, including a gate replacement process, the creation of gate and source / drain contacts, and the creation of a front-side interconnect. Fig. 29A shows embodiments which Fig. 16 to 18 and 27A correspond, in which the channel isolation structures 56 are only produced between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective). Fig. 29B shows embodiments which Fig. 19 to 21 and 27B correspond to the channel isolation structures 56 between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective) and between the lower semiconductor nanostructures 26L (collective) and the semiconductor fins 20'. Fig. 29C shows embodiments which Fig. 22 to 24 and 27C correspond to the channel isolation structures 56 between the upper semiconductor nanostructures 26U (collective) and the lower semiconductor nanostructures 26L (collective), between the lower semiconductor nanostructures 26L (collective) and the semiconductor fins 20' and over the upper semiconductor nanostructures 26U (collective).

[0071] Various embodiments provide a stacked transistor structure comprising an upper and a lower transistor stacked vertically; and methods for fabricating the stacked transistor. Channel isolation structures are fabricated from lower channel regions of the lower transistor between the upper channel regions of the upper transistor, isolating the upper channel regions of the upper transistor from the lower channel regions of the lower transistor. The channel isolation structures can be fabricated separately from other isolation structures in the device, such as internal spacers, which prevent an upper and lower gate stack from directly contacting an upper and lower source / drain region. Exemplary channel isolation structures fabricated with simplified process sequences that are readily implementable enable improved electrical performance, e.g.,an improved alternating current flow (AC flux), a reduced leakage loss, or the like.

[0072] In some embodiments, a device comprises a multilayer stack containing: a first plurality of nanostructures; a second plurality of nanostructures above the first plurality of nanostructures; and a first channel isolation structure. The device further comprises: first source / drain regions at opposite ends of the first plurality of nanostructures; second source / drain regions above the first source / drain regions, the second source / drain regions being located at opposite ends of the second plurality of nanostructures; a first gate structure surrounding the first plurality of nanostructures, the first gate structure contacting a first side face of the first channel isolation structure; and a second gate structure surrounding the second plurality of nanostructures.Optionally, in some embodiments, the first channel insulation structure is arranged between the first and second plurality of nanostructures. Optionally, in some embodiments, the second gate structure contacts a second side surface of the first channel insulation structure. Optionally, in some embodiments, the first channel insulation structure is arranged beneath the first plurality of nanostructures. Optionally, in some embodiments, the device further comprises an interlayer dielectric (ILD) beneath the first source / drain regions, the ILD extending along side walls of the first channel insulation structure. Optionally, in some embodiments, the multilayer stack further comprises a second channel insulation structure above the second plurality of nanostructures.Optionally, in some embodiments, the device further comprises: first internal spacers between side walls of the first gate structure and the first source / drain regions; and second internal spacers between side walls of the second gate structure and the second source / drain regions, wherein the first and second internal spacers have the same material composition. Optionally, in some embodiments, the first and second internal spacers have a different material composition than the first channel insulation structure.

[0073] In some embodiments, a device comprises: a first plurality of nanostructures; a second plurality of nanostructures above the first plurality of nanostructures; and a channel insulation structure between the first and second plurality of nanostructures. The channel insulation structure has a multilayer structure with a first channel insulation material and a second channel insulation material between the upper and lower parts of the first channel insulation material. The device further comprises: first source / drain regions at opposite ends of the first plurality of nanostructures; second source / drain regions above the first source / drain regions, the second source / drain regions being located at opposite ends of the second plurality of nanostructures; a first gate structure surrounding the first plurality of nanostructures; and a second gate structure surrounding the second plurality of nanostructures.Optionally, in some embodiments, the multilayer stack further comprises a third channel insulation material on the sidewalls of the second channel insulation material, and the device further comprises: first internal spacers between the sidewalls of the first gate structure and the first source / drain regions; and second internal spacers between the sidewalls of the second gate structure and the second source / drain regions, wherein the first and second internal spacers and the third channel insulation material have the same material composition. Optionally, in some embodiments, the second internal spacers overlap the first, second, and third channel insulation materials. Optionally, in some embodiments, the second channel insulation material has a lower dielectric constant than the first channel insulation material.Optionally, in some embodiments, the first channel insulation material is harder than the second channel insulation material.

[0074] In some embodiments, a method comprises fabricating a multilayer stack containing: lower semiconductor nanostructures stacked alternately with first dummy nanostructures; upper semiconductor nanostructures stacked alternately with second dummy nanostructures; and a third dummy nanostructure between the lower and upper semiconductor nanostructures.The method further comprises: structuring a source / drain recess with the multilayer stack; replacing the third dummy nanostructure with one or more channel insulating materials; after replacing the third dummy nanostructure with the one or more channel insulating materials, recessing sidewalls of the first and second dummy nanostructures; fabricating internal spacers on recessed sidewalls of the first and second dummy nanostructures; creating a first and a second source / drain region in the source / drain recess, wherein the first source / drain region is adjacent to the lower semiconductor nanostructures and the second source / drain regions are adjacent to the upper semiconductor nanostructures; replacing the first dummy nanostructures with a first gate structure; and replacing the second dummy nanostructures with a second gate structure.Optionally, in some embodiments, the third dummy nanostructure is in direct contact with the first and second dummy nanostructures. Optionally, in some embodiments, the third dummy nanostructure is in direct contact with a first and a second dummy semiconductor nanostructure, wherein the first and second dummy semiconductor nanostructures have the same material composition as the lower and upper semiconductor nanostructures.Optionally, in some embodiments, replacing the third dummy nanostructure with one or more channel insulating materials comprises the following: removing the third dummy nanostructure to define a gap between the lower and upper semiconductor nanostructures; depositing a first channel insulating material layer on the top and bottom surfaces of the gap; filling the remaining portion of the gap with a second channel insulating material layer; and removing excess portions of the first and second channel insulating material layers located outside the gap to define a first and a second channel insulating material. Optionally, in some embodiments, the second channel insulating material layer has a lower k-value than the first channel insulating material layer.Optionally, in some embodiments, the method further comprises: during the embedding of sidewalls of the first and second dummy nanostructures, embedding a sidewall of the second channel insulation material; and during the fabrication of the internal spacers, fabricating a third channel insulation material on an embeddingd sidewall of the second channel insulation material. Optionally, in some embodiments, the first and second dummy nanostructures and the third dummy nanostructure each contain silicon germanium, the third dummy nanostructure having a higher germanium concentration than the first and second dummy nanostructures.

[0075] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 700.005

[0001]

Claims

[1] Device with: a multi-layer stack containing the following: a first majority of nanostructures, a second plurality of nanostructures over the first plurality of nanostructures, and a first channel insulation structure; first source / drain regions at opposite ends of the first plurality of nanostructures; second source / drain regions above the first source / drain regions, wherein the second source / drain regions are arranged at opposite ends of the second plurality of nanostructures; a first gate structure around the first plurality of nanostructures, wherein the first gate structure contacts a first side face of the first channel insulation structure; and a second gate structure surrounding the second plurality of nanostructures. [2] Device according to claim 1, wherein the first channel isolation structure is arranged between the first and the second plurality of nanostructures. [3] Device according to claim 1 or 2, wherein the second gate structure contacts a second side surface of the first channel isolation structure. [4] Device according to one of the preceding claims, wherein the first channel insulation structure is arranged below the first plurality of nanostructures. [5] Device according to any one of the preceding claims, further comprising: an intermediate layer dielectric (ILD) beneath the first source / drain regions, wherein the ILD extends along sidewalls of the first channel insulation structure. [6] Device according to one of the preceding claims, wherein the multilayer stack further comprises a second channel insulation structure over the second plurality of nanostructures. [7] Device according to any one of the preceding claims, further comprising: first internal spacers between side walls of the first gate structure and the first source / drain areas; and second internal spacers between side walls of the second gate structure and the second source / drain areas, wherein The first and second internal spacers have the same material composition. [8] Device according to claim 7, wherein the first and second internal spacers have a different material composition than the first channel insulation structure. [9] Device with: a first plurality of nanostructures; a second plurality of nanostructures over the first plurality of nanostructures; a channel isolation structure between the first and second plurality of nanostructures, wherein the channel isolation structure has a multilayer structure comprising the following: a first channel insulation material, and a second channel insulation material between the upper and lower parts of the first channel insulation material; first source / drain regions at opposite ends of the first plurality of nanostructures; second source / drain regions above the first source / drain regions, wherein the second source / drain regions are arranged at opposite ends of the second plurality of nanostructures; a first gate structure surrounding the first plurality of nanostructures; and a second gate structure surrounding the second plurality of nanostructures. [10] Device according to claim 9, wherein the multilayer structure continues to have a third channel insulation material on the side walls of the second channel insulation material, and the device further features the following: first internal spacers between side walls of the first gate structure and the first source / drain areas; and second internal spacers between side walls of the second gate structure and the second source / drain areas, where The first and second internal spacers and the third channel insulation material have the same material composition. [11] Device according to claim 10, wherein the second internal spacers overlap the first, the second and the third channel insulation material. [12] Device according to any one of claims 9 to 11, wherein the second channel insulation material has a lower dielectric constant than the first channel insulation material. [13] Device according to any one of claims 9 to 12, wherein the first channel insulation material is harder than the second channel insulation material. [14] Procedures, including: Manufacturing a multi-layer stack, wherein the multi-layer stack contains the following: lower semiconductor nanostructures stacked alternately with first dummy nanostructures, upper semiconductor nanostructures stacked alternately with second dummy nanostructures, and a third dummy nanostructure between the lower and upper semiconductor nanostructures; Structuring a source / drain recess using the multi-layer stack; Replacing the third dummy nanostructure with one or more channel insulation materials; After replacing the third dummy nanostructure with one or more channel insulation materials, the side walls of the first and second dummy nanostructures are left bare; Fabrication of internal spacers on recessed side walls of the first and second dummy nanostructures; Creating a first and a second source / drain region in the source / drain recess, wherein the first source / drain region is adjacent to the lower semiconductor nanostructures and the second source / drain regions are adjacent to the upper semiconductor nanostructures; Replacing the first dummy nanostructures with a first gate structure; and Replacing the second dummy nanostructures with a second gate structure. [15] Method according to claim 14, wherein the third dummy nanostructure is in direct contact with the first and the second dummy nanostructures. [16] Method according to claim 14 or 15, wherein the third dummy nanostructure is in direct contact with a first and a second dummy semiconductor nanostructure, wherein the first and the second dummy semiconductor nanostructure have the same material composition as the lower and the upper semiconductor nanostructures. [17] Method according to any one of claims 14 to 16, wherein replacing the third dummy nanostructure with one or more channel insulation materials comprises: Removing the third dummy nanostructure to define a gap between the lower and upper semiconductor nanostructures; Deposition of a first channel insulation material layer on the top and bottom surfaces of the gap; Filling the remaining parts of the gap with a second layer of channel insulation material; and Removing excess portions of the first and second channel insulation material layers located outside the gap to define a first and a second channel insulation material. [18] Method according to claim 17, wherein the second channel insulation material layer has a lower k-value than the first channel insulation material layer. [19] The method of claim 17 or 18, further comprising: During the omission of side walls of the first and second dummy nanostructures, omission of a side wall of the second channel insulation material; and During the production of the internal spacers, a third channel insulation material is produced on a recessed side wall of the second channel insulation material. [20] Method according to any one of claims 14 to 19, wherein the first and second dummy nanostructures and the third dummy nanostructure each contain silicon germanium, wherein the third dummy nanostructure has a higher germanium concentration than the first and second dummy nanostructures.

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