Operating circuit for a light source and method for data transmission

Abstract

Operating circuit for a light source (3), comprising: a first integrated circuit (14; 20), a second integrated circuit (15; 30) and at least one galvanically isolated transmission channel (16; 31, 32) between the first integrated circuit (14; 20) and the second integrated circuit (15; 30), wherein the first integrated circuit (14; 20) is set up to determine a baud rate of the second integrated circuit (15; 30) by means of baud rate detection, wherein the second integrated circuit (15; 30) is configured for the transmission of synchronization data (74, 75) via the at least one galvanically isolated transmission channel (16; 31, 32), wherein the first integrated circuit (14; 20) is set up to detect the baud rate of the second integrated circuit (15; 30) depending on the signal edges of the synchronization data (74, 75).

Description

[0001] The invention relates to an operating circuit for a light source. The invention particularly relates to operating circuits comprising several integrated circuits, for example, several microcontrollers or several microprocessors.

[0002] With the increasing prevalence of light sources such as LEDs, LED modules, or gas discharge lamps, operating circuits for these light sources are gaining in importance. These operating circuits can be designed as LED converters or electronic ballasts. The primary function of the operating circuit is to provide the desired energy supply to the light source. Additional functions can be integrated into the operating circuit to enable, for example, dimming of the light source and / or color control.

[0003] The operating circuit can comprise one or more integrated circuits that perform control, regulation, logging, and / or communication functions. The operating circuit can include one integrated circuit on a primary side and another integrated circuit on a secondary side. The primary and secondary sides can be galvanically isolated. Similarly, a transmission channel for data transmission between the primary and secondary integrated circuits can be galvanically isolated. Such a transmission channel allows the transmission of commands from the primary to the secondary and / or the feedback of measured values ​​from the secondary to the primary.

[0004] Data transmission between the primary and secondary integrated circuits can be a digital serial transmission. Differences in the baud rates of the integrated circuits can lead to problems in the operation of the operating circuit. Such differences can be caused, for example, by oscillator tolerances, temperature variations within the operating circuit, differing temperature-dependent behavior of the integrated circuits, or aging.

[0005] DE 10 2012 020 988 A1 discloses a method for controlling at least one control gear for light sources, in particular LEDs, and an interface for receiving control commands via a control line. The interface receives two-discrete signals for the light source's control gear, wherein an optocoupler with an integrated LED is arranged in series with two transistors. The first transistor has a current-regulating function, and the second transistor has a switching function. A resistor is connected between the two transistors.

[0006] The invention is based on the objective of providing devices and methods in which the susceptibility to errors in data transmission between integrated circuits is reduced, even in the case of temperature differences within the operating circuit, different temperature-dependent behavior of the integrated circuits, larger oscillator tolerances, or aging.

[0007] An operating circuit for a light source and a method with the features specified in the independent claims are described. The dependent claims define embodiments of the invention.

[0008] According to exemplary embodiments of the invention, a first integrated circuit coupled to a second integrated circuit performs baud rate detection to determine the baud rate of the second integrated circuit. This allows the baud rate of the first integrated circuit to be matched to the determined baud rate of the second integrated circuit.

[0009] An operating circuit for a light source according to one embodiment comprises a first integrated circuit, a second integrated circuit, and at least one galvanically isolated transmission channel between the first and second integrated circuits. The first integrated circuit is configured to determine the baud rate of the second integrated circuit by means of baud rate detection.

[0010] The first integrated circuit can be a processor, a microprocessor, a controller, a microcontroller, or an application-specific integrated circuit (ASIC). The first integrated circuit can be designed to perform at least one control function and / or regulation function. The first integrated circuit can be designed to control at least one circuit component of a primary side of the operating circuit.

[0011] The second integrated circuit can be a processor, a microprocessor, a controller, a microcontroller, or an application-specific integrated circuit (ASIC). The second integrated circuit can be configured to provide feedback to the first integrated circuit at least one measured value acquired on a secondary side of the operating circuit. The second integrated circuit can be configured to perform at least one control function. The second integrated circuit can be different from the first integrated circuit.

[0012] The second integrated circuit can be located in a SELV (Separated Extra-Low Voltage) section of the operating circuit. The second integrated circuit can be coupled to the first integrated circuit via at least one transmission channel and a SELV barrier.

[0013] The first integrated circuit can be configured so that its baud rate is variable. The first integrated circuit can be configured to adjust its baud rate to match the baud rate of the second integrated circuit, depending on the baud rate detected by the second. The first integrated circuit can be configured to set its baud rate to be equal to the baud rate of the second integrated circuit. When data is transferred from the second integrated circuit to the first, the first integrated circuit can select sampling times based on the detected baud rate of the second integrated circuit.

[0014] The second integrated circuit is configured according to the invention for transmitting synchronization data via at least one galvanically isolated transmission channel. The synchronization data can comprise one or more synchronization bytes. Each synchronization byte can be transmitted in a UART (Universal Asynchronous Receiver Transmitter) frame.

[0015] The second integrated circuit can be configured to monitor the state of at least one galvanically isolated transmission channel in order to automatically initiate the transmission of synchronization data. This allows for a simple triggering of the synchronization data transmission.

[0016] The second integrated circuit can be configured to begin transmitting synchronization data when at least one galvanically isolated transmission channel is in a sleep state. The second integrated circuit can be configured to begin transmitting synchronization data when a galvanically isolated transmission channel remains in a sleep state, also known in engineering as the "idle bus" state, for a predetermined period of time.

[0017] The first integrated circuit can be configured to withhold data transmission to the second integrated circuit via at least one galvanically isolated transmission channel for a predetermined period, thereby triggering the transmission of synchronization data. The transmission of synchronization data can thus be easily initiated by the first integrated circuit delaying or interrupting data transmission to the second integrated circuit.

[0018] The first integrated circuit can be configured to delay or interrupt data transmission to the second integrated circuit at least until the first integrated circuit receives the synchronization data. The first integrated circuit can also be configured to delay or interrupt data transmission to the second integrated circuit at least until the first integrated circuit has completed baud rate detection to determine the baud rate of the second integrated circuit.

[0019] According to the invention, the first integrated circuit is configured to determine the baud rate of the second integrated circuit based on the synchronization data. The first integrated circuit can be configured to determine at least one time interval between a signal edge of a bit of the synchronization data and a subsequent signal edge of another bit of the synchronization data.

[0020] The first integrated circuit can be configured to determine multiple time intervals between signal edges of bits in the synchronization data and to perform a consistency check of these intervals. For the consistency check, a measure of deviations between the multiple time intervals can be determined. For example, a variance or a maximum deviation from a mean value can be calculated as a measure of the deviations between the multiple time intervals. The first integrated circuit can continue evaluating the synchronization data until the measure of deviations meets a predetermined criterion.

[0021] The first integrated circuit can be configured to terminate the transmission of synchronization data by transferring data to the second integrated circuit. This allows the transmission of synchronization data to be terminated easily.

[0022] The first integrated circuit can be set up to perform baud rate detection depending on frame errors in data transmitted from the second integrated circuit to the first integrated circuit.

[0023] The first integrated circuit can include a counter and can be configured to perform baud rate detection depending on a value of the counter.

[0024] The first integrated circuit can be configured to increment the counter value if a data frame has a frame error. The first integrated circuit can also be configured to decrement the counter value if a data frame does not have a frame error.

[0025] The first integrated circuit can be set up to perform baud rate detection when the operating circuit is started and subsequently again depending on the value of the counter.

[0026] The operating circuit can have a primary side with the first integrated circuit and a galvanically isolated secondary side with the second integrated circuit. The primary and secondary sides can be separated by a SELV barrier. The primary side can have the primary inductance of a transformer. The secondary side can have the secondary inductance of the transformer.

[0027] The operating circuitry can be housed in a single enclosure. Both the first and second integrated circuits can be located within the enclosure.

[0028] The first integrated circuit and the second integrated circuit can be arranged on the same substrate. The first integrated circuit and the second integrated circuit can be arranged on the same printed circuit board.

[0029] The operating circuit can be designed as an LED operating circuit. The operating circuit can be designed as an LED converter. The operating circuit can be designed as an electronic ballast for a discharge lamp.

[0030] According to a further embodiment, a lighting system is specified which comprises the operating circuit according to an embodiment and at least one light source that is connected to the operating circuit.

[0031] The light source can consist of LEDs or an LED module with multiple LEDs. The LEDs can be inorganic and / or organic.

[0032] The light source can include a gas discharge lamp.

[0033] In a further embodiment, a method for data transmission between a first integrated circuit and a second integrated circuit of an operating circuit for a light source is described. In this method, the first integrated circuit determines the baud rate of the second integrated circuit. Data is transmitted between the first and second integrated circuits via at least one galvanically isolated transmission channel. During data transmission, the first integrated circuit is controlled based on the determined baud rate of the second integrated circuit.

[0034] In methods according to embodiments of the invention, the first integrated circuit, the second integrated circuit and / or the operating circuit may have the features described with reference to the embodiments of the operating circuit.

[0035] According to the invention, the method comprises the transmission of synchronization data from the second integrated circuit to the first integrated circuit via at least one galvanically isolated transmission channel. The synchronization data can comprise one or more synchronization bytes. Each synchronization byte can be transmitted in a UART frame.

[0036] The method can include monitoring the state of at least one galvanically isolated transmission channel by the second integrated semiconductor circuit. The transmission of the synchronization data can be started automatically depending on the result of the monitoring.

[0037] The second integrated circuit can automatically begin transmitting synchronization data when at least one galvanically isolated transmission channel is in a sleep state. The second integrated circuit can automatically begin transmitting synchronization data when a galvanically isolated transmission channel is in a sleep state for a specific period.

[0038] The duration of the idle state, i.e., the so-called "idle bus" state, remains.

[0039] The method may include delaying or interrupting data transmission from the first integrated circuit to the second integrated circuit at least until the first integrated circuit receives the synchronization data. The method may also include delaying or interrupting data transmission from the first integrated circuit to the second integrated circuit at least until the first integrated circuit has completed baud rate detection to determine the baud rate of the second integrated circuit.

[0040] According to the invention, the baud rate of the second integrated circuit is determined by the first integrated circuit depending on the synchronization data. For this purpose, at least a time interval between a signal edge of a bit of the synchronization data and a further signal edge of another bit of the synchronization data can be determined.

[0041] Determining the baud rate of the second integrated circuit can involve determining several time intervals between signal edges of bits in the synchronization data. The procedure can include a consistency check of the determined time intervals. For this consistency check, a measure of deviations between the time intervals can be determined.

[0042] The procedure may include data transmission from the first integrated circuit to the second integrated circuit to complete the transmission of the synchronization data.

[0043] In this method, baud rate detection can be performed depending on frame errors in the data transmitted from the second integrated circuit to the first integrated circuit.

[0044] Baud rate detection can be performed based on the value of a counter. The procedure can involve incrementing the counter value if a data frame has a frame error. The procedure can involve decrementing the counter value if a data frame does not have a frame error.

[0045] In this method, the first integrated circuit can perform a baud rate detection to determine the baud rate of the second integrated circuit when the operating circuit starts. The first integrated circuit can perform the baud rate detection again depending on the counter value.

[0046] The procedure can be executed automatically using the operating circuit according to an exemplary embodiment.

[0047] The methods according to the various embodiments and the effects achieved thereby correspond to the configurations of the operating circuit according to exemplary embodiments.

[0048] An operating circuit for a light source according to a further embodiment comprises a first integrated circuit, a second integrated circuit, and at least one transmission channel between the first and second integrated circuits. The first integrated circuit is configured to determine the baud rate of the second integrated circuit by means of baud rate detection.

[0049] The invention is explained below with reference to the figures and preferred embodiments. In the figures, identical reference numerals denote identical elements. Fig. Figure 1 shows a lighting system according to an exemplary embodiment. Fig. Figure 2 shows a block diagram of an operating circuit according to an exemplary embodiment. Fig. Figure 3 is a flowchart of a process according to an exemplary embodiment. Fig. Figure 4 is a flowchart of a procedure that is executed by a first integrated circuit in an exemplary embodiment. Fig. Figure 5 is a flowchart of a procedure that is executed by a second integrated circuit in one embodiment. Fig. Figure 6 illustrates the operation of an operating circuit and a method according to an exemplary embodiment. Fig. Figure 7 shows an implementation of a UART frame with a synchronization byte. Fig. Figure 8 illustrates an adjustment of baud rates. Fig. Figure 9 is a block diagram of a first integrated circuit of an operating circuit according to an exemplary embodiment.

[0050] Fig. Figure 1 shows a representation of a lighting system 1, which includes a control gear with an operating circuit 2 for a light source 3. The light source 3 can be LEDs, an LED module with multiple LEDs, or a gas discharge lamp. The LEDs can be inorganic or organic. The control gear can be connected to an external bus or a wireless communication system to receive dimming commands from a controller and / or output status messages.

[0051] The operating circuit 2 can, for example, be designed as an electronic ballast (ECG) for a gas discharge lamp, fluorescent lamp or other fluorescent lamp or as an LED converter.

[0052] As described in more detail below, the operating circuit 2 has two integrated circuits (ICs) 14, 15 and at least one transmission channel for data transmission between the integrated circuits 14, 15.

[0053] At least one transmission channel is a galvanically isolated transmission channel, i.e. it has a galvanic isolation 16.

[0054] As with reference to Fig. 2 to Fig. As described in detail in Section 9, at least one of the integrated circuits 14, 15 has an automatic baud rate detection (ABD) function to determine the baud rate of the other integrated circuit. The integrated circuit performing the ABD adjusts its operation to the detected baud rate of the other integrated circuit.

[0055] The operating circuit can have a primary side 17 and a secondary side 18, which are galvanically isolated. The secondary side 18 can be a SELV section separated from the primary side 17 by an SELV barrier 19. Power transfer can be achieved, for example, by a transformer whose primary-side inductance is located on the primary side 17 and whose secondary-side inductance is located on the secondary side 18. Other converters can be used.

[0056] The specific design of the other circuit components of the operating device can be selected depending on the application. For example, the operating circuit 2 can include a rectifier 10 for rectifying a supply voltage, such as the mains voltage. The operating circuit 2 can also include a power factor correction circuit 11. The power factor correction circuit 11 provides a voltage, also known as a bus voltage, for downstream components of the operating circuit 2. Further voltage conversion and / or dimming functions can be achieved, for example, via a converter 12. The converter 12 can be designed as a resonant converter. Other converter circuits can also be used. The converter 12 can include a transformer or other converter to achieve galvanic isolation between the primary side 18 and the secondary side 17.An output circuit 13 can be provided to supply a desired supply voltage and / or a desired supply current for the light source 3 at an output of the operating circuit.

[0057] The integrated circuits 14, 15 can each perform different functions, depending on the specific design of the operating circuit 2.

[0058] The integrated circuit 14 on the primary side 17 can perform a control and / or regulation function. The primary-side integrated circuit 14 can control the power factor correction circuit 11 and / or the converter 12. For this purpose, the primary-side integrated circuit 14 can control at least one controllable switching device on the primary side 17. The primary-side integrated circuit 14 can control the at least one controllable switching device depending on a measured quantity detected on the primary input. The primary-side integrated circuit 14 can perform a control and / or regulation function that depends on data that is fed back to the integrated circuit 14 from the integrated circuit 15 of the secondary side 18 via the at least one galvanically isolated transmission channel.For example, the primary-side integrated circuit 14 can control the power factor correction circuit 11 and / or the converter 12 depending on a measured value that is acquired on the secondary side 18 and transmitted by the secondary-side integrated circuit 15 to the primary-side integrated circuit 14 via the galvanically isolated transmission channel. The primary-side integrated circuit 14 can also perform communication functions. For example, the primary-side integrated circuit 14 can be connected to an interface for an external bus or a wireless system to report information about the status of the operating circuit 2 or other data to a central controller.

[0059] The integrated circuit 15 on the secondary side 18 can, for example, be configured to transmit a measured value acquired on the secondary side 18 to the primary-side circuit 14 via the galvanically isolated transmission channel. The secondary-side integrated circuit 15 can perform a control and / or regulation function. For example, depending on configuration data transmitted by the primary-side integrated circuit 14 via the galvanically isolated transmission channel, the secondary-side integrated circuit 15 can control a controllable switching device of the output circuit 13.

[0060] Other configurations and functions of the primary-side integrated circuit 14 and / or the secondary-side integrated circuit 15 can be implemented in further embodiments. The operating circuit 2 can be arranged in a housing. The integrated circuits 14 and 15 can be arranged on the same substrate.

[0061] The integrated circuits 14 and 15 can be configured for asynchronous data transmission. The operating circuit 2 can be designed such that there is no clock line between the integrated circuits 14 and 15. The integrated circuits 14 and 15 can be configured for UART data transmission.

[0062] As with reference to Fig. 2 to Fig. As described in detail in Section 9, the integrated circuits 14 and 15 are configured such that the baud rate of one integrated circuit can be adapted to the baud rate of the other integrated circuit. One of the integrated circuits can synchronize its baud rate against the baud rate of the other integrated circuit. To do this, the corresponding integrated circuit performs automatic baud rate detection to determine the baud rate of the other integrated circuit.

[0063] Fig. Figure 2 schematically shows the integrated circuits 20, 30 of an operating circuit for a light source. A first integrated circuit 20 and a second integrated circuit 30 are coupled for data transmission by at least one galvanically isolated transmission channel 31, 32.

[0064] The first integrated circuit 20 can be the primary-side integrated circuit 14, and the second integrated circuit 30 can be the secondary-side integrated circuit 15. Alternatively, the first integrated circuit 20 can be the secondary-side integrated circuit 15, and the second integrated circuit 30 can be the primary-side integrated circuit 14.

[0065] The first integrated circuit 20 and the second integrated circuit 30 can each be designed as a processor, a microprocessor, a controller, a microcontroller or an application-specific integrated circuit (ASIC).

[0066] In the illustrated embodiment, at least one transmission channel comprises a first bus 31 and a second bus 32. The first bus 31 has a galvanic isolation device 33. The second bus 32 has a galvanic isolation device 34. The galvanic isolation devices 33 and 34 can, for example, each comprise inductive galvanic isolation, capacitive galvanic isolation, an optocoupler, or other elements.

[0067] At the in Fig. In the embodiment shown in Figure 2, the first bus 31 can be used for unidirectional data transmission from the first integrated circuit 20 to the second integrated circuit 30. The second bus 32 can be used for unidirectional data transmission from the second integrated circuit 30 to the first integrated circuit 20. Other embodiments of the at least one transmission channel can be used. For example, a bidirectional interface can also be provided to allow bidirectional data transmission. More bus lines can also be provided.

[0068] The at least one galvanically isolated transmission channel 31, 32 serves as an interface for digital data transmission. This at least one galvanically isolated transmission channel 31, 32 can be configured to allow serial digital data transmission between the first integrated circuit 20 and the second integrated circuit 30. In this process, one of the integrated circuits 20, 30 can transmit a sequence of data bits to the other. The other integrated circuit 20, 30 can monitor the signal level on the bus to detect transitions between signal levels corresponding to a logical "1" and a logical "0". The data bits can be transmitted in a frame.For example, a UART frame can be generated by one of the integrated circuits 20, 30, transmitted via at least one galvanically isolated transmission channel and received and evaluated by the other of the integrated circuits 20, 30.

[0069] An asynchronous operating mode can be used, in which no dedicated clock signal is used on a transmission line. The integrated circuits 20 and 30, each acting as a receiver for data transmission, can detect the start of a frame of data bits by a signal edge of a start bit. The subsequent data bits can be determined based on the signal level at several sampling points, which are defined according to a baud rate.

[0070] To reduce the risk of transmission errors between the integrated circuits 20 and 30, the operating circuit for the light source is designed to allow for adjustment of the baud rates of the integrated circuits 20 and 30. For this purpose, at least one of the integrated circuits 20 or 30 has an ABD function 21 for automatic baud rate detection. In the illustrated embodiment, only the first integrated circuit 20 has an ABD function to detect the baud rate of the second integrated circuit 30. The second integrated circuit 30 does not need to have an ABD function.

[0071] For automatic baud rate detection, the first integrated circuit 20 can determine the time interval between at least two signal edges of bits in a data frame that is transmitted by the second integrated circuit 30, for example, via bus 32. The first integrated circuit 20 can adapt its operation when evaluating a received signal and / or when generating and transmitting a data frame to the second integrated circuit to the detected baud rate of the second integrated circuit 30. The baud rate of the first integrated circuit 20 can be set so that it is equal to the detected baud rate of the second integrated circuit 30.

[0072] Automatic baud rate detection can be performed using synchronization data transmitted from the second integrated circuit 30 to the first integrated circuit 20. The synchronization data can consist of a sequence of bits with alternating logical values ​​"0" and "1". At least one frame of synchronization data can be transmitted from the second integrated circuit 30 to the first integrated circuit 20. The transmission of such frames can be initiated by the first integrated circuit 30. The first integrated circuit 20 can transmit a specific command via bus 31 to the second integrated circuit 30 to cause the second integrated circuit 30 to transmit the synchronization data. As described with reference to Fig. 4 and Fig. As described in more detail in section 5, the second integrated circuit 30 can also automatically begin transmitting synchronization data if it detects that no data transmission has occurred from the first integrated circuit 20 to the second integrated circuit 30 for a specified period of time. The second integrated circuit 30 can also monitor whether the bus 31 is in a resting state for a certain period of time, a state typically referred to as the "idle bus" state.

[0073] The first integrated circuit 20 can automatically detect the baud rate when the operating circuit is started. Alternatively or additionally, the first integrated circuit 20 can detect the baud rate automatically when it detects errors in the data transmission between the second integrated circuit 30 and the first integrated circuit 20. For example, the first integrated circuit 20 can detect frame errors and, depending on the findings, determine whether the baud rate of the second integrated circuit 30 should be recalculated. The operation of the first integrated circuit 20 can be adjusted to the determined baud rate of the second integrated circuit 30.

[0074] Fig. Figure 3 is a flowchart of a method 40 according to an exemplary embodiment. The method 40 can be executed automatically by the first integrated circuit 20 and the second integrated circuit 30.

[0075] Step 41 starts the operating circuit.

[0076] In step 42, a procedure for adjusting the baud rates is performed. The first integrated circuit 20 can perform automatic baud rate detection to determine the baud rate of the second integrated circuit 30. The second integrated circuit 30 can transmit a predefined bit sequence to the first integrated circuit 20. The first integrated circuit 20 can determine the baud rate of the second integrated circuit 30 based on at least one time interval between signal edges of bits in the bit sequence.

[0077] In step 43, the first integrated circuit 20 can transfer configuration data to the second integrated circuit 30. The first integrated circuit 20 can then configure the second integrated circuit 30 for subsequent operation. During the transfer of configuration data to the second integrated circuit 30, the first integrated circuit 20 can adjust the baud rate for data transmission based on the detected baud rate of the second integrated circuit 30.

[0078] In step 44, the operating circuit is in a functional mode. The operating circuit supplies the light source with energy. During functional operation, data transmission can take place between the first integrated circuit 20 and the second integrated circuit 30.

[0079] When receiving data from the second integrated circuit 30 during operation, the first integrated circuit 20 can select sampling times, at which the signal level on bus 32 is sampled to distinguish a bit with a logical value "0" from a bit with a logical value "1", depending on the previously determined baud rate of the second integrated circuit. This allows, for example, oscillator tolerances or temperature-dependent differences between the first integrated circuit 20 and the second integrated circuit 30 to be at least partially compensated.

[0080] When transferring data from the first integrated circuit 20 to the second integrated circuit 30, the first integrated circuit 20 can control the signal level on the bus 31 so that the signal edges of bits are generated at times that depend on the detected baud rate of the second integrated circuit 30.

[0081] During normal operation, the first integrated circuit can detect 20 transmission errors. For example, the first integrated circuit can detect frame errors in data transmitted from the second integrated circuit 30 to the first integrated circuit 20.

[0082] In step 45, the first integrated circuit 20 can determine, based on the detected frame errors, whether the baud rate of the second integrated circuit 30 should be recalculated. For this purpose, the value of a counter, which is incremented and / or decremented depending on whether frame errors are present, can be compared with a threshold value. If a recalculation of the baud rate of the second integrated circuit 30 is not required to adjust the baud rates, operation can continue at step 44.

[0083] In step 46, the first integrated circuit 20 can again determine the baud rate of the second integrated circuit 30 if a baud rate adjustment is required. The re-determination of the baud rate of the second integrated circuit 20 can be performed as described in step 42. During the baud rate re-determination procedure, data transmission between the first integrated circuit 20 and the second integrated circuit 30 can be interrupted. The second integrated circuit 30 can transmit synchronization data to the first integrated circuit 20 during this phase.In subsequent data transmissions from the first integrated circuit 20 to the second integrated circuit 30 and / or from the second integrated circuit 30 to the first integrated circuit 20, the first integrated circuit 20 can operate depending on the newly detected baud rate of the second integrated circuit 30.

[0084] The automatic baud rate detection in step 42 and / or step 46 can be based on synchronization data transmitted by the second integrated circuit 30 to the first integrated circuit 20. The synchronization data can comprise at least one frame with a predefined bit sequence. The predefined bit sequence can include multiple transitions between the bit values ​​"0" and "1". Multiple consecutive frames with the predefined bit sequence can be transmitted.

[0085] The transmission of synchronization data can be triggered by the first integrated circuit 20 sending a corresponding command to the second integrated circuit 30. In response, the second integrated circuit 30 can begin transmitting the synchronization data. Several frames can be transmitted until the second integrated circuit 30 is signaled that no further synchronization data should be transmitted. The transmission of synchronization data can be terminated by the first integrated circuit 20 sending a corresponding command to the second integrated circuit 30 via bus 31.

[0086] The transmission of synchronization data can also be triggered by the first integrated circuit 20 delaying or interrupting data transmission to the second integrated circuit 30. The second integrated circuit 30 can be configured to automatically send synchronization data if it does not receive any data transmission from the first integrated circuit 20 for a predetermined period. The second integrated circuit 30 can monitor whether the bus 31 is in an "idle bus" state. The transmission of synchronization data can be terminated when the second integrated circuit 30 detects that data transmission is taking place from the first integrated circuit 20 to the second integrated circuit 30. For this purpose, the second integrated circuit 30 can monitor whether the bus 31 is leaving the "idle bus" state.The corresponding procedures, which are executed by the first integrated circuit 20 and the second integrated circuit 30, are described with reference to . Fig. 4 and Fig. 5 described.

[0087] Fig. Figure 4 is a flowchart of a procedure 50 executed by the first integrated circuit 20 in a method according to an embodiment. The first integrated circuit 20 controls the transmission of synchronization data by the second integrated circuit 30 by delaying or interrupting data transmission to the second integrated circuit 20.

[0088] In step 51, the first integrated circuit is started. This can happen when the operating circuit is started.

[0089] Step 52 checks whether the first integrated circuit 20 is already receiving synchronization data. If no synchronization data has been received, the check in step 52 can be repeated after a waiting period in step 53. This delays data transmission to the second integrated circuit 30 in order to trigger the transmission of synchronization data. If synchronization data is received, procedure 50 continues in step 54.

[0090] In step 54, the baud rate of the second integrated circuit 30 is determined. For this purpose, at least one time interval between signal edges of bits in the synchronization data can be determined. To determine the baud rate, several frames of the synchronization data can be received and analyzed. For example, the first integrated circuit 20 can determine the intervals between signal edges for each received frame of the synchronization data. This can be repeated for further frames of the synchronization data until a consistency criterion is met.

[0091] In step 55, the baud rate of the first integrated circuit 20 is adjusted to match the determined baud rate of the second integrated circuit 30. This can be achieved by defining sampling points for the signal level on bus 32 and / or the timing of signal edges on bus 31, depending on the baud rate of the second integrated circuit 30. The operation of the first integrated circuit 20 when receiving and transmitting data can then be adjusted so that its baud rate matches the determined baud rate of the second integrated circuit 30.

[0092] In step 56, the first integrated circuit 20 can transmit data to the second integrated circuit 30. This signals to the second integrated circuit 30 that no further frames with synchronization data should be sent. The timing of the signal edges of the bits of a frame on bus 31 can be determined depending on the baud rate of the second integrated circuit 30.

[0093] In step 57, the first integrated circuit 20 can receive data from the second integrated circuit 30. The sampling points for the signal level on bus 32 can be set depending on the baud rate of the second integrated circuit 30.

[0094] Step 58 allows you to check whether another automatic baud rate detection should be performed. This check can be carried out as described for step 45. If no further automatic baud rate detection is to be performed, the procedure returns to step 56.

[0095] If another automatic baud rate detection is to be performed, the first integrated circuit 20 interrupts the data transmission to the second integrated circuit 30 at step 59. The procedure returns to step 52. The data transmission from the first integrated circuit 20 to the second integrated circuit 30 is interrupted to cause the second integrated circuit 30 to send synchronization data.

[0096] Fig. Figure 5 is a flowchart of a procedure 60 that can be executed by the second integrated circuit 30. The second integrated circuit 30 automatically sends synchronization data if data transmission from the first integrated circuit 20 to the second integrated circuit 30 is delayed or interrupted.

[0097] In step 61, the second integrated circuit 30 is started. This can happen when the operating circuit is started.

[0098] In step 62, it is checked whether the second integrated circuit 30 receives data from the first integrated circuit via the at least one galvanically isolated transmission channel. If data is received, the second integrated circuit can process the data in step 63 and perform appropriate actions. For example, in step 63, the second integrated circuit 30 can transmit data to the first integrated circuit 20 to report a measured value. The procedure then returns to step 62.

[0099] If no data is received from the first integrated circuit 20, step 64 can be used to check whether a criterion for transmitting synchronization data is met. This can be done by determining whether bus 31 is in an "idle bus" state. It can also be determined whether bus 31 has been in an "idle bus" state for a specified duration. If the criterion for transmitting synchronization data is not met, the procedure returns to step 62.

[0100] If the criterion for transmitting synchronization data is met, the second integrated circuit 30 transmits synchronization data to the first integrated circuit 20 in step 65. A frame with a predefined bit sequence can be transmitted. The procedure then returns to step 62. The transmission of synchronization data continues with subsequent repetitions of steps 62, 64, and 65 until the second integrated circuit 30 receives data from the first integrated circuit.

[0101] Fig. Figure 6 illustrates automatic baud rate detection. A signal level 71 on a first bus 31 is evaluated by the second integrated circuit 30 to receive frames with multiple data bits. A signal level 72 on a second bus 32 is evaluated by the first integrated circuit 20 to receive frames with multiple data bits.

[0102] At time 70, the first bus 31 is in an "idle bus" state for a certain period of time. The second integrated circuit 30 transmits at least one frame 73, 74 containing synchronization data. The second frame 74 containing synchronization data is transmitted because the bus 31 is still in an idle state. Based on signal edges of bits from frame 73 and / or bits from frame 74, the first integrated circuit 21 determines the baud rate of the second integrated circuit 30.

[0103] When the first integrated circuit 20 has determined a baud rate value for the second integrated circuit 30 at time 75, the first integrated circuit 20 begins transmitting frames 76 containing data bits. The second integrated circuit 30 detects that the "Idie Bus" state is no longer present and stops transmitting frames containing synchronization data. In response to the data received from the first integrated circuit 20, the second integrated circuit 30 can transmit frames 77 containing data bits to the first integrated circuit 20.

[0104] As with reference to Fig. 6 and Fig. As described in section 7, the second integrated circuit 30 can be configured such that, with the exception of the transmission of synchronization data, it only transmits data to the first integrated circuit 20 when it has received a corresponding command from the first integrated circuit 20 via the galvanically isolated transmission channel. The first integrated circuit 20 can operate as a master unit, and the second integrated circuit 30 can operate as a slave unit. The second integrated circuit 30 can also perform automatic data transmission without receiving a corresponding data frame for the purpose of transmitting synchronization data.

[0105] Fig. Figure 7 shows frame 74 containing synchronization data. In the Fig. In the configuration shown in Figure 7, frame 74 has a start bit 80, eight data bits 81-88, a parity bit 89, and a stop bit 90. The eight data bits 81-88 contain several bits with a logical value of "0" and several bits with a logical value of "1". Four bits with a logical value of "0" and four bits with a logical value of "1" can alternate.

[0106] To determine the baud rate of the second integrated circuit 30, the first integrated circuit 20 can determine time intervals between signal edges of the bits of frame 74. The first integrated circuit 20 can determine time intervals 91-94 between successive rising or falling signal edges of the signal level.

[0107] The multiple time intervals 91-94 can be further processed computationally. The first integrated circuit 20 can subject the multiple time intervals 91-94 to a consistency check. In doing so, the first integrated circuit 20 can check whether deviations between the multiple time intervals 91-94 are not too large. The first integrated circuit 20 can determine a variance of the multiple time intervals 91-94, or another suitable measure of deviations between the multiple time intervals 91-94, and compare it with a threshold value. If the deviations between the multiple time intervals 91-94 are too large, the time intervals 91-94 can be discarded and recalculated for a new frame with synchronization data.

[0108] To robustly determine the baud rate of the second integrated circuit 30, the first integrated circuit 20 can perform an average calculation of the several time intervals 91-94.

[0109] Fig. Figure 8 shows a frame 95 containing data being transferred from the second integrated circuit 30 to the first integrated circuit 20. In the Fig. In the configuration shown in Figure 8, frame 95 also has a start bit 80, eight data bits 81-88, a parity bit 89 and a stop bit 90.

[0110] A signal edge 79 of the start bit 80 marks the beginning 96 of the frame and is detected by the first integrated circuit 20. The signal level is sampled at sampling times 97 to read the bit values ​​of the various bits. The sampling times 97 are determined by the first integrated circuit 20 depending on the previously determined baud rate of the second integrated circuit 30.

[0111] Similarly, when transferring data to the second integrated circuit 30, the first integrated circuit 20 can determine the timing of signal edges depending on the previously determined baud rate of the second integrated circuit 30.

[0112] The first integrated circuit 20 can detect erroneous data transmissions caused by a drift in the baud rates of the first and second integrated circuits by analyzing received frames 95. For example, the first integrated circuit 20 can be configured to detect so-called frame errors. The first integrated circuit 20 can detect whether a frame is received without a stop bit 90.

[0113] Frames 74 and 95 can be UART frames.

[0114] Fig. Figure 9 is a functional block diagram of the first integrated circuit 20. The corresponding functions may be provided in the first integrated circuit 20 according to exemplary embodiments, but not all of them need to be provided.

[0115] A receiver circuit 23 can monitor the signal level on a bus 32 to detect the transmission of a frame. Frame error detection 24 can be performed to identify faulty frames. For example, the absence of a stop bit can be detected. If a frame error is detected, the value of a counter 25 can be incremented. If a frame without frame errors is received, the value of the counter 25 can be decremented.

[0116] The value of counter 25 can be compared to a threshold value 26. If the value of counter 25 reaches or exceeds the threshold value 26, an automatic baud rate detection procedure can be executed.

[0117] A transmitter circuit 22 can be controlled to trigger the transmission of synchronization data. The transmitter circuit 22 can transmit a corresponding command via bus 31. The transmitter circuit 22 can maintain an "idle bus" state for bus 31 until the baud rate of the second integrated circuit has been determined.

[0118] Synchronization data received by receiver circuit 23 can be analyzed by ABD function 21. Depending on a single time interval or multiple time intervals between signal edges, the baud rate of the second integrated circuit can be determined. The multiple time intervals can be subjected to a consistency check 27. If the consistency check is positive, the baud rate can be determined, for example, by averaging multiple time intervals, by selecting one of the time intervals, by averaging the time intervals between signal edges over multiple frames of synchronization data, or by other means.

[0119] The transmitter circuit 22 and / or the receiver circuit 23 can then operate depending on the detected baud rate of the second integrated circuit 30. The first integrated circuit 20 can adapt to the detected baud rate of the second integrated circuit 30 when transmitting data to it and / or when receiving data from it. The first integrated circuit 20 can send and receive data such that its baud rate matches the detected baud rate of the second integrated circuit 30.

[0120] While exemplary embodiments have been described with reference to the figures, variations can be implemented in further embodiments. For example, the interface between the first integrated circuit and the second integrated circuit can be designed as a bidirectional interface.

[0121] An automatic baud rate detection function can be provided not only in one of the two integrated circuits, but also in both integrated circuits.

[0122] The transmission of synchronization data can be triggered not only by a delay and / or interruption of data transmission from the first integrated circuit to the second integrated circuit, but also by a corresponding command transmitted from the first integrated circuit to the second integrated circuit.

[0123] The first integrated circuit and / or the second integrated circuit can be programmable. The first integrated circuit and / or the second integrated circuit can be designed as a processor, microprocessor, controller, or microcontroller programmed to perform the corresponding functions.

[0124] Detecting the baud rate of the second integrated circuit can, for example, involve determining the time interval between bit signal edges. This time interval can be determined in units of a clock cycle of the first integrated circuit or another suitable unit. Detecting the baud rate can also involve determining the inverse of the time interval between bit signal edges. Detecting the baud rate of the second integrated circuit can involve determining the shift of the signal edge time interval relative to a reference value. This shift can be determined in units of a clock cycle of the first integrated circuit.

[0125] Data transmission between the first integrated circuit and the second integrated circuit can be UART data transmission.

[0126] Methods and devices according to the exemplary embodiments can be used in control devices for light sources, for example in an LED converter or an electronic ballast.

Claims

[1] Operating circuit for a light source (3), comprising: a first integrated circuit (14; 20), a second integrated circuit (15; 30) and at least one galvanically isolated transmission channel (16; 31, 32) between the first integrated circuit (14; 20) and the second integrated circuit (15; 30), wherein the first integrated circuit (14; 20) is set up to determine a baud rate of the second integrated circuit (15; 30) by means of baud rate detection, wherein the second integrated circuit (15; 30) is configured for the transmission of synchronization data (74, 75) via the at least one galvanically isolated transmission channel (16; 31, 32), wherein the first integrated circuit (14; 20) is set up to detect the baud rate of the second integrated circuit (15; 30) depending on the signal edges of the synchronization data (74, 75). [2] Operating circuit according to claim 1, wherein the second integrated circuit (15; 30) is configured to monitor a state of the at least one galvanically isolated transmission channel (16; 31) in order to automatically start the transmission of the synchronization data (74, 75). [3] Operating circuit according to claim 1 or claim 2, wherein the second integrated circuit (15; 30) is configured to initiate the transmission of the synchronization data (74, 75) when the at least one galvanically isolated transmission channel (16; 31) is in a quiescent state. [4] Operating circuit according to one of claims 1 to 3, wherein the first integrated circuit (14; 20) is configured to refrain from transmitting any data over the at least one galvanically isolated transmission channel (16; 31) for a predetermined period of time in order to trigger the transmission of the synchronization data (74, 75). [5] Operating circuit according to one of claims 1 to 4, wherein the first integrated circuit (14; 20) is configured to delay or interrupt data transmission to the second integrated circuit (15; 30) at least until the first integrated circuit (14; 20) receives the synchronization data (74, 75). [6] Operating circuit according to one of claims 1 to 5, wherein the first integrated circuit (14; 20) is configured to determine several intervals (91-94) between signal edges of bits of the synchronization data (74, 75) and to perform a consistency check of the determined several intervals (91-94). [7] Operating circuit according to one of the preceding claims, wherein the first integrated circuit (14; 20) is configured to perform baud rate detection depending on frame errors of data transmitted from the second integrated circuit (15; 30) to the first integrated circuit (14; 20). [8] Operating circuit according to claim 7, wherein the first integrated circuit (14; 20) includes a counter (25) and is configured to perform baud rate detection depending on a value of the counter (25), wherein the first integrated circuit (14; 20) is configured to increment the value of the counter (25) when a data frame (95) has a frame error, and to decrement the value of the counter (25) when a data frame (95) does not have a frame error. [9] Operating circuit according to one of the preceding claims, wherein the first integrated circuit (14; 20) is configured to match a baud rate of the first integrated circuit (14; 20) to the determined baud rate of the second integrated circuit (15; 30). [10] Operating circuit according to one of the preceding claims, wherein the operating circuit has a primary side (17) with the first integrated circuit (14; 20) and a secondary side (18) galvanically isolated therefrom with the second integrated circuit (15; 30). [11] Operating circuit according to one of the preceding claims, which is designed as an LED converter or as an electronic ballast. [12] Lighting system comprising the operating circuit (2) according to one of the preceding claims and at least one light source (3) connected to the operating circuit (2). [13] Method for data transmission between a first integrated circuit (14; 20) and a second integrated circuit (15; 30) of an operating circuit (2) for a light source (3), the method comprising: Determining a baud rate of the second integrated circuit (15; 30) by the first integrated circuit (14; 20), and Data transmission (76, 77) between the first integrated circuit (14; 20) and the second integrated circuit (15; 30) via at least one galvanically isolated transmission channel (16; 31, 32), wherein the first integrated circuit (14; 20) is controlled depending on the determined baud rate of the second integrated circuit (15; 30), wherein the second integrated circuit (15; 30) is configured for the transmission of synchronization data (74, 75) via the at least one galvanically isolated transmission channel (16; 31, 32), wherein the first integrated circuit (14; 20) is set up to detect the baud rate of the second integrated circuit (15; 30) depending on the signal edges of the synchronization data (74, 75).

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