Silicon carbide semiconductor device and method for manufacturing the same

Abstract

Silicon carbide semiconductor device comprising the following: - a drift layer (2a) of a first conductivity type, which is formed in an active region (30) and a termination region (40) which is an ambient region of the active region (30); - a base region (3) of a second conductivity type, which is formed in an upper region of the drift layer (2a) in the active region (30); - a source region (4) of the first conductivity type, which is formed in an upper region in the base region (3); - an active trench (5a) that penetrates the source area (4) and the base area (3) and is formed in the active area (30); - a termination trench (5b) designed to surround the active trench (5a) in the drift layer (2a) of the termination area (40); - a gate insulation layer (6) formed on a bottom surface and a side surface of the active trench (5a); - a gate electrode (7) formed in the active trench (5a) with the gate insulating layer (6) inserted between it; - a protective diffusion layer (13) of the second conductivity type, which is formed in a lower area of ​​the active trench (5a) and in a lower area of ​​the containment trench (5b) and has a fault concentration of the second conductivity type, which is a first fault concentration; and - a termination diffusion layer (16) of the second conductivity type, which is formed on an outer peripheral side of the protective diffusion layer (13) in a lower area of ​​the termination trench (5b) and has a fault concentration of the second conductivity type, which is a second fault concentration that is lower than the first fault concentration, wherein the silicon carbide semiconductor device further comprises a source electrode (9) which is connected to the source region (4), wherein the protective diffusion layer (13) is connected to the source electrode (9).

Description

Technical area

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. More particularly, it relates to a trench-gate type silicon carbide semiconductor device and a method for manufacturing the same. State of the art

[0002] In power electronics equipment, a switching element called an insulated-gate semiconductor device, such as an IGBT (insulated-gate bipolar transistor) and a MOSFET (metal-oxide semiconductor field-effect transistor), is widely used to control the supply of power to a load such as an electric motor. Some insulated-gate semiconductor devices include a trench-gate semiconductor device with a gate electrode embedded in a semiconductor layer.

[0003] On the other hand, attention is being paid to semiconductor devices using silicon carbide (SiC) (hereinafter, such a device is referred to as a "silicon carbide semiconductor device") as a next-generation semiconductor device. This device is capable of achieving high withstand voltage and low losses, and the development of a trench-gate type silicon carbide semiconductor device has also been advanced.

[0004] For a trench-gate semiconductor device using silicon (Si), the avalanche electric field strength of a semiconductor layer is lower than the electric field strength of a gate insulating layer during dielectric breakdown. Therefore, the withstand voltage of the semiconductor device is determined by the avalanche electric field strength of the semiconductor layer. On the other hand, the avalanche electric field strength of SiC is approximately 10 times that of Si.

[0005] Therefore, in the case of a silicon carbide semiconductor device, the avalanche electric field strength of the semiconductor layer (SiC) is equivalent to the electric field strength of the gate insulating layer during dielectric breakdown. In the trench-gate type semiconductor device, when a voltage is applied to the semiconductor device, an electric field concentration occurs in a corner region of a bottom portion of a trench.

[0006] Therefore, dielectric breakdown occurs earlier across a gate insulating layer in a corner region of a trench in the silicon carbide semiconductor device. For this reason, in a trench-gate type silicon carbide semiconductor device, the withstand voltage is limited by the electric field strength of the gate insulating layer.

[0007] Therefore, it has been proposed that a protective diffusion layer with p-type impurities implanted at a high concentration be provided on a drift layer in a lower region of a trench in the case of an n-type channel in a conventional trench-gate type silicon carbide semiconductor device (e.g., in JP 2001-267570 A). In a conventional trench-gate type semiconductor device, it is also known that a plurality of trenches are provided and a protective diffusion layer is provided in a lower region of each of the trenches, as described in JP 2007-242852 A. Therefore, by providing the protective diffusion layer in the lower region of the trench, it is possible to mitigate the electric field concentration in a corner region of the trench and improve the withstand voltage.

[0008] US 2005 / 0 029 557 A1 discloses a high breakdown voltage semiconductor device comprising: a high-resistance semiconductor layer; trenches formed on the surface thereof in the shape of a longitudinal plane and parallel to each other; first regions formed on the semiconductor layer to be sandwiched between adjacent trenches and having a higher impurity concentration than the semiconductor layer; a second region having a conductivity opposite to the first regions and continuously disposed in a trench sidewall and a bottom region; a sidewall insulating layer disposed on the second region of the trench sidewall; a third region disposed on the second region of the trench bottom region and having the same conductivity as the second region and a higher impurity concentration than the second region;a fourth region disposed on the back surface of the semiconductor layer; a first electrode formed on each first region; a second electrode connected to the third region; and a third electrode formed on the fourth region.

[0009] US 2013 / 0 099 251 A1 shows a SiC semiconductor device with an element region provided with a semiconductor element and a termination region surrounding the element region in plan view.The SiC semiconductor device further comprises: a SiC substrate made of SiC having a hexagonal single crystal structure and having a first side and a second side opposite to each other in a thickness direction, the first side of the SiC substrate being provided with a sidewall and a bottom surface in the termination region, the sidewall surrounding the element region and having a plane orientation of {0-33-8} or {0-11-4}, and the bottom surface surrounding the sidewall and having a plane orientation of {000-1}; an insulating film disposed on the sidewall and the bottom surface; a first electrode disposed on the first side of the SiC substrate in the element region; and a second electrode disposed on the second side of the SiC substrate.

[0010] US 2011 / 0 115 033 A1 discloses a semiconductor device with a power MOSFET having a super junction structure formed in a cell region using a trench-filling technique. A drift region surrounding the cell region has a super junction structure aligned parallel to each side of the cell region. Summary of the inventionProblems to be solved by the invention

[0011] As described above, if the protective diffusion layer is provided in the bottom region of the trench, it is necessary to gradually increase the impurity concentration of the protective diffusion layer to sufficiently mitigate the electric field concentration in the corner region of the trench. However, if the impurity concentration of the protective diffusion layer is gradually increased, the electric field occurring at a PN junction region of the protective diffusion layer and the drift layer will also increase.

[0012] As a result, the protective diffusion layer is destroyed due to an avalanche breakdown that occurs earlier than the breakdown of the gate insulating layer in the corner region of the trench. Therefore, it is feared that the withstand voltage of the semiconductor device is limited by a voltage (hereinafter referred to as the "avalanche breakdown voltage") at which the avalanche breakdown occurs in the protective diffusion layer.

[0013] In addition, when a plurality of trenches are provided and the protective diffusion layer is provided in the lower part of each of the trenches, an electric field generated at the protective diffusion layer is attenuated by adjacent protective diffusion layers. However, the outermost peripheral protective diffusion layer among the plurality of protective diffusion layers has the protective diffusion layer on only one side. Therefore, the electric field is increased the most in the outermost peripheral protective diffusion layer.

[0014] As a result, the avalanche breakdown occurs earlier in the outermost peripheral protective diffusion layer. Therefore, there is a concern that the withstand voltage may be limited by the avalanche breakdown voltage at the outermost peripheral protective diffusion layer. As mentioned above, there is a concern that the withstand voltage may be limited by the avalanche breakdown voltage of the protective diffusion layer in the conventional trench-gate silicon carbide semiconductor device.

[0015] The present invention was conceived to solve the problems described above. Its object is to provide a silicon carbide semiconductor device capable of mitigating the electric field in a protective diffusion layer formed in a bottom region of a trench, thereby improving the withstand voltage. Ways to solve the problems

[0016] The object is achieved by a silicon carbide semiconductor device having the features of claim 1. Advantageous further developments emerge from subclaims 2 to 8. Furthermore, the object is achieved by a method for producing a silicon carbide semiconductor device having the features of claim 9. Effects of the invention

[0017] In the silicon carbide semiconductor device according to the present invention, the termination trench is formed in the termination region surrounding the active region, and the termination diffusion layer is formed in the lower portion of the termination trench. Therefore, the termination diffusion layer is present around the protective diffusion layer formed in the lower portion of the trench in the active region.

[0018] As a result, it is possible to attenuate the electric field in the protective diffusion layer by extending a depletion layer from the terminal diffusion layer. Furthermore, the second impurity concentration, which is the second conductivity type impurity concentration in the terminal diffusion layer, is lower than the first impurity concentration, which is the second conductivity type impurity concentration in the protective diffusion layer.

[0019] Therefore, the electric field generated in the terminal diffusion layer itself is reduced more than the electric field in the protective diffusion layer, and avalanche breakdown in the terminal diffusion layer is also prevented. Consequently, it is possible to weaken the electric field in the protective diffusion layer and also prevent avalanche breakdown in the terminal diffusion layer. Therefore, it is possible to improve the withstand voltage of the silicon carbide semiconductor device. Short description of the drawings

[0020] The drawings show: Fig. 1 is a plan view showing a silicon carbide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a sectional view showing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 3 is a sectional view showing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 4 is a sectional view showing manufacturing steps of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 5 is a sectional view showing manufacturing steps of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 6 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 7 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 8 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 9 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 10 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 11 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 12 is a sectional view showing manufacturing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 13 is a sectional view showing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 14 is a sectional view showing the silicon carbide semiconductor device according to the first embodiment of the present invention. Fig. 15 is a sectional view showing the silicon carbide semiconductor device according to a second embodiment of the present invention. Fig. 16 is a sectional view showing the silicon carbide semiconductor device according to a third embodiment of the present invention. Description of the embodimentsFirst embodiment

[0021] First, the structure of a silicon carbide semiconductor device 100 according to a first embodiment will be described with reference to FIG. Fig. 1 to 3 shown. Fig. 1 is a plan view showing the silicon carbide semiconductor device 100 according to the first embodiment. In Fig. 1 are not shown: a gate insulating layer 5, a gate electrode 7, an interlayer insulating layer 8, and a source electrode 9 to be formed on a semiconductor layer 2 and in a trench. Therefore, Fig. 1 the semiconductor layer 2 with a trench 5a and a termination trench 5b formed thereon.

[0022] Note that in the following description, an "active region" is assumed to indicate a region where a current flows through the formation of a channel in an on-state of a semiconductor device, and a "termination region" is assumed to indicate a region located around the termination region. Furthermore, an "impurity concentration" is assumed to indicate the peak value of an impurity concentration in each region.

[0023] Further, in the following description, an “outer peripheral side” indicates the direction from the inside of the silicon carbide semiconductor device 100 toward the outside of the silicon carbide semiconductor device 100 in a plan view of the silicon carbide semiconductor device 100 (in a planar direction), as shown in Fig. 1, and an "inner peripheral side" indicates the direction opposite to the "outer peripheral side." Accordingly, the right-to-left direction indicates the outer peripheral side, and the left-to-right direction indicates the inner peripheral side, as shown in Fig. 3 shown.

[0024] The silicon carbide semiconductor device 100 according to the first embodiment is a trench-gate type MOSFET. Fig. 1, the semiconductor layer 2 of the silicon carbide semiconductor device 100 has the trench 5a formed in an active region 30, and the termination trench 5b formed around the trench 5a in a termination region 40. As shown in Fig. 1, the trench 5a is also provided like a grid in the planar direction.

[0025] A plurality of blocks (cells) separated by the trench 5a each function as MOSFETs. Although the cell is configured to be provided in a divided grid shape in the present embodiment, the cell array may also assume another configuration in which the cell is arranged in the shape of a comb or in a zigzag pattern. Fig. 1, the width 41 of the termination trench 5b is also larger than each width 31 of the active trench 5a, which is provided like a grid. The details of the silicon carbide semiconductor device 100 will be described below.

[0026] With reference to Fig. 2, the structure of the silicon carbide semiconductor device 100 in the active region 30 is described. Fig. 2 is a sectional view along AA in Fig. 1, and it is a sectional view in the active region 30 of the silicon carbide semiconductor device 100 according to the first embodiment.

[0027] In Fig. 2, the silicon carbide semiconductor device 100 includes, in the active region 30, an n-type silicon carbide substrate 1, the semiconductor layer 2 formed on an upper surface of the silicon carbide substrate 1, the interlayer insulating layer 8 and the source electrode 9 formed on the semiconductor layer 2, and a drain electrode 10 formed on a back surface side of the silicon carbide substrate 1.

[0028] The semiconductor layer 2 is formed of an n-type epitaxial layer grown epitaxially on the silicon carbide substrate 1; a p-type base region 3 is formed at the upper portion of the semiconductor layer 2, and an n-type source region 4 is formed at an upper portion of the base region 3. Furthermore, an n-type region of the semiconductor layer 2, on which no base region 3 is formed, serves as a drift layer 2a. Note that the semiconductor layer 2 is a general term that collectively refers to the drift layer 2a, the base region 3, and the source region 4.

[0029] The following is assumed: The n-type impurity concentration in the drift layer 2a is 1.0E15 cm -3 up to 1.0E17 cm -3 ; the p-type impurity concentration in the base region 3 is 1.0E17 cm -3 up to 1.0E18 cm -3; and the n-type impurity concentration in source region 4 is 1.0E18 cm -3 up to 1.0E21 cm -3 .

[0030] In Fig. 2, the trench 5a, which reaches the drift layer 2a by penetrating the source region 4 and the base region 3, is formed on the semiconductor layer 2 in the active region 30. A gate insulating layer 6 is provided on a side surface and a bottom surface of the trench 5a. Further, the gate electrode 7 is embedded in the trench 5a with the gate insulating layer 6 interposed therebetween. Further, a p-type protective diffusion layer 13 having a p-type impurity concentration, which is a first impurity concentration, is formed on the drift layer 2a in a lower region of the trench 5a. Note that the first impurity concentration will be described later.

[0031] In Fig. 2, the interlayer insulating layer 8 is formed on an upper surface of the semiconductor layer 2 to cover the gate electrode 7. A contact hole reaching the source region 4 and the base region 3 on an upper surface of the semiconductor layer 2 is formed in the interlayer insulating layer 8. The source electrode 9 is formed on the interlayer insulating layer 8, and the source electrode 9 is connected to the source region 4 and the base region 3 via the contact hole of the interlayer insulating layer 8.

[0032] With reference to Fig. 3, the structure of the silicon carbide semiconductor device 100 in a boundary region between the active region 30 and the termination region 40 and in the termination region 40 will be described next. Fig. 3 is a sectional view along BB in Fig. 1, and it is a sectional view in the boundary portion between the active region 30 and the termination region 40 and in the termination region 40 in the silicon carbide semiconductor device 100 according to the first embodiment.

[0033] As in Fig. 3, also in the termination region 40, the semiconductor layer 2 (the drift layer 2a) is formed on the upper surface side of the silicon carbide substrate 1, and the drain electrode 10 is formed on the rear surface side of the silicon carbide substrate 1. In Fig. 3, the base region 3 is formed on the upper region in the semiconductor layer 2 of the active region 30, the source region 4 is formed on the upper region in the base region 3, and the source region 4 according to Fig. 3 serves as the outermost peripheral source region 4 in the active region 30.

[0034] The termination trench 5b is formed on the semiconductor layer 2 (the drift layer 2a) on the outer peripheral side of the outermost peripheral source region 4. Although the termination trench 5b is formed in the termination region 40, it is not formed at one end in the planar direction of the semiconductor layer 2. In addition, the termination trench 5b is formed to surround the active region 30 of the silicon carbide semiconductor device 100, as shown in Fig. 1. It should be noted that in Fig. 3 the outer peripheral side of the region in which the termination trench 5b is formed serves as the termination region 40, and the inner peripheral side of the region in which the termination trench 5b is formed serves as the active region 30.

[0035] In Fig. 3, a protective diffusion layer 13 is formed on the inner peripheral side, and a termination diffusion layer 16 is formed on the outer peripheral side in the lower region of the termination trench 5b. The protective diffusion layer 13 formed in the lower region of the termination trench 5b is bonded to the protective diffusion layer 13 formed on the lower region of the trench 5a in the active region 30. Furthermore, the protective diffusion layer 13 formed on the lower region of the termination trench 5b is extended to the end of the inner peripheral side in the lower region of the termination trench 5b.

[0036] The terminal diffusion layer 16, in turn, is a p-type semiconductor layer having a p-type impurity concentration, which is a second impurity concentration. The second impurity concentration will be described below. Furthermore, the terminal diffusion layer 16 is extended toward the end in the planar direction of the semiconductor layer 2, on the outer peripheral side of the protective diffusion layer 13, and is formed by dividing it into a plurality of small regions on the outer peripheral side of the semiconductor layer 2.

[0037] In Fig. 3, the gate insulating layer 6 is also formed on the side surface and bottom surface of the termination trench 5b, and the gate electrode 7 is formed on a portion on the active region 30 side of the gate insulating layer 6 in the termination trench 5b. The gate electrode 7 is formed such that it extends to the source region 4 at the outermost periphery of the active region 30 from the inner part of the termination trench 5b on the protective diffusion layer 13. Fig. 3, the interlayer insulating layer 8 is further extended from the end in the planar direction of the semiconductor layer 2 toward the active region 30 on the gate insulating layer 6 and the gate electrode 7.

[0038] Furthermore, a contact hole is formed in the interlayer insulating film 8 on the gate electrode 7, and a gate terminal 17 is connected to the gate electrode 7 via the contact hole of the interlayer insulating film 8. The position at which the gate terminal 17 is connected to the gate electrode 7 is selected on the protective diffusion layer 13 formed in the lower region of the termination trench 5b.

[0039] It is preferable that the first impurity concentration serving as the p-type impurity concentration of the protective diffusion layer 13 is set to an impurity concentration at which the protective diffusion layer 13 is not completely depleted, when the rated voltage of the silicon carbide semiconductor device 100 is applied between the drain electrode 10 and the source electrode 9. More specifically, it is preferable that the first impurity concentration is equal to or higher than 5.0E17 cm -3 and equal to or less than 5.0E18 cm -3 should be.

[0040] On the other hand, the second impurity concentration, which is the p-type impurity concentration of the termination diffusion layer 16, is set to an impurity concentration lower than the first impurity concentration, which is the p-type impurity concentration of the protection diffusion layer 13. More specifically, it is preferable that the second impurity concentration is equal to or higher than 1.0E17 cm -3 and equal to or less than 1.0E18 cm -3 should be.

[0041] The operation of the silicon carbide semiconductor device 100 according to the present embodiment will be described below. When a voltage equal to or greater than a threshold voltage is applied to the gate electrode 7 of the silicon carbide semiconductor device 100, a channel is formed in a portion of the base region 3 opposite the gate electrode 7 in the active region 30.

[0042] As a result, a path is formed along which electrons flow as charge carriers between the n-type source region 4 and the n-type drift layer 2a. The electrons flowing from the source region 4 into the drift layer 2a reach the drain electrode 10 via the drift layer 2a and the silicon carbide substrate 1 according to an electric field generated by a voltage (a drain voltage) applied between the drain electrode 10 and the source electrode 9.

[0043] As a result, a voltage equal to or higher than the threshold voltage is applied to the gate electrode 7, so that a current flows from the drain electrode 10 to the source electrode 9, and this causes an on-state of the silicon carbide semiconductor device 100.

[0044] In turn, in a state where a voltage equal to or lower than the threshold voltage is applied to the gate electrode 7, the channel is not formed in the base region 3, so the p-type base region 3 is present between the n-type source region 4 and the n-type drift layer 2a. For this reason, the path along which electrons flow as carriers is not formed, and a current from the drain electrode 10 toward the source electrode 9 does not flow. As a result, the silicon carbide semiconductor device 100 is brought into an off state.

[0045] With reference to the Fig. 4 to 12, a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described below. Fig. 4 to 12 are views each showing manufacturing steps in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. In each of the figures, part (A) is a sectional view corresponding to a section along AA in Fig. 1, and part (B) is a sectional view corresponding to a section along BB in Fig. 1. It should be noted that part (B) in each of the Fig. 4 to 12 illustrates an area that is Fig. 3 is surrounded by a dashed line. The following description also assumes that the steps in both parts (A) and (B) are described in each figure, unless otherwise stated.

[0046] First, Fig. 4, the n-type silicon carbide substrate 1 is prepared, which has a first main surface (a top surface) and a second main surface (a back surface) that are opposite to each other and have a 4H polytype. Then, in the active region 30 and the termination region 40, the n-type semiconductor layer 2 is epitaxially grown on the top surface of the silicon carbide substrate 1 by a chemical vapor deposition (CVD) method. Furthermore, the thickness of the semiconductor layer 2 is set to be 5 to 50 μm, and the n-type impurity concentration of the semiconductor layer 2 is set to be 1.0E15 cm -1 -3 up to 1.0E17 cm -3 is.

[0047] As in Fig. Then, as shown in Fig. 4(A), in the active region 30, Al ions are implanted as p-type impurities into the upper surface of the semiconductor layer 2 through an implantation mask (not shown) to form the base region 3 on the upper surface of the semiconductor layer 2. The implantation depth of the Al ions is set to be smaller than the thickness of the semiconductor layer 2, for example, approximately 0.5 to 3.0 μm.

[0048] In addition, the ion implantation ensures that the p-type impurity concentration of the base region 3 reaches a value of 1.0E17 cm -3 up to 1.0E18 cm -3which is higher than the n-type impurity concentration of the semiconductor layer 2. Accordingly, a region of the semiconductor layer 2 into which the Al ions are implanted serves as the p-type base region 3, and a region of the semiconductor layer 2 into which the Al ions are not implanted serves as the n-type drift layer 2a. The base region 3 can be formed by epitaxial growth.

[0049] Even in such a case, the impurity concentration and thickness are equivalent to those in the case where the formation is performed by ion implantation. Furthermore, the p-type impurities to be implanted into the base region 3 can be various p-type impurities, such as B and other than Al, and the case of implanting the p-type impurities is also the same in the following description.

[0050] Next, N ions are implanted as n-type impurities into the upper surface of the semiconductor layer 2 through an implantation mask (not shown) to form the source region 4 on a part of the upper region in the base region 3. It is assumed that the implantation depth of the N ions is smaller than the thickness of the base region 3. Furthermore, the n-type impurity concentration in the source region 4 ranges from 1.0E18 cm -3 up to 1.0E21 cm -3 , and it is equal to or higher than the p-type impurity concentration in the base region 3. In addition, the n-type impurities to be implanted into the source region 4 may be various n-type impurities other than N.

[0051] In Fig. 5, a silicon oxide layer 11 having a thickness of approximately 1.0 to 2.0 µm is then deposited on the upper surface of the semiconductor layer 2. Then, an etching mask 12 made of a resist material is formed on the upper surface of the silicon oxide layer 11. An opening is formed in the etching mask 12 at positions where the trench 5a and the termination trench 5b, which will be described below, will be formed.

[0052] In Fig. 6, the silicon oxide layer 11 is then etched by reactive ion etching (RIE) treatment in a state where the etching mask 12 is formed on the upper surface. As a result, an opening is formed on the silicon oxide layer 11, and the silicon oxide layer 11 with the opening formed thereon serves as an etching mask in the next step.

[0053] In Fig. 7, the RIE process is subsequently performed by using the silicon oxide layer 11 as an etching mask to etch the semiconductor layer 2. Consequently, the trench 5a and the termination trench 5b are formed. Accordingly, the trench 5a, which penetrates the base region 3 from the source region 4, is formed in the active region 30, as shown in Fig. 7(A), and the termination trench 5b is formed on the drift layer 2a in the termination region 40 as shown in Fig. 7(B).

[0054] In addition, the closure trench 5b is formed around the trench 5a so that it surrounds the trench 5a, as shown in Fig. 1. The depths of the trench 5a and the termination trench 5b are set to be approximately 0.5 to 3.0 µm, and the depth of the trench 5a is set to be equal to or greater than the depth of the base region 3.

[0055] In Fig. 8, after removing the silicon oxide layer 11, an implantation mask 14 is formed on the semiconductor layer 2, and Al ions are implanted as p-type impurities. The implantation mask 14 is formed to cover an area defined by the trench 5a in Fig. 8(A) and so as to cover an area separated from a part of the termination trench 5b on the side of the active region 30 in Fig. 8(B) is different.

[0056] As a result, a protective diffusion layer 13 is formed on the drift layer 2a in the lower portion of the trench 5a and on the inner peripheral side of the lower portion of the termination trench 5b, which corresponds to the opening of the implantation mask 14. An ion implantation value for implanting into the protective diffusion layer 13 will be described below.

[0057] To form the protective diffusion layer 13 in the lower portion of the trench 5a, a residual layer of the silicon oxide layer 11 used for etching the trench 5a can be utilized, and the implantation mask 14 can be used only in the formation of the protective diffusion layer 13 in the lower portion of the termination trench 5b. In such a case, when the etching conditions or the thickness of the silicon oxide layer 11 are controlled, it is necessary to perform ion implantation in such a way that the silicon oxide layer 11 remains even after ion implantation. Consequently, alignment accuracy of the implantation mask 14 with the trench 5a of the active region 30 is not required, so the protective diffusion layer 13 can be formed with higher accuracy.

[0058] After removing the implantation mask 14, the procedure is as follows Fig. 9, an implantation mask 15 is again formed on the semiconductor layer 2, and Al ions are implanted as p-type impurities. The implantation mask 15 is designed to cover the entire upper surface of the semiconductor layer 2 in Fig. 9(A), and is formed so that an opening on the outer peripheral side of the protective diffusion layer 13 in the lower portion of the termination trench 5b in Fig. 9(B). In Fig. 9(B), a plurality of openings are also formed on the implantation mask 15, and the opening on the active region 30 side has a larger opening width than the other openings.

[0059] Then, ion implantation is performed using the implantation mask 15, so that a termination diffusion layer 16 is formed on the drift layer 2a in the lower region of the termination trench 5b corresponding to the opening of the implantation mask 15. A value of ion implantation for implantation into the termination diffusion layer 16 will be described below.

[0060] Although the terminal diffusion layer 16 is formed after the protective diffusion layer 13 is formed in the present embodiment, the protective diffusion layer 13 may also be formed after the terminal diffusion layer 16 is formed.

[0061] It is preferable that the implantation be performed with such an ion implantation value for implantation into the protective diffusion layer 13 that a first impurity concentration, which is a p-type impurity concentration of the protective diffusion layer 13, is set to be an impurity concentration that does not cause complete depletion of the protective diffusion layer 13 when the rated voltage of the silicon carbide semiconductor device 100 is applied between the drain electrode 10 and the source electrode 9. More specifically, it is preferable to perform the implantation in such a manner that the implantation concentration is equal to or higher than 5.0E17 cm -3 and that it is equal to or less than 5.0E18 cm -3 .

[0062] On the other hand, the implantation is performed with such an ion implantation value for implantation into the termination diffusion layer 16 that a second impurity concentration, which is the p-type impurity concentration of the termination diffusion layer 16, is an impurity concentration which is lower than the p-type impurity concentration of the protection diffusion layer 13.

[0063] More specifically, it is preferable to perform the implantation in such a way that the implantation concentration is equal to or higher than 1.0E17 cm -3 and is equal to or less than 1.0E18 cm -3 , and it is set to be an impurity concentration which is lower than the first impurity concentration.

[0064] After removing the implantation mask 15, an annealing heat treatment is then performed using a heat treatment device. The annealing heat treatment is carried out at 1300°C to 1900°C for 30 seconds to one hour in an inert gas atmosphere of argon (Ar) gas or the like. As a result, the impurities of N and Al implanted as ions are activated.

[0065] According to Fig. Next, the gate insulating layer 6, made of silicon oxide, is formed on the upper surface of the semiconductor layer 2, including the source region 4 and the base region 3, and the bottom surfaces and side surfaces (inner walls) of the trench 5a and the termination trench 5b. The gate insulating layer 6 can be formed by thermally oxidizing the semiconductor layer 2 or by depositing a silicon oxide layer on the upper region of the semiconductor layer 2.

[0066] Then, the gate electrode 7 is formed in the trench 5a and the termination trench 5b. It is possible to form the gate electrode 7 by forming a polycrystalline silicon layer with conductivity using a low-pressure CVD method and by patterning the polycrystalline silicon layer.

[0067] Here, the gate electrode 7 is embedded in the trench 5a with the gate insulating layer 6 interposed therebetween, and thus is formed as shown in Fig. 10(A). The gate electrode 7 is formed on the gate insulating layer 6 on the active region 30 side of the upper portion of the protective diffusion layer 13 in the termination trench 5b, as shown in Fig. 10(B).

[0068] According to Fig. 11, the interlayer insulating layer 8 is then formed on the upper surface of the semiconductor layer 2 by means of a low-pressure CVD method so as to cover the gate electrode 7. Then, the contact hole is formed in the interlayer insulating layer 8 and the gate insulating layer 7 in Fig. 11(A), and the contact hole is formed in the interlayer insulating film 8 formed on the gate electrode 7 in Fig. 11(B).

[0069] According to Fig. 12(A), the source electrode 9 to be electrically connected to the source region 4 is then formed in the contact hole formed on the interlayer insulating film 8, as well as on the interlayer insulating film 8. According to Fig. 12(B), a gate terminal 17 to be electrically connected to the gate electrode 7 is further formed in the contact hole formed in the interlayer insulating film 8 and on the interlayer insulating film 8.

[0070] Finally, the drain electrode 10 is formed on the back surface of the silicon carbide substrate 1. Here, the materials constituting the source electrode 9, the gate terminal 17, and the drain electrode 10 can be appropriately selected from electrode materials such as Al, Cu, and Ni. Through the above steps, the silicon carbide semiconductor device 100 is completed.

[0071] The silicon carbide semiconductor device 100 according to the present embodiment has the structure described above, so that the following advantages can be achieved.

[0072] First, the problems of a trench-gate type silicon carbide semiconductor device having a protective diffusion layer provided in the bottom of a trench will be described. In the off-state of the silicon carbide semiconductor device, the drain voltage is a high voltage of 100 to 10,000 V, and it is held in a depletion layer extending from the protective diffusion layer provided in the bottom of the trench to a drift layer. In this case, the electric field is concentrated in the lower portion of the protective diffusion layer, particularly in a corner portion of the lower portion of the protective diffusion layer.

[0073] If the electric field in the corner region exceeds the drift layer's electric field required for avalanche breakdown, there is a risk that an avalanche breakdown may occur in the protective diffusion layer, which may cause dielectric breakdown. Furthermore, there is a risk that the gate insulation layer may cause dielectric breakdown, since the electric field concentration also occurs across the gate insulation layer in the corner region of the trench.

[0074] However, if the gate insulating layer is sufficiently protected by the protective diffusion layer, dielectric breakdown of the protective diffusion layer occurs earlier. Therefore, there is a risk that the withstand voltage of the semiconductor devices may be limited by a voltage that causes avalanche breakdown (hereinafter referred to as an "avalanche breakdown voltage") in the protective diffusion layer.

[0075] In the case where a plurality of trenches are provided in the trench-gate type semiconductor device, a protective diffusion layer is further provided in a lower region of each of the trenches. Accordingly, an electric field generated in a corner region of the protective diffusion layer is attenuated by the extension of a depletion layer from the adjacent protective diffusion layers.

[0076] However, the outermost peripheral protective diffusion layer among the protective diffusion layers has the protective diffusion layer only on one side. For this reason, the electric field is highest at the outermost peripheral protective diffusion layer. As a result, there is a risk that avalanche breakdown may occur earlier in the outermost peripheral protective diffusion layer, and the withstand voltage may consequently be limited by the avalanche breakdown voltage in the outermost peripheral protective diffusion layer.

[0077] In the present embodiment, the termination trench 5b is formed in the termination region 40, which is the surrounding area of ​​the active region 30, and the termination diffusion layer 16 is formed in the lower region of the termination trench 5b. Therefore, the termination diffusion layer 16 is present around the protective diffusion layer 13 formed in the lower region of the trench 5a in the active region 30. For this reason, the termination diffusion layer 16 is also present on the outer peripheral side of the protective diffusion layer 13 formed in the outermost periphery.

[0078] Therefore, the electric potential distribution in the outermost peripheral protective diffusion layer 13, particularly in the corner region of the outermost peripheral protective diffusion layer 13, is smoothed by the propagation of the depletion layer from the terminal diffusion layer 16. As a result, it is possible to attenuate the electric field applied to the corner region of the outermost peripheral protective diffusion layer 13.

[0079] In addition, if the second impurity concentration, which is the impurity concentration of the terminal diffusion layer 16, is equal to or higher than the first impurity concentration, which is the impurity concentration of the protective diffusion layer 13, then there is a risk that the electric field in the terminal diffusion layer 16 may be higher than the electric field in the protective diffusion layer 13, and the withstand voltage may consequently be limited by the avalanche breakdown voltage in the terminal diffusion layer 16.

[0080] In the present embodiment, the second impurity concentration is lower than the first impurity concentration. Therefore, the electric field generated in the terminal diffusion layer 16 itself can also be reduced compared to the electric field generated in the protective diffusion layer 13. Consequently, it is possible to suppress the limitation of the withstand voltage of the semiconductor device by the avalanche breakdown voltage in the outermost peripheral protective diffusion layer 13 or the terminal diffusion layer 16. Consequently, the withstand voltage of the silicon carbide semiconductor device 100 can be improved.

[0081] In the present embodiment, the protective diffusion layer 13 is also provided in the lower region of the trench 5a. Therefore, it is possible to weaken the electric field to be applied to the gate insulating layer 6 in the trench 5a. Even if the protective diffusion layer 13 is provided in the lower region of the trench 5a, the electric field is again applied to the gate insulating layer 6 in the trench 5a when the protective diffusion layer 13 is completely depleted. Consequently, there is a risk that breakdown may occur in the corner region of the gate insulating layer 6.

[0082] Therefore, the impurity concentration of the protective diffusion layer 13 is set to be the impurity concentration at which the protective diffusion layer 13 is not completely depleted when the rated voltage of the silicon carbide semiconductor device 100 is applied between the drain electrode 10 and the source electrode 9. As a result, the protective diffusion layer 13 is prevented from being completely depleted in the off-state of the silicon carbide semiconductor device 100.

[0083] Consequently, the gate insulating layer 6 can be reliably protected. More specifically, if the impurity concentration of the protective diffusion layer 13 is set to be equal to or higher than 5.0E17 cm -3 and that it is equal to or less than 5.0E18 cm -3 then it is possible to reliably protect the gate insulating layer 6.

[0084] If the impurity concentration of the protective diffusion layer 13 is gradually increased so that it does not cause complete depletion, as described above, the electric field generated in the protective diffusion layer 13 is enhanced. For this reason, there is a risk that the avalanche breakdown may occur in the protective diffusion layer 13 earlier than the breakdown of the gate insulating layer 6. In particular, there is a risk that the avalanche breakdown may occur earlier in the outermost peripheral protective diffusion layer 13 than in the other protective diffusion layers 13, as described above.

[0085] However, in the present embodiment, the terminal diffusion layer 16 is provided. Therefore, the terminal diffusion layer 16 is also formed in the outermost peripheral protective diffusion layer 13, so that the electric field generated in the outermost peripheral protective diffusion layer 13 can also be attenuated. Consequently, it is possible to prevent the occurrence of avalanche breakdown earlier than in the other protective diffusion layers 13.

[0086] As described above, in the present embodiment, it is possible to reduce the electric field generated in the gate insulating layer 6, the protective diffusion layer 13, and the terminal diffusion layer 16. Therefore, it is possible to suppress both the dielectric breakdown of the gate insulating layer 6 and the avalanche breakdown in the protective diffusion layer 13 and the terminal diffusion layer 16. Consequently, the withstand voltage of the silicon carbide semiconductor device 100 can be improved.

[0087] Although the trench 5a is formed like a grid in the present embodiment, it may also be formed in a comb shape or a zigzag shape. Even in such a case, the termination trench 5b is formed around the trench 5a so that the electric field of the protective diffusion layer 13 can be attenuated by the termination diffusion layer 16 provided in the lower region of the termination trench 5b.

[0088] In addition, a plurality of small regions separated from each other are formed on the outer peripheral side of the termination diffusion layer 16. With this structure, the termination diffusion layer 16 also functions as a guard ring formed in the termination region 40 in a general semiconductor device. Therefore, the depletion layer extends from the termination diffusion layer 16 toward the end of the semiconductor layer 2 in the termination region 40, so that the electric field in the termination region 40 can be weakened.

[0089] In addition, the structure on the outer peripheral side of the termination diffusion layer 16 may be another termination structure, such as a JTE (Junction Termination Extension) structure, which has a gradation such that the impurity concentration is gradually reduced toward the outer peripheral side.

[0090] Furthermore, the gate insulating layer 6 is also formed in the termination trench 5b. Therefore, the electric field concentration occurs in the corner region of the gate insulating layer 6 in the termination trench 5b. However, the protective diffusion layer 13 is formed on the inner peripheral side (the active region 30 side) in the planar direction of the lower portion of the termination trench 5b. Consequently, it is possible to mitigate the electric field that will be applied to the gate insulating layer 6 in the termination trench 5b.

[0091] In the case where the electric field that will be applied to the corner region of the gate insulating layer 6 in the termination trench 5b is lower than the electric field that will be applied to the corner region of the gate insulating layer 6 in the trench 5a, or in the case where the insulating property of the gate insulating layer 6 to be formed in the termination trench 5b is sufficiently high, the protective diffusion layer 13 is not formed in the lower region of the termination trench 5b, but only the termination diffusion layer 16 may be provided over the entire area of ​​the lower region of the termination trench 5b.

[0092] In such a case, the electric field that will be applied to the outermost peripheral protective diffusion layer 13 formed in the lower region of the trench 5a is attenuated by the terminating diffusion layer 16.

[0093] On the other hand, in the case where the protective diffusion layer 13 is provided in the lower portion of the termination trench 5b, the protective diffusion layer 13 formed in the lower portion of the termination trench 5b serves as the outermost peripheral protective diffusion layer 13.

[0094] For this reason, the electric field applied to the outermost peripheral protective diffusion layer 13 among the protective diffusion layers 13 formed in the lower region of the trench 5a is attenuated by the protective diffusion layer 13 formed in the lower region of the termination trench 5b. However, there is a risk that avalanche breakdown may occur in the outermost peripheral protective diffusion layer 13 formed in the lower region of the termination trench 5b.

[0095] However, in the present embodiment, the electric field that will be applied to the outermost peripheral protective diffusion layer 13 formed in the lower region of the termination trench 5b is attenuated by the termination diffusion layer 16. Therefore, it is possible to prevent the withstand voltage from being limited by the avalanche breakdown voltage of the outermost peripheral protective diffusion layer 13 formed in the lower region of the termination trench 5b.

[0096] Furthermore, the Fig. 13 and Fig. 14 are sectional views showing a silicon carbide semiconductor device 101 and a silicon carbide semiconductor device 102, respectively, according to variants of the silicon carbide semiconductor device 100 according to the present embodiment.

[0097] As in Fig. As shown in FIG. 13, in the present embodiment, a field insulating film 18 may be formed on a part of the bottom surface of the termination trench 5b toward the end of the semiconductor layer 2. The field insulating film 18 is formed between the gate insulating film 6 and the semiconductor layer 2 in such a manner that the gate electrode 7 formed in the termination trench 5b comes onto the field insulating film 18. More specifically, the interlayer insulating film 8 is opened so that the gate terminal 17 is formed from the inner peripheral side (the active region 30 side) of a connection portion toward the outer peripheral side (the termination region 40 side).

[0098] It is sufficient that the field insulating layer 18 be formed using a low-pressure CVD method, and that the field insulating layer 18 be formed so that it is thicker than the thickness of the gate insulating layer 6. By providing the field insulating layer 18 in this way, it is possible to reduce the parasitic capacitance between the gate and drain. This enables a reduction in switching losses.

[0099] As in Fig. 14, the gate electrode 7 may also be formed to be located above the termination diffusion layer 16, connecting the gate terminal 17 to the gate electrode 7 above the termination diffusion layer 16. With this structure, the electric potential distribution is bent by the gate electrode 7 above the termination diffusion layer 16, and the location of the electric field concentration in the termination diffusion layer 16 is dispersed.

[0100] For this reason, the electric field distribution of the termination diffusion layer 16 can be smoothed, so that the width of the termination region 40 can be reduced and the chip area of ​​the silicon carbide semiconductor device 102 can be reduced more.

[0101] In the present embodiment, the MOSFET is shown with a structure in which the drift layer 2a and the silicon carbide substrate 1 have the same conductivity type. However, the present invention can also be applied to an IGBT with a structure in which the drift layer 2a and the silicon carbide substrate 1 have different conductivity types.

[0102] For example, if the silicon carbide substrate 1 is set to be a p-type semiconductor substrate at the Fig. 2, then the structure of the IGBT is obtained. In such a case, the source region 4 and the source electrode 9 in the MOSFET correspond to an emitter region and an emitter electrode, respectively, in the IGBT, and the drain electrode 10 of the MOSFET corresponds to a collector diode. Second embodiment

[0103] Fig. 15 is a sectional view showing a silicon carbide semiconductor device 103 according to a second embodiment. In Fig. 15 indicate components which have the same reference numerals and symbols as those in Fig. 14 have the same or corresponding structures. Compared to the Fig. The present embodiment differs from the structure shown in Figure 14 according to the first embodiment in that a source electrode 9 is connected to a protective diffusion layer 13 in a termination trench 5b. Accordingly, in the following description, only the differences from the first embodiment will be described, and a description of the same structures as those in the first embodiment will be omitted.

[0104] As in Fig. As shown in FIG. 15, a contact hole is formed penetrating a field insulating layer 18, a gate electrode 7, and an interlayer insulating layer 8 in the termination trench 5b. The source electrode 9 is connected to the protective diffusion layer 13 via the contact hole. Furthermore, the interlayer insulating layer 8 is also formed on a side surface of the contact hole in such a manner that the gate electrode 7 and the source electrode 9 are not connected to each other.

[0105] In the present embodiment, the following advantages can be obtained by the structure described above. When the silicon carbide semiconductor device 103 performs a switching operation, it switches between an on-state and an off-state in one switching cycle.

[0106] Therefore, carriers diffuse from the protective diffusion layer 13 to form a depletion layer when the silicon carbide semiconductor device 103 is in the off state, and the diffused carriers are returned to the original state when the silicon carbide semiconductor device 103 is in the on state. If the return of the carriers occurs late when the silicon carbide semiconductor device 103 is brought into the on state, there is a risk that the switching speed may be correspondingly reduced, resulting in an increase in switching losses.

[0107] However, in the present embodiment, the protective diffusion layer 13, which has the spreading depletion layer, is connected to the source electrode 9. Therefore, when the silicon carbide semiconductor device 103 is brought into the on-state, the carriers are returned to the protective diffusion layer 13 by means of the source potential of the source electrode 9. Consequently, it is possible to suppress an increase in switching losses.

[0108] In addition, in the same manner as in the first embodiment, the electric field of the protective diffusion layer 13 can be weakened by a terminal diffusion layer 16, and the withstand voltage of the silicon carbide semiconductor device 103 can thus be improved. Third embodiment

[0109] Fig. 16 is a sectional view showing a silicon carbide semiconductor device 104 according to a third embodiment. In Fig. 16 indicate components which have the same reference numerals and symbols as those in Fig. 15 have the same or corresponding structures. Compared to the Fig. The present embodiment differs from the structure shown in FIG. 15 according to the second embodiment in the structure of a termination trench 5b. Accordingly, in the following description, only the differences from the first embodiment will be described, and a description of the same structures as those in the first embodiment will be omitted.

[0110] As in Fig. As shown in Fig. 16, the termination trench 5b is formed to reach one end of a semiconductor layer 2. Accordingly, the end of the semiconductor layer 2, that is, a chip end of the silicon carbide semiconductor device 104, has the same height as the heights of a trench 5a and the termination trench 5b.

[0111] In the present embodiment, the following advantages can be obtained by the structure described above. The termination trench 5b is extended to the end of the semiconductor layer 2, so that a difference in the level of the chip end of the silicon carbide semiconductor device 104 can be eliminated. Therefore, it is possible to reduce the process load.

[0112] In addition, corner regions are eliminated on the outer peripheral sides of a gate insulating layer 6 and a field insulating layer 18 to be formed in the termination trench 5b. Therefore, electric field concentration does not occur in the corner regions, and it is possible to eliminate the risk that dielectric breakdown may occur in the corner regions of the gate insulating layer 6 and the field insulating layer 18.

[0113] In addition, in the same manner as in the first embodiment, the electric field of the protective diffusion layer 13 can be weakened by a terminal diffusion layer 16, and the withstand voltage of the silicon carbide semiconductor device 104 can thus be improved. Reference symbols in the drawings 1 silicon carbide substrate 2 semiconductor layer 2a Drift layer 3 Basic area 4 Source area 5a Ditch 5b Final trench 6 Gate insulating layer 7 Gate electrode 8 Interlayer insulation layer 9 Source electrode 10 Drain electrode 11 Silicon oxide layer 12 Etching mask 13 Protective diffusion layer 14 Implantation mask 15 Implantation mask 16 Final diffusion layer 17 Gate connection 18 Field insulation layer 20 contact holes 30 active area 40 Final area 100 silicon carbide semiconductor devices 101 Silicon carbide semiconductor device 102 silicon carbide semiconductor device 103 Silicon carbide semiconductor device 104 silicon carbide semiconductor device

Claims

[1] A silicon carbide semiconductor device comprising: - a drift layer (2a) of a first conductivity type formed in an active region (30) and a termination region (40) which is a surrounding region of the active region (30); - a base region (3) of a second conductivity type formed in an upper region of the drift layer (2a) in the active region (30); - a source region (4) of the first conductivity type formed in an upper region in the base region (3); - an active trench (5a) formed in the active region (30) penetrating the source region (4) and the base region (3); - a termination trench (5b) formed to surround the active trench (5a) in the drift layer (2a) of the termination region (40); - a gate insulating layer (6) formed on a bottom surface and a side surface of the active trench (5a); - a gate electrode (7) formed in the active trench (5a) with the gate insulating layer (6) interposed therebetween; - a protective diffusion layer (13) of the second conductivity type formed in a lower region of the active trench (5a) and in a lower region of the termination trench (5b) and having an impurity concentration of the second conductivity type which is a first impurity concentration; and - a second conductivity type termination diffusion layer (16) formed on an outer peripheral side of the protective diffusion layer (13) in a lower region of the termination trench (5b) and having a second conductivity type impurity concentration which is a second impurity concentration lower than the first impurity concentration, wherein the silicon carbide semiconductor device further comprises a source electrode (9) connected to the source region (4), wherein the protective diffusion layer (13) is connected to the source electrode (9). [2] A silicon carbide semiconductor device according to claim 1, wherein the width of the termination trench (5b) is larger than the width of the active trench (5a). [3] A silicon carbide semiconductor device according to claim 1 or 2, further comprising: - a drain electrode (10) formed on a back surface of the semiconductor layer, - wherein the first impurity concentration is an impurity concentration at which the protective diffusion layer (13) is not completely depleted when a rated voltage of the silicon carbide semiconductor device is applied between the drain electrode (10) and the source electrode (9). [4] A silicon carbide semiconductor device according to any one of claims 1 to 3, where the first impurity concentration is equal to or higher than 5.0E17 cm -3 and equal to or less than 5.0E18 cm -3 is, and where the second impurity concentration is equal to or higher than 1.0E17 cm -3 and equal to or less than 1.0E18 cm -3 is, and which is lower than the first impurity concentration. [5] The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the protective diffusion layer (13) is further formed in a lower region of the termination trench (5b) and on an inner peripheral side of the termination diffusion layer (16). [6] A silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the termination diffusion layer (16) has a plurality of second conductivity type regions formed separately from each other. [7] A silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the termination trench (5b) is extended to one end of the semiconductor layer. [8] A silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the gate electrode (7) extends to a top surface of the termination trench (5b) and is connected to a gate terminal (17) on the top surface of the termination trench (5b). [9] A method of manufacturing a silicon carbide semiconductor device, comprising the following steps: - preparing a semiconductor substrate (11) having an active region (30) and a termination region (40), which is a surrounding region of the active region (30), and having a semiconductor layer (2) of a first conductivity type formed from a silicon carbide semiconductor in the active region (30) and the termination region (40); - forming a base region (3) of a second conductivity type on an upper region in the semiconductor layer in the active region (30); - forming a source region (4) of the first conductivity type in an upper region in the base region (3); - forming a source electrode (9) connected to the source region (4), - forming, using a mask formed on an upper surface of the semiconductor layer, an active trench (5a) penetrating the source region (4) and the base region (3) in the active region (30), and forming a termination trench (5b) surrounding the active trench (5a) in the termination region (40); and - Implanting impurities into the lower region of the active trench (5a) or the terminating trench (5b) so as to form a protective diffusion layer (13) of the second conductivity type which has a concentration of impurities of the second conductivity type which is a first impurity concentration, and so as to form a terminating diffusion layer (16) of the second conductivity type which has a concentration of impurities of the second conductivity type which is a second impurity concentration which is lower than the first impurity concentration, wherein the protective diffusion layer (13) is connected to the source electrode (9).

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