Distortion compensation system and communication device

Abstract

Distortion compensation system comprising:- a first communication node (4, 104, 204) having a first receiving unit (13, 113) and a first transmitting unit (10, 110), wherein the first receiving unit (13, 113) has an equalizer (12, 112) and the equalizer (12, 112) has a first digital filter unit (FF1, FB1, FF101), and wherein the first transmitting unit (10, 110) has a weighting circuit (8, 108) and the weighting circuit (8, 108) has a second digital filter unit (FF2, FB2, FF102), and- a second communication node (5, 105, 205a) having a second transmitting unit (23), wherein the second transmitting unit (23) transmits a training pattern determined in advance before the second communication node receives normal data from the first transmitting unit (10, 110) of the first communication node (4, 104, 204) via a first transmission line (6, 6a, 206a), wherein- the first communication node (4, 104, 204) receives the training pattern,which is transmitted by the second transmitting unit (23) of the second communication node (5, 105, 205a), using the first receiving unit (13, 113), - the equalizer (12, 112) converges a filter constant of the first digital filter unit (FF1, FB1, FF101) such that an error with respect to the training pattern to be received is converged, - the first transmitting unit (10, 110) of the first communication node (4, 104, 204) carries out distortion compensation on the normal data to be transmitted using the converged filter constant of the first digital filter unit (FF1, FB1, FF101) as at least a part of a filter constant of the second digital filter unit (FF2, FB2, FF102) of the weighting circuit (8, 108) and then the normal data sends,- the first communication node is a sending node that mainly sends the normal data to the second communication node,- the second communication node is a receiving node that mainly receives the normal data sent from the first communication node, and - the receiving node does not include a circuit that performs distortion compensation.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a distortion compensation system and a communication device, each of which compensates for distortion occurring during data transmission. STATE OF THE ART

[0002] When multiple communication nodes exchange data over a transmission line, as the data rate increases, the transmission waveform becomes more likely to be distorted. At this time, the distortion of the transmission waveform leads to intersymbol interference, which prevents digital communication processing from being performed properly.

[0003] When the transmission path characteristics of the transmission line are detected in advance and a communication device includes a weighting circuit, waveform distortion can be compensated and data communication can be properly performed by minimizing the influence of the distortion. Generally, a weighting circuit includes a pre-distortion type and a post-distortion type, which have essentially the same implementation and essentially the same effect.

[0004] This type of post-equalization is used, for example, in the internal bus of a PC or similar device. The PC's internal bus addresses waveform distortion, which, for example, causes a particular transmitted bit to affect the immediately following bit.

[0005] Generally, if the influence of a particular transmitted bit on the immediately following bit is considered, compensation can be applied to offset the distortion caused by that influence. However, the transmission characteristics of a transmission line vary depending on the cable length, material, etc. Consequently, the transmission characteristics can be difficult to identify if a situation cannot be detected in advance.

[0006] Another method for improving waveform distortion is known as adaptive DFE (Decision Feedback Equalizer). According to the DFE method, a receiving unit compensates for distortion using a received waveform.

[0007] When the DFE method described above is applied, a circuit scale usually increases. Assume that a communication node that transmits normal data is a first communication node, and a communication node that receives the normal data is a second communication node. For example, if the second communication node is more restricted by size constraints than the first communication node, it is difficult to provide the DFE circuit in the second communication node. There are also cases where, under various constraints not limited to size constraints, the second communication node cannot include a distortion compensation circuit such as the DFE circuit.

[0008] JP 2008-503929 A (JP 4 841 548 B2) discloses a distortion compensation method, according to which the first communication node transmits a test pattern to the second communication node, and a test pattern reception result is transmitted back to the first communication node. However, this configuration requires additional communication circuitry in the second communication node to transmit the test pattern reception result from the second communication node back to the first communication node.

[0009] US 4,995,057 A relates to digital communications, and in particular to a technique that makes the theoretical coding gain associated with any error correction technique substantially achievable. The theoretical coding gain associated with an error correction technique can be realized in a digital communications system employing this error correction by performing the equalization in the transmitter rather than the receiver. This involves setting an automatic equalizer in the receiver of a digital communications system using a training sequence. The equalizer coefficients for the optimal setting are then transmitted back to the transmitter and fed to an equalizer there. After the training period has elapsed, this transmit equalizer, which now has optimal coefficients, is activated, and the receiver equalizer is deactivated.EP 1 540 820 B1 also discloses a device and a method for channel equalization. SUMMARY OF THE INVENTION

[0010] In view of the above difficulties, it is an object of the present invention to provide a distortion compensation system that can compensate for signal distortion caused by a transmission line used for communication processing between a first communication node and a second communication node without disposing a distortion compensation circuit in the second communication node serving as a receiving node or disposing a communication circuit in the second communication node for sending a test pattern reception result from the second communication node back to the first communication node. It is also an object of the present invention to provide a communication device included in the above distortion compensation system.

[0011] The object is achieved by a distortion compensation system according to claim 1 and a communication device according to claim 39. Advantageous further developments are the subject of the subclaims.

[0012] According to the distortion compensation system of the present invention, before performing communication processing on the normal data between the first communication node and the second communication node, the second transmitting unit of the second communication node transmits the training pattern determined in advance to the first communication node. The first receiving unit of the first communication node converges the filter constant of the first digital filter of the equalizer to reduce reception errors of the training pattern.

[0013] Subsequently, the first transmitting unit of the first communication node performs distortion correction in advance using the converged filter constants of the first digital filter as at least part of the filter constants of the second digital filter of the weighting circuit, and the first transmitting unit of the first communication node transmits the corrected signal. Consequently, the first and second communication nodes can compensate for signal distortion due to the transmission line.

[0014] In the above configuration, a distortion compensation circuit is no longer required in the second communication node serving as the data receiver. It is sufficient for the second communication node to have only a transmission circuit for transmitting the training pattern. This configuration further eliminates the need to arrange the communication circuit for returning the test pattern reception result in the second communication node.

[0015] In the communication device of the present invention, the first transmission unit performs distortion correction in advance using the converged filter constant of the first digital filter as at least part of the filter constant of the second digital filter of the weighting circuit, and then transmits the corrected signal to the weighting circuit. This configuration can compensate for signal distortion due to a transmission line between the above communication device and the external second communication node without disposing a distortion compensation circuit in the second communication node or disposing a communication circuit for returning the test pattern reception result from the second communication node to the above communication device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The objects, features, and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Fig. 1 is a schematic block diagram illustrating an example of an electrical configuration of a distortion compensation system according to a first embodiment of the present invention; Fig. 2 is a schematic block diagram illustrating an example of an electrical configuration of a vehicle system; Fig. 3 is a schematic diagram of an electrical configuration illustrating an example of a configuration of a DFE circuit; Fig. 4 is a schematic diagram of an electrical configuration illustrating an example of a configuration of a DFE processing unit; Fig. 5A is a schematic diagram of an electrical configuration illustrating an example of a configuration of a digital filter when a first feedforward filter is provided by an FIR filter; Fig. 5B is a schematic diagram of an electrical configuration illustrating an example of a configuration of a digital filter when a first feedback filter is provided by an FIR filter; Fig. 6 is a schematic diagram of an electrical configuration illustrating an example of a configuration of a weighting circuit; Fig. 7A is a schematic diagram of an electrical configuration illustrating an example of a configuration of a digital filter when a second feedforward filter is provided by an FIR filter; Fig. 7B is a schematic diagram of an electrical configuration illustrating an example of a configuration of a digital filter when a second feedback filter is provided by an FIR filter; Fig. 8 is a schematic timing chart illustrating an example of the flow of communication processing of a training pattern and communication processing of normal data; Fig. 9 is a diagram illustrating an example of a response waveform on a transmission line; Fig. 10A and Fig. 10B Figures illustrating an example of a simulation of the converged filter constants of the digital filters; Fig. 11 is a schematic diagram illustrating an example of a simulation for illustrating a transmission waveform from a second communication node and an output waveform from a DFE circuit in the receiving unit of a first communication node; Fig. 12 is a schematic diagram illustrating an example of a simulation for illustrating a transmission waveform from the first communication node and a reception waveform in the reception unit of the second communication node; Fig. 13 is a diagram illustrating an example of a configuration of a weighting circuit having the function of adjusting the tap length of a digital filter according to a second embodiment of the present invention; Fig. 14 is a diagram illustrating an example of the transmission characteristic of the transmission line; Fig. 15 is a schematic electrical configuration diagram showing an example of a connection form in which three or more communication nodes are connected via a vehicle network according to a third embodiment of the present invention; Fig. 16 is a schematic diagram of an electrical configuration illustrating an example of a connection form in which three or more communication nodes are connected via a Y-branch line; Fig. 17 is a schematic diagram of an electrical configuration illustrating an example of a form in which terminating resistors are arranged at the end portions of a network; Fig. 18 is a schematic diagram of an electrical configuration illustrating an example of a form in which terminating resistors are arranged at the end portions of a network having a Y-branch line; Fig. 19 is a diagram illustrating an example of the filter constants of the digital filters acquired by the first communication node; Fig. 20 is a diagram illustrating an example of a CAN FD frame format according to a fourth embodiment of the present invention; Fig. 21 is a diagram illustrating an example of a data rate characteristic in a CAN FD data phase; Fig. 22 is a diagram illustrating an example of a network connection form when a program rewriting device is applied to the first communication node; Fig. 23 is a timing chart illustrating an example of the flow of communication processing among a plurality of communication nodes; Fig. 24 is a diagram illustrating an example of a connection form in which a vehicle network is connected to a higher-order network via a gateway according to a fifth embodiment of the present invention; Fig. 25A is a diagram illustrating an example of simulation data to be sent when a method is applied to an example of a comparison target; Fig. 25B is a diagram illustrating an example of an eye diagram when the method is applied to the example of the comparison target; Fig. 26A is a diagram illustrating an example of simulation data to be sent when a method in the first embodiment is applied; Fig. 26B is a diagram illustrating an example of an eye diagram when the method in the first embodiment is applied; Fig. 27A is a diagram illustrating an example of a data sequence in the training pattern according to a sixth embodiment of the present invention; Fig. 27B is a diagram illustrating a conceptual view of the representation of a case where a data sequence is a data sequence divided into subbits in the sixth embodiment; Fig. 28A is a diagram illustrating an example of simulation data to be sent; Fig. 28B is a diagram illustrating an example of an eye diagram; Fig. 29A is a diagram illustrating an example of a data sequence in the training pattern; Fig. 29B is a diagram illustrating a conceptual view of the representation of a case where a data sequence is a data sequence divided into subbits in a seventh embodiment of the present invention; Fig. 30A is a diagram illustrating an example of simulation data to be sent when each single bit is divided into three subbits; Fig. 30B is a diagram illustrating an example of an eye diagram; Fig. 31A is a diagram illustrating an example of simulation data to be sent when each individual bit is divided into five subbits; Fig. 31B is a diagram illustrating an example of an eye diagram; Fig. 32 is a schematic block diagram illustrating an example of an electrical configuration of a distortion compensation system according to an eighth embodiment of the present invention; Fig. 33 is a diagram illustrating an example of an eye diagram when each individual bit is divided into two subbits; Fig. 34 is a diagram illustrating an example of an eye diagram when each individual bit is divided into three subbits; Fig. 35 is a diagram illustrating an example of an eye diagram when each individual bit is divided into four subbits; Fig. 36 is a diagram illustrating an example of an eye diagram when each individual bit is divided into five subbits; Fig. 37 is a schematic block diagram illustrating an example of an electrical configuration of a distortion compensation system according to a ninth embodiment of the present invention; Fig. 38 is a diagram illustrating an example of an eye diagram when each individual bit is divided into two subbits; Fig. 39 is a diagram illustrating an example of an eye diagram when each individual bit is divided into three subbits; Fig. 40 is a diagram illustrating an example of an eye diagram when each individual bit is divided into four subbits; Fig. 41 is a diagram illustrating an example of an eye diagram when each individual bit is divided into five subbits; Fig. 42 is a schematic block diagram illustrating an example of an electrical configuration of a distortion compensation system according to a tenth embodiment of the present invention; Fig. 43 is a schematic diagram of an electrical configuration illustrating an example of a configuration of an equalizer; Fig. 44A is a schematic electrical configuration diagram showing an example of a configuration of an equalizer processing unit; Fig. 44B is a schematic diagram of an electrical configuration illustrating an example of a configuration of the first feedforward filter; Fig. 45A is a schematic electrical configuration diagram showing an example of a configuration of the weighting circuit; Fig. 45B is a schematic diagram of an electrical configuration illustrating an example of a configuration of the second feedforward filter; Fig. 46 is a schematic block diagram illustrating an example of an electrical configuration when a training pattern selection signal line for selecting a node to which the training pattern is to be sent is connected, according to an eleventh embodiment of the present invention; Fig. 47 is a schematic timing chart illustrating an operation when a training pattern transmission request is issued; Fig. 48 is a schematic block diagram illustrating an exemplary implementation according to a twelfth embodiment of the present invention; Fig. 49 a schematic block diagram illustrating an exemplary implementation; Fig. 50 is a schematic timing chart illustrating an operation when the training pattern transmission request is issued; Fig. 51 is a schematic block diagram illustrating an exemplary implementation; and Fig. 52 is a schematic block diagram illustrating an exemplary implementation according to a thirteenth embodiment of the present invention. EMBODIMENTS FOR CARRYING OUT THE INVENTION

[0017] Several embodiments of a distortion compensation system are described below with reference to the accompanying drawings. Elements with the same or similar functions are designated by the same reference numerals and, to avoid redundancy, are not described repeatedly. The sections containing the characteristic features of the respective embodiments are mainly described below. (First embodiment)

[0018] The Fig. 1 to 12 show the first embodiment. Fig. 1 shows an example of an electrical configuration of a distortion compensation system S. Fig. 2 schematically shows an example of a connection configuration in a vehicle system.

[0019] In a vehicle, as in Fig. 2, an ECU 1 serving as a master and a drive circuit 2 serving as a slave are connected via, for example, a bus 3. The drive circuit 2 may be arranged to drive an actuator. Comparing the ECU 1 with the drive circuit 2, the ECU 1 has a larger circuit scale than the drive circuit 2 and also has a larger mounting space for a circuit or the like than in the drive circuit 2.

[0020] A communication device (corresponding to a first communication node) 4 is mounted in the ECU 1. A communication device (corresponding to a second communication node) 5 is mounted in the drive circuit 2. Each of the communication devices 4 and 5 comprises, for example, a semiconductor integrated circuit. The communication device 4 of the ECU 1 comprises a circuit that mainly transmits normal data. The communication device 5 of the drive circuit 2 comprises a circuit that mainly receives the normal data.

[0021] The one in the Fig. Bus 3 shown in Figure 2 serves electrically as a Fig. 1 shown transmission line 6. The communication device 4 of the ECU 1 has, as in Fig. 1, a transmitting unit 10 includes a control circuit 7, a weighting circuit 8, and a transmitting amplifier 9. The control circuit 7 includes, as a main component, a microcomputer. The microcomputer includes a CPU, a ROM, a RAM, a non-volatile memory, and the like. The control circuit 7 functionally includes a data transmitting unit 7a and a data receiving unit 7b. The data transmitting unit 7a generates digital data and outputs the digital data to the weighting circuit 8.

[0022] The weighting circuit 8 is a functional block that receives the digital data transmitted from the data transmitting unit 7a at normal times, performs distortion compensation on the digital data, and outputs the digital data to the transmitting amplifier 9 via a D / A conversion unit (not shown). The weighting circuit 8 has a filter constant holding unit 8a. The filter constant holding unit 8a is a storage unit that stores constants (coefficients h1[0] to h1[k1]) of a second feedforward filter FF2 in the Fig. 7A and coefficients h2[0] to h2[k2] a second feedback filter FB2 in Fig. 7B, the coefficients of which are described below) required for internal processing in the digital filters. The filter constant holding unit 8a can be provided, for example, by a register.

[0023] The transmission amplifier 9 converts the amplitude of an output signal of the weighting circuit 8 into the amplitude of an electrical signal and outputs the signal to the transmission line 6. A transmission signal from the transmission unit 10 is transmitted via the transmission line 6 to the communication device 5.

[0024] The communication device 4 of the ECU 1 includes a receiving unit 13, and the receiving unit 13 includes a receiving amplifier 11 and a DFE circuit 12. The DFE circuit 12 serves as an equalizer. The receiving unit 13 receives the signal transmitted from the communication device 5 of the drive circuit 2 via the transmission line 6. The receiving amplifier 11 amplifies the signal transmitted from the communication device 5 via the transmission line 6. The receiving amplifier 11 then outputs the signal to the DFE circuit 12.

[0025] The DFE circuit 12 is a block that performs equalization processing for improving waveform distortion and has an embedded filter constant holding unit 12a. The filter constant holding unit 12a is a storage unit that stores constants (coefficients h1[0] to h1[n1]) of a first feedforward filter FF1 in the Fig. 5A and coefficients h2[0] to h2[n2] of a first feedback filter FB1 in Fig. 5B) required for internal processing in the digital filters, which will be described below. The filter constant holding unit 12a is provided, for example, by a register.

[0026] After the equalization processing, the DFE circuit 12 outputs the processed signal to the data receiving unit 7b of the control circuit 7. The data receiving unit 7b receives the signal transmitted from the DFE circuit 12 and outputs the received signal as digital data.

[0027] The communication device 4 of the ECU 1 includes a transmission unit 14. The transmission unit 14 is a block that transmits the filter constants from the filter constant holding unit 12a of the DFE circuit 12 to the filter constant holding unit 8a of the weighting circuit 8. The transmission unit 14 can be implemented by internal software of the microcomputer included in the control circuit 7 or by a hardware circuit.

[0028] The communication device 4 further includes a clock generation unit 17. The clock generation unit 17 is a block that receives a control signal from the control circuit 7 to generate clock signals for operating the DFE circuit 12 and the weighting circuit 8. The clock generation unit 17 is configured to change the frequencies of the clock signals in accordance with, for example, the control signal from the control circuit 7. The clock generation unit 17 generates required clock signals as operation clock signals and outputs them to the control circuit 7, the receiving unit 13 (such as the DFE circuit 12 or the data receiving unit 7b), and the transmitting unit 10 (such as the data transmitting unit 7a, the weighting circuit 8, or the D / A conversion unit (not shown)).

[0029] The communication device 5 of the drive circuit 2 includes a control circuit 20, a receiving amplifier 21, and a transmitting amplifier 22. The control circuit 7 includes a microcomputer as a main component. The microcomputer includes a CPU, a ROM, a RAM, a non-volatile memory, and the like. The control circuit 7 functionally includes a data transmitting unit 20a and a data receiving unit 20b. The communication device 5 further includes a clock generating unit 27. The clock generating unit 27 generates a clock signal with a predetermined frequency and provides the clock signal for operating the control circuit 20. The data transmitting unit 20a generates digital data and outputs the digital data to the transmitting amplifier 22. The transmitting amplifier 22 amplifies a digital data signal and outputs the amplified digital data signal to the transmission line 6.

[0030] The receiving amplifier 21 receives the transmission signal from the transmitting unit 10 of the communication device 4 via the transmission line 6, amplifies the received signal, and outputs the amplified signal to the data receiving unit 20b. The data receiving unit 20b receives the signal amplified by the receiving amplifier 21 and outputs the signal as digital data.

[0031] The data receiving unit 20a and the transmitting amplifier 22 are included in a transmitting unit 23 (corresponding to a second transmitting unit) of the communication device 5. The receiving amplifier 21 and the data receiving unit 20b are included in a receiving unit 24 of the communication device 5. According to the configuration described above, the communication devices 4 and 5 can exchange data bidirectionally.

[0032] The DFE circuit 12 in the communication device 4 is provided by a so-called adaptive DFE (Decision Feedback Equalizer). The DFE circuit 12 has, as shown in Fig. 3, an A / D conversion unit 15 and a DFE processing unit 16. The DFE processing unit 16 performs DFE processing on the conversion result from the A / D conversion unit 15. The A / D conversion unit 15 subjects the received signal amplified by the receiving amplifier 21 to A / D conversion processing and outputs a digital signal converted from the analog signal to the DFE processing unit 16.

[0033] The DFE processing unit 16 performs, as in Fig. 4, the DFE processing unit 16 performs distortion compensation processing on the digital signal output from the A / D conversion unit 15. The DFE processing unit 16 includes a first feedforward filter FF1, an adder A1, a data slicer S1, a subtractor M1, and a first feedback filter FB1.

[0034] In the example of Fig. 4, the first feedforward filter FF1 performs digital filter processing (such as an FIR filter) on the signal input to the DFE processing unit 16 and outputs the filtered digital signal to the adder A1. The first feedback filter FB1 performs digital filter processing (such as an FIR filter) on the digital signal output from the DFE processing unit 16 and outputs the filtered digital signal to the adder A1.

[0035] The first feedforward filter FF1 has, as in Fig. As shown in Figure 5A, the circuit comprises 1-clock delay elements D1a to Dn1a connected in series, multipliers Mu0a to Mun1a, and an adder Aa. The number of 1-clock delay elements is n1, and the number of multipliers is (n1 + 1).

[0036] Each of the delay elements D1a to Dn1a performs delay processing corresponding to one clock in response to the clocks (not shown) provided by the control circuit 7. The filter constant holding unit 12a holds the coefficients h1[0] to h1[n1] and outputs the coefficients h1[0] to h1[n1] to the multipliers Mu0a to Mun1a.

[0037] Multipliers Mu0a to Mun1a of the first feedforward filter FF1 multiply 0 to n1 clock delay data items, which are delayed by the respective n1 delay elements D1a to Dn1a, by the respective coefficients h1[0] to h1[n1]. Here, the 0-clock delay data item represents the input data IN. Adder Aa of the first feedforward filter FF1 sums the respective results of the multiplications by multipliers Mu0a to Mun1a to generate the output data OUT.

[0038] The first feedback filter FB1 has, as shown in Fig. 5B shows 1-clock delay elements D1b to Dn2b connected in series, multipliers Mu0b to Mun2b, and an adder Ab. The number of 1-clock delay elements is n2, and the number of multipliers is (n2 + 1).

[0039] The multipliers Mu0b to Mun2b of the first feedback filter FB1 multiply 0 to n2 clock delay data items, which are delayed by the respective n2 delay elements D1b to Dn2b, by the respective coefficients h2[0] to h2[n2]. Here, the 0-clock delay data item describes the input data IN. The adder Ab of the first feedback filter FB1 sums the respective results of the multiplications by the multipliers Mu0b to Mun2b to generate the output data OUT.

[0040] For example, in the above description, FIR filters are used. Alternatively, another type of digital filter (such as IIR filters) could also be used.

[0041] Below we refer again to the Fig. 4. The Fig. The adder A1 shown in Figure 4 adds the respective output signals of the first feedforward filter FF1 and the first feedback filter FB1 and outputs the summation result to the data slicer S1. The data slicer S1 is a circuit that converts a signal waveform into a data value and outputs the conversion result as an output of the DFE processing unit 16.

[0042] A signal waveform is distorted under the influence of the transmission line 6. The data slicer S1 determines a nearest signal level for the distorted waveform.

[0043] The subtractor M1 calculates the signal difference between an input signal to the data slicer S1 and the output symbol OUT and outputs the calculation result as an error to the control circuit 7. The control circuit 7 receives the error, converges the respective coefficients h1[0] to h1[n1] and h2[0] to h2[n2] to be set in the first feedforward filter FF1 and the first feedback filter FB1 so that the error approaches 0, and stores the converging coefficients in the filter constant holding unit 12a.

[0044] Examples of a method for converting the filter constants of digital filters include a method using an algorithm such as LMS (Least Mean Square), Sign-Data, Sign-Error, Sign-Sign LMS, or Leaky LMS. The convergence method is not limited to the described methods.

[0045] The control circuit 7 converts the respective coefficients h1[0] to h1[n1] and h2[0] to h2[n2] to be set in the first feedforward filter FF1 and the first feedback filter FB1 such that the input of the data slicer S1 is equal to the output of the data slicer S1. Here, when the input / output error (input / output voltage error) falls below a predetermined value, it is considered that convergence is complete.

[0046] After the convergence is completed, the update processing for the filter constants may be terminated. According to another example, it is also possible to continue the update processing, for example, every predetermined period, or to continue the update processing while gradually decreasing the update frequency from the predetermined period. The update processing may also be performed in such a way that the amount of update load is reduced. If it is empirically clear, for example, that the error assumes a value less than or equal to the predetermined value after the convergence processing is performed for a certain period of time, it may also be assumed that the approximation is completed after the certain period of time described above has elapsed using a timer.The “predetermined value” used for the convergence processing of the error is determined in terms of design in accordance with the S / N required for the system.

[0047] The Fig. The weighting circuit 8 shown in FIG. 6 includes the second feedforward filter FF2, the second feedback filter FB2, an adder A2, and the filter constant holding unit 8a. Herein, the second feedforward filter FF2 may be provided, for example, by a structure similar to that of the first feedforward filter FF1. The second feedback filter FB2 may be provided, for example, by a structure similar to that of the first feedback filter FB1. The weighting circuit 8 is functionally different from the circuit of the DFE processing unit 16. The weighting circuit 8 is provided by a circuit in which the data slicer S1 and the subtractor M1 are omitted from the DFE processing unit 16.

[0048] The Fig. 7A and Fig. 7B schematically shows an example of a configuration of the digital filter when both the second feedforward filter FF2 and the second feedback filter FB2 are provided by an FIR filter.

[0049] The second feedforward filter FF2 has, as in Fig. As shown in Figure 7A, the 1-clock delay elements TD1a to TDk1a are connected in series, and multipliers TMu0a to TMuk1a are connected. The number of 1-clock delay elements is k1, and the number of multipliers is (k1 + 1).

[0050] Each of the delay elements TD1a to TDn1a of the second feedforward filter FF2 performs delay processing corresponding to one clock in response to the clocks from the control circuit 7. The multipliers TMu0a to TMuk1a of the second feedforward filter FF2 are supplied with the coefficients h1[0] to h1[k1], respectively, from the filter constant holding unit 8a of the weighting circuit 8.

[0051] The DFE processing unit 16 calculates the multiplication coefficients h1[0] to h1[n1] of the first feedforward filter FF1 as described above. The calculation results are stored in the filter constant holding unit 12a of the DFE circuit 12. The transmission unit 14 transmits these coefficients h1[0] to h1[n1] to the filter constant holding unit 8a of the weighting circuit 8.

[0052] Herein, the multipliers TMu0b to TMuk1a of the second feedforward filter FF2 are provided with the coefficients h1[0] to h1[n1] (the coefficients of the multipliers Mu0a to Mun1a of the first feedforward filter FF1), which are transmitted from the transmission unit 14 to the filter constant holding unit 8a.

[0053] Herein, when the second feedforward filter FF2 uses the digital filter satisfying k1 = n1, the multiplication coefficients h1[0] to h1[n1] of the first feedforward filter FF1 are directly given to the multipliers TMu0a to TMuk1a of the second feedforward filter FF2.

[0054] Multipliers TMu0b to TMuk1a of the second feedforward filter FF2 multiply 0 to k1 clock delay data elements generated by the (k1 + 1) delay elements TD1a to TDn1a by the respective coefficients h1[0] to h1[k1]. Adder Aa2 of the second feedforward filter FF2 sums the respective results of the multiplications by multipliers TMu0a to TMuk1a to generate the output OUT.

[0055] The second feedback filter FB2 has the Fig. As shown in Figure 7B, the circuit comprises 1-clock delay elements TD1b to TDk2b connected in series, multipliers TMu0b to TMuk2b, and an adder Ab2. The number of 1-clock delay elements is k2, and the number of multipliers is (k2 + 1).

[0056] Each of the delay elements TD1b to TDk2b of the second feedback filter FB2 performs delay processing corresponding to one clock in response to the clocks from the control circuit 7. The coefficients h2[0] to h2[k2] from the filter constant holding unit 8a of the weighting circuit 8 are input to the multipliers TMu0b to TMuk2b of the second feedback filter FB2.

[0057] The DFE processing unit 16 of the DFE circuit 12 calculates the multiplication coefficients h2[0] to h2[n2] of the first feedback filter FB1 as described above. The calculation results are stored in the filter constant holding unit 12a of the DFE circuit 12. The transmission unit 14 transmits the coefficients h2[0] to h2[n2] to the filter constant holding unit 8a of the weighting circuit 8. Subsequently, the filter constant holding unit 8a outputs the coefficients h2[0] to h2[n2] of the multipliers Mu0b to Mun2b of the first feedback filter FB1 to the multipliers TMu0b to TMuk2b of the second feedback filter FB2.

[0058] Herein, when the second feedback filter FB2 uses a digital filter satisfying k2 = n2, the multiplication coefficients h2[0] to h2[n2] of the first feedback filter FB1 can be directly given to the multipliers TMu0b to TMuk2b of the second feedback filter FB2.

[0059] The multipliers TMu0b to TMuk2b of the second feedback filter FB2 multiply 0 to k2 clock delay data items generated by the (k2 + 1) delay elements TD1b to TDk2b as needed through delay processing by the respective coefficients h2[0] to h2[k2].

[0060] The adder Ab2 of the second feedback filter FB2 sums the respective multiplication results by the multipliers TMu0b to TMuk2b to generate the output OUT. Consequently, even if the input data IN has a digital level corresponding to the binary values "0" and "1," the output data OUT is digital data with a decimal level different from the binary values.

[0061] The following is a communication operation in the above configuration with reference to the Fig. 8. The communication device 4 of the ECU 1 performs transmission processing on the large-capacity normal data between the communication device 4 and the communication device 5 of the drive circuit 2 via the transmission line 6. In the present embodiment, before performing transmission / reception processing on the normal data, the communication device 4 performs communication processing on a training pattern.

[0062] Examples of the timing for communicating the training pattern between the ECU 1 and the drive circuit 2 include, for example, a time when the vehicle is turned on (when an ignition switch is turned on: power-on). Further, examples of the timing for communicating the training pattern may also include the time when the ECU 1 or the drive circuit 2 is reset (restarted), and the time of relearning (new training) when the transmission line 6 is changed, such as when the transmission line 6 is newly provided / added / changed / removed (see S1 in the Fig. 8).

[0063] It should be noted that, in the present embodiment, for example, while the normal large-capacity data is transmitted in the direction from the communication device 4 of the ECU 1 to the communication device 5 of the drive circuit 2, the training pattern is transmitted from the communication device 5 of the drive circuit 2 to the communication device 4 of the ECU 1 (see S2 in the Fig. 8). Consequently, training processing occurs before large-capacity communication.

[0064] The communication device 5 does not include a distortion compensation circuit corresponding to the weighting circuit 8 in the ECU 1. Accordingly, when the communication device 5 transmits the training pattern in the form of a binary signal using, for example, a PRBS (Pseudorandom Binary Sequence), the signal waveform received by the communication device 4 is distorted under the influence of the transmission line 6 or the like.

[0065] It should be noted that any pattern can be used as the training pattern, as long as the pattern is determined in advance such that the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters FF1 and FB1 of the DFE processing unit 16 converge. Preferably, the PRBS is used to randomly generate different patterns with equal probabilities and without distortion. The PRBS is typically generated using, for example, an LFSR (Linear Feedback Shift Register).

[0066] The communication device 4 of the ECU 1 receives the training pattern (see S2 in the Fig. 8). The reception amplifier 11 in the communication device 4 amplifies the training pattern. Here, the training pattern has distortion due to the transmission line 6. The DFE processing unit 16 performs correction processing on the distortion in the signal waveform. When the correction processing is performed on the distortion of the signal waveform, the DFE processing unit 16 converges the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters FF1 and FB1 in the DFE processing unit 16 (see S3 in the Fig. 8).

[0067] In this case, the DFE processing unit 16 converges the respective coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the first feedforward filter FF1 and the first feedback filter FB1 to maximally suppress an error, and then the DFE processing unit 16 stores the coefficients in the filter constant holding unit 12a. Following the convergence of these filter constants, the transmission unit 14 transmits the filter constants held in the filter constant holding unit 12a to the filter constant holding unit 8a of the weighting circuit 8 (see S4 in the Fig. 8).

[0068] The weighting circuit 8 in the communication device 5 corrects, with reference to the filter constants held in the filter constant holding unit 8a, transmission data such that compensation is performed in advance (see S5 in the Fig. 8). At this time, the transmitted data immediately after correction is a signal in which the data is distorted.

[0069] The transmitting unit 10 of the communication device 4 transmits the normal data (normal pattern) to the communication device 5 of the drive circuit 2 (see S6 in the Fig. 8). The transmission signal undergoes distortion when it passes through the transmission line 6. Since the weighting circuit 8 has corrected the transmission signal in such a way that compensation is performed in advance, the effects of the correction and the distortion cancel each other out to allow the data receiving unit 20b of the drive circuit 2 to receive a signal waveform that has substantially no distortion (see S7 in the Fig. 8). (Description of the principle)

[0070] The following describes the principle of how distortion can be corrected during data communication, based on the process described above. The characteristics of the transmission line 6 can generally be described using S-parameters. Even in a differential transmission line, four ports are present. In the differential transmission line, if the primary focus is on a differential signal, an approximation can be made using two-port S-parameters. Generally, the characteristics of the transmission line 6 are described using S-parameters in 2 x 2 rows and columns.For example, if conditions are met, in such a case, for example, that the transmission line 6 has no internal positive element but a passive characteristic, the S-parameters in the 2 x 2 rows and columns described by S11, S21, S12 and S22 satisfy the following equation:. S21=S12

[0071] After approximating the filter constants of the digital filters FF1 and FB, if a quantization error or the like is ignored, it can be considered that the transmission line 6 has a linear characteristic.

[0072] Since the DFE processing unit 16 includes the data slicer S1, the DFE processing unit 16 exhibits a non-linear characteristic. However, when the error is completely zero, or when the error is not completely zero but has a substantially small value that can be ignored, a state is realized in which no signal change occurs even when the data slicer S1 executes the processing assigned to the data slicer S1. In a situation where the signal is not affected by the data slicer S1, the DFE processing unit 16 can be considered to exhibit a linear characteristic.

[0073] When the frequency dependence of the transmission characteristic of the DFE processing unit 16 is defined as G_dfe, the transmission characteristic of the drive circuit 2 from the transmitting amplifier 22 to the receiving amplifier 11 of the ECU 1 can be described by S12 × G_dfe. At this time, when the coefficients of the digital filters FF1 and FB1 are converged, the value becomes a constant value (constant), as shown below. S12×G_dfe=constant

[0074] This value has no frequency dependence. Accordingly, waveform distortion can be compensated. Typical transmission lines 6, typical DFE processing units 16, and the like have frequency-dependent characteristics and are not guaranteed, for example, in extremely high frequency ranges.

[0075] The operating frequencies at which various circuits, such as the transmission line 6 and the DFE processing unit 16, operate have been determined in advance based on transmission data. It can be assumed that, within the range of operating frequencies, the frequency dependence of both the transmission line 6 and the DFE processing unit 16, etc., is substantially constant.

[0076] Hereinafter, assume that the frequency characteristic of the weighting circuit 8 is defined as G_emph. The weighting circuit 8 has the same filter constants as the DFE processing unit 16 and a circuit configuration similar to the DFE processing unit 16. Consequently, the weighting circuit 8 and the DFE processing unit 16 have the same frequency response characteristics, as shown below. G_dfe=G_emph

[0077] The transmission characteristic from the transmitting unit 10 of the communication device 4 of the ECU 1 to immediately before the receiving amplifier 21 of the communication device 5 of the control circuit 2 can be described by G_emph x S21. Considering the relationships outlined above, Equation 4 can be calculated as follows. G_emph×S21=S21×G_emph=S12×G_emph=S12×G_dfe

[0078] Accordingly, the transmission characteristic from the transmitting unit 10 of the ECU 1 to immediately before the receiving amplifier 21 of the control circuit 2 is the same as the transmission characteristic from immediately after the transmitting amplifier 22 of the control circuit 2 to the DFE circuit 12 of the ECU 1.

[0079] Consequently, when the weighting circuit 8 of the ECU 1 performs digital filtering on the signal waveform using the same filter constant, even if the signal waveform is distorted on the transmission line 6, the distortion of the signal waveform is compensated in the receiving unit of the drive circuit 2. This configuration can minimize the error. (Result of the simulation)

[0080] The inventors of the present invention have verified the above-described point through simulation. For example, consider the case where a Fig. 9 is received via the transmission line 6 (cable) in the receiving unit 13 of the ECU 1 when the communication device 5 sends a step-like waveform W1 which changes from “0” to “1”.

[0081] In this case, according to the equation 1, when the data transmission unit 7a of the ECU 1 transmits the jump-like waveform W1, which, as shown in Fig. 9, changes from “0” to “1”, the data receiving unit 20b of the drive circuit 2 generates the step response waveform W2.

[0082] The Fig. The transmission signal shown in Figure 9, for example, uses a 1 Gbit / s transmission signal and shows the result of a simulation in a step cycle of one nanosecond. Accordingly, during a step of one nanosecond, the result obtained using linear interpolation is shown. However, the obtained result may differ from the result of actual monitoring.

[0083] When the data transmission unit 20a of the communication device 5 transmits a pattern in the form of a pseudorandom signal as the training pattern, the communication device 4 performs distortion correction using the DFE processing unit 16. At this time, the DFE processing unit 16 converges the filter constants of the first feedforward filter FF1 and the first feedback filter FB1.

[0084] Fig. Figure 10A shows an example of the result of a simulation of the converged filter constants of the first feedforward filter FF1. Fig. Figure 10B shows an example of the result of a simulation of the converged filter constants of the first feedback filter FB1.

[0085] Fig. Fig. 11 schematically shows a transmission waveform W3 (open squares) from the communication device 5 and further a waveform W4 (filled diamonds) after the DFE processing by the DFE processing unit 16. It can be seen that, in the example of Fig. 11, the transmission waveform W3 and the post-processing waveform W4 substantially coincide with each other. It should be noted that, in practice, the time at which the reception waveform is given to the communication device 4 and the time after the waveform processing by the DFE processing unit 16 do not completely coincide under the influence of a filter delay time after the DFE processing or the like. Fig. 11, in order to simplify the comparison between the post-processing waveform W4 and the transmission waveform W3, the post-processing waveform W4 shown in the drawings has been shifted by the delay time to match the transmission waveform W3.

[0086] It is, as shown by the post-processing waveform W4 in the Fig. 11, it can be seen that since the DFE processing unit 16 of the communication device 4 compensates for the distortion, the transmission waveform W3 is reproduced substantially perfectly.

[0087] Subsequently, the transmitting unit 14 transmits the filter constants stored in the filter constant holding unit 12a of the DFE circuit 12 to the filter constant holding unit 8a of the weighting circuit 8. The weighting circuit 8 performs distortion correction using the filter constants held in the filter constant holding unit 8a.

[0088] If that in the Fig. 12 shown signal (waveform W5: blank squares) is input, the weighting circuit 8 generates the signal shown in the Fig. 12 (waveform W6). When the communication device 4 transmits the signal over the transmission line 6, the signal on the transmission line 6 undergoes waveform distortion.

[0089] This results in the communication device 5 having a Fig. 12 receives the signal waveform W7 (filled diamonds). It can be seen that the Fig. 12 is essentially the same as the signal waveform W7 shown in Fig. 12. This is because the weighting circuit 8 has compensated for the waveform distortion in advance.

[0090] There is, as in Fig. 12, a period of time during which the output signal waveform W6 of the weighting circuit 8 exceeds the signal level of 2. This is because the output signal waveform W6 depends on the magnitudes of the filter constants of the digital filters FF1 and FF2 of the DFE processing unit 16 and is determined in accordance with the internal processing in the DFE processing unit 16. The use of the output waveform W6 is not limited to that in the present method.

[0091] If the output signal from the communication device 4 has an excessively high waveform amplitude, the output voltage is adjusted as needed. Even in this case, the input waveform of the communication device 5 is adjusted only by the same amount, and the input waveform of the communication device 5 does not change. Accordingly, by appropriately determining an input threshold (threshold for discriminating between "0" and "1") for the input signal data of the communication device 5, the reception performance is no longer degraded.

[0092] According to the present embodiment, the communication device 5 first transmits the training pattern to the receiving unit 13 of the communication device 4 via the transmission line 6, and the DFE processing unit 16 of the communication device 4 performs distortion compensation. At this time, the DFE processing unit 16 converges the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters (the first feedforward filter FF1 and the first feedback filter FB1) to appropriately compensate for the distortion occurring on the transmission line 6. This configuration allows the digital data Vout_D received by the communication device 4 to be substantially equal to the digital data transmitted from the communication device 5.

[0093] The weighting circuit 8 uses all the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] converged by the DFE processing unit 16 as the filter constants of the second feedforward filter FF2 and the second feedback filter FB2.

[0094] Subsequently, the communication device 4 corrects the distortion in advance and transmits the data. Accordingly, even if the circuit size of the communication device 5 of the drive circuit 2 is limited and the communication device 5 is to be limited to a circuit scale smaller than that of the communication device 4 of the ECU 1, distortion compensation can be appropriately performed on the communication signals transmitted between the communication devices 4 and 5.

[0095] The above-described configuration eliminates the need to provide a distortion compensation circuit in the drive circuit 2 that receives the high-capacity data. It is sufficient to provide only a transmission circuit for the training pattern in the drive circuit 2. This further eliminates the need to provide another communication circuit for returning the reception result of the test pattern. (Second embodiment)

[0096] A second embodiment is described below with reference to the Fig. 13 and Fig. 14. The above-described embodiment shows a configuration in which the ratio between the respective numbers of filter taps of the first and second feedforward filters FF1 and FF2 and the ratio between the respective numbers of filter taps of the first and second feedback filters FB1 and FF2 satisfy the relationships n1 = k1 and n2 = k2 in the DFE processing unit 16 and the weighting circuit 8. However, the ratios between the numbers of taps may be different, and the present invention specifically shows an example in which the filter taps satisfy the relationships k1 < n1 and k2 < n2, which are considered desirable.

[0097] The DFE processing unit 16 determines the filter constants upon receiving the training sample. Consequently, a highly accurate calculation is required to approximate the filter constants. Accordingly, filters with a relatively high number of filter branches n1 and n2 can be used, as appropriate.

[0098] The weighting circuit 8 uses only the filter constants determined in the DFE processing unit 16 and does not concern itself with convergence. Accordingly, the numbers of filter branches k1 and k2 can be smaller than the numbers of filter branches n1 and n2, respectively. Consequently, if the ratios between the numbers of filter branches are determined to satisfy, for example, k1 < n1 and / or k2 < n2, the circuit scale can be further reduced. In this case, the circuit layout area in the semiconductor integrated circuit can be reduced.

[0099] If k1 < n1 is satisfied, the multipliers TMu0a to TMuk1a of the second feedforward filter FF2 are provided with the same multiplication coefficients h1[0] to h1[n1] of the first feedforward filter FF1, without any change.

[0100] If k2 < n2 is satisfied, the multipliers TMu0b to TMuk2b of the second feedback filter FB2 are provided with the same multiplication coefficients h2[0] to h2[n2] of the first feedback filter FB1, without any change.

[0101] The weighting circuit 8 must be provided with the number of filter branches that can maintain minimum operation. Fig. Figure 13 shows a branch length tuning function with each of the variable arrows. It is, as in Fig. 13, it may also be possible to limit the section of a second feedforward filter FF2a and / or a second feedback filter FB2a that is in use and to skip the remaining sections.

[0102] The above configuration can stop the operation of some elements in the second feedforward filter FF2a and / or the second feedback filter FB2a and reduce power consumption. Consequently, with the digital filters FF2a and FB2a each having the branch length adjustment function, power consumption can be effectively reduced. Here, the digital filters FF2a and FB2a serve as a second digital filter unit.

[0103] Furthermore, it is sufficient for the weighting circuit 8 to clarify a specific S / N as a communication quality requirement. Consequently, in the weighting circuit 8, the number of effective bits and the accuracy can be further reduced compared to those of the filter constants or the calculation accuracy in the DFE processing unit 16.

[0104] The second feedforward filter FF2a may be configured such that the numbers of digits in the data (such as the numbers of digits of effective bits in a binary system) of the coefficients h2[0] to h2[n2] are less than the numbers of digits in the data (such as the numbers of digits of effective bits in a binary system) of the coefficients h1[0] to h1[n2] of the first feedforward filter FF1.

[0105] When the filter constant holding units 12a and 8a hold the filter constants such as digital binary values, the multipliers TMu0b to TMuk2b of the second feedforward filter FF2 are provided with only the effective digits of the higher-order bits of the same multiplication coefficients h1[0] to h1[n1] of the first feedforward filter FF1 held in the filter constant holding unit 12a.

[0106] Consequently, for the same reasons as described above, the second feedback filter FB2a may also be configured such that the numbers of digits in the data (such as the numbers of digits of effective bits) of the coefficients h2[0] to h2[k2] are less than the numbers of digits in the data (such as the numbers of digits of effective bits) of the coefficients h2[0] to h2[n2] of the first feedback filter FB1.

[0107] In such a case, the multipliers TMu0b to TMuk2b of the second feedback filter FB2a are provided with only the effective positions of the higher-order bits of the same multiplication coefficients h2[0] to h2[n2] of the first feedback filter FB1. Even in such a case, functions and effects similar to those in the above-described embodiment can be achieved.

[0108] The transmission line 6 has a transmission characteristic that changes under the influence of the transmission quality of the cable or the like. For example, the transmission characteristic of a single-pulse waveform W10 changes as shown in the transmission characteristic of the Fig. 14, variously into a waveform W11, a waveform W12, or the like, as examples. The transmission characteristic of waveform W12 is inferior to the transmission characteristic of waveform W11 and exerts a greater influence on a subsequent signal. Consequently, digital filters FF2a and FB2a, each having a larger number of filter branches, are required to maximally eliminate the influence of the transmission line 6.

[0109] For example, when the communication device 4 is included in a semiconductor integrated circuit (such as an IC or LSI), the same communication device 4 is preferably used even if the characteristics of the transmission line 6 have been changed due to cable replacement or the like. Taking this point into account, the DFE processing unit 16 can be appropriately configured by preparing the number of filter taps that allow the transmission line 6 to communicate under the worst conditions in each of the digital filters FF2a and FB2a.

[0110] In this case, the number of filter branches to be prepared in each of the digital filters FF2a and FB2a can be determined based on a characteristic simulation, experiment, or the like under the worst conditions (such as a transmission line with the transfer characteristic of the waveform W12 in the Fig. 14). This is because the filter constants of the unused branches tend toward zero.

[0111] When it is known in advance that the communication devices 4 and 5 perform communication using the transmission line 6 having a transmission characteristic of relatively high quality (of, for example, the waveform W11), although the number of filter branches is reduced to be less than the number of filter branches determined under the worst conditions as described above, the communication quality can be maintained.

[0112] That is, in preparation for such a case, the DFE processing unit 16 may be designed to use the second feedforward filter FF2a and / or the second feedback filter FB2a, which, as shown in Fig. 13, each having a tap length adjustment function. This can reduce power consumption by stopping the operation of some of the elements of the second feedforward filter FF2a and / or the second feedback filter FB2a.

[0113] According to the present embodiment, the communication device 4 uses some of the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] converged by the DFE processing unit 16 as the filter constants of the digital filters FF2 and FB2 of the weighting circuit 8. The communication device 4 corrects the distortion in advance and transmits the signal. Also with this configuration, appropriate distortion compensation can be performed with respect to the communication between the communication devices 4 and 5. Furthermore, the circuit scale can be reduced. In addition, since the weighting circuit 8 operates using only a part of the digital filters FF2 and FB2, the power consumption of the circuit can be reduced. (Third embodiment)

[0114] A third embodiment is described below with reference to Fig. 15 to 18. The third embodiment shows a bus connection form in the case where a CAN (Controller Area Network) is applied to a vehicle LAN (vehicle-mounted LAN).

[0115] The CAN 6a forms the transmission line 6 and is mounted as the vehicle LAN (Local Area Network). The CAN 6a is constructed of a pair of cables. Several ECUs 1a to 1z (such as ECU_A to ECU_Z) are connected as shown in Fig. 15, connected to the CAN 6a. The plurality of ECUs 1a to 1z are distributed in a vehicle. Accordingly, the CAN 6a, as shown in Fig. 16, also have a Y-branching path 100. On the Fig. 15 shown CAN 6a can be used to suppress the reflection of a signal, as in Fig. 17, terminating resistors (termination resistors) 101 may be arranged at the end sections of the CAN 6a.

[0116] In the above case, for example, when the predetermined ECU 1a (such as the ECU_A) connected to the CAN 6a sends a pulse signal to another ECU 1b (such as the ECU_B), the pulse signal is received by the ECU 1b but also transmitted on another line of the CAN 6a (see arrow Y0).

[0117] The termination resistors 101 are connected to the terminal ends of the CAN 6a. Consequently, the energy of the pulse signal can be dissipated by the termination resistors 101 in such a way that a reflection component of the signal is less likely to be generated (see arrow Y0a). Consequently, the signal component on the CAN 6a is less likely to be distorted.

[0118] In the CAN 6a with the Y-branch path 100, the terminating resistors 101 can be arranged as in Fig. 16, should also be provided at all of the terminal ends. If, as shown in Fig. 16, two branching paths are provided, the terminating resistor 101, as shown in Fig. 18, preferably provided at the terminal end of one of the branches and the terminating resistor 101 is not provided at the terminal end of the other branch (see reference numeral 101a).

[0119] This is because, in the case of the branch line in the Fig. 18, impedance matching between the line impedance of the CAN 6a and the terminating resistor 101 can be more easily achieved and the signal amplitude can be more easily increased if the terminating resistors 101 are provided at some of the connection ends than if the terminating resistors 101 are provided at all of the connection ends.

[0120] In the case that the CAN 6a has the Y-branch path 100, as in Fig. 18, for example, when the ECU 1a sends a pulse signal to another ECU 1b, the pulse signal is received by the other ECU 1b, but also transmitted to another path on the CAN 6a (see arrow Y0).

[0121] At this time, the pulse signal reaches the Y-branch path 100. However, an impedance mismatch is likely to occur on the Y-branch path 100. On the Y-branch path 100, a reflection wave exists, which is reflected on the entrance path along with the pulse signals traveling in both branch directions Y1 and Y2 (see arrow Y3).

[0122] Furthermore, since the terminating resistor 101 is connected to one of the terminal ends of the CAN 6a, a reflection component is less likely to be generated in the terminating resistor 101. Furthermore, since the terminating resistor 101 is not connected to the other terminal end, the signal that has reached the other terminal end is reflected from the terminal end (see arrow Y4). Since another ECU 1b receives such a reflection signal, the received signal received by the other ECU 1b has a distorted waveform different from the transmission waveform from the ECU 1a.

[0123] In the example of Fig. 16 and Fig. Figure 18 shows only one example of a Y-branch. In an actual situation, with recent advances in vehicle control, CAN 6a is widely available throughout the vehicle, and the number of ECUs 1a to 1z connected to CAN 6a is increasing year by year. Accordingly, if CAN 6a has a branch line or an undetermined line, significant waveform distortion is likely to occur in the reflected signals.

[0124] In such a case, if the DFE processing unit 16 and the weighting circuit 8, each described in the above embodiments, are included in each of the ECUs 1a to 1z, and each of the ECUs 1a to 1z holds the filter constants of the digital filters FF2 and FB2 for the corresponding communication partner, the distortion can be compensated.

[0125] The configuration described above may also be provided. In an actual situation, an ECU with a limited circuit scale or size is also present. In some cases, the ECU may not internally incorporate the DFE processing unit 16 and the weighting circuit 8.

[0126] In such a case, among the large number of ECUs 1a to 1z connected to the CAN 6a, at least one ECU 1a (such as the ECU_A) may appropriately include the DFE processing unit 16 and the weighting circuit 8, respectively shown in the above-described embodiments. At this time, it is desirable to provide the DFE processing unit 16 and the weighting circuit 8 in a communication node that transmits particularly high-capacity data.

[0127] Before transmission processing, in which one ECU 1a transmits the normal data to another ECU 1b, the other ECU 1b transmits the training pattern to the one ECU 1a, and the one ECU 1a converges the filter constants of the digital filters FF1 and FB1 of the DFE processing unit 16. The one ECU 1a can appropriately use the converged filter constants as the filter constants of the digital filters FF2 and FB2 in the weighting circuit 8.

[0128] In such a case, no matter which signal transmission path (such as a reflection unit such as the branch path 100 or the terminal portion without the terminating resistor 101) is included on the transmission line 6 arranged between the ECU 1a and another ECU (such as the ECU 1b: ECU_B), by determining the filter constants in accordance with the signal transmission path, appropriate filter constants can be set for the digital filters FF2 and FB2 in the weighting circuit 8.

[0129] Herein, the "other ECU" may be provided by any of the ECUs (such as ECU_C to ECU_Z in the above-described example) connected to the CAN 6a. At this time, the ECU 1a receives the training patterns from various other ECUs 1b to 1z and converges / calculates the filter constants of the digital filters FF2 and FB2 in accordance with each of the other ECUs 1b to 1z with which the ECU 1a can communicate. Fig. 19 shows a matrix as an example of the filter constants obtained from the ECU 1a.

[0130] The ECU 1a sets the filter constants in the embedded weighting circuit 8. By performing the distortion compensation in advance using the weighting circuit 8, the ECU 1a can excellently perform communication processing on the normal data between the ECU 1a and at least one other ECU 1b to 1z (such as the ECU_B, ECU_C, ECU_D, ..., and ECU_Z).

[0131] According to the present embodiment, even when the communication processing is performed using the CAN 6a or the like, effects similar to those in the above-described embodiments can be produced.

[0132] According to the present embodiment, when three or more than three ECUs 1a to 1z are connected to, for example, the CAN 6a or the like, if one ECU 1a (such as the ECU_A) has the DFE processing unit 16 and the weighting circuit 8, the one ECU 1a can excellently perform communication with the remaining ECUs 1b to 1z while compensating for the distortion of a signal. (Fourth embodiment)

[0133] A fourth embodiment is described below with reference to Fig. 20 to 23. The fourth embodiment shows a configuration in which a CAN FD (Flexible Data Rate) protocol is applied to the communication.

[0134] Waveform distortion becomes more noticeable as the data rate of communication processing between the multiple ECUs 1a to 1z (multiple communication nodes) increases. Currently, in the technical field of, for example, in-vehicle devices, the introduction of a CAN FD protocol is being considered to further increase the data rate of CAN 6a.

[0135] In the CAN-FD protocol, as in the frame format of the CAN-FD protocol in the Fig. 20, a data rate in the interval of a CAN FD arbitration phase is not changed from that of the conventional CAN.

[0136] However, in the interval of a CAN FD data phase with a data field, the data rate is, as in Fig. 21, the maximum communication data rate can be increased by 4 Mbps. This can improve the overall communication data rate without degrading arbitration performance among multiple ECUs. The specification of a CAN FD frame header is designed to ignore received data among frames except for a receiving node (ID), which is a communication destination.

[0137] Accordingly, at a communication node different from the communication destination receiving node, a waveform changes under the influence of the distortion transmitted over CAN 6a, and the data is ignored even if it enters a state where erroneous data is received. Consequently, using the CAN FD frame, high-speed transmission can be performed without causing erroneous operation.

[0138] One of the purposes of using the CAN-FD protocol is program writing processing performed in an ECU. A program rewriting device 102 is, as shown in Fig. 22, connectable to the CAN 6a via a programming cable 103, and can transfer a program at high speed to a program rewriting target ECU (such as the ECU 1a) using the CAN FD frame.

[0139] Since the performance of the ECU needs to be improved as needed, the program embedded in the ECU is frequently updated. Due to cost considerations or the like, the ECU is rarely intentionally replaced during a program update. It is also possible to provide the DFE circuit 12 (DFE processing unit 16) and the weighting circuit 8 in all the ECUs expected to perform the above-described update processing. However, this method is of little use.

[0140] Accordingly, in the present embodiment, at least the program rewriting device 102 includes the above-described DFE circuit 12 and the above-described weighting circuit 8. The program rewriting device 102 is used only temporarily during production, testing, such as a vehicle inspection, or the like. In most cases, the program rewriting device 102 is not mounted in a vehicle as a final product.

[0141] As a result, even if the DFE circuit 12 and the weighting circuit 8 are mounted in the program rewriting device 102, it is sufficient to provide a circuit that transmits the above-described training pattern in each of the ECUs 1a to 1z, and it is not necessary to provide an additional dedicated circuit in each of the ECUs 1a to 1z.

[0142] The above-described configuration can prevent an increase in the number of parts of each of the ECUs 1a to 1z mounted in the vehicle main body. Consequently, high-speed communication processing using the CAN-FD protocol can be performed without providing the DFE circuit 12 and the weighting circuit 8 in each of the ECUs, which must perform update processing.

[0143] When the program rewriting device 102 and the vehicle ECU (such as the ECU 1b) perform high-capacity data communication using the CAN-FD protocol, the data transmission speed is higher than a data transmission speed between the plurality of ECUs (such as between the ECUs 1b and 1c) that do not use the CAN-FD protocol.

[0144] In the present embodiment, high-speed communication processing using the CAN-FD is described as an example. Alternatively, the communication processing described in the present embodiment may be used not only for the CAN-FD but also applicable to a pair of communication nodes, as explained in the following method. When a pair of communication nodes is freed from the influence of waveform distortion in low-speed communication based on a different communication standard, the communication processing described in the present embodiment may be applied to high-speed data transmission between the paired communication nodes.At this time, in the transmitting node, the weighting circuit 8 can appropriately compensate the distortion to be caused by the cable in advance, after which it starts the data transmission.

[0145] The following describes a processing flow for determining the pair of communication nodes (communication device) during low-speed communication processing and then executing high-speed data transmission between the paired communication nodes that are determined.

[0146] Fig. 23 shows an example in which, for example, the program rewriting device 102 (communication node A) has the configuration of the communication device 4, and each of the other ECUs 1b to 1z (the communication node B, the communication node C, ..., and the communication node Z) has the configuration of the communication device 5.

[0147] In the notation of the Fig. 23, processing corresponding to "Tx from Node A" shows the processing executed by the transmitting unit 10 of the communication device 4 of the program rewriting device 102, and processing corresponding to "Rx from Node A" shows the processing executed by the receiving unit 13 of the communication device 4 of the program rewriting device 102. Likewise, processing corresponding to "Tx from Node B" shows the processing executed by the transmitting unit 23 of the communication device 5 of the ECU 1b, and processing corresponding to "Rx from Node B" shows the processing executed by the receiving unit 24 of the communication device 5 of the ECU 1b. Similarly, processing corresponding to "Tx from Node C" shows the processing executed by the transmitting unit 23 of the communication device 5 of the ECU 1c, and processing corresponding to "Rx from Node C" shows the processing executed by the receiving unit 24 of the communication device 5 of the ECU 1c.

[0148] Fig. 23 shows an example in which the program rewriting device 102 performs training between the program rewriting device 102 and one of the ECUs 1b to 1z during low-speed communication processing and then performs high-speed data transmission. The subsequent processing performed by the rewriting device 102 can also be changed to a form performed by another device, such as the ECU 1a or the like. Fig. 23 shows the processing shown in a double rectangle, low-speed communication processing, and shows the processing shown in a single rectangle, high-speed communication processing.

[0149] During power-on, restart, relearning, or the like, when training is started between the rewriting device 102 serving as a master and the ECUs 1b to 1z each serving as a slave, the rewriting device 102 initiates a low-speed communication mode with the ECU 1b as a communication partner node, and the rewriting device 102 sends a training request command (T1).

[0150] When receiving the training request command, the ECU 1b recognizes that the training request has reached the node of the ECU 1b (training matched) because the training request is issued to the ECU 1b.

[0151] Another ECU 1c also receives the training request, but since the request is issued to the ECU 1b, it switches to a mode in which the input data is ignored during training of the ECU 1b from the time the ECU 1c receives the request.

[0152] The ECU 1b switches to a low-speed communication mode and transmits a training start reception command (T2: Training Start). Subsequently, the rewriting device 102 receives the training start reception command (Receive Training Start). The ECU 1b switches to a high-speed communication mode, sets the training start time in the header, and transmits the training data at high speed only for a predetermined period of time (training pattern).

[0153] The rewriting device 102 identifies the time at which the transmission of the training data was started based on the training start header received from the ECU 1b, and receives the training data for a predetermined period of time from the time at which the training was started.

[0154] The rewriting device 102 performs training processing while receiving the training data. In the training processing, the filter constants set in the first feedforward filter FF1 and the first feedback filter FB1 are converged such that the data items before and after the data slicer S1 in the DFE processing unit 16 are the same.

[0155] At this time, the rewriting device 102 causes the filter constant holding unit 12a to hold the converged filter constants. The rewriting device 102 and the ECUs 1c and the like other than the ECU 1b check the header of the frame being communicated, recognize that the training period is present, and continue to ignore the input data during the training period (ignoring period).

[0156] When the convergence processing of the filter constants is completed, the rewriting device 102 holds the converged filter constants as filter constants corresponding to the ECU 1b (node B) in the filter constant holding unit 12a. The rewriting device 102 executes training processing in the ECU 1c as the communication partner node for the calculation processing of the filter constants between the rewriting device 102 and the ECU 1b. That is, the rewriting device 102 initiates low-speed communication with the ECU 1c (node C) as a transmission destination node and sends a training request command (T3).

[0157] Upon receiving the training request command, the ECU 1c detects that the training request has reached the node of the ECU 1c (training matched) because the training request has been issued to the ECU 1c.

[0158] The ECU 1c switches to the low-speed communication mode and transmits the training start reception command (T4: Training Start). Subsequently, the rewriting device 102 receives the training start reception command (Receive Training Start). The ECU 1c switches to a high-speed communication mode, determines the start of training in the header, and transmits the training data at high speed only for a predetermined period (training pattern).

[0159] The rewriting device 102 identifies the time at which the transmission of the training data was started based on the training start header received from the ECU 1c, and receives the training data for a predetermined period from the time at which the training was started.

[0160] The rewriting device 102 performs training processing while receiving the training data. During training processing, the filter constants in the first feedforward filter FF1 and the first feedback filter FB1 are converged such that the data items before and after the data slicer S1 in the DFE processing unit 12 are the same. The rewriting device 102 causes the filter constant holding unit 12a to hold the converged filter constants.

[0161] The rewriting device 102 repeats the above processing with the other predetermined communication nodes (such as the ECUs 1d to 1z) that require training processing as the communication partner nodes. This allows the rewriting device 102 to acquire the filter constants to be set with respect to each communication node requiring training processing.

[0162] The rewriting device 102 determines the start of sending the normal data to the ECU 1b in the header during low-speed communication and notifies the ECU 1b. Then, the rewriting device 102 sends the normal data through high-speed communication. At this time, during a high-speed communication period, the rewriting device 102 inputs the filter constants corresponding to the ECU 1b (node B) to the digital filters FF2 and FB2 in the weighting circuit 8, and the rewriting device 102 further sends the normal data through the weighting circuit 8 (T5: node B normal).

[0163] The ECU 1b can recognize, by referring to the header during low-speed communication, that the data communication processing is the high-speed transmission processing of the normal data to the node of the ECU 1b (receive normal start). Accordingly, the ECU 1b receives the data via high-speed communication. At this time, the transmission signal from the rewriting device 102 has been processed in advance in the weighting circuit 8. Consequently, even if waveform distortion occurs on the CAN 6a, the ECU 1b can receive the signal with reduced distortion once the transmission signal has arrived.

[0164] ECUs 1c and the like other than ECU 1b can recognize through the header during low-speed communication that the data communication processing is not transmission processing to the nodes of ECUs 1c and the like. Accordingly, ECUs 1c and the like ignore data communication processing during the high-speed communication period described above (Ignore Start).

[0165] Since the rewriting device 102 transmits the normal data at a high speed using the filter constants suitable for the ECU 1b, when the ECUs 1c and the like receive the normal communication data during high-speed communication, it can be concluded that the ECUs 1c and the like are receiving completely unsuitable data. Since the data communication processing is ignored during the high-speed communication period, no problem arises.

[0166] In another case, when the rewriting device 102 performs high-speed communication, the rewriting device 102 determines filter constants (filter constants corresponding to nodes B and C to Z) in accordance with the communication partner nodes, and the rewriting device 102 transmits data at a high speed. The rewriting device 102 performs appropriate distortion compensation processing on each communication node of the other plurality of ECUs 1b to 1z and high-speed data transmission. This allows the rewriting device 102 to transmit data at high speed to the other ECUs 1b and the like. It should be noted that the communication protocol is applicable in a modified form as needed.

[0167] According to the present embodiment, even when high-speed communication processing is performed using the CAN-FD protocol, the same effect as in the above-described embodiments is achieved. When the program rewriting device 102 includes the DFE circuit 12 and the weighting circuit 8, high-speed communication processing can be performed while compensating for the distortion of a transmission signal without providing an additional distortion compensation circuit in each of the ECUs 1b to 1z as the program rewriting targets.

[0168] Furthermore, according to the present embodiment, the pair of communication nodes between which communication processing is performed during low-speed communication processing is determined, and then high-speed data transmission is performed between the determined pair of communication nodes (the rewriting device 102 and the ECUs 1b to 1z) in a state where appropriate filter constants are set in the weighting circuit 8 of the transmitting communication node. Consequently, when data reaches one of the ECUs 1b to 1z as a communication partner during high-speed data transmission, the one of the ECUs 1b to 1z as the communication partner can receive the signal with reduced distortion. (Fifth embodiment)

[0169] A fifth embodiment is described below with reference to the Fig. 24. In the present embodiment, a vehicle network (vehicle-based network) is connected to a higher-order network via a gateway.

[0170] A Gateway ECU 1gw is, as in Fig. 24, is connected to the CAN 6a in the network, and the gateway ECU 1gw is connected to a higher-order network N that is higher than the CAN 6a. The higher-order network may be a network having at least a part provided outside the vehicle, such as a wireless communication network such as a cellular network, or a short- or medium-range wireless communication network, a wired communication network such as a telephone network, or various local area networks such as a wired LAN and a wireless LAN. The gateway ECU 1gw has a relay function (gateway function) that connects the higher-order network N and the CAN 6a.

[0171] The program rewriting device 102 described in the fourth embodiment is connected to the higher-order network N via a port different from the port connected to the bus 6a. The program rewriting device 102 can communicate with each of the ECUs 1a to 1z via the higher-order network and the gateway ECU 1gw. Such a communication form also produces the same function and effect as in the above-described embodiments.

[0172] If any data is transmitted at a high speed via the higher-order network and the gateway ECU 1gw, the data can also be used for an application other than programming.

[0173] According to the present embodiment, even if the CAN 6a is connected to the higher-order network N via the gateway ECU 1gw, the same function and effect as in the above-described embodiments can be brought about.

[0174] In the fourth embodiment, the program rewriting processing application has been described. However, even if a network such as the CAN 6a described above is connected to the higher-order network N, the program rewriting device 102 can be used for high-speed communication processing for an application other than the program rewriting processing application. (Sixth Embodiment)

[0175] A sixth embodiment is described below with reference to the Fig. 25A to 28B. One of the characteristic features of the sixth embodiment is that the DFE circuit 12 of the communication device (corresponding to the first communication node) 4 receives the training pattern at a sampling frequency that divides each of the bits in the training pattern into a plurality of subbits having the same consecutive data values, and converges the filter constants of the digital filters FF1 and FB1 to converge errors in the subbits and allow the training pattern to be received.Another of the characteristic features of the sixth embodiment is such that the transmitting unit 10 of the communication device 4 performs distortion compensation on the normal data in units of subbits by using the converged filter constants of the digital filters FF1 and FB1 as at least parts of the filter constants of the digital filters FF2 and FB2 of the weighting circuit 8, and transmits the normal data.

[0176] In the first embodiment, for example, the method is described in which the communication device 4 of the ECU 1 performs predistortion processing using the weighting circuit 8. At this time, the communication device 4 of the ECU 1 operates in response to the clock signal generated by the clock generation unit 17, and the communication device 4 outputs a signal level in accordance with the operating frequency determined for each of the bits.

[0177] In this case, the DFE circuit 12 corrects waveform distortion at a point in an eye diagram. Consequently, only the distortion at that point is accurately corrected, and at each of the other points in the eye diagram, a distortion detection value different from the actual distortion detection value is used as a proxy, causing an error. The inventors of the present invention have verified the amount of the error.

[0178] First, the simulation data to be sent is in the Fig. 25A. Assuming that the simulation data to be transmitted is transmitted via the transmission line 6 without applying the predistortion method shown in the above-described embodiments, the data receiver, as shown in the simulation waveform (eye diagram) at the receiver in the Fig. 25B, is affected by the transmission line 6. The eyes are not open, as shown in this eye diagram, and erroneous data reception increases.

[0179] On the other hand, it has been confirmed that if it is assumed that the weighting circuit 8 of the communication device 4 performs pre-distortion processing as shown in the Fig. 26A using the method in the first embodiment, and sends the signal after processing to the receiving communication device 5 via the transmission line 6 described above, the receiving communication device 5 can receive data in a state where the eyes are opened.

[0180] If you compare the Fig. 26B with the Fig. 25B, it is evident that the eyes have improved significantly. It should be noted that in the simulations shown in the Fig. 25B and Fig. 26B, analyses were performed using signal waveforms in which the points at which predistortion waveforms change change linearly. This is because the predistortion waveforms are determined in accordance with the simulations. It should be noted that, in an actual situation, the points at which the predistortion waveforms change change more smoothly over time.

[0181] In the eye diagram of the Fig. 26B, the waveform distortion has been periodically corrected at correction times t1 and t2. Accordingly, at these periodic distortion correction times t1 and t2, all of the signal values (voltage values) are substantially the same. Even in this case, reception characteristics can be sufficiently improved, but the time durations AW1 in the transition regions between adjacent bits are likely to be increased.

[0182] Accordingly, the present embodiment shows a form in which the communication device 4 operates at a higher operating frequency to enable reductions in the time periods AW2 in the transition regions between the adjacent bits.

[0183] The present embodiment also applies the concept of multiple (= m ≥ 2) subbits into which one bit is divided. For example, consider the case where the communication device 5 serving as a slave, as shown in Fig. 27A, sends a 5-bit data string “01001” as the training pattern to the communication device 4 serving as a master.

[0184] At this time, the communication device 4 receives the 5-bit data string "01001" assuming that each of the bits in the 5-bit data string has, for example, two (=m) subbits. That is, when a frequency corresponding to the data rate in the above-described embodiments is a certain frequency f1, the receiving unit 13 (the DFE circuit 12 and the data receiving unit 7b) of the communication device 4 of the ECU 1, in the present embodiment, receives the 5-bit data string using a frequency f2 (such as twice (=m times) the frequency) exceeding the frequency f1 as the sampling frequency. Specifically, the control circuit 7 outputs a control signal to the clock generation unit 17 to control the frequency of the clock signal generated by the clock generation unit 17 to a frequency corresponding to f2 / f1 times the frequency in the above-described embodiments.Consequently, the clock generation unit 17 outputs the clock signal with the frequency f2 to the control circuit 7 and to the receiving unit 13 (such as the DFE circuit 12 or the data receiving unit 7b). At this time, the receiving unit 13 of the communication device 4 operates at the frequency f2, which exceeds the frequency f1. This allows the receiving unit 13 to receive data using the frequency f2 as the sampling frequency.

[0185] The following description assumes that the frequency f2 is twice the frequency f1, but the multiple is not limited to 2.

[0186] At this time, the DFE circuit 12 of the communication device 4 calculates the coefficients h1[0] to h1[n1] of the first feedforward filter FF1 and the filter constants h2[0] to h2[n2] of the first feedback filter FB1 with the frequency f2 which is twice (= m times) the frequency f1.

[0187] This results in the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters FF1 and FB1 of the DFE circuit 12, as shown in Fig. 27B, can be converged such that, hypothetically assuming that the leading first bit "0" is "00", the second bit "1" is "11", the third bit "0" is "00", the fourth bit "0" is "00", and the fifth bit "1" is "11", the two (= m) subbits in each of the first to fifth bits can be received in an overlapping relationship. That is, the receiving communication device 4 can receive the training pattern in which each of the bits is divided into the m subbits with the same consecutive values.

[0188] After the DFE circuit 12 of the communication device 4 has executed the processing and determined the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters FF1 and FB1 serving as a first digital filter unit for the filter constant holding unit 12a, the transmission unit 14 transmits the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] of the digital filters FF1 and FB1 to the filter constant holding unit 8a.

[0189] By using at least some or all of the coefficients h1[0] to h1[n1] and h2[0] to h2[n2] transmitted as the coefficients h1[0] to h1[k1] and h2[0] to h2[k2] of the digital filters FF2 and FB2 of the weighting circuit 8 to the filter constant holding unit 8a, the transmitting unit 10 can perform predistortion processing and distortion compensation on the normal data and transmit the normal data. Here, the digital filters FF2 and FB2 of the weighting circuit 8 serve as a second digital filter unit. At this time, the transmitting unit 10 performs predistortion processing in units of subbits using the weighting circuit 8, and the transmitting unit 10 transmits the data.

[0190] That is, if the communication device 4 has the Fig. 27A, hypothetically assuming that the bit sequence "01001" is "0011000011", the transmitting unit 10 performs pre-emphasis processing on each of the bits in the data in units of m consecutive sub-bits. Specifically, the clock generation unit 17 outputs the clock signal having the above-described frequency f2 to the transmitting unit 10 (such as the data transmitting unit 7a, the weighting circuit 8, or a D / A converter (not shown)). Consequently, the transmitting unit 10 of the communication device 4 of the ECU 1 operates at the same frequency f2 as the receiving unit 13. This allows the transmitting unit 10 to perform pre-emphasis processing on the data in units of m consecutive sub-bits and transmit the normal data. In this case, the deterioration of jitter can be suppressed and erroneous reception of the data by the communication device 5 can be maximally suppressed.

[0191] The result of the verification by the inventors using the simulations is described below. Fig. 28A shows a simulation data waveform to be transmitted. Fig. Figure 28B schematically shows an eye diagram when simulation data is received. Signal values (voltage values) are correct, as in the Fig. 28A and Fig. 28B, at each of the timings t11, t12, t21, and t22, the signal values (voltages) match in accordance with the frequency f2 for transmitting / receiving sub-bit data. This is because the timings t11, t12, t21, and t22 at which the signal values (voltages) match serve as distortion correction timings.

[0192] In the Fig. 28B, times t11 and t12 are times for sampling subbits having the same data values (voltage values), and times t21 and t22 are times for sampling subbits having the same data values (voltage values).

[0193] At this time, the time interval between the distortion correction times t12 and t22 is reduced to enable a reduction in signal change time during the period from the distortion correction time t12 corresponding to a particular bit to the distortion correction time t21 corresponding to the following bit. This allows the time durations AW2 in the transition regions between the adjacent bits to be reduced.

[0194] Furthermore, the time interval between the distortion correction times t11 and t12 is reduced to enable a reduction in a signal change time during the period from the distortion correction time t11 corresponding to a subbit with a certain data value to the distortion correction time t12 corresponding to the following subbit with the same data value. As a result, the voltage amplitude between these subbits can be reduced. This can increase a voltage margin M2 between these subbits. Consequently, the deterioration of jitter can be suppressed, and erroneous data reception by the communication device 5 can be maximally suppressed. (Seventh Embodiment)

[0195] A seventh embodiment is described below with reference to the Fig. 30A to 31B. One of the characteristic features of the seventh embodiment is such that the number of subbits into which a single bit is divided in the sixth embodiment is set to an odd number (preferably, for example, 3).

[0196] When the communication device 5 as a slave uses a typical receiving circuit, a time point midway between the two adjacent transition areas is used as a data sampling time point in most cases.

[0197] For example, if each individual bit is divided into several subbits and the number of divided subbits is set to an even number (such as 2), and the time point in the middle between two adjacent transition areas R is used as the data sampling time point, as shown in Fig. 28B, the times t1a and t2a with the small voltage margins M2 are essentially used as data sampling times.

[0198] Also at these times t1a and t2a, as in Fig. 28B, which ensures sufficient voltage margins M2. Accordingly, the number of divided subbits can also be set to an even number, but the number of divided subbits is preferably set to an odd number. When the number of divided subbits is an odd number, the operating frequency f2 of the communication device 4 as the master is set to an odd multiple of the frequency f1 of the data rate described above. When one bit is divided into, for example, three subbits, the receiving unit 13 of the communication device 4 as the master performs sampling processing at the frequency f2 corresponding to, for example, three times the frequency f1 and operates. Then, the communication device 4 assumes that one bit corresponds to three subbits and calculates the filter constants of the DFE circuit 12 in units of subbits.

[0199] For example, if the data sequence of the training pattern is as in Fig. 29A, is “1001”, the communication device 4 as the master receives the training pattern as a data sequence of hypothetical sub-bits “111000000111”, as shown in the Fig. 29B. The receiving unit 13 of the communication device 4 converges the filter constants of the DFE circuit 12. Then, the weighting circuit 8 of the communication device 4 transmits the data in units of subbits using the filter constants.

[0200] Fig. For example, Fig. 30A shows simulation data to be sent when the number of divided subbits is 3, and Fig. 30B schematically shows an eye diagram. When the receiving unit 13 operates at the frequency f2 corresponding, for example, to three times the original data rate frequency f1, as shown in the Fig. 30A and Fig. 30B, compared with the time period AW1 (see Fig. 26B) in the transition area when the receiving unit 13 operates at the frequency of the data rate, and the time period AW2 (see Fig. 28B) in the transition area, when the receiving unit 13 operates at a frequency corresponding to twice the data rate, a time period AW3 in the data transition area can be further reduced.

[0201] When the receiving communication device (such as 5) uses a typical receiving circuit, and when substantially middle timings between the two adjacent transition regions R are used as the data sampling timings t1a and t2a, the timings t1a and t2a can basically coincide with the distortion correction timings t12 and t22, and the voltage margin M3 can basically be maximized.

[0202] In simulation, for example, no consideration is given to the influence of external noise or the like. However, if an odd number is used as the number of divided subbits, the voltage margin M3 can be increased. Accordingly, even under the influence of external noise or the like, erroneous reception can be further prevented. This can further improve the reception characteristics. Therefore, from the point of view of timing or signal level, the number of divided subbits is preferably set to an odd number. In the above description, the example where the number of divided subbits is 3 is shown. However, the number of divided subbits can also be an odd number greater than or equal to 5.By setting the number of divided subbits to an odd number greater than or equal to 5, the time duration in the transition region between data sampling times can also be further reduced. This can reduce jitter in the time domain and enable excellent reception.

[0203] Fig. 31A shows a simulation data waveform to be transmitted when the number of divided subbits is 5. Fig. Figure 31B shows a schematic of an eye diagram. Fig. 31B shows the distortion correction times t12 to t15 and t21 to t25. At times t12 to t15, the data values are the same, and at times t21 to t25, the data values are also the same.

[0204] As the number of divided subbits is increased, the time intervals between the adjacent distortion correction times (such as between t12 and t13 and between t13 and t14) can be increased as shown in the Fig. 31A and Fig. 31B. Specifically, a signal change time during the period from the distortion correction time t15 corresponding to a certain data value to the distortion correction time t21 corresponding to the following data value can be reduced. This allows the time duration AW5 in the transition region between the adjacent bits and jitter in the time domain to be reduced, while enabling excellent reception in the data receiver.

[0205] As in the Fig. 31A and Fig. As shown in Figure 31B, as the number of divided subbits is increased, distortion can be reduced more significantly, and the effect of reducing the voltage amplitude can be enhanced. It should be noted that when the average timings between the transition regions R are t1a and t2a, the voltage margin M5 is substantially consistent with the voltage margins at the distortion correction timings t13 and t23, and the maximum voltage can basically be obtained.

[0206] Furthermore, as the number of divided subbits is increased, the voltage amplitude between the subbits into which the same data is divided can be reduced. Consequently, a voltage margin M15 (see Fig. 31B) in the time domain, when the number of divided subbits is 5, is greater than a voltage margin M13 (see Fig. 30B) in the time domain if the number of divided subbits is 3.

[0207] It should be noted that when the number of divided subbits is set to a value greater than or equal to 5, either an odd number or an even number can achieve substantially the same distortion reduction effects. As the number of divided subbits increases, the operating frequency of the communication device 4 increases, requiring a high-performance circuit. Accordingly, the number of divided subbits can be appropriately determined based on a trade-off between a signal propagation condition on the transmission line 6, the performances of the communication devices 4 and 5, cost, and the like.

[0208] When attempting to satisfy the condition that the number of divided subbits is an odd number greater than 1 while keeping the operating frequency of the communication device 4 low, the control circuit 7 preferably sets the operating frequency of the communication device 4 such that the number of divided subbits is 3. When the influence of distortion in a proceeding signal due to the transmission line 6 is relatively small, the operating frequency is preferably set such that the number of divided subbits is greater than or equal to two or four times. When the influence of distortion in the proceeding signal due to the transmission line 6 is relatively large, the operating frequency is preferably set such that the number of divided subbits is greater than or equal to five times. (Eighth Embodiment)

[0209] An eighth embodiment is described below with reference to the Fig. 32 to 36. The sixth embodiment described above shows that when the number of divided subbits is set to 2, for example, the voltage margins M2 at the middle times t1a and t2a between the transition regions R in the eye diagrams are reduced. This is because, for example, a 2-subbit transmission waveform has a signal component that is twice the frequency component in accordance with the pre-distortion processing and is not included in the original data, in addition to the frequency components inherently included in the original data. The inventors of the present invention have found that when the additional frequency component is removed, the voltage margins can be improved.Accordingly, the eighth embodiment shows a form in which, when normal data to which distortion compensation has been performed in units of subbits is transmitted, a filter 9a-1 that reduces a component in a high frequency region is provided.

[0210] Fig. Figure 32 shows an example of a configuration of a distortion compensation system S2 in analogy to Fig. 1. Herein, the communication device 4 as a master in the Fig. 1 the transmit amplifier 9 at the output of the weighting circuit 8. Accordingly, a communication device 104 uses as a master in the present embodiment, as in Fig. 32, a transmitting amplifier 9a with the filter 9a-1 instead of the transmitting amplifier 9.

[0211] The filter 9a-1 in the transmitting amplifier 9a is provided, for example, as an analog low-pass filter. If the transmitting amplifier 9a is configured in a stage before or after the transmitting amplifier 9, or if the transmitting amplifier 9 has multiple amplification stages, the filter 9a-1 is configured between the multiple amplification stages.

[0212] The cutoff frequency in the high-frequency range of the filter 9a-1 can be suitably set to a Nyquist frequency corresponding to the operating frequency of the DFE circuit 12 to enable the DFE circuit 12 to operate to perform the division into units of m subbits. The type of the filter 9a-1 is not particularly limited. For example, a tertiary Butterworth filter can be suitably used.

[0213] If a simulation is performed using the filter 9a-1 assuming that the number of divided subbits is 2, as in the Fig. 32 is shown, this can be done in the Fig. 33 can be obtained. It should be noted that the simulation result is the result of a simulation under the hypothetical condition that the transmit amplifier 9 and the filter 9a-1 are cascade-connected and all of their input / output impedances are matched. In this case, a frequency component corresponding to twice the data rate is reduced. This allows voltage margins M2a at the middle times t1a and t2a between the transition regions R to be larger than those in the Fig. 28B shown stress margins M2.

[0214] According to the present embodiment, at the data transmission unit, the filter 9a-1 in the transmission amplifier 9 reduces the high-frequency component. Consequently, the voltage margins M2a can be increased, and erroneous reception can be maximally suppressed.

[0215] Furthermore, since the communication device 104 has the filter 9a-1 as the master, the unnecessary frequency component of the signal to be transmitted on the transmission line 6 can be reduced in advance, and an unnecessary radiation component generated as the signal progresses on the transmission line 6 can be reduced.

[0216] It should be noted that the ninth embodiment described below shows a form in which a filter 21a-1 (see Fig. 37) corresponding to the filter 9a-1 in the present embodiment is arranged in the receiving communication device 5. However, when the filter 21a-1 is arranged in the receiver, an additional space for a component should be provided in the receiving communication device 5. For example, when the communication device 5 is a vehicle device, the part / component space in the vehicle device is preferably minimized. In view of this point, the distortion compensation system S2 in the present embodiment achieves an effect that the receiving communication device 5 can be designed more simply than in the ninth embodiment described below.

[0217] The present embodiment above shows the example in which one bit is halved and assumed to be two subbits. However, the same effect can be achieved by dividing one bit into three or more subbits. Fig. Figure 34 shows a simulation result (eye diagram) for the case where a bit is divided into three subbits. Fig. Figure 35 shows a simulation result (eye diagram) for the case where one bit is divided into four subbits. Fig. Figure 36 shows a simulation result (eye diagram) for the case where a bit is divided into five subbits. Fig. 34 to 36 show voltage margins M3a to M5a at the middle times t1a and t2a between each transition region R. The effect of improving the voltage margins M2a to M5a is maximum when one bit is divided into two subbits (M2a) rather than when one bit is divided into three or more than three subbits (M3a to M5a).

[0218] If the number of sub-bits divided is increased, the voltage amplitude between the individual sub-bits into which the data is divided can be reduced more significantly. This allows a voltage margin M15a (see Fig. 31B) in this time range, when the number of divided subbits is 5, is greater than a voltage margin M13a (see Fig. 30B) in this time range if the number of divided subbits is 3.

[0219] Furthermore, the filter 9a-1 can be provided using a Nyquist frequency corresponding to the frequency of the data rate as a cutoff frequency, without assuming one bit as m (multiple) subbits into which the one bit has been divided. In this case, too, the same effects as in the first to fifth embodiments can be achieved in the same way, and the effect of reducing unnecessary radiation from the transmission line 6 can be achieved. (Ninth Embodiment)

[0220] A ninth embodiment is described below with reference to the Fig. 37 to 41. The ninth embodiment shows a form in which the filter 21a-1 is provided at the receiver. Fig. Figure 37 shows an example of a configuration of a distortion compensation system S3 in analogy to the system S in the Fig. 1. The communication device 5 as the slave has, as shown in Fig. 1, the receiving amplifier 21 is located in the receiving unit 24. However, a communication device 105 in the distortion compensation system S3 in the present embodiment uses a receiving amplifier 21a with the additional filter 21a-1 instead of the receiving amplifier 21.

[0221] In the same way as in the filter 9a-1 of the eighth embodiment, the filter 21a-1 in the receiving amplifier 21a can be suitably provided, for example, by an analog low-pass filter. When the filter 21a-1 is configured in the stage before or after the receiving amplifier 21a, or when the receiving amplifier 21a has multiple amplification stages, the filter 21a-1 is configured midway between the multiple amplification stages.

[0222] Also in the present embodiment, the cutoff frequency in the high-frequency range of the filter 21a-1 can be appropriately set to the Nyquist frequency corresponding to the operating frequency of the DFE circuit 12 to enable the DFE circuit 12 to operate to perform division in units of m subbits. The type of the filter 21a-1 is not particularly limited. For example, a tertiary Butterworth filter can be appropriately used.

[0223] If a simulation is performed using the filter 21a-1 assuming that the number of divided subbits is 2, as in the Fig. 37 is shown, this can be done in the Fig. 38 can be obtained. In this case, too, a frequency component corresponding to twice the data rate can be reduced in the same way. This allows the voltage margins M2b at the middle times t1a and t2a between the two transition regions R to be increased.

[0224] It should be noted that the Fig. 38 is essentially different from the eye diagram shown in Fig. 33 is indistinguishable. This is because when the propagation characteristic of the transmission line 6 is Gc(f) and the propagation characteristic of each of the filters 9a-1 and 21a-1 is Glpf(f), either when the configuration ( Fig. 32) is used in the eighth embodiment or when the configuration ( Fig. 37) is used in the ninth embodiment, an overall characteristic Gtotal (f) is described by the following equation and remains unchanged. Accordingly, the same effect can be achieved either through the configuration in the eighth embodiment or the configuration in the ninth embodiment: Gtotal(f)=Gc(f)×Glpf(f)=Glpf(f)×Gc(f)

[0225] According to the present embodiment, the filter 21a-1 reduces the high-frequency range in the receiver. This allows the voltage margins M2b to be increased and erroneous reception to be maximally suppressed.

[0226] The present embodiment above shows the example in which one bit is halved and assumed to be two subbits. However, the same effect can be achieved by dividing one bit into three or more subbits. Fig. Figure 39 shows a simulation result (eye diagram) when one bit is divided into three subbits. Fig. Figure 40 shows a simulation result (eye diagram) when one bit is divided into four subbits. Fig. Figure 41 shows a simulation result (eye diagram) when a bit is divided into five subbits. Fig. 39 to 41 show voltage margins M3b to M5b at the middle times t1a and t2a between the transition regions R. The effect of improving the voltage margins M2b to M5b is maximum when one bit is divided into two subbits (M2b) rather than when one bit is divided into three or more subbits (M3b to M5b).

[0227] If the number of sub-bits divided is increased, the voltage amplitude between the sub-bits into which the same data is divided can be reduced more significantly. This allows a voltage margin M15b (see Fig. 41) in this time range, when the number of divided subbits is 5, is greater than a voltage margin M13b (see Fig. 39) in this time range if the number of divided subbits is 3.

[0228] It is also possible to provide the filter 21a-1 using the Nyquist frequency corresponding to the frequency of the data rate as a cutoff frequency, without assuming one bit as m (multiple) subbits into which one bit has been divided. In this case, too, the same effects as in the first to fifth embodiments can be achieved in the same way. (Tenth Embodiment)

[0229] A tenth embodiment is described below with reference to the Fig. 42 to 45B. The tenth embodiment shows a form configured using an adaptive linear equalizer serving as an equalizer circuit 112 or the like instead of the DFE circuit 12 in the above-described embodiments. Fig. 42, as a replacement for the receiving unit 13 in the communication device (corresponding to the first communication node) 4, includes the equalizer circuit 112 as an equalizer. The equalizer circuit 112 is a block that performs equalization processing for improving waveform distortion. The equalizer circuit 112 includes, as shown in Fig. 43, the A / D conversion unit 15 and an equalizer processing unit 116 that performs adaptive linear equalization processing on the result of the conversion by the A / D conversion unit 15. The equalizer processing unit 116 performs, as shown in Fig. 44A, distortion compensation processing is performed on a digital output signal from the A / D conversion unit 15. The equalizer processing unit 116 includes a first feedforward filter FF101 as a first digital filter unit, a determination unit S101, and a subtractor M101, and is configured with a training pattern holding unit 117 connected to the equalizer processing unit 116.

[0230] In the example of Fig. 44A, the first feedforward filter FF101 performs digital filtering processing (such as an FIR filter) on the digital input signal of the equalizer processing unit 116, and the first feedforward filter FF101 outputs the filtered digital signal to the determining unit S101 and to the positive input of the subtractor M101.

[0231] The first feedforward filter FF101 has, as shown in Fig. 44B, the n1 series-connected 1-clock delay elements D1a to Dn1a, the (n1 + 1) multipliers Mu0a to Mun1 and the adder Aa.

[0232] Each of the delay elements D1a to Dn1a performs delay processing corresponding to one clock in response to the clock (not shown) provided from the control circuit 7. The filter constant holding unit 12a holds the coefficients h1[0] to h1[n1] and the coefficients h1[0] to h1[n1] to the multipliers Mu0a to Mun1a. The multipliers Mu0a to Mun1a of the first feedforward filter FF101 multiply 0 to n1 clock delay data resulting from delay processing using the n1 delay elements D1a to Dn1a by the respective coefficients h1[0] to h1[n1]. Here, the 0-clock delay data represents the input data IN. The adder Aa of the first feedforward filter FF101 sums the respective results of the multiplications by the multipliers Mu0a to Mun1a to generate the output data OUT.

[0233] The negative input of the subtractor M101 is connected as shown in Fig. 44A, an initial training pattern is given as an initial value by the training pattern holding unit 117. The training pattern holding unit 117 stores, for example, a pseudorandom pattern as the initial training pattern.

[0234] The determination unit S101 is a circuit that converts a signal waveform into a data value and provides the conversion result as an output from the equalization processing unit 116. A signal waveform is distorted under the influence of the transmission line 6. The first feedforward filter FF101 serves to restore the distorted waveform into a corrected waveform close to the original signal waveform. The determination unit S101 determines a closest signal level for the corrected waveform. First, the difference from the initial training pattern is output as an error to the control circuit 7. The control circuit 7 adjusts the filter coefficients h1[0] to h1[n1] of the first feedforward filter FF101 to minimize the error, i.e., to correct the distortion.After the tuning has been successful to a certain extent, the control circuit 7 switches a switch SW and the subtractor M1 detects the difference between an output of the first feedforward filter FF101 and the output OUT and the subtractor M1 outputs the difference as an error to the control circuit 7.

[0235] The control circuit 7 compensates for the influence of the distortion that occurred under the influence of the transmission line 6, converts each of the coefficients h1[0] to h1[n1] to be adjusted in the first feedforward filter FF101 to make the error approach 0, and stores the converged coefficients in the filter constant holding unit 12a. Examples of a convergence method for the filter constant of the digital filter include a method using an algorithm such as LMS (Least Mean Square). However, the convergence method is not limited to this method.

[0236] The control circuit 7 converges each of the coefficients h1[0] to h1[n1] to be set in the first feedforward filter FF101 such that the positive and negative inputs of the determination unit S101 are equal to each other. Herein, it is assumed that the convergence is completed when the error (voltage error) between the positive and negative inputs falls below a positive value.

[0237] The Fig. The weighting circuit 108 shown in Figure 45A includes a second feedforward filter FF102 and the filter constant holding unit 8a. Here, the second feedforward filter FF102 is configured to have the same structure as, for example, the first feedforward filter FF101. The weighting circuit 108 differs, as shown in Fig. 45A, functionally from the equalizer circuit 112 and is provided by a circuit obtained by omitting the determination unit S101, the subtractor M1 and the switch SW from the equalizer circuit 112.

[0238] The second feedforward filter FF102 has, as shown in Fig. 45B, the k1 series-connected 1-clock delay elements TD1a to TDk1a and the (k1 + 1) multipliers TMu0a to Tmuk1a.

[0239] The delay elements TD1a to TDn1a of the second feedforward filter FF102 perform delay processing corresponding to a clock in response to a clock provided by the control circuit 7. The multipliers TMu0a to TMuk1a of the second feedforward filter FF2 are supplied with the coefficients h1[0] to h1[k1] from the filter constant holding unit 8a of the weighting circuit 8.

[0240] That is, compared with the first embodiment or the like, the present embodiment has a configuration similar to a configuration obtained by omitting the first and second feedback filters FB1 and FB2 or the like from the configuration of the first embodiment. In such a form, the equalizer processing unit 116 calculates the multiplication coefficients (tap coefficients corresponding to the filter constant) h1[0] to h1[n1] of the first feedforward filter FF101. The calculation result is stored in the filter constant holding unit 12a in the equalizer processing unit 116.

[0241] The transmission unit 14 transmits the coefficients h1[0] to h1[n1] to the filter constant holding unit 8a of the weighting circuit 108. Subsequently, the coefficients h1[0] to h1[n1] (the coefficients of the multipliers Mu0a to Mun1a of the first feedforward filter FF1) transmitted from the transmission unit 14 to the filter constant holding unit 8a are given to the multipliers TMu0b to TMUk1a of the second feedforward filter FF102. This embodiment illustrates the form in which all of the coefficients are used, but it is sufficient if some of the coefficients are used.

[0242] Even in such a form, the same effect as in the above-described embodiments can be achieved. It should be noted that the method in the present embodiment is suitable when the frequency dependence of the signal distortion due to the transmission line 6 is not high. The method in the present embodiment is also applicable to a case where the frequency-dependent characteristic of the transmission line 6 is complicated and approximation is difficult even when the DFE circuit 12 is used. This is because, since the feedback filters FB1 and FB2 are not provided, the configuration is simpler and more stable than that of the DFE circuit 12. (Eleventh embodiment)

[0243] An eleventh embodiment is described below with reference to the Fig. 46 and Fig. 47. In the above-described embodiments, bidirectional communication is performed between the communication devices 4 and 5, and before communication of normal data between the communication devices 4 and 5, the communication device 5 sends the training pattern to the communication device 4, and the communication device 5 monitors the influence of the transmission line 6.

[0244] However, it may also be the case that, due to a temperature change, a noisy environment, or a communication malfunction between the communication devices 4 and 5, the training is preferably carried out again. In such a case, as in Fig. 46, a training pattern selection signal line SS is suitably provided adjacent to the transmission line 6.

[0245] When the control circuit 7 of the communication device 4 sends / outputs a training transmission request command to the training pattern selection signal line SS, the control circuit 20 of the communication device 5 receives the training transmission request command via the training pattern selection signal line SS.

[0246] At this time, when a predetermined signal level (such as “H”) is defined in advance as a training pattern transmission request level (command) between the communication devices 4 and 5, the communication device 4 outputs Fig. 47, the predetermined signal level is sent to the communication device 5, thereby issuing a request to transmit the training pattern (U11). Upon receiving the transmission request (U12), the control circuit 20 of the communication device 5 transmits the training pattern (U13), thereby enabling the communication device 4 to switch to the training processing.

[0247] When the DFE circuit 12 or the equalizer circuit 112 of the communication device 4 executes the equalization processing so as to make the error approach 0 and determine the filter constant, a training pattern processing completion signal is set to a signal level (such as "L") different from the predetermined signal level so as to indicate the end of the training processing, and then transmitted (U14).

[0248] Upon receiving the transmission request (U15), the control circuit 20 of the communication device 5 allows the data communication processing between the communication devices 4 and 5 to switch to the transmission / reception processing of the normal data (U16).

[0249] By providing the training pattern selection signal line SS described above, the communication device 4 plays an important role in switching between training processing and communication processing for normal data. Specifically, when the ground level G1 of the communication device 4 and the ground level G2 of the communication device 5 are the same (such as 0) or different from each other but have only a small difference between them, only one training pattern selection signal line SS can be appropriately provided. When the communication devices 4 and 5 comprise integrated circuits, this configuration can be achieved by adding only one pin.

[0250] Although the example in which a digital level (such as "H") is used as the transmission request level is shown above, the transmission request level is not limited to this digital level. However, a predetermined command using multiple bit strings (a predetermined pattern of digital data) may also be used as the training pattern transmission request command. It is also possible that individual identification codes are assigned in advance to the respective communication devices 205a to 205n, and the transmission request command is determined in advance using a format including the identification codes (some or all of the identification codes) of a communication node to which the transmission request is to be issued. In this case, too, the same function and effect are achieved. (Twelfth Embodiment)

[0251] A twelfth embodiment is described below with reference to the Fig. 48 to 50. The twelfth embodiment shows a form in which, with a communication device serving as a master, communication devices serving as a plurality of slaves are connected. In such a case, as shown in Fig. 48, a communication device 204 (corresponding to the first communication node) serving as the master, instead of the communication device 4, is connected via respective transmission lines 206a to 206n to the communication devices 205a to 205n serving as the plurality of slaves, instead of the communication device 5. The communication device 204 has, as shown in the Fig. 48 and Fig. 49, the receiving unit 13 and the transmitting unit 10 are arranged in correspondence with the transmission lines 206a to 206n.

[0252] The communication device 205a corresponds to the second communication node. The communication devices 205b to 205n correspond to a third communication node. In this case, the transmission lines 206a to 206n are applicable to data communication lines. The communication devices 204 and 205a to 205n are applicable to an example in which the communication devices 204 and 205a to 205n are mounted on the same circuit board substrate 210. Even if they are not mounted on the circuit board substrate 210, the communication devices 204 and 205a to 205n are applicable to different communications.

[0253] In such a connection form, when considering the provision of the training pattern selection signal line SS described in the eleventh embodiment, the training pattern selection signal lines SSa to SSn can be appropriately connected between the communication devices 204 and 205a to 205n.

[0254] Such a connection form can be appropriately used, whereby if a communication error occurs between certain communication devices (such as between 204 and 205a), it is highly likely that the same error will occur between other communication devices (such as between 204 and 205b). In such a case, the communication device 204 can appropriately execute the training processing with all the communication devices 205a to 205n. This can improve the stability of the entire system.

[0255] In such a case, the Fig. 48 shown training pattern selection signal lines SSa to SSn are suitably unified (standardized) to provide a training pattern selection signal line SSz, as shown in the Fig. 49. For example, as shown in Fig. 49, only one training pattern selection signal line SSz is connected to the control circuit 7 of the communication device 204. The training pattern selection signal line SSz is connected to the control circuit 20 of each of the communication devices 205a to 205n. In the present embodiment, the command using the predetermined digital level "H" is used as the training pattern transmission request command.

[0256] Fig. 50 schematically shows a timing chart for the case where the training pattern transmission request is issued. When the control circuit 7 of the communication device 204 transmits the training pattern transmission request command via the training pattern selection signal line SSz (U21), the control circuit 20 of each of the communication devices 205a to 205n receives the transmission request (U22), and the control circuit 20 of each of the communication devices 205a to 205n transmits the training pattern (U24). Consequently, the communication device 204 executes distortion compensation processing for the transmission line 206a. Upon completion of the training processing, the control circuit 7 of the communication device 204 transmits a termination command indicating the end of the training processing via the training pattern selection signal line SSz (U25).When the communication devices 205a to 205n receive the termination command (U26), the communication devices 204 and 205a to 205n can perform normal data transmission / reception processing. This can compensate for the influence of the distortion due to the transmission line 206a and improve the stability of the entire system.

[0257] When the communication device 204 is provided by the integrated circuit by the configuration in the Fig. 49 is applied to the communication device 204, the configuration can be provided by adding only one connection pin for transmitting the training pattern transmission request command to the communication devices 205a to 205n. This can minimize an increase in the number of pins.

[0258] In the configuration of the Fig. 49, the training pattern selection signal line SSz crosses the transmission lines 206a and the like two-dimensionally (see crossing portions 207a, 207b, and the like). To realize the configurations of the crossing portions 207a and 207b in the printed circuit board substrate 210, the printed circuit board substrate 210 can be suitably provided by a multilayer substrate having an inner layer or a double-sided substrate. As a result, even when the crossing portions 207a and 207b are present in an electrical circuit, the training pattern selection signal line SSz or the transmission lines 206a to 206n can be realized through the inner layer of the multilayer substrate of the printed circuit board substrate 210 or across both surfaces of the double-sided substrate. Accordingly, even if the training pattern selection signal line SSz two-dimensionally crosses the transmission lines 206a and the like formed in the Fig. 49 shown configuration can be provided.

[0259] When the printed circuit board substrate 210 is provided by a multilayer substrate, the wiring in the inner layer in the printed circuit board substrate 210 may become complicated. Therefore, it may be desirable to avoid forming the printed circuit board substrate 210 from a multilayer substrate as much as possible. If the above configuration is to be provided using a double-sided substrate without an inner layer as the printed circuit board substrate 210, a power supply node or the ground node G1 or G2, which preferably occupies a larger area, will be shared. In this case, the transmission characteristics of the transmission lines 206a to 206n may deteriorate.

[0260] For example, when an improvement in transmission characteristics is required, and when, for example, the communication devices 205a to 205n are provided by integrated circuits, it is appropriate to use multiple wiring layers in the integrated circuit in the communication device 205a and to form the crossing portions 211a, 211b and the like between the training pattern selection signal line SSz and the transmission lines 206a, 206b and the like.

[0261] This allows the training pattern selection signal line SSy to be configured between the communication devices 204 and 205a, eliminating the need to directly connect the training pattern selection signal line SSy to the other communication devices 205b to 205n. Between the adjacent communication devices 205a and 205b, 205b and 205c, and the like, as shown in Fig. 51, routing lines 212 can be formed appropriately. This can minimize the increase in the number of wiring layers of the printed circuit board substrate 210.

[0262] The training pattern transmission request command contains a small amount of information, even if the identification codes of communication partners, such as the communication devices 205a, 205b, and the like, are included in the training pattern transmission request command. As described above, the training pattern transmission request command may also be only a predetermined digital level (such as "H"). Accordingly, it is sufficient for the transmission speed to be low compared to the transmission speed for transmitting / receiving the training pattern, the transmission speed for transmitting / receiving normal data, or the like. Consequently, the adverse effect exerted upon passing through the communication device 205a and the like can be maximally suppressed. (Thirteenth Embodiment)

[0263] A thirteenth embodiment is described below with reference to the Fig. 52. The thirteenth embodiment shows a form in which a waveform shaping unit is provided. Signal deterioration occurs as shown in Fig. 52, when the training pattern selection signal line SSy passes through the inner layers of the multiple wiring layers of the communication device 205a, etc. When the influence of signal degradation is ignorable, there is essentially no problem. However, at some times, the influence cannot be ignored.

[0264] This is because, as the lengths of the training pattern selection signal line SSy and the relay lines 212 are increased, the series resistance components are consequently increased, and a noise source becomes closer. In this case, it is appropriate, as needed, to provide a buffer circuit 213 as a waveform shaping unit in the integrated circuit of each of the communication devices 205a and the like to shape the waveform of a signal and allow the communication device 205a to send the signal to each of the communication devices 205b to 205n. This can minimize the deterioration of the transmission characteristic. (Other embodiments)

[0265] The present invention is not limited to the embodiments described above, but can be modified or expanded in various ways as shown below.

[0266] Although the example in which the distortion compensation system S is configured in the vehicle is shown above, the application of the distortion compensation system S is not limited to an on-vehicle communication form. The distortion compensation system S is also applicable to other communication forms outside the vehicle. In the embodiments described above, the connection form using the CAN 6a of the in-vehicle LAN is shown. However, the connection form is not limited to a bus connection. As long as the plurality of communication devices that perform transmission / reception processing use the same transmission line 6, the communication device can also be applied to other connection forms. Although the form in which the in-vehicle network is applied to the CAN 6a is shown above, the in-vehicle network is not limited to the CAN 6a.The vehicle network is applicable to another vehicle network system (vehicle-mounted network system).

[0267] Although the example described above describes the configuration of ECUs such that the circuit sizes of other ECUs (such as ECU_B) are smaller than the circuit size of one of the ECUs (such as ECU_A), the configuration is not limited to this. The configuration is also applicable to ECUs with circuit sizes that may be greater than or equal to the others.

[0268] For the sake of simplicity, the transmission line 6 described above implements single-ended signaling, but the transmission line 6 is not limited to this transmission method. The use of differential transmission lines is particularly desirable.

[0269] Although the form in which the DFE circuit 12 stores the processed filter constant in the filter constant holding unit 12a and the transfer unit 14 transfers the filter constant to the filter constant holding unit 8a of the weighting circuit 8 is described above, it is also conceivable to use the same register as each of the filter constant holding units 12a and 8a in common. As long as at least some of the filter constants of the DFE circuit 12 are used as the filter constants of the weighting circuit 8, it is not necessary to use all of the filter constants of the DFE circuit 12.

[0270] The second feedforward filter FF2 of the weighting circuit 8 may also be configured such that the number of filter branches of the second feedforward filter FF2 is less than the number of filter branches of the second feedback filter FB2 of the weighting circuit 8. This is because it has been found that even if the number of filter branches of the second feedforward filter FF2 of the weighting circuit 8 is reduced, the reduced number of filter branches of the second feedforward filter FF2 is less influential than that of the second feedback filter FB2.

[0271] The second feedforward filter FF2 of the weighting circuit 8 may also be configured such that the number of filter branches of the second feedforward filter FF2 is less than the number of filter branches of the second feedback filter FB2 of the weighting circuit 8. This is because it has been found that even if the number of filter branches of the second feedforward filter FF2 of the weighting circuit 8 is reduced, the reduced number of filter branches of the second feedforward filter FF2 is less influential than that of the second feedback filter FB2.

[0272] Although the form in which the filter constant holding units 8a and 12a hold the coefficients of the digital filters FF1, FF2, FB1, and FB2 is shown above, a method for holding the respective parameters of the digital filters FF1, FF2, FB1, and FB2 is not limited to this method, but may also be in the form in which the parameters are held or stored in a different data format. In this case, the number of digits in the data defining an error in the filter constant of each of the digital filters can be appropriately adjusted.

Claims

[1] Distortion compensation system with: - a first communication node (4, 104, 204) having a first receiving unit (13, 113) and a first transmitting unit (10, 110), wherein the first receiving unit (13, 113) has an equalizer (12, 112) and the equalizer (12, 112) has a first digital filter unit (FF1, FB1, FF101), and wherein the first transmitting unit (10, 110) has a weighting circuit (8, 108) and the weighting circuit (8, 108) has a second digital filter unit (FF2, FB2, FF102), and - a second communication node (5, 105, 205a) having a second transmitting unit (23), wherein the second transmitting unit (23) transmits a training pattern determined in advance before the second communication node receives normal data from the first transmitting unit (10, 110) of the first communication node (4, 104, 204) via a first transmission line (6, 6a, 206a), wherein - the first communication node (4, 104, 204) receives the training pattern transmitted by the second transmitting unit (23) of the second communication node (5, 105, 205a) using the first receiving unit (13, 113), - the equalizer (12, 112) converges a filter constant of the first digital filter unit (FF1, FB1, FF101) such that an error with respect to the training pattern to be received is converged, - the first transmitting unit (10, 110) of the first communication node (4, 104, 204) performs distortion compensation on the normal data to be transmitted using the converged filter constants of the first digital filter unit (FF1, FB1, FF101) as at least a part of a filter constant of the second digital filter unit (FF2, FB2, FF102) of the weighting circuit (8, 108) and then transmits the normal data, - the first communication node is a transmitting node that mainly sends the normal data to the second communication node, - the second communication node is a receiving node that mainly receives the normal data sent from the first communication node, and - the receiving node does not contain any circuitry that performs distortion compensation. [2] Distortion compensation system according to claim 1, wherein - the equalizer (12) of the first receiving unit (13) is provided by an equalizer circuit with quantized feedback (DFE, 12), - the equalizer (12) of the first receiving unit (13), as the first digital filter unit (FF1, FB1), has a first feedforward filter (FF1) and a first feedback filter (FB1), - the equalizer (12) of the first receiving unit (13) further comprises a data slicer (S1), - the first feedforward filter (FF1) performs a first digital filter processing on input data to the DFE circuit (12), - the first feedback filter (FB1) performs a second digital filter processing on output data from the DFE circuit, - the data slicer (S1) sums an output of the first feedforward filter (FF1) and an output of the first feedback filter (FB1) and compares the summation result with an output of the DFE circuit (12) in order to compare the summation result with the output of the DFE circuit (12), - the weighting circuit (8) of the first transmitting unit (10), as the second digital filter unit (FF2, FB2), comprises a second feedforward filter (FF2) and a second feedback filter (FB2), - the second feedforward filter (FF2) performs a first digital filter processing on input data to the weighting circuit (8), - the second feedback filter (FB2) performs a second digital filter processing on output data from the weighting circuit (8), and - the weighting circuit (8) of the first transmitting unit (10) sums an output of the second feedforward filter (FF2) and an output of the second feedback filter (FB2) and then outputs a summation result. [3] Distortion compensation system according to claim 1, wherein - the equalizer (112) of the first receiving unit (113) is provided by an adaptive linear equalizer (112), - the adaptive linear equalizer (112) of the first receiving unit (113) comprises, as the first digital filter unit (FF101), a first feedforward filter (FF101) which performs a first digital filter processing on input data to the adaptive linear equalizer (112), - the adaptive linear equalizer (112) of the first receiving unit (113) further comprises a determination unit (S101) which compares output data from the equalizer (112) with an output of the first feedforward filter (FF101) in order to compare the output data from the equalizer (112) with the output of the first feedforward filter (FF101), - the weighting circuit (108) of the first transmitting unit (110), as the second digital filter unit (FF102), has a second feedforward filter (FF102) which performs a first digital filter processing on input data to the weighting circuit (108), and - the weighting circuit (108) of the first transmitting unit (110) provides an output of the second feedforward filter (FF102) as an output result. [4] Distortion compensation system according to one of claims 1 to 3, wherein - the first receiving unit (13, 113) receives each bit of the training pattern at an operating frequency, - the equalizer (12, 112) operates at an operating frequency higher than the operating frequency of the first receiving unit (13, 113) to divide each bit of the training pattern into two or more subbits, the divided subbits having equal consecutive data values, - the equalizer (12, 112) converges the filter constant of the first digital filter unit (FF1, FB1, FF101) such that errors in the subbits of the received training pattern are converged, - the first transmitting unit (10, 110) of the first communication node (4, 104, 204) operates at the same frequency as the equalizer (12, 112), and - the first transmitting unit (10, 110) of the first communication node (4, 104, 204) performs the distortion compensation on the normal data to be transmitted in units of subbits by using the converged filter constants of the first digital filter unit (FF1, FB1, FF101) as at least a part of the filter constants of the second digital filter unit (FF2, FB2, FF102) of the weighting circuit (8, 108) and then transmits the normal data. [5] The distortion compensation system according to claim 4, wherein a number of the divided subbits is an odd number. [6] The distortion compensation system according to claim 5, wherein the number of divided subbits is three. [7] The distortion compensation system according to any one of claims 4 to 6, wherein the first communication node (104) further comprises a filter (9a-1) that reduces components in a high frequency range when the first communication node (104) performs the distortion compensation on the normal data in units of subbits and sends the normal data to the second communication node (5). [8] The distortion compensation system according to any one of claims 4 to 6, wherein the second communication node (105) further comprises a filter (21a-1) that reduces components in a high frequency range when the second communication node (105) receives, from the first communication node (4), the normal data on which the distortion compensation has been performed in units of subbits. [9] Distortion compensation system according to claim 7 or 8, wherein - the filter (9a-1, 21a-1) has a cutoff frequency in the high frequency range, and - the cutoff frequency is set to a Nyquist frequency corresponding to the operating frequency of the equalizer (12, 112) at which the equalizer divides each bit of the training pattern into the subbits. [10] Distortion compensation system according to claim 2 or 3, wherein a number of filter taps in the second feedforward filter (FF2, FF102) of the weighting circuit (8, 108) is less than a number of filter taps in the first feedforward filter (FF1, FF101) of the equalizer (12, 112). [11] Distortion compensation system according to claim 2, wherein a number of filter branches in the second feedback filter (FB2) of the weighting circuit (8) is less than a number of filter branches in the first feedback filter (FB1) of the DFE circuit (12). [12] The distortion compensation system according to claim 2, wherein a number of filter branches in the second feedforward filter (FF2) of the weighting circuit (8) is less than a number of filter branches in the second feedback filter (FB2) of the weighting circuit (8). [13] The distortion compensation system of claim 2, wherein a number of digits of values defining an error in a filter constant of the second feedforward filter (FF2) of the weighting circuit (8) is less than a number of digits of values defining an error in a filter constant of the first feedback filter (FB1) of the DFE circuit (12). [14] The distortion compensation system of claim 2, wherein a number of digits of values defining an error in a filter constant of the second feedback filter (FB2) of the weighting circuit (8) is less than a number of digits of values defining an error in a filter constant of the first feedback filter (FB1) of the DFE circuit (12). [15] The distortion compensation system according to claim 2, wherein a number of effective bits defining an error in a filter constant of the second feedforward filter (FF2) of the weighting circuit (8) is less than a number of effective bits defining an error in a filter constant of the second feedback filter (FB2) of the weighting circuit (8). [16] The distortion compensation system according to any one of claims 1 to 15, wherein the training pattern comprises a pseudorandom number pattern. [17] The distortion compensation system according to any one of claims 1 to 16, wherein the first communication node (4, 104) sends, as the normal data, a program to the second communication node (5, 105). [18] The distortion compensation system according to any one of claims 1 to 17, wherein the first communication node (4, 104, 204a) has a filter constant holding unit (12a, 8a) that holds the filter constants of the first digital filter unit (FF1, FB1, FF101) and the second digital filter unit (FF2, FB2, FF102) when the second communication node (5, 105, 205a) is a communication partner node. [19] The distortion compensation system according to any one of claims 1 to 18, wherein the first transmission line comprises a bus (6a) and the bus (6a) comprises an endpointless branch path (100). [20] Distortion compensation system according to one of claims 1 to 19, wherein - the first transmission line has a bus (6a), - the first communication node (4 of 1a, 4 of 102) and the second communication node (5 of 1b) are connected to the bus (6a), and - the distortion compensation system further comprises one or more third communication nodes (5 of at least one of 1c to 1z) different from the first and second communication nodes, wherein the one or more third communication nodes (5 of at least one of 1c to 1z) are also connected to the bus (6a). [21] Distortion compensation system according to claim 20, wherein - each of the one or more third communication nodes (5 of at least one of 1c to 1z) has the second transmission unit (23) that transmits the training pattern determined in advance before the normal data is communicated between the second transmission unit (23) and the first communication node (4 of 1a, 4 of 102), - the first communication node (4 of 1a, 4 of 102) has a transmission request unit (7) which successively sends at least one transmission request to at least one other communication node, - the at least one other communication node is at least one of the second communication node (5 of 1b) or the one or more third communication nodes (5 of at least one of 1c to 1z) that are different from the first communication node (4 of 1a, 4 of 102), and - when the at least one other communication node receives the at least one transmission request from the transmission request unit (7) of the first communication node (4 of 1a, 4 of 102), the second transmission unit (23) of each of the at least one other communication node transmits the training pattern to the first communication node (4 of 1a, 4 of 102). [22] Distortion compensation system according to claim 20 or 21, wherein - a data transmission speed from the first communication node (4 of 1a, 4 of 102) to the second communication node (5 of 1b) is higher than a data transmission speed between the second communication node (5 of 1b) and each of the one or more third communication nodes (5 of at least one of 1c to 1z) on the bus (6a), and - the data transmission speed from the first communication node (4 of 1a, 4 of 102) to the second communication node (5 of 1b) is also higher than a data transmission speed between any two of the one or more third communication nodes (5 of at least two of 1c to 1z) on the bus (6a). [23] Distortion compensation system according to one of claims 20 to 22, wherein - while the first communication node (4 of 1a, 4 of 102) is carrying out communication with the second communication node (5 of 1b) or with the third communication node (5 of one of 1c to 1z) on the bus (6a), the remaining communication nodes which do not join the communication ignore the data being communicated on the bus (6a). [24] Distortion compensation system according to one of claims 19 to 23, wherein the first communication node (4 of 102) is connectable to the bus (6a) using a cable (103) detachable from the bus (6a). [25] Distortion compensation system according to one of claims 19 to 24, wherein the first communication node (4 of 1a) is connected to a higher-order network (N) via a port different from a port connected to the bus (6a). [26] Distortion compensation system according to one of claims 1 to 18, further comprising: - a training pattern selection signal line (SS, SSa, SSz, SSy) connecting the first communication node (204) to the second communication node (205a), wherein - the first communication node (204) has a transmission request unit (7) which sends a transmission request requesting transmission of the training pattern to the second communication node via the training pattern selection signal line (SS, SSa, SSz, SSy), and - the second transmission unit (23) of the second communication node (205a) transmits the training pattern to the first communication node (204) in response to the transmission request from the transmission request unit (7) of the first communication node (204). [27] Distortion compensation system according to one of claims 1 to 18, further comprising: - one or more third communication nodes (205b to 205n) different from the first communication node (204) and the second communication node (205a), wherein the one or more third communication nodes (205b to 205n) are connected to the first communication node (204) via respective second transmission lines (206b to 206n); - a first training pattern selection signal line (SSa) connecting the first communication node (204) to the second communication node (205a); and - one or more second training pattern selection signal lines (SSb to SSn) each connecting the first communication node (204) to the one or more third communication nodes (205b to 205n), wherein - the first communication node (204) has a transmission request unit (7) that sends a transmission request for the training pattern to both the second communication node (205a) and the one or more third communication nodes (205b to 205n) as a target communication node via both the first and second training pattern selection signal lines (SSa, SSb to SSn), and - the second transmission unit (23) of the target communication node transmits the training pattern to the first communication node (204) in response to the transmission request from the transmission request unit (7) of the first communication node (204). [28] Distortion compensation system according to one of claims 1 to 18, further comprising: - one or more third communication nodes (205b to 205n) different from the first communication node (204) and the second communication node (205a), wherein the one or more third communication nodes (205b to 205n) are connected to the first communication node (204) via respective second transmission lines (206b to 206n); and - a training pattern selection signal line (SSz) connecting the first communication node (204) to both the second communication node (205a) and the one or more third communication nodes (205b to 205n), wherein - the first communication node (204) has a transmission request unit (7) which sends a transmission request for the training pattern to both the second communication node (205a) and the one or more third communication nodes (205b to 205n) as a target communication node via the training pattern selection signal line (SSz), and - the second transmission unit (23) of the target communication node transmits the training pattern to the first communication node (204) in response to the transmission request from the transmission request unit (7) of the first communication node (204). [29] Distortion compensation system according to one of claims 1 to 18, further comprising: - one or more third communication nodes (205b to 205n) different from the first communication node (204) and the second communication node (205a), wherein the one or more third communication nodes (205b to 205n) are connected to the first communication node (204) via respective second transmission lines (206b to 206n); - a training pattern selection signal line (SSy) connecting the first communication node (204) to the second communication node (205); and - a forwarding line (212) connecting the second communication node (205a) to the one or more third communication nodes (205b to 205n), wherein - the first communication node (204) has a transmission request unit (7) which communicates with the second communication node (205a) via the training pattern selection signal line (SSy) in order to send a transmission request for the training pattern to the second communication node (205a) or to each of the one or more third communication nodes (205b to 205n), - the second communication node (205a) is provided by an integrated circuit, and the integrated circuit has a plurality of wiring layers that enable the transmission request to be sent to each of the one or more third communication nodes (205b to 205n) via the plurality of wiring layers and the forwarding line (212) when the transmission request is sent from the transmission request unit (7) of the first communication node (204), and - the second transmission unit (23) transmits the training pattern to the first communication node (204) from a target communication node, which is one of the second communication node (205a) and the one or more third communication nodes (205b to 205n) to which the transmission request is sent. [30] The distortion compensation system of claim 29, wherein the first communication node (204) and the second communication node (205a) are mounted on a printed circuit board substrate (210). [31] The distortion compensation system according to claim 29, wherein the integrated circuit of the second communication node (205a) comprises a waveform shaping unit (213) that shapes a waveform of the transmission request. [32] The distortion compensation system according to any one of claims 26 to 29, wherein the transmission request unit (7) transmits the transmission request for the training pattern to each of the one or more target communication nodes. [33] Distortion compensation system according to one of claims 26 and 28 to 31, characterized by that a number of training pattern selection signal lines (SS, SSz, SSy) is only one. [34] The distortion compensation system according to any one of claims 26 and 28 to 33, wherein the transmission request unit (7) outputs a predetermined digital level as the transmission request for the training pattern to the training pattern selection signal line (SS, SSa to SSn, SSz, SSy) when transmitting the transmission request for the training pattern via the training pattern selection signal line (SS, SSa to SSn, SSz, SSy). [35] The distortion compensation system according to claim 27, wherein the transmission request unit (7) outputs a predetermined digital level as the transmission request for the training pattern to the first or second training pattern selection signal line (SSa or SSb to SSn) when transmitting the transmission request for the training pattern via the first or second training pattern selection signal line (SSa or SSb to SSn). [36] Distortion compensation system according to one of claims 1 to 25, wherein the second communication node (5, 105) is provided on a drive circuit (2) of a vehicle actuator. [37] Distortion compensation system according to one of claims 1 to 25, wherein the first communication node (4, 104) is provided on a vehicle ECU (1, 1a to 1z). [38] The distortion compensation system according to any one of claims 1 to 25, wherein the first communication node (4, 104) is provided on a program rewriting device (102) and sends a program as the normal data to the second communication node (5, 105). [39] Communication device with a first communication node (4, 104, 204), comprising: - a first receiving unit (13, 113) with an equalizer (12, 112), wherein the equalizer (12, 112) has a first digital filter unit (FF1, FB1, FF101), and - a first transmitting unit (10, 110) with a weighting circuit (8, 108), wherein the weighting circuit (8, 108) has a second digital filter unit (FF2, FB2, FF102), wherein - the first receiving unit (13, 113) receives a training pattern when the training pattern, which is determined in advance, is transmitted from a second transmitting unit (23) of a second communication node (5, 105, 205a), - the equalizer (12, 112) converges a filter constant of the first digital filter unit (FF1, FB1, FF101) such that an error with respect to the training pattern to be received is converged, - the first transmitting unit (10, 110) performs distortion compensation on normal data to be transmitted using the converged filter constants of the first digital filter (FF1, FB1, FF101) as at least a part of a filter constant of the second digital filter unit (FF2, FB2, FF102) of the weighting circuit (8, 108) and then transmits the normal data, - the first communication node is a transmitting node that mainly sends the normal data to the second communication node, - the second communication node is a receiving node that mainly receives the normal data sent from the first communication node, and - the receiving node does not contain any circuitry that performs distortion compensation.

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