Radio frequency system

Abstract

Radio frequency system (12) configured to enable wireless communication of data between electronic devices (10), comprising: a first power switching amplifier (64A, 64C) and a second power switching amplifier (64B, 64D), wherein the first power switching amplifier (64A, 64C) is configured to transmit a first amplified analog electrical signal, which is transmitted with a desired output power, at least partially based on a first analog electrical input signal and an envelope voltage of an envelope voltage supply rail (70), wherein the first power switching amplifier (64A, 64C) comprises: a first transistor (74A, 74C) of the first power switching amplifier (64A, 64C), wherein a gate of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a source of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) is electrically connected to the envelope voltage supply rail (70), and a drain of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) is electrically connected to the first output of the first power switching amplifier (64A, 64C); a second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) connected in parallel to the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C), wherein a gate of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a source of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) is electrically connected to ground (72), and a drain of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) is electrically connected to the first output of the first power switching amplifier (64A, 64C); and a third transistor (80A, 80C) of the first power switching amplifier (64A, 64C), wherein a gate of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a drain of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) is electrically connected to the envelope voltage supply rail (70) is coupled, and a source of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) is electrically coupled to a second output of a second power switching amplifier (64B, 64D).

Description

BACKGROUND

[0001] The present disclosure relates generally to radio frequency systems and in particular to power switching amplifiers used in a radio frequency system.

[0002] This section is intended to introduce the reader to various aspects of the technology related to the different aspects of the present technologies described and / or claimed below. The explanation is considered helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light and not as an admission of prior art.

[0003] Many electronic devices can include a radio frequency system to facilitate wireless data communication with another electronic device and / or a network. The radio frequency system may include a transceiver that outputs an analog representation of data as an analog electrical signal, which can then be transmitted wirelessly via an antenna. Because the electronic device may be separated by some distance, the radio frequency system may include an amplifier component to control the output power (e.g., the strength of the analog electrical signals) of the radio frequency system.

[0004] In some embodiments, the amplifier component may include a power switching amplifier (e.g., class D) that uses one or more transistors as electronic switches. In some embodiments, the power switching amplifier may amplify an analog electrical input signal to a desired output power. In particular, the power switching amplifier may generate the amplified analog electrical signal by providing an output with an envelope voltage supply rail (e.g., v). env -supply rail) or ground, which is based at least partially on an analog electrical input signal.

[0005] Ideally, a power switching amplifier should achieve high power efficiency (e.g., output power / DC consumption), linearly adjust the output power of the amplified analog electrical signals, and maintain a constant phase shift between the analog electrical input signals and the amplified analog electrical output signals. In real-world operation, however, a transistor generally has parasitic capacitance, which can cause the transistor to conduct a leakage current from its gate to its drain. This leakage current can, in fact, degrade the efficiency of the power switching amplifier, the linearity of the output power adjustments, and / or the consistency of the phase shift between the amplified analog electrical input and output signals.

[0006] The prior art document US 2014 / 0022013 A1 describes an antenna driver device configured to apply a pulsed antenna driver voltage to an antenna. SUMMARY

[0007] The present invention is defined in independent claim 1. Advantageous embodiments are specified in the dependent claims.

[0008] A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these particular embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may include a variety of aspects that may not be set forth below.

[0009] The present disclosure relates generally to the improvement of the operation of a switching amplifier (e.g., class D) used in a radio frequency system. In general, a power switching amplifier receives an analog electrical input signal and outputs an amplified analog electrical signal, which can then be transmitted wirelessly to another electronic device or a network. In particular, the power switching amplifier can generate the amplified analog electrical signal by driving the output of the power switching amplifier either with an envelope voltage supply rail (e.g., VA). env -supply rail) or ground, which is based on the analog electrical input signal, connects via one or more transistors.

[0010] However, each transistor generally has a parasitic capacitance through which a leakage current can flow from its gate to its drain. As such, especially when the output power of the amplified analog electrical signal is low, the leakage current can limit the minimum output power, thereby reducing the linearity of the output power adjustments and / or causing an inconsistent phase shift between the electrical input and output signals.

[0011] Accordingly, the techniques described here can improve the operation of a power switching amplifier by enhancing the linearity of the output power adjustments and / or the consistency of a phase shift between an electrical input and output signal. In some embodiments, if the radio frequency system uses a differential scheme with a positive analog electrical signal (e.g., +V), in ) and a negative, analog electrical signal (e.g., -V) in ) used, a first power switching amplifier may be included in a first branch that receives the positive, analog electrical signal, and a second power switching amplifier may be included in a second branch that receives the negative, analog electrical signal.

[0012] In particular, each power switching amplifier can include a first p-type metal-oxide-semiconductor transistor (PMOS transistor) whose source is electrically connected to an envelope voltage supply rail (e.g., V). envThe power switching amplifier comprises a first n-type metal-oxide-semiconductor transistor (NMOS transistor) whose source is electrically coupled to ground, whose gate is electrically coupled to the analog electrical input signal, and whose drain is electrically coupled to an output of the power switching amplifier. Additionally, each power switching amplifier may include a second NMOS transistor whose gate is electrically coupled to the electrical input signal, whose drain is electrically coupled to the envelope voltage supply rail, and whose source is electrically coupled to an output of the switching amplifier of the opposite branch.

[0013] Thus, during operation, when the output power is low because the voltage on the envelope voltage supply rail is lower than a threshold range (e.g., voltages between the order of magnitude of the PMOS transistor threshold voltage and the voltage of the high-voltage analog input signal minus the NMOS transistor threshold voltage), each power switching amplifier can function as a dual NMOS inverter (e.g., the first NMOS transistor can be coupled in parallel with the second NMOS transistor from the opposite branch). As such, any leakage current following through the NMOS transistors can be canceled out, since the NMOS transistors share a common output node and are supplied with inverted (e.g., opposite) analog electrical signals.In this way, the linearity of the output power adjustments and / or the consistency of a phase shift between an analog electrical input and output signal can be improved, especially at low output powers.

[0014] However, a dual-NMOS architecture can lead to higher DC current consumption at high output power due to the higher drive voltage of NMOS transistors compared to PMOS transistors. Accordingly, since linearity and / or phase shift are less affected by leakage current at high output power (e.g., an envelope voltage greater than the threshold), any power switching amplifier can function as an NMOS / PMOS inverter (e.g., a first NMOS transistor connected in parallel with the first PMOS transistor) when the output power is high, as the voltage on the envelope voltage supply rail is higher than the threshold. Additionally, if the voltage on the envelope voltage supply rail is within the threshold, any power switching amplifier can operate in parallel as both a dual-NMOS inverter and an NMOS / PMOS inverter.In this way, the power consumption of the power switching amplifiers can also be reduced, thereby improving the efficiency (e.g. output power / DC consumption) of the radio frequency system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various aspects of this revelation can be better understood by reading the following detailed description and referring to the drawings, in which the following applies: Fig. 1 is a block diagram of an electronic device with a radio frequency system according to one embodiment; Fig. 2 is an example of the electronic device of Fig. 1 according to one embodiment; Fig. 3 is an example of the electronic device of Fig. 1 according to one embodiment; Fig. 4 is an example of the electronic device of Fig. 1 according to one embodiment; Fig. 5 is a block diagram of the radio frequency system of Fig. 1 according to one embodiment; Fig. 6 is a schematic diagram of an amplifier component used in the radio frequency system of Fig. 5 is used according to one embodiment; Fig. 7 is a schematic diagram of an embodiment of power switching amplifiers used in the radio frequency system of Fig. 6 can be used, according to one embodiment; Fig. 8A is a schematic diagram of the power switching amplifiers from Fig. 7, if the envelope voltage is high, according to one embodiment; Fig. 8B is a schematic diagram of the power switching amplifiers of Fig. 7, if the envelope voltage is low, according to one embodiment; Fig. Figure 9 is a flowchart describing a method for operating power switching amplifiers according to one embodiment; Fig. Figure 10 is a flowchart describing a method for assembling power switching amplifiers according to one embodiment; Fig. 11 is a schematic diagram of another embodiment of power switching amplifiers used in the radio frequency system of Fig. 6 can be used, according to one embodiment; Fig. 12A is a schematic diagram of the power switching amplifiers from Fig. 11, if the envelope voltage is high, according to one embodiment; Fig. 12B is a schematic diagram of the power switching amplifiers of Fig. 11, when the envelope voltage is low, according to one embodiment; Fig. Figure 13 is a graphical representation of the output power and phase shift as a function of the envelope voltage in the power switching amplifiers of Fig. 11 according to one embodiment; Fig. Figure 14 is a graphical representation of the current in the transistors in relation to the envelope voltage in the power switching amplifiers of Fig. 11 according to one embodiment; Fig. Figure 15 is a graphical representation of the amplified analog electrical signal output of a power switching amplifier. Fig. 11 at different envelope voltages according to one embodiment; and Fig. Figure 16 is a graphical representation of the power consumption and efficiency in relation to the envelope voltage in the power switching amplifiers of Fig. 11 according to one embodiment. DETAILED DESCRIPTION

[0016] One or more specific embodiments of the present disclosure are described below. These described embodiments represent only examples of the techniques disclosed herein. Furthermore, in an effort to provide a concise and precise description of these embodiments, not all features of an actual implementation may be described. It should be evident that, as with any development or design project, the development of any such actual implementation will require numerous implementation-specific decisions to be made in order to achieve the developers' specific objectives, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.Furthermore, it should be evident that such a development effort may be complex and time-consuming for the person skilled in the art in possession of the benefit of this disclosure, but may nevertheless be a routine undertaking in terms of design, manufacturing and production.

[0017] When introducing elements of different embodiments of the present disclosure, the articles "a", "an", and "the", "a", and their declensions shall mean that there is one or more of the elements. The terms "comprising", "including", "possessing", and "having" shall be inclusive and mean that there may be additional elements other than those listed. Furthermore, it should be understood that references to "an embodiment" of the present disclosure are not to be interpreted as excluding the existence of additional embodiments that also include the specified features.

[0018] As mentioned above, an electronic device can include a radio frequency system to facilitate wireless data communication with another electronic device and / or a network. Specifically, the radio frequency system can modulate radio waves to allow the electronic device to communicate over a personal area network (e.g., a Bluetooth network), a local area network (e.g., an 802.11x Wi-Fi network), and / or a wide area network (e.g., a 4G or LTE cellular network). In other words, the radio frequency systems can use various wireless communication protocols to facilitate data exchange.

[0019] Nevertheless, radio frequency systems can generally operate similarly regardless of the wireless communication protocol used. For example, to transmit data, the processing circuitry can generate a digital representation of the data as a digital electrical signal, and a transceiver (e.g., a transmitter and / or a receiver) can then convert the digital electrical signal into one or more analog electrical signals. Based on various factors (e.g., wireless communication protocol, power consumption, distance, etc.), the analog electrical signals can be transmitted wirelessly at different output powers. To facilitate control of the output power, the radio frequency system can include an amplifier component that receives the analog electrical signals and outputs amplified analog electrical signals at a desired output power for transmission via an antenna.

[0020] In some embodiments, the amplifier component may comprise one or more switching amplifiers (e.g., class D) that use multiple transistors to generate the amplified analog electrical signals. In particular, a power switching amplifier may generate the amplified analog electrical signals by providing an output based on the analog input signal, either with an envelope voltage supply rail (e.g., V). env -supply rail) or ground. For example, if the analog input signal is low (e.g., zero volts), the power switching amplifier can turn on a first transistor and turn off a second transistor to connect the output to the envelope voltage supply rail. Conversely, if the input signal is high (e.g., a positive voltage), the switching amplifier can turn off the first transistor and turn on the second transistor to connect the output to ground.

[0021] In this way, the output power of the amplified analog electrical signals can be controlled by adjusting the envelope voltage. To facilitate control of the output power, it may therefore be desirable for the output power of the amplified analog electrical signal to depend proportionally on the magnitude of the envelope voltage. In other words, it may be desirable for the output power and the envelope voltage to vary linearly. Additionally, it may be desirable for the phase shift between the amplified analog electrical signals and the input signals to remain relatively constant, independent of the output power.

[0022] In theory, transistors would act as electrical switches, cutting off the power supply when off and connecting it when on. However, under real-world conditions, a transistor generally has parasitic capacitance, allowing leakage current to flow from its gate to its drain. In other words, a transistor's operation can deviate from that of an ideal switch. Indeed, this leakage current can affect the linearity (e.g., output / input amplitude) and phase shift of the power switching amplifier, especially at low output powers (e.g., when the envelope voltage is below a threshold).For example, if the power switching amplifier contains only one P-type metal oxide semiconductor transistor (PMOS transistor) and one n-type metal oxide semiconductor transistor (NMOS transistor) connected in parallel, the leakage current in the transistors can impose a lower limit on the output power of the power switching amplifier, thereby reducing the linearity and causing the phase shift to vary significantly with the output power (e.g., 100 degrees).

[0023] Accordingly, the techniques described in the present embodiment can improve the operation of radio frequency systems by enhancing the control of the output power and the consistency of the phase shift in power switching amplifiers. For example, some embodiments of a radio frequency system use a differential scheme. In such embodiments, a first power switching amplifier may be included in a first branch that receives a positive analog electrical signal (e.g., +V). in ) receives, and a second power switching amplifier may be included in a second branch that receives a negative analog electrical signal (e.g., -V). in ) receives. In particular, each power switching amplifier can include a first p-type metal-oxide-semiconductor transistor (PMOS transistor) whose source is electrically connected to an envelope voltage supply rail (e.g., V). env-supply rail) wherein its gate is electrically coupled to the analog electrical input signal, and its drain is electrically coupled to an output of the power switching amplifier, and include a first n-type metal-oxide-semiconductor transistor (NMOS transistor) whose source is electrically coupled to ground, whose gate is electrically coupled to the analog electrical input signal, and whose drain is electrically coupled to the output. Additionally, each power switching amplifier can include a second NMOS transistor whose gate is electrically coupled to the analog electrical input signal, whose drain is electrically coupled to the envelope voltage supply rail, and whose source is electrically coupled to an output of a power switching amplifier in the opposite branch.

[0024] Thus, when the output power is low (e.g., an envelope voltage below a threshold), the power switching amplifiers can connect the first NMOS transistor of one branch in parallel with the second NMOS transistor of the other branch. In other words, the power switching amplifiers can function as two dual-NMOS inverters. More precisely, in each dual-NMOS inverter, the first and second NMOS transistors receive inverted (e.g., opposite) analog input signals at their respective gates. As such, the leakage current that follows through the first and second NMOS transistors can be canceled out, since the NMOS transistors share a common output node and are supplied with inverted analog electrical input signals.In this way, the linearity of the output power adjustments, the consistency of a phase shift between an analog electrical input and output signal and / or both can be improved, especially at low output powers.

[0025] On the other hand, during operation, when the output power is high (e.g., envelope voltage higher than the threshold), the power switching amplifiers can connect the first NMOS transistor and the first PMOS transistor of a branch in parallel. In other words, the power switching amplifiers can function as two NMOS / PMOS inverters. More precisely, since the first PMOS can use a lower drive voltage than the NMOS transistors, the power consumption of the power switching amplifier can be reduced. Because the output power is high, the effects of leakage current on the amplified analog electrical signals can be small and thus do not significantly affect linearity and / or phase shift. In this way, the techniques described here can improve the operation of the radio frequency system (e.g.,to improve the control of output power and the consistency of the phase shift in the power switching amplifier), while simultaneously reducing power consumption (e.g. improving efficiency).

[0026] For illustration, an electronic device 10, which can use a radio frequency system 12, is shown in Fig. 1 described. As described in more detail below, the electronic device 10 can be any suitable electronic device, such as a handheld computer device, a tablet computer device, a notebook computer and the like.

[0027] Accordingly, the electronic device 10, as shown, includes the radio frequency system 12, the input structures 14, the memory 16, one or more processors 18, one or more data storage devices 20, a power source 22, input / output ports 24, and an electronic display 26. The various, in Fig. The components described in section 1 may include hardware elements (including circuits), software elements (including computer code stored on a non-volatile, machine-readable medium), or a combination of hardware and software elements. It should be noted that Fig. Figure 1 is merely an example of a particular implementation and is intended to illustrate the types of components that may be present in the electronic device 10. It should also be noted that the various components shown can be combined into fewer components or separated into additional components. For example, the memory 16 and a data storage device 20 can be contained within a single component.

[0028] As shown, the processor 18 is operationally coupled to the memory 16 and the data storage device 20. In particular, the processor 18 can execute an instruction stored in the memory 16 and / or the data storage device 20 to perform operations in the electronic device 10, such as instructing the radio frequency system 12 to communicate with another device. As such, the processor 18 can include one or more general-purpose microprocessors, one or more application-specific integrated circuits (ASICs), one or more field-programmable logic arrays (FPGAs), or any combination thereof. Additionally, the memory 16 and / or the data storage device 20 can be a physical, non-volatile, computer-readable medium that stores the instructions executable by the processor 18 and the data to be processed.For example, the memory 16 can include random access memory (RAM) and the data storage device 20 can include read-only memory (ROM), rewritable flash memory, hard disk drives, optical disks and the like.

[0029] Additionally, the processor 18 is operationally coupled, as shown, to the power source 22, which supplies energy to the various components in the electronic device 10. For example, the power source 22 can supply the radio frequency system 12 with direct current (DC). As such, the power source 22 can include any suitable power source, such as a rechargeable lithium polymer battery (Li-Poly battery) and / or an alternating current voltage converter (AC converter). Furthermore, the processor 18 is operationally coupled, as shown, to I / O ports 24, which allow the electronic device 10 to be connected to various other electronic devices and input structures 14, enabling a user to interact with the electronic device 10. Accordingly, the input structures 14 can include buttons, keyboards, mice, trackpads, and the like.Additionally, in some embodiments the electronic display may include 26 touch-sensitive components.

[0030] In addition to enabling user input, the electronic display 26 can display individual images, such as a graphical user interface (GUI) for an operating system, an application interface, a still image, or video content. As shown, the display is operationally coupled to the processor 18. Accordingly, the individual images displayed by the electronic display 26 can be based on display image data received by the processor 18.

[0031] As shown, the processor 18 is also operationally coupled to the radio frequency system 12, which can facilitate the communicative coupling of the electronic device 10 with one or more other electronic devices and / or networks. For example, the radio frequency system 12 can enable the electronic device 10 to communicate with a personal area network (PAN), such as a Bluetooth network, a local area network (LAN), such as an 802.11x Wi-Fi network, and / or a wide area network (WAN), such as a 4G or LTE mobile network. As can be seen, the radio frequency system 12 can enable communication using different communication protocols and / or varying output powers (e.g., the strength of the transmitted analog electrical signals).

[0032] The operational principles of the Radio Frequency System 12 can be similar for any of the communication protocols (e.g., Bluetooth, LTE, 802.11x Wi-Fi, etc.). More specifically, the Radio Frequency System 12, as described in more detail below, can convert a digital electrical signal containing data to be transmitted as an analog electrical signal using a transceiver. The Radio Frequency System 12 can then amplify the analog electrical signal to a desired output using an amplifier component and output the amplified analog signal using one or more antennas. In other words, the techniques described herein can be applied to any suitable Radio Frequency System 12 operating in any appropriate manner, regardless of the communication protocol used.

[0033] As described above, the electronic device 10 can be any suitable electronic device. For illustration, an example of a handheld device 10A is described, which is in Fig. Figure 2 shows a handheld device 10A, which can be a portable phone, a media playback device, a personal data organizer, a handheld gaming platform, or any combination of such devices. For example, the handheld device 10A can be a smartphone, such as any iPhone® model available from Apple Inc. As shown, the handheld device 10A includes a bezel 28, which can protect internal components from physical damage and shield them from electromagnetic interference. The bezel 28 can surround the electronic display 26, which, in the illustrated embodiment, displays a graphical user interface (GUI) 30 with an array of icons 32. For example, when an icon 32 is selected either by an input structure 14 or a touch-sensitive component of the electronic display 26, an application program can be started.

[0034] Additionally, as shown, the input structures 14 can open through the enclosure (e.g., housing) 28. As described above, the input structures 14 can allow a user to interact with the handheld device 10A. For example, the input structures 14 can activate or deactivate the handheld device 10A, navigate a user interface to a home screen, navigate a user interface to a user-definable application screen, activate a speech recognition function, provide volume control, and switch between vibration and ring modes. Furthermore, the I / O ports 24 open through the enclosure 28 as shown. In some embodiments, the I / O ports 24 can, for example, include an audio jack to connect to external devices.Additionally, the radio frequency system 12 can also be enclosed within the enclosure 28 and arranged internally in the handheld device 10A.

[0035] To further illustrate a suitable electronic device 10, in Fig. 3 describes a tablet device 10B, such as any iPad® model available from Apple. Additionally, in other embodiments, the electronic device 10 can be as described in Fig. 4 described the form of a computer 10C, such as any Macbook® or iMac® model available from Apple Inc. The tablet device 10B and the computer 10C also include a display 26, input structures 14, I / O ports 24, and an enclosure (e.g., housing) 28. Similar to the handheld device 10A, the radio frequency system 12 can also be enclosed within the enclosure 28 and arranged internally in the tablet device 10B and / or the computer 10C.

[0036] As described above, the Radio Frequency System 12 can facilitate communication with other electronic devices and / or a network through wireless data transmission. For illustration, Section 34 of Radio Frequency System 12 is shown in Fig. Section 5 is described. As shown, section 34 includes a digital signal generator 36, a transceiver 38, an amplifier component 40, one or more filters 42, and an antenna 44. The digital signal generator 36 can produce a digital representation of data to be transmitted by the electronic device 10 by outputting a digital electrical signal. Accordingly, in some embodiments, the digital signal generator 36 can include the processor 18 and / or a separate processing circuit, such as a baseband processor or a modem, in the radio frequency system 12.

[0037] The transceiver 38 can then receive the digital electrical signal and generate an analog representation of the data. In some embodiments, the transceiver 38 can generate an analog representation by applying an envelope voltage (e.g., V). env) outputs to specify a desired output power of the radio frequency system 12, and one or more analog electrical signals (e.g. +V in and-V in The transceiver 38 outputs an envelope voltage of 1.2 volts to indicate the phase (e.g., high or low) of the digital electrical signal. For example, if the desired output is 20 dBm, the transceiver 38 can output this envelope voltage. Additionally, if the digital electrical signal is high (e.g., "1"), the transceiver 38 can output an analog electrical signal with a positive voltage, and if the digital electrical signal is low (e.g., "0"), the transceiver 38 can output an analog electrical signal with zero volts.

[0038] Additionally, in some embodiments the transceiver 38 can use a differential scheme, whereby a positive analog electrical signal (e.g. +V) in ) and a negative analog electrical signal (e.g., -V) in). In particular, instead of generating a single analog electrical signal, the transceiver can generate the positive analog electrical signal and the negative analog electrical signal, such that these are inverses of each other and their magnitudes are equal to half the magnitude of the single analog electrical signal. In other words, if the digital electrical signal is high (e.g., "1"), then the positive analog electrical signal can be a positive voltage and the negative analog electrical signal can be zero volts. Conversely, if the digital electrical signal is low (e.g., "0"), then the positive analog electrical signal can be zero volts and the negative analog electrical signal can be a positive voltage.

[0039] Since the output power of the analog electrical signal can be small, the amplifier component 40 can receive and amplify the analog electrical signal by outputting an amplified analog electrical signal. For example, if the positive and negative analog electrical signals are received, then the amplifier component 40 can output a positive, amplified analog electrical signal (e.g., +V). out ) and a negative, amplified, analog electrical signal (e.g., -V) out ) output. As can be seen, the positive, amplified, analog electrical signal and the negative, amplified, analog signal can also be inverses of each other.

[0040] Furthermore, the amplifier component 40 can vary the amplitude of the amplified analog electrical signal to allow the output power of the radio frequency system 12 to be adjusted. As described in more detail below, the amplifier component 40 can include one or more power switching amplifiers, which in turn include one or more transistors. In such an embodiment, the power switching amplifiers can generate the amplified analog electrical signal by switching the transistors on and off based on the analog electrical input signal received from the transceiver 38, in order to drive the output of the power switching amplifier either with an envelope voltage supply rail (e.g., VA). env) or ground. For example, if the positive analog electrical signal is high and the negative analog electrical signal is low, the positive amplified analog electrical signal can be the envelope voltage and the negative amplified analog electrical signal can be zero volts. Conversely, if the positive analog electrical signal is low and the negative analog electrical signal is high, the positive amplified analog electrical signal can be zero volts and the negative amplified analog electrical signal can be the envelope voltage.

[0041] As can be seen, noise, such as spurious or out-of-band noise, can be introduced by the transceiver 38 and / or the amplifier component 40. One or more filters 42 can then remove the introduced noise from the amplified analog electrical signal and output a filtered analog electrical signal. This filtered analog electrical signal can then be wirelessly transmitted as modulated radio waves via the antenna 44 to other electronic devices and / or a network.

[0042] As described above, the amplifier component 40 can include one or more power switching amplifiers to facilitate control of the magnitude of the amplified analog electrical signal and thus the output power of the radio frequency system 12. A more detailed view of the amplifier component 40 is shown in Figure 1. Fig. 6 described. In the illustrated embodiment, the amplifier component 40 uses a differential scheme and includes an envelope voltage amplifier 46, a first branch 48 which carries the positive, analog electrical signal +V in receives, and a second branch 50, which carries the negative, analog electrical signal-V in receives.

[0043] As shown, the envelope voltage amplifier 46 connects to an operational amplifier 52, which provides the envelope voltage V envThe operational amplifier 52 receives a signal from the transceiver 38 and includes a power supply rail 54, a transistor 56, and a capacitor 58. In the illustrated embodiment, the envelope voltage amplifier 46 is connected in a negative feedback loop. Specifically, the operational amplifier 52 can receive the envelope voltage at its inverting terminal and the output voltage of the envelope amplifier 46 (e.g., voltage at output 60) at its non-inverting terminal. Accordingly, the operational amplifier 52 can amplify the difference between the output voltage, filtered by the capacitor 58, and the envelope voltage.

[0044] Additionally, in the illustrated embodiment, transistor 56 has a gate connected to the output of operational amplifier 52, a source connected to the power supply rail 54, and a drain connected to the output 60 of envelope voltage amplifier 46. More precisely, a current source, such as current source 22, can supply DC power to the power supply rail 54, so that the power supply rail 54 has a voltage of V DD The transistor 56 can selectively connect the output 60 to the power supply rail 54 based on the difference between the output voltage and the envelope voltage. In this way, the envelope voltage amplifier 46 can output electrical power at approximately the envelope voltage to the first branch 48 and the second branch 50.

[0045] As shown, each branch 48 or 50 contains one or more preamplifiers (e.g., driver amplifiers, e.g., inverters) 62 and a power switching amplifier 64. In particular, during operation, the one or more preamplifiers 62 can each amplify (i.e., increase the magnitude of) the received analog electrical signals to a voltage sufficient to drive the power switching amplifier 64. The power switching amplifiers 64 can then each amplify the received analog electrical signals to a desired output power, which is based at least partially on the electrical power output of the envelope voltage amplifier 46. For example, in the illustrated embodiment, the first branch 48 can receive a positive, amplified analog electrical signal +V out output, and the second branch 50 can output a negative, amplified, analog electrical signal -V out spend.

[0046] The amplified analog electrical signal can then be received for transmission by a load 66, such as a filter 42 and / or an antenna 44. Therefore, if the radio frequency system 12 uses a differential scheme, the positive amplified analog electrical signal and the negative amplified analog electrical signal can be combined by a transformer 68 to form a single amplified analog electrical signal.

[0047] As described above, the 64A and 64B power switching amplifiers can output the amplified analog electrical signals with a desired output power, which is based at least partially on the envelope voltage. For illustration, in Fig. Figure 7 describes a more detailed view of a first power switching amplifier 64A in the first branch 48 and a second power switching amplifier 64B in the second branch 50. As shown, the first power switching amplifier 64A receives a positive analog electrical signal (e.g., +Vin), and the second power switching amplifier 64B receives a negative analog electrical signal (e.g., -V). in ) and both power switching amplifiers 64A and 64B are coupled in parallel between an envelope voltage supply rail 70 and ground 72. More precisely, the envelope voltage amplifier 46 supplies the envelope voltage supply rail with electrical energy at the envelope voltage (Venv).

[0048] Additionally, as shown, the power switching amplifiers 64A and 64B each include a first PMOS transistor 74, a first NMOS transistor 76, a second PMOS transistor 78, a second NMOS transistor 80, and measurement components (e.g., smoothing components) that include a capacitor 82 and an inductor 84 in series. Specifically, the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel such that the source of the first PMOS transistor 74 is electrically coupled to the envelope voltage supply rail 70, the source of the first NMOS transistor 76 is electrically coupled to ground 72, the drains are electrically coupled to the measurement components, and the gates are electrically coupled to the analog electrical input signal.Additionally, the second NMOS transistor 80 and the second PMOS transistor 78 are coupled in parallel such that the drain of the second NMOS transistor 80 is electrically coupled to the envelope voltage supply rail 70, the drain of the second PMOS transistor 78 is electrically coupled to ground 72, the sources are electrically coupled to the measurement components of the opposite branch, and the gates are electrically coupled to the analog electrical input signal. Furthermore, in some embodiments, the NMOS transistors 76 and 80 can generally have the same operating characteristics (e.g., parasitic capacitances and / or leakage current), and the PMOS transistors 74 and 78 can generally have the same operating characteristics (e.g., parasitic capacitances and / or leakage current) to allow a reduction in the effects of the leakage current.

[0049] In operation, the power switching amplifiers 64A and 64B can function as NMOS / PMOS inverters when the envelope voltage is above a threshold range, as dual NMOS inverters when the envelope voltage is below the threshold range, and as combination inverters (e.g., a dual NMOS inverter coupled in parallel with an NMOS / PMOS inverter) when the envelope voltage is within the threshold range. In some embodiments, the threshold range can include voltages between the threshold voltage of the PMOS transistors (e.g., 74 and 78) and the voltage of the analog input signal when it is high (e.g., the driver voltage of the preamplifiers 62), minus the threshold voltage of the NMOS transistors (e.g., 76 and 80). For illustration, [reference to relevant section] Fig. 8A the operation of the power switching amplifiers 64A and 64B when the envelope voltage (e.g. V) envHigh ) above the threshold range, and Fig. Section 8B describes the operation of the power switching amplifiers 64A and 64B when the envelope voltage (e.g. V) envLow ) is below the threshold range.

[0050] As in Fig. As shown in Figure 8A, if the envelope voltage is higher than the threshold, the second NMOS transistors 80 and the second PMOS transistors 78 can be held in an off state. In particular, the NMOS transistors 76 and 80 can have a threshold voltage (e.g., gate-source voltage) that is greater than the difference between the voltage of the analog input signal (e.g., +V) and the threshold voltage. in or-V in ) and the envelope voltage (e.g. V envHighIn other words, when the analog input signal is low, the second NMOS transistor 80 can be switched off because the gate voltage is approximately zero volts. Additionally, the second NMOS transistor 80 can remain switched off even when the analog electrical input signal is high because the difference between the gate voltage (e.g., the voltage of the analog input signal) and the source voltage (e.g., the envelope voltage) is less than the threshold voltage of the second NMOS transistor 80.

[0051] Furthermore, the PMOS transistors 74 and 78 can have a threshold voltage (e.g., a source-gate voltage) that is greater than the difference between the envelope voltage (e.g., V). envHigh) and the voltage of the received analog electrical signal. In other words, if the received analog electrical signal is high, the second PMOS transistor 78 can be switched off, since the gate voltage is the positive voltage of the received analog electrical signal. Additionally, the second PMOS transistor 78 can remain switched off even if the received analog electrical signal is low, since the gate voltage and the source voltage are both approximately zero volts.

[0052] As such, if the envelope voltage is above the threshold range, the power switching amplifiers 64A and 64B can function as NMOS / PMOS inverters, with the first PMOS transistor 74 and the first NMOS transistor 76 coupled in parallel. In particular, in each power switching amplifier 64A and 64B, if the analog electrical input signal (e.g., +V) in or-V inIf the received analog electrical signal is high, the first PMOS transistor 74 is switched off, and the first NMOS transistor 76 can be switched on, thus connecting the output to ground. Conversely, if the received analog electrical signal is low, then the first NMOS transistor 76 can be switched off, and the first PMOS transistor 74 can be switched on, thus connecting the output to the envelope voltage supply rail 70.

[0053] In this way, the first power switching amplifier 64A outputs a positive, amplified, analog electrical signal +V out off, and the second power switching amplifier 64B outputs a negative, amplified, analog electrical signal-V out at a desired output power (e.g., based at least partially on the envelope voltage). Furthermore, the power switching amplifiers 64A and 64B generate the amplified analog electrical signals (e.g., +V). out and-V out), which are based on inverted signals, the amplified, analog electrical signals can also be inverses of each other.

[0054] On the other hand, as in Fig. As shown in Figure 8B, when the envelope voltage is lower than the threshold, the first PMOS transistor 74 and the second PMOS transistor 78 are held in an off state. As described above, the threshold can be voltages between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the analog electrical input signal, when it is high, minus the threshold voltage of the NMOS transistors 76 and 80. Thus, when the analog electrical input signal is high, the first PMOS transistor 74 and the second PMOS transistor 78 can be off, since the gate voltage is the positive voltage of the analog input signal. Additionally, even when the analog electrical input signal is low, the first PMOS transistor 74 and the second PMOS transistor 78 can remain off because the difference between the source voltage (e.g., the envelope voltage) and the gate voltage (e.g., the gate voltage) is low.zero volts) is smaller than the threshold voltage of the PMOS transistors 74 and 78.

[0055] If the envelope voltage is below the threshold range, the power switching amplifiers 64A and 64B can function as dual NMOS inverters, with the first NMOS transistor 76 coupled in parallel to the second NMOS transistor of the opposite branch. In particular, if the analog electrical input signal (e.g., +V) in or-V in If the received analog electrical signal is high, the first NMOS transistor 76 is switched on and the second NMOS transistor 80 of the opposite branch can be switched off, thus connecting the output to ground. Conversely, if the received analog electrical signal is low, then the first NMOS transistor 76 can be switched off and the second NMOS transistor 80 of the opposite branch can be switched on, thus connecting the output to the envelope voltage supply rail 70.

[0056] Furthermore, since the power switching amplifiers 64A and 64B function as dual NMOS inverters, the effects of leakage current can be reduced. In particular, as described above, each transistor generally exhibits a parasitic capacitance that allows leakage current to flow. For example, in the illustrated embodiment, a first leakage current can flow through the first PMOS transistor 74A and the first NMOS transistor 76A in the first power switching amplifier 64A, and a second leakage current can flow through the second PMOS transistor 78B and the second NMOS transistor 80B of the second power switching amplifier 64B, both of which are connected to the positive, amplified, analog electrical signal +V. out can be supplied.

[0057] In general, the amount of leakage current conducted by a transistor can be at least partially based on the transistor's parasitic capacitance. Since the parasitic capacitance across the first PMOS transistor 74A and the first NMOS transistor 76A is generally equal to the parasitic capacitance across the second NMOS transistor 80B and the second PMOS transistor 78B, the magnitude of the first leakage current and the second leakage current are approximately identical. Furthermore, since the analog input signals (e.g., +V) in and-V in ) are inverses of each other, the phase of the first leakage current and the second leakage current can also be inverses of each other (e.g. opposites), thus canceling each other out.

[0058] Similarly, in the illustrated embodiment, a third leakage current can flow through the first PMOS transistor 74B and the first NMOS transistor 76B of the second power switching amplifier 64B, and a fourth leakage current can flow through the second PMOS transistor 78A and the second NMOS transistor 80A of the first power switching amplifier, both of which are connected to the negative, amplified, analog electrical signal V out can be supplied. However, since the analog input signals (e.g., -V) in and +V in Since the parasitic capacitances are inverses of each other and the parasitic capacitance is approximately equal, the third leakage current and the fourth leakage current can also cancel each other out.

[0059] In this way, the power switching amplifiers 64A and 64B can be operated to reduce the effect of leakage current, especially when the output power is low (e.g., below an output power threshold range), thus improving the linearity of the control over the output power and the consistency of the phase shift between the analog electrical input and the analog electrical output signal. Additionally, the power switching amplifiers 64A and 64B can be operated to reduce the DC current consumption supplied by the power source 22, especially when the output power is high (e.g., above the output power threshold range), thus improving the efficiency (e.g., power / DC consumption) of the radio frequency system 12.

[0060] To further illustrate this, in Fig. Figure 9 describes an embodiment of a process 86 for operating power switching amplifiers 64. In general, the method includes determining the envelope voltage (process block 88), determining whether the envelope voltage is less than a threshold range (decision block 90), using a dual NMOS inverter if the envelope voltage is less than the threshold range (process block 92), determining whether the envelope voltage is greater than the threshold range if the envelope voltage is not less than the threshold range (decision block 94), using an NMOS / PMOS inverter if the envelope voltage is greater than the threshold range (process block 96), and using a combination of the dual NMOS inverter and the NMOS / PMOS inverter if the threshold voltage is not greater than the threshold range (process block 100).In some embodiments, the process 86 may be implemented using instructions stored in the memory 16 and / or another suitable, tangible, non-volatile, computer-readable medium and may be executed by the processor 18 and / or another suitable processing circuit.

[0061] Accordingly, the radio frequency system 12 can determine the envelope voltage (process block 88). In some embodiments, the radio frequency system 12 can query the transceiver 38 for the envelope voltage output, which is used to generate the desired output power. Additionally or alternatively, the radio frequency system 12 can include one or more sensors (e.g., voltage sensors) to measure the voltage output by the transceiver and / or the voltage output at the envelope voltage supply rail 70.

[0062] The radio frequency system 12 can then determine whether the envelope voltage is less than a threshold range (decision block 90). In some embodiments, the threshold range can include voltages between the threshold voltage of the PMOS transistors (e.g., 74 and 78) and the voltage of the analog input signal, when high, minus the threshold voltage of the NMOS transistors (e.g., 76 and 80). Additionally, in some embodiments, the threshold range can be predefined and stored in the memory 16 and / or the data storage device 20. Accordingly, in such embodiments, the radio frequency system 12 can retrieve the threshold range and compare it with the envelope voltage.

[0063] If the envelope voltage is lower than the threshold range, the radio frequency system 12 can operate the power switching amplifiers 64 as a dual NMOS inverter (process block 92). Specifically, the radio frequency system 12 can keep the first PMOS transistor 74 and the second PMOS transistor 78 in an off state. Additionally, the radio frequency system 12 can connect the first NMOS transistor 76 of one branch in parallel with the second NMOS transistor 80 of the other branch. As described above, the dual NMOS inverters can cancel the leakage current, thereby improving the linearity and / or consistency of the phase shift, particularly at low output powers (e.g., low envelope voltage).

[0064] On the other hand, if the envelope voltage is not less than the threshold, the radio frequency system 12 can determine whether it is greater than the threshold (decision block 94). If the envelope voltage is greater than the threshold, the radio frequency system 12 can operate the power switching amplifiers 64 as NMOS / PMOS inverters (process block 96). In particular, the radio frequency system 12 can keep the second PMOS transistor 78 and the second NMOS transistor 80 in an off state. Additionally, the radio frequency system 12 can connect the first PMOS transistor 74 and the first NMOS transistor 76 of each branch in parallel. As described above, the use of NMOS / PMOS inverters can reduce power consumption, thereby improving efficiency, especially at high output powers (e.g., high envelope voltage).

[0065] Additionally, if the voltage is neither greater nor less than the threshold range, the radio frequency system can operate the power switching amplifiers 64 as a dual NMOS inverter coupled in parallel with an NMOS / PMOS inverter (process block 100). As described above, the threshold can be a range of voltages between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the analog electrical input signal, or, if high, the threshold voltage of the NMOS transistors 76 and 80. If the envelope voltage is within the threshold range, the transistors can be in a partially switched-on state.

[0066] As such, the radio frequency system 12 can operate the power switching amplifiers 64 using a combination of the first PMOS transistors 74, the first NMOS transistors 76, and the second NMOS transistors 80. In other words, each power switching amplifier 64 can output the amplified analog electrical signal, which is based at least partially on the current conducted through the first PMOS transistor 74 of that branch and the current conducted through the second NMOS transistor 80 of the opposite branch. In fact, as will be described in more detail below, the first PMOS transistor 74 and the second NMOS transistor 80 can be selected such that the sum of the output current varies linearly with the envelope voltage, even in the threshold region.

[0067] Thus, the techniques described herein describe power switching amplifiers 64 that can be used to improve the operation of a radio frequency system 12. An embodiment of a process 102 for manufacturing a pair of power switching amplifiers (e.g., 64A and 64B) is described in Fig. 10. In general, process 102 includes the formation of a first power switching amplifier (process block 104) and the formation of a second power switching amplifier (process block 106). In some embodiments, process 102 can be implemented by a manufacturer using instructions stored on any suitable physical, non-volatile, computer-readable medium and executable by any suitable processing circuit.

[0068] Accordingly, the manufacturer can form the first power switching amplifier (process block 104), which includes forming a first PMOS transistor (process block 108), a first NMOS transistor (process block 110), a second NMOS transistor (process block 112), and optionally a second PMOS transistor (process block 114). In some embodiments, the manufacturer can form the first PMOS transistor (e.g., the first PMOS transistor 74A) and the first NMOS transistor (e.g., the first NMOS transistor 76A) in the first power switching amplifier (e.g., power switching amplifier 64A) so that they are coupled in parallel. In particular, the first PMOS transistor 74 can be configured such that its source is electrically connected to an envelope voltage supply rail (e.g., V). env-supply rail) 70 can be coupled, its gate electrically connected to an analog electrical signal input to the first power switching amplifier (e.g. +V in ) can be coupled and its drain electrically connected to an output of the first power switching amplifier (e.g. +V out ) can be coupled, and the first NMOS transistor 76 can be configured such that its source can be electrically coupled to ground 72, its gate can be electrically coupled to the analog electrical signal input to the first power switching amplifier, and its drain can be electrically coupled to the output of the first power switching amplifier.

[0069] Additionally, the second NMOS transistor (e.g., the second NMOS transistor 80A) in the first power switching amplifier can be configured such that its gate can be electrically connected to the analog electrical signal input of the first power switching amplifier, its drain can be electrically coupled to the envelope voltage supply rail 70, and its source can be electrically coupled to an output of the second power switching amplifier. Furthermore, the second PMOS transistor (e.g., the second PMOS transistor 78A) can be configured to be coupled in parallel with the second NMOS transistor 80.In particular, the second PMOS transistor 78 in the first power switching amplifier can be configured such that its gate can be electrically coupled to the analog electrical signal input to the first power switching amplifier, its drain can be electrically connected to ground 72, and its source can be electrically coupled to the output of the second power switching amplifier.

[0070] It should be noted that with regard to the embodiment of the power switching amplifiers 64A and 64B, which are described in Fig. As described in section 7, the second PMOS transistor 78 is generally kept in an off state. In fact, as will be described in more detail below, even if the second PMOS transistor 78 is omitted, the effects of the leakage current can still be reduced. As such, the second PMOS transistor 78 can optionally be implemented in the first power switching amplifier.

[0071] Similar to the first power switching amplifier, the manufacturer can construct the second power switching amplifier (process block 106), which includes constructing a first PMOS transistor (process block 116), a first NMOS transistor (process block 118), a second NMOS transistor (process block 120), and optionally a second PMOS transistor (process block 122). In some embodiments, the manufacturer can construct the first PMOS transistor (e.g., the first PMOS transistor 74B) and the first NMOS transistor (e.g., the first NMOS transistor 76B) in the second power switching amplifier (e.g., power switching amplifier 64B) so that they are coupled in parallel. In particular, the first PMOS transistor 74 can be configured such that its source is electrically connected to an envelope voltage supply rail (e.g., V). env-supply rail) 70 can be coupled, its gate electrically connected to the analog electrical signal input to the second power switching amplifier (e.g. -V in ) can be coupled and its drain electrically connected to an output of the second power switching amplifier (e.g. -V out ) can be coupled, and the first NMOS transistor 76 can be configured such that its source can be electrically coupled to ground 72, its gate can be electrically coupled to the analog electrical signal input to the second power switching amplifier, and its drain can be electrically coupled to the output of the second power switching amplifier.

[0072] Additionally, the second NMOS transistor (e.g., the second NMOS transistor 80B) can be configured such that its gate can be electrically coupled to the analog electrical signal input of the second power switching amplifier, its drain can be electrically coupled to the envelope voltage supply rail 70, and its source can be electrically coupled to the output of the first power switching amplifier. Furthermore, the second PMOS transistor (e.g., the second PMOS transistor 78B) can be configured to be coupled in parallel with the second NMOS transistor 80. In particular, the second PMOS transistor 78 can be configured such that its gate can be electrically coupled to the analog electrical signal supplied to the second power switching amplifier, its drain can be electrically coupled to ground 72, and its source can be electrically coupled to the output of the first power switching amplifier.

[0073] Furthermore, as with the first power switching amplifier, the second PMOS transistor 78 can optionally be implemented in the second power switching amplifier, while still reducing the effects of the leakage current. For illustration, see in Fig. 11 describes an embodiment of the power switching amplifiers 64 without the second PMOS transistors 78. Similar to the embodiment in Fig. In the embodiment described in section 7, a first power switching amplifier 64C receives a positive, analog electrical signal +V in , a second power switching amplifier 64D receives a negative, analog electrical signal -V in , and both power switching amplifiers 64C and 64D are coupled in parallel between an envelope voltage supply rail 70 and ground 72.

[0074] Furthermore, the first power switching amplifier 64C and the second power switching amplifier 64D, as shown, each include the first PMOS transistor 74, the first NMOS transistor 76, the second NMOS transistor 80, and the measurement components (e.g., the capacitor 82 and the inductor 84 in series). Specifically, the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel such that the source of the first PMOS transistor 74 is electrically coupled to the envelope voltage supply rail 70, the source of the first NMOS transistor 76 is electrically coupled to ground 72, the drains are electrically coupled to the measurement components, and the gates are electrically coupled to the analog input signal.Additionally, the second NMOS transistor 80 is coupled such that the drain is electrically coupled to the envelope voltage supply rail 70, the source is electrically coupled to the measurement components of the opposite branch, and the gate is electrically coupled to the analog electrical input signal. Furthermore, the NMOS transistors 76 and 80 can generally exhibit the same operating characteristics (e.g., parasitic capacitances and / or leakage current).

[0075] Similar to the one in Fig. In the embodiment described in section 7, the power switching amplifiers 64C and 64D can function as NMOS / PMOS inverters when the envelope voltage is above the threshold range, as dual NMOS inverters when the envelope voltage is below the threshold range, and as combination inverters (e.g., an NMOS / PMOS inverter coupled in parallel with a dual NMOS inverter) when the envelope voltage is within the threshold range. For illustration, the following is described. Fig. 12A the operation of the power switching amplifiers 64C and 64D when the envelope voltage (e.g. V) envHigh ) above the threshold range, and Fig. Section 8B describes the operation of the power switching amplifiers 64C and 64D when the envelope voltage (e.g. V) envLow ) is below the threshold range.

[0076] As in Fig. As shown in Figure 12A, if the envelope voltage is higher than the threshold range, the second NMOS transistors 80 can be kept in an off state, since their threshold voltage (e.g., gate-to-source voltage) is greater than the difference between the voltage of the analog electrical input signal (e.g., +V). in or-V in ) and the envelope voltage (e.g. V envHigh In other words, when the analog electrical input signal is low, the second NMOS transistor 80 can be switched off because the gate voltage is approximately zero volts. Additionally, the second NMOS transistor 80 can remain switched off even when the analog electrical input signal is high because the difference between the gate voltage (e.g., the voltage of the analog electrical input signal) and the source voltage (e.g., the envelope voltage) is less than the threshold voltage of the second NMOS transistor 80.

[0077] As such, if the envelope voltage is above the threshold range, the power switching amplifiers 64C and 64D can function as NMOS / PMOS inverters, with the first PMOS transistor 74 and the first NMOS transistor 76 coupled in parallel. In particular, in each power switching amplifier 64C and 64D, if the analog electrical input signal (e.g., +V) in or-V in When the analog electrical input signal is high, the first PMOS transistor 74 is switched off, and the first NMOS transistor 76 can be switched on, thus connecting the output to ground. Conversely, when the analog electrical input signal is low, the first NMOS transistor 76 can be switched off, and the first PMOS transistor 74 can be switched on, thus connecting the output to the envelope voltage supply rail 70. In this way, the first power switching amplifier 64C outputs a positive, amplified, analog electrical signal +V. outoff, and the second power switching amplifier 64D outputs a negative, amplified, analog electrical signal-V out at a desired output power.

[0078] On the other hand, as in Fig. As shown in Figure 12B, when the envelope voltage is lower than the threshold, the first PMOS transistor 74 is held in an off state. As described above, the threshold can be voltages between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the analog electrical input signal when it is high, minus the threshold voltage of the NMOS transistors 76 and 80. Thus, when the analog electrical input signal is high, the first PMOS transistor 74 can be off, since its gate voltage is the positive voltage of the analog electrical input signal. Additionally, even when the analog electrical input signal is low, the first PMOS transistor 74 can remain off because the difference between the source voltage (e.g., the envelope voltage) and the gate voltage (e.g., zero volts) is smaller than the threshold voltage of the first PMOS transistor 74.

[0079] If the envelope voltage is below the threshold range, the power switching amplifiers 64C and 64D can function as dual NMOS inverters, with the first NMOS transistor 76 coupled in parallel to the second NMOS transistor 80 of the opposite branch. In particular, if the analog electrical input signal (e.g., +V) in or-V in If the analog electrical input signal is high, the first NMOS transistor 76 is switched on, and the second NMOS transistor 80 of the opposite branch can be switched off, thus connecting the output to ground. Conversely, if the analog electrical input signal is low, then the first NMOS transistor 76 can be switched off, and the second NMOS transistor 80 of the opposite branch can be switched on, thus connecting the output to the envelope voltage supply rail 70.

[0080] Furthermore, although the power switching amplifiers 64C and 64D do not include the second PMOS transistor 78, the effects of the leakage current can still be reduced. For example, in the illustrated embodiment, a first leakage current can flow through the first PMOS transistor 74C and the first NMOS transistor 76C in the first power switching amplifier 64C, and a second leakage current can flow through the second NMOS transistor 80D of the second power switching amplifier 64D, both of which are connected to the positive, amplified, analog electrical signal +V. outcan be supplied. However, since the parasitic capacitance across the first PMOS transistor 74C and the first NMOS transistor 76C may differ from the parasitic capacitance across the second NMOS transistor 80D, the magnitude of the first and second leakage currents may vary slightly and thus may not completely cancel each other out. Nevertheless, as will be explained in more detail below, a small amount of remaining leakage current may not significantly affect the operation of the power switching amplifiers 64C and 64D.

[0081] Similarly, in the illustrated embodiment, a third leakage current can flow through the first PMOS transistor 74D and the first NMOS transistor 76D of the second power switching amplifier 64D, and a fourth leakage current can flow through the second NMOS transistor 80C of the first power switching amplifier 64C, both of which are connected to the negative, amplified, analog electrical signal V outcan be supplied. Since the parasitic capacitance across the first PMOS transistor 74D and the first NMOS transistor 76D may differ from the parasitic capacitance across the second NMOS transistor 80C, the magnitude of the third and fourth leakage currents may vary slightly and thus may not completely cancel each other out. Nevertheless, a small amount of remaining leakage current may not significantly affect the operation of the power switching amplifiers 64C and 64D.

[0082] To illustrate, he describes Fig. 13 the output power of the amplified analog electrical signal and the phase shift between the analog electrical input and output signals of the power switching amplifiers 64C and 64D in relation to the envelope voltage. In particular, Fig. Figure 13 shows a graphical representation that includes an output power curve 124, which describes the output power of the amplified analog electrical signal, and a phase shift curve 126, which describes a phase shift between the analog electrical input signals and the analog electrical output signals.

[0083] As described by the phase shift curve 126, the phase shift between the analog electrical input signal and the analog electrical output signal is relatively constant. In some embodiments, the phase shift can vary by a few degrees with the envelope voltage. However, such a small phase shift can be accounted for in software in the radio frequency system 12. In other words, any effect of the leakage current on the consistency of the phase shift between the analog electrical input and output signals may not significantly affect the operation of the power switching amplifiers 64.

[0084] Additionally, as described by output power curve 124, the output power of the 64C and 64D power switching amplifiers varies relatively linearly from a minimum output power, when the envelope voltage is at its minimum, to a maximum output power, when the envelope voltage is at its maximum. In fact, the linearity of the changes in output power is maintained even at low envelope voltages (e.g., at the minimum). In other words, any leakage current present has only a negligible effect on the linearity of the control over the output power of the amplified analog electrical signal.

[0085] As described above, linearity in output power adjustments can be achieved by using two NMOS inverters when the envelope voltage is below the threshold, by NMOS / PMOS inverters when the envelope voltage is above the threshold, and by combination inverters (e.g., parallel dual NMOS inverters and NMOS / PMOS inverters) when the envelope voltage is within the threshold. To illustrate this, [reference to relevant section] Fig. 14 an example of a current passed through the first NMOS transistor 76 and the first PMOS transistor 74 in a first power switching amplifier (e.g. power switching amplifier 64C) and a current passed through the second NMOS transistor 80 in a second power switching amplifier (e.g. power switching amplifier 64D) in relation to the envelope voltage.

[0086] In particular, Fig. Figure 14 shows a graphical representation that includes a first NMOS current curve 128, which describes the current conducted through the first NMOS transistor 76, a PMOS current curve 130, which describes the current conducted through the first PMOS transistor 74, and a second NMOS current curve 132, which describes the current conducted through the second NMOS transistor 80. Since the first NMOS transistor 76 is always switched on when the power switching amplifier 64 outputs an amplified analog electrical signal, the first NMOS current curve 128 can also describe a current output to the measurement components.

[0087] In the illustrated embodiment, the threshold range can lie between a lower threshold voltage and an upper threshold voltage. Thus, as shown, when the envelope voltage is lower than the lower threshold voltage, the second NMOS transistor 80 is switched on to supply electrical energy, while the first PMOS transistor 74 is switched off, generally making it function as a dual NMOS inverter. Additionally, when the envelope voltage is higher than the upper threshold voltage, the first PMOS transistor 74 is switched on to supply electrical energy, while the second NMOS transistor 80 is switched off, generally making it function as an NMOS / PMOS inverter.

[0088] Furthermore, if the envelope voltage lies between the lower and upper threshold voltages, the first PMOS transistor 74 and the second NMOS transistor 80 can both be partially switched on to each supply a portion of the electrical power, thus operating the power switching amplifier 64 as a combination inverter (e.g., a dual NMOS inverter and an NMOS / PMOS inverter in parallel). In fact, as shown, the linearity of the output power is generally maintained even when the envelope voltage lies between the lower and upper threshold voltages. As such, the transistors can be selected to provide a smooth, gradual transition within the threshold range between the power switching amplifier 64 operating as a dual NMOS inverter and as an NMOS / PMOS inverter.

[0089] To further illustrate the improved linearity of the output power, describes Fig. 15 amplified analog electrical signals output by a power switching amplifier 64 (e.g., output powers) when a quadratic analog electrical signal and variable envelope voltages are introduced. In particular, shows Fig. 15 a graphical representation that shows a first output curve 134 describing the amplified analog electrical signal when the envelope voltage is a first (e.g., minimum) envelope voltage, a second output curve 136 describing the amplified analog electrical signal when the envelope voltage is a second envelope voltage, a third output curve 138 describing the amplified analog electrical signal when the envelope voltage is a third envelope voltage, a fourth output curve 140 describing the amplified analog electrical signal when the envelope voltage is a fourth envelope voltage, a fifth output curve 142 describing the amplified analog electrical signal when the envelope voltage is a fifth envelope voltage, a sixth output curve 144 describing the amplified analog electrical signal when the envelope voltage is a sixth envelope voltage (e.g.,lower threshold voltage), a seventh output curve 146 that describes the amplified analog electrical signal when the envelope voltage is a seventh envelope voltage, an eighth output curve 148 that describes the amplified analog electrical signal when the envelope voltage is an eighth envelope voltage (e.g., upper threshold voltage), a ninth output curve 150 that describes the amplified analog electrical signal when the envelope voltage is a ninth envelope voltage, a tenth output curve 152 that describes the amplified analog electrical signal when the envelope voltage is a tenth envelope voltage, and an eleventh output curve 154 that describes the amplified analog electrical signal when the envelope voltage is an eleventh (e.g., maximum) envelope voltage.

[0090] As illustrated by output curves 134-154, the fidelity of the analog electrical input signal is maintained by the amplified analog electrical signal even when the envelope voltage is low (e.g., the minimum envelope voltage). Furthermore, the fidelity of the input curve of the analog electrical input signal is maintained by the amplified analog electrical signal even when the envelope voltage lies within the threshold range (e.g., between the lower and upper threshold voltages). As such, the techniques described here can reduce the effects of leakage current on the operation of a power switching amplifier 64, thereby improving linearity and phase shift.

[0091] Furthermore, as described above, the efficiency (e.g., output power / DC consumption) of the radio frequency system can also be improved by using a combination of dual NMOS inverters and NMOS / PMOS inverters. To illustrate this, the following describes Fig. 16 the DC current consumption by the one or more power amplifiers (e.g., inverters) 62, the DC current consumption by a power switching amplifier 64, the total DC current consumption of the one or more preamplifiers 62 and the power switching amplifier 64, and the efficiency of the amplifier component 40 in relation to the envelope voltage. In particular, Fig.16 a graphical representation which includes a power amplifier power consumption curve 156, which describes the DC consumption by the one or more preamplifiers 62, a power switching amplifier power consumption curve 158, which describes the DC consumption by the power switching amplifier 64, a total power consumption curve 160, which describes the total DC consumption by the one or more preamplifiers 62 and the power switching amplifier 64, and an efficiency curve 162, which describes the efficiency of the amplifier component 40.

[0092] As described by the power amplifier power consumption curve 156, the DC current consumption of the one or more preamplifiers 62 remains relatively constant from the minimum envelope voltage to the maximum envelope voltage. Additionally, as described by the power switching amplifier power consumption curve 158, the DC current consumption of the power switching amplifier 64 increases relatively linearly from the minimum envelope voltage to the maximum envelope voltage. Thus, as described by the total power consumption curve 160, the total DC current consumption of the power switching amplifier 64 and the one or more preamplifiers 62 also increases relatively linearly from the minimum envelope voltage to the maximum envelope voltage.

[0093] Furthermore, with increasing envelope voltage (e.g., increasing output power), the efficiency (e.g., output power / DC consumption) also increases. In fact, as described by efficiency curve 162, the efficiency can increase at a slower rate when the envelope voltage is below the lower threshold voltage (e.g., below the threshold range) and at a faster rate when the envelope voltage is above the upper threshold voltage (e.g., above the threshold range). In particular, the difference in the efficiency increase can be a result of operating the power switching amplifier 64 as a dual NMOS inverter below the threshold range and operating the power switching amplifier 64 as an NMOS / PMOS inverter above the threshold range. In this way, the efficiency of amplifier component 40 can reach 50.7% when the envelope voltage is at the maximum envelope voltage.

[0094] In fact, the efficiency of amplifier component 40 may be limited to 66% due to the power consumption of the envelope voltage amplifier 46 and / or the measurement components (e.g., capacitor 82 and inductor 84). As such, the techniques described herein can allow the one or more preamplifiers 62 and the power switching amplifier 64 to achieve an efficiency of 76.81% relative to the maximum achievable efficiency.

[0095] Accordingly, the technical implications of this disclosure include the improvement of the operation of a power switching amplifier used in a radio frequency system. Specifically, the linearity of the output power adjustments and the consistency of the phase shift between analog electrical input and output signals can be improved by operating the power switching amplifier as a dual NMOS inverter when the desired output power is low (e.g., an envelope voltage below a threshold), thereby reducing the effects of leakage current. Additionally, the efficiency of the radio frequency system can be improved by operating the power switching amplifier as an NMOS / PMOS inverter when the desired output power is high (e.g., an envelope voltage above the threshold), thereby reducing the power consumption of the power switching amplifier.

[0096] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be subject to numerous modifications and alternative forms. It should further be understood that the claims are not intended to be limited to the specific disclosed forms, but rather to cover all modifications, equivalents, and alternatives that are within the spirit and scope of this disclosure.

Claims

[1] Radio frequency system (12) configured to enable wireless communication of data between electronic devices (10), comprising: a first power switching amplifier (64A, 64C) and a second power switching amplifier (64B, 64D), wherein the first power switching amplifier (64A, 64C) is configured to transmit a first amplified analog electrical signal, which is transmitted with a desired output power, at least partially based on a first analog electrical input signal and an envelope voltage of an envelope voltage supply rail (70), wherein the first power switching amplifier (64A, 64C) comprises: a first transistor (74A, 74C) of the first power switching amplifier (64A, 64C), wherein a gate of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a source of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) is electrically connected to the envelope voltage supply rail (70), and a drain of the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) is electrically connected to the first output of the first power switching amplifier (64A, 64C); a second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) connected in parallel to the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C), wherein a gate of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a source of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) is electrically connected to ground (72), and a drain of the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) is electrically connected to the first output of the first power switching amplifier (64A, 64C); and a third transistor (80A, 80C) of the first power switching amplifier (64A, 64C), wherein a gate of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a drain of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) is electrically connected to the envelope voltage supply rail (70) is coupled, and a source of the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) is electrically coupled to a second output of a second power switching amplifier (64B, 64D). [2] Radio frequency system (12) according to claim 1, wherein the second power switching amplifier (64B, 64D) is configured to transmit a second amplified analog electrical signal, which is transmitted with the desired output power, at least partially based on a second analog electrical input signal and the envelope voltage of the envelope voltage supply rail (70), wherein the second power switching amplifier (64B, 64D) comprises: a first transistor (74B, 74D) of the second power switching amplifier (64B, 64D), wherein a gate of the first transistor (74B, 74D) of the second power switching amplifier (64B, 64D) receives the second analog electrical input signal, a source of the first transistor (74B, 74D) of the second power switching amplifier (64B, 64D) is electrically connected to the envelope voltage supply rail (70), and a drain of the first transistor (74B, 74D) of the second power switching amplifier (64B, 64D) is electrically connected to the second output of the second power switching amplifier (64B, 64D); a second transistor (76B, ​​76D) of the second power switching amplifier (64B, 64D) connected in parallel to the first transistor (74B, 74D) of the second power switching amplifier (64B, 64D), wherein a gate of the second transistor (76B, ​​76D) of the second power switching amplifier (64B, 64D) receives the second analog electrical input signal, a source of the second transistor (76B, ​​76D) of the second power switching amplifier (64B, 64D) is electrically coupled to ground (72), and a drain of the second transistor (76B, ​​76D) of the second power switching amplifier (64B, 64D) is electrically connected to the second output of the second power switching amplifier (64B, 64D); and a third transistor (80B, 80D) of the second power switching amplifier (64B, 64D), wherein a gate of the third transistor (80B, 80D) of the second power switching amplifier (64B, 64D) receives the second analog electrical input signal, a drain of the third transistor (80B, 80D) of the second power switching amplifier (64B, 64D) is electrically coupled to the envelope voltage supply rail (70), and a source of the third transistor (80B, 80D) of the second power switching amplifier (64B, 64D) is electrically coupled to the first output of the first power switching amplifier (64A, 64C). [3] Radio frequency system (12) according to claim 2, wherein the first analog electrical input signal and the second analog electrical input signal are inverses of each other, and the first amplified analog electrical signal and the second amplified analog electrical signal are inverses of each other. [4] Radio frequency system (12) according to claim 1, wherein the first power switching amplifier (64A, 64C) comprises a fourth transistor (78A) connected in parallel to the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C), wherein a gate of the fourth transistor (78A) of the first power switching amplifier (64A, 64C) receives the first analog electrical input signal, a drain of the fourth transistor (78A) of the first power switching amplifier (64A, 64C) is electrically connected to ground (72), and a source of the fourth transistor (78A) of the first power switching amplifier (64A, 64C) is electrically connected to the second output of the second power switching amplifier (64B, 64D). [5] Radio frequency system (12) according to claim 1, wherein the first power switching amplifier (64A, 64C) comprises a capacitor (B2) and an inductor (B4) connected to the first output of the first power switching amplifier (64A, 64C), wherein the capacitor (B2) and the inductor (B4) are configured to smooth the first amplified analog electrical signal. [6] Radio frequency system (12) according to claim 1, wherein the second transistor (76A, 76C) of the first power switching amplifier (64A, 64C) and the third transistor (80A, 80C) of the first power switching amplifier (64A, 64C) are n-type metal oxide semiconductor transistors, NMOS, and the first transistor (74A, 74C) of the first power switching amplifier (64A, 64C) is a p-type metal oxide semiconductor transistor, PMOS.

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