Stacked transistors with the last contact formed

Abstract

Integrated circuit arrangement structure, which includes the following: a first transistor (106; 206; 306) comprising a source region (112; 214; 314) and a drain region (114; 216; 316) with a channel region (108; 208; 308) in between; a first dielectric layer (116; 218; 318) over the first transistor (106; 206; 306); a second transistor (126; 232; 332) comprising a source region (132; 238; 338) and a drain region (134; 242; 342) with a channel region (128; 234; 334) in between, the second transistor (126; 232; 332) being located above the first dielectric layer (116; 218; 318); a second dielectric layer (136; 244; 344) over the second transistor (126; 232; 332); and a first contact (140; 347; 352), wherein the first contact (140; 347; 352) is coupled to the source region (112; 314) of the first transistor (106; 206; 306), wherein the first contact (140; 347; 352) comprises a metal with a side wall (146) extending through both the first (116; 318) and the second dielectric layer (136; 344); and a second contact (144; 348; 354), wherein the second contact (144; 348; 354) is coupled to the drain region (114; 316) of the first transistor (106; 306), wherein the second contact (144) comprises a metal and a side wall (148) that is orthogonal to a surface (138) of the second dielectric layer (136), wherein the second contact (144) extends through both the first (116) and the second dielectric layer (136); and a third contact (142; 346; 356) coupled to the source region (132; 338) or the drain region (342) of the second transistor (126; 332), wherein the third contact (142; 346; 356) comprises a metal and is formed directly on or below the surface of the source region (132; 338) or the drain region (342) of the second transistor (126; 332).

Description

GENERAL STATE OF THE ART

[0001] As more and more transistors need to be integrated into smaller dimensions, the focus in semiconductor devices has shifted to stacking transistors. While stacking transistors has the potential to achieve more highly integrated devices, the processing of the subsequently formed transistors can expose the previously formed lower device layers to potentially damaging conditions. For example, a high-temperature annealing process could damage a previously formed feature, such as a metal contact. Partly due to the very small dimensions of the transistor metal contacts, any creeping or cracking damage could impede the formation of a subsequent conductive connection. Poor metal connections between separate contacts can create increased resistance, which can ultimately lead to device failure.Document US 2015 / 0348909A1 discloses a device in the form of a circuit arrangement structure comprising a first transistor with a source region, a drain region and a channel region in between, wherein a first dielectric layer is arranged over the first transistor, wherein a second transistor with a source region, a drain region and a channel region in between is located on the dielectric layer, wherein a second dielectric layer is located over the second transistor and comprises a contact, wherein the contact comprises a metal with a side wall extending through the first and second dielectric layers, and wherein the contact is coupled to the source region or the drain region of the first transistor.Patent application US 2002 / 0119640A1 discloses a device in the form of a circuit arrangement structure comprising a first transistor with a source region, a drain region and a channel region in between, wherein a first dielectric layer is arranged over the first transistor, wherein a second transistor with a source region, a drain region and a channel region in between is located on the dielectric layer, wherein a second dielectric layer is located over the second transistor and includes a contact, the contact being coupled to the source region or the drain region of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be more fully understood from the detailed description provided below and from the accompanying drawings of various embodiments of the disclosure, which, however, are not intended to limit the disclosure to the specific embodiments, but merely serve for explanation and understanding. Fig. Figure 1 illustrates a cross-sectional view of an example semiconductor device with stacked transistors with the last contact formed according to some embodiments. Fig. Figures 2A - 2F illustrate cross-sectional views of manufacturing steps of semiconductor devices with stacked transistors with the contact formed last according to some embodiments. Fig. Figures 3A and 3B illustrate cross-sectional views of other example semiconductor devices with stacked transistors with the last contact formed according to some embodiments. Fig. Figure 4 illustrates a flowchart of a method for forming a semiconductor device with stacked transistors with a contact formed last, in accordance with some embodiments, and Fig. Figure 5 illustrates an intelligent device or computer system or system-on-a-chip (SoC) which includes a semiconductor device with stacked transistors with last formed contact, according to some embodiments. DETAILED DESCRIPTION

[0003] Stacked transistors with the contact formed last are generally described. In this respect, embodiments of the present disclosure can enable high-quality electrical contacts. The elimination of potentially poorly conductive couplings between separate metal contacts, which are formed independently, can result in reduced resistance in the electrical conduction. A person skilled in the art would be aware that this approach can enable more highly integrated semiconductor devices with lower energy consumption.

[0004] Numerous details are discussed in the following description to provide a more thorough explanation of embodiments of the present disclosure. However, it will be obvious to a person skilled in the art that embodiments of the present disclosure can also be implemented in practice without these specific details. In other cases, well-known structures and components are shown in the form of a block diagram rather than in detail to avoid obscuring embodiments of the present disclosure.

[0005] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more important signal paths and / or have arrows at one or more ends to indicate a primary direction of information flow. Such indications are not intended to be restrictive. Rather, the lines are used in conjunction with one or more exemplary embodiments to facilitate a simpler understanding of a circuit or logic unit. Any signal shown may, as dictated by design requirements or preferences, actually comprise one or more signals that can move in any direction and may be implemented with any suitable type of signal scheme.

[0006] Throughout this specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the connected items without any intervening components. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the connected items, or an indirect connection via one or more passive or active intervening components. The term "circuit" or "module" may refer to one or more passive and / or active components capable of cooperating to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of "a" and "the" includes references to the plural form.The meaning of "in" includes "in" and "on".

[0007] Unless otherwise specified, the use of the ordinal adjectives 'first', 'second', 'third', etc., to describe a common object merely indicates that different instances of the same object are being referred to, and is not intended to imply that the objects so described must be in any given order, whether temporal, spatial, rank-wise, or in any other way.

[0008] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The terms “left,” “right,” “front,” “back,” “above,” “below,” “over,” “under,” and the like in the description and in the claims are used, where present, for descriptive purposes and not necessarily to describe permanent relative positions.

[0009] Fig. Figure 1 illustrates a cross-sectional view of an example semiconductor device with stacked transistors with the last contact formed according to some embodiments. As shown, the device 100 includes the substrate 102, the semiconductor layer 104, the transistor 106, the channel region 108, the gate stack 110, the source region 112, the drain region 114, the dielectric layer 116, the wire 118, the etch stop 120, the binder layer 122, the semiconductor layer 124, the transistor 126, the channel region 128, the gate stack 130, the source region 132, the drain region 134, the dielectric layer 136, the dielectric surface 138, the contacts 140, 142 and 144 and the contact sidewalls 146 and 148. While the device 100 is shown to include raised source / drain (RSD) transistors, it can be incorporated in other embodiments different topologies, such as FinFET transistors, or different components, such as...Diodes are included.

[0010] In some embodiments, the substrate 102 comprises at least one layer of an undoped semiconductor, such as Ge, Si, SiGe, InGaAs, AlSb, etc. In some embodiments, the semiconductor layer 104, which may include the channel region 108, can be formed separately from the substrate 102 and can contain different semiconductor materials, including, but not limited to, InGaAs, InAs, InGaAs, InGaAsSb, InSb, GaSb, Ge, or SiGe. The substrate 102 can be composed of one or more semiconductor material layers on top of another semiconductor material, such as silicon.

[0011] When transistor 106 is in an active mode, channel region 108 can serve as a channel between source region 112 and drain region 114, which are located on opposite sides of channel region 108. In some embodiments, transistor 106 can be a PMOS or NMOS transistor, and source region 112 and drain region 114 are p-doped or n-doped variants of the same semiconductor as channel region 108.

[0012] The gate stack 110 can include a gate dielectric, a gate region, and spacers on the channel region 108. The gate stack 110 can include metallic or polycrystalline silicon coupled with intermediate compounds (not shown) to provide a voltage near the channel region 108 to switch the transistor 106 into an active mode. In some embodiments, the gate stack 110 can include one or more layers of oxides and / or nitrides.

[0013] In some embodiments, the wire 118 and the etch stop 120 can be present as part of a process for creating a conductive contact with the source region 112 and the drain region 114, respectively, as shown in more detail below. In other embodiments, contacts, such as contact 140 or contact 144, can be formed directly on or within the source region 112 and / or the drain region 114.

[0014] The dielectric layer 116 can encapsulate the transistor 106 and insulate electrical connections. In some embodiments, the dielectric 116 can be an interlayer dielectric (ILD), such as silicon dioxide or another dielectric with a low k-value. The dielectric layer 116 can be formed by any known method, such as chemical vapor deposition.

[0015] The bonding layer 122 may be present in some embodiments to connect the semiconductor layer 124 to the dielectric layer 116. In some embodiments, the semiconductor layer 124 may be epitaxially grown on a separate substrate and then transferred and bonded to the dielectric layer 116 via the bonding layer 122, which may, for example, be a polymer adhesive. In other embodiments, the bonding layer 122 may not be present, and the semiconductor layer 124 may be deposited over the dielectric layer 116. In some embodiments, the semiconductor layer 124 may have the same semiconductor material as the semiconductor layer 104, while in other embodiments, the semiconductor layer 124 may have a different semiconductor material than the semiconductor material 104.

[0016] Transistor 126 can be the same as transistor 106 or different from it. In some embodiments, component 100 can be a CMOS component and transistor 106 can be an NMOS transistor, while transistor 126 can be a PMOS transistor, or vice versa. In some embodiments, transistor 126 can be aligned with transistor 106, for example as shown, such that source region 132 and drain region 134 are located directly above source region 112 and drain region 114, respectively. In other embodiments, transistor 126 can be offset from transistor 106.

[0017] In some embodiments, the contacts 140, 142, and 144 can be formed by the dielectric surface 138 and can be made of any metallic or other conductive material, including, but not limited to, copper, tungsten, tantalum, titanium, aluminum, or palladium. In some embodiments, the contact 140 can be formed by the dielectric layer 136, the semiconductor layer 124, the binder layer 122, and the dielectric layer 116, thereby making contact with the wire 118. The contact sidewall 146 can be straight. As used herein, a straight sidewall may have some curvature or roughness, but without significant deviations at transitions between material layers, for example, between the binder layer 122 and the dielectric layer 116.In some embodiments, the contact sidewall 146 can be inclined such that the contact 140 at the dielectric surface 138 can be wider than at the wire 118. In some embodiments, the contact 142 can form a contact on, or in some cases, below a surface of the source region 132. In some embodiments, the contact 144 can be formed by the dielectric layer 136, the drain region 134, the semiconductor layer 124, the binder layer 122, the dielectric layer 116, and the etch stop 120, thereby being in contact with the drain region 114. In some embodiments, the contact sidewall 148 can be orthogonal to the dielectric surface 138, and the contact 144 can have a substantially constant width, within about 10%, from the dielectric surface 138 to the drain region 114.While a coupling of drain region 134 with drain region 114 has been shown, in some embodiments drain region 114 and drain region 134 can also be isolated from each other.

[0018] Fig. Figures 2A - 2F illustrate cross-sectional views of manufacturing steps of semiconductor devices with stacked transistors with the contact formed last according to some embodiments. Fig. 2A - 2F are not drawn to scale, and a gate contact is omitted for clarity. The embodiments of Fig. 2A - 2F may include features previously referred to Fig. 1 were described.

[0019] As in Fig. As shown in Figure 2A, the assembly 200 comprises the substrate 202, the semiconductor layer 204, the transistor 206, the channel region 208, the gate stack 212, the source region 214, and the drain region 216. In some embodiments, the substrate 202 can be undoped silicon, while the semiconductor layer 204 can be doped (n-type or p-type) silicon; however, other semiconductor materials can also be used. In some embodiments, the source region 214 and the drain region 216 can be epitaxially formed on the semiconductor layer 204 by known deposition techniques, such as atomic layer deposition (ALD). In some embodiments, the gate stack 212 can be formed by either gate-first or gate-last processes.

[0020] Fig. Figure 2B shows the assembly 210, which may include the dielectric layer 218, the wire 222, and the etch stop 224. In some embodiments, the wire 222, which may be made of copper or any other metal, may provide a contact formed by subsequent layers above it to couple with the source region 214. While the wire 222 is shown to be formed over a top surface of the source region 214, in some embodiments it may be in contact with a side wall or another surface of the source region 214. The etch stop 224 may be selected to stop a chemical etchant that could otherwise etch through the drain region 216. In some embodiments, the etch stop 224 may not be necessary; for example, an etchant may be selected to stop at the drain region 216, or laser etching may be used.

[0021] As in Fig. As shown in Figure 2C, the assembly 220 can include the binder layer 226 and the semiconductor layer 228. In some embodiments, the semiconductor layer 228 may have been transferred into the assembly 220 as part of a comprehensive transfer process, in which the semiconductor layer 228 was epitaxially formed on a separate substrate, isolated from that substrate, and then adhered to the dielectric layer 218 by the binder layer 226. In other embodiments, the binder layer 226 may not be required, for example, if the semiconductor layer 228 can be deposited directly over the dielectric layer 218.

[0022] Now, referring to Fig. In 2D, the assembly 230 can include the transistor 232, including the channel region 234, the gate stack 236, the source region 238, and the drain region 242. In some embodiments, the source region 238 and the drain region 242 can be heavily doped with a p-type dopant, such as boron or the like, or an n-type dopant, such as phosphorus or arsenic or the like. In some embodiments, the gate stack 236 can include a gate dielectric with a high k-value adjacent to the channel region 234.

[0023] Fig. Figure 2E shows the assembly 240, in which the dielectric layer 244 can be formed above the semiconductor layer 228 and the transistor 232. In some embodiments, the dielectric layer 244 can be a form of silicon dioxide or the like to provide insulation for conductive materials and to be further etched for the formation of intermediate connections.

[0024] As in Fig. As shown in Figure 2F, the assembly 250 can include the openings 252, 254, and 256 and the opening sidewalls 258 and 260. In some embodiments, the openings 252, 254, and 256 can be formed by one or more suitable forming techniques, including, but not limited to, chemical etching or laser etching. In some embodiments, a laser, for example, a CO2 laser, can form the opening 252 with the inclined sidewall 258 by ablation through the dielectric layer 244, the semiconductor layer 228, the binder layer 226, and the dielectric layer 218 before stopping at the metal wire 222.In some embodiments, a chemical etchant, for example an anisotropic etchant, can form the opening 256 with the vertical side wall 260 by etching through the dielectric layer 244, the drain region 252, the semiconductor layer 228, the binder layer 226, and the dielectric layer 218 before stopping at the etch stop 224. At least one section of the etch stop 224 can then be selectively etched to expose the drain region 216 for metal deposition. In some embodiments, a metal deposition using any suitable technique can fill the openings 252, 254, and 256 to create a device, such as the device 100.

[0025] Fig. Figures 3A and 3B illustrate cross-sectional views of other example semiconductor devices with stacked transistors with the last contact formed according to some embodiments. Fig. Figures 3A and 3B can represent alternative embodiments of component 100, which have regions of an upper transistor that are oriented differently relative to the lower transistor. While two examples are shown, a person skilled in the art would be aware that other transistor orientations or configurations would also be possible, which could implement contacts as described herein. Fig. The components 300 and / or 350 shown in 3A & 3B may include materials or features previously mentioned with reference to other embodiments.

[0026] As in Fig. As shown in Figure 3A, the device 300 includes the substrate 302, the semiconductor layer 304, the transistor 306, the channel region 308, the gate stack 312, the source region 314, the drain region 316, the dielectric layer 318, the junction layer 326, the semiconductor layer 328, the transistor 332, the channel region 334, the gate stack 336, the source region 338, the drain region 342, the dielectric layer 344, the dielectric surface 345, and the contacts 346, 347, and 348. In some embodiments, the device 300 can be a CMOS device that may include the drain region 342 of the transistor 332 coupled with the source region 314 of the transistor 306, wherein the transistor 306, for example, is a The transistor 332 can be an NMOS transistor, and the transistor 332 can be a PMOS transistor.

[0027] Fig. Figure 3B shows component 350, which may include contacts 352, 354, and 356. In some embodiments, component 350 may be a CMOS component that includes the drain region 316 of transistor 306 coupled to the source region 338 of transistor 332, where transistor 306 may, for example, be an NMOS transistor and transistor 332 may be a PMOS transistor. In some embodiments, the metal contacts 352 or 354 may extend below a surface of the source region 314 or the drain region 316, respectively.

[0028] Fig. Figure 4 illustrates a flowchart of a method for forming a semiconductor device with stacked transistors, with the contact formed last, in accordance with some embodiments. Although the blocks in the flowchart refer to Fig. While the four steps are shown in a specific order, the sequence of actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions / blocks can be performed in parallel. Some of the steps shown in Fig. The four listed blocks and / or operations are optional in accordance with certain embodiments. The numbering of the blocks shown is for clarity and does not prescribe a sequence in which the various blocks must be performed. Furthermore, operations from the different flows can be used in a multitude of combinations.

[0029] Method 400 begins with the formation (402) of a first transistor. In some embodiments, a first transistor can be formed by epitaxial growth or regrowth of source and drain regions on a semiconductor layer. In some embodiments, metal wires or etch-stop layers can be formed in contact with the source and / or drain region. Next, a first dielectric layer is formed over the first transistor (404). In some embodiments, an interlayer dielectric, for example, the dielectric 116, can be deposited over the transistor 106 by atomic layer deposition or another suitable deposition process.

[0030] Then a semiconductor layer can be formed over the first dielectric layer (406). In some embodiments, a semiconductor layer can be transferred and bonded to the dielectric layer. In other embodiments, the semiconductor layer can be deposited onto the dielectric layer by any suitable deposition technique. Next, a second transistor can be formed on the semiconductor layer (408). In some embodiments, the second transistor can be aligned directly over the first transistor such that a source region and a drain region of the second transistor are located directly over a source region and a drain region of the first transistor. In other embodiments, the second transistor can be offset in a different orientation or not at all from the first transistor.

[0031] The method continues with the formation (410) of a second dielectric layer over the second transistor. In some embodiments, the second dielectric layer may be of the same material as the first dielectric layer. Next, openings may be created through the second and first dielectric layers (and other intervening layers) (412) to expose portions of the first transistor. In some embodiments, laser drilling may expose a source or drain region, or a metal in contact with the source or drain region, of the first (lower) transistor. In some embodiments, chemical etching may expose a source or drain region, or an etch stop in contact with the source or drain region, of the first (lower) transistor.

[0032] The openings can then be filled with metal (414) to create source and drain contacts with the first transistor. In some embodiments, the etch stop, if present, can be removed before metal plating the openings. Finally, further processing steps can be carried out (416) to form the semiconductor device. In some embodiments, gate contacts and other interconnect layers are formed.

[0033] Fig.Figure 5 illustrates an intelligent device, computer system, or system-on-a-chip (SoC) 500, which includes a semiconductor device with stacked transistors having last-formed contact, according to some embodiments. In some embodiments, the computing device 500 is a mobile computing device, such as a tablet PC, a mobile phone or smartphone, a Wi-Fi-enabled e-reader, or another wireless mobile device. It is understood that certain components are shown in general terms and that not all components of such a device are shown in the computing device 500. In some embodiments, one or more components of the computing device 500, for example, the processor 510 and / or the memory subsystem 560, include a semiconductor device with stacked transistors having last-formed contact as described above.

[0034] For the purposes of these embodiments, the transistors in the various circuits and logic blocks described herein are metal oxide semiconductor (MOS) transistors or their derivatives, wherein the MOS transistors include drain, source, gate, and ground terminals. The transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, tunneling FETs (TFETs), square-wire or rectangular-ribbon transistors, ferroelectric FETs (FeFETs), or other devices implementing transistor functionality, such as carbon nanotubes or spintronic devices. Symmetrical MOSFET source and drain terminals are identical and are used interchangeably here. Conversely, a TFET device has asymmetrical source and drain terminals. Experts in the field will be aware that other transistors, for example bipolar junction transistors - BJT PNP / NPN, BiCMOS, CMOS, etc., are also available., can be used without straying from the scope of the disclosure.

[0035] In some embodiments, the computing device 500 includes a first processor 510. The various embodiments of the present disclosure may also include a network interface within 570, such as a wireless interface, so that a system implementation can be enclosed in a wireless device, for example, a mobile phone or a PDA.

[0036] In one embodiment, the processor 510 may include one or more physical components, such as microprocessors, application processors, microcontrollers, programmable logic circuits, or other processing means. The processing operations performed by the processor 510 include the execution of an operating platform or operating system on which applications and / or device functions are executed. These processing operations include I / O (input / output) operations with a human user or other devices, power management operations, and / or operations related to connecting the computing device 500 to another device. The processing operations may also include audio I / O and / or display I / O operations.

[0037] In one embodiment, the computing device 500 includes the audio subsystem 520, which comprises hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components related to providing audio functions to the computing device. Audio functions may include speaker and / or headphone output as well as microphone input. Components for such functions may be integrated into or connected to the computing device 500. In one embodiment, a user interacts with the computing device 500 by providing audio commands, which are received and processed by the processor 510.

[0038] The display subsystem 530 comprises hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with the computing device 500. The display subsystem 530 includes the display interface 532, which includes the specific screen or hardware component used to provide a display to a user. In one embodiment, the display interface 532 includes logic separate from the processor 510 to perform at least some processing related to the display. In one embodiment, the display subsystem 530 includes a touchscreen (or touchpad) component that provides both output and input to a user.

[0039] The I / O Controller 540 represents hardware components and software components related to user interaction. The I / O Controller 540 is capable of managing hardware that is part of the Audio Subsystem 520 and / or the Display Subsystem 530. Furthermore, the I / O Controller 540 illustrates a connection point for additional devices that can be connected to the Computing Device 500, through which a user could interact with the system. For example, devices that could be connected to the Computing Device 500 might include microphones, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I / O devices for use with specific applications, such as card readers or other devices.

[0040] As mentioned above, the I / O controller 540 can interact with the audio subsystem 520 and / or the display subsystem 530. For example, input from a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 500. Furthermore, audio output can be provided instead of, or in addition to, display output. In another example, if the display subsystem 530 includes a touchscreen, the display device also acts as an input device that can be managed, at least partially, by the I / O controller 540. Additional buttons or switches may also be present on the computing device 500 to provide I / O functions that are managed by the I / O controller 540.

[0041] In one embodiment, the I / O controller 540 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in the computing device 500. The input can be part of a direct user interaction as well as provide environmental input to the system to influence its operations (such as noise filtering, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0042] In one embodiment, the computing device 500 includes the power management system 550, which manages battery power usage, battery charging, and features related to power-saving operation. The memory subsystem 560 includes storage devices for storing information in the computing device 500. The memory can include non-volatile (the state does not change when power to the storage device is interrupted) and / or volatile (the state is indeterminate when power to the storage device is interrupted) storage devices. The memory subsystem 560 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 500.

[0043] Elements of embodiments also include a machine-readable medium (e.g., Memory 560) for storing computer-executable instructions. The machine-readable medium (e.g., Memory 560) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that can be transmitted by means of data signals over a communication link (e.g., a modem or network connection) from a remote computer (e.g., a server) to a requesting computer (e.g., a client).

[0044] The Connectivity 570 includes hardware components (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stack) to enable the Computing Device 500 to communicate with external devices. The Computing Device 500 could consist of separate devices, such as other Computing Devices, wireless access points or base stations, as well as peripheral devices, such as headsets, printers, or other equipment.

[0045] Connectivity 570 can include several different types of connectivity. For generalization, the computing device 500 is illustrated with cellular connectivity 572 and wireless connectivity 574. Cellular connectivity 572 generally refers to cellular network connectivity provided by wireless carriers, such as GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, or other mobile service standards. Wireless connectivity (or wireless interface) 574 refers to wireless connectivity that is not cellular and can include personal networks (such as Bluetooth, Near Field Communication, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as...).WiMax) or other wireless communication.

[0046] Peripheral connections 580 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral connections. It is understood that the computing device 500 could be both a peripheral device (“to” 582) to other computing devices and could have peripheral devices (“from” 584) connected to it. The computing device 500 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on the computing device 500. Furthermore, a docking connector of a computing device 500 may allow it to connect to certain peripheral devices to enable the computing device 500 to control content output, for example, to audiovisual or other systems.

[0047] In addition to a proprietary docking connector or other proprietary connection hardware, the Computing Device 500 can also establish peripheral connections 580 via common or standards-based connectors. Common types may include a USB (Universal Serial Bus) connector (which can encompass any of a range of different hardware interfaces), DisplayPort, including MDP (Mini DisplayPort), HDMI (High Definition Multimedia Interface), FireWire, or other types.

[0048] A reference in the specification to "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or property described in connection with the embodiments is present in at least some, but not necessarily all, embodiments. The repeated occurrence of "one embodiment" or "some embodiments" does not necessarily always refer to the same embodiments. If the specification states that a component, feature, structure, or property "may" or "might" be present, that particular component, feature, structure, or property need not be present. If the specification or the claims refer to "one" element, this does not mean that only one of the elements is present.If the specification or claims refer to "an additional" element, this does not preclude the presence of more than one of the additional element.

[0049] Furthermore, the specific features, structures, functions, or properties can be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment, provided that the specific features, structures, functions, or properties associated with the two embodiments are not mutually exclusive.

[0050] While the disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be obvious to the average person skilled in the art in the field, given the foregoing description. The embodiments of the disclosure are intended to encompass all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0051] Furthermore, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown within the present figures, for the sake of simplicity of illustration and discussion, and to avoid obscuring the disclosure. Arrangements in the form of a block diagram may also be shown to avoid obscuring the disclosure, particularly given that specifics relating to the implementation of such block diagram arrangements are highly independent of the platform on which the present disclosure is to be implemented (i.e., such specifics should be well within the reach of a person skilled in the art). Where specific details (e.g.,Since the circuits are presented to describe exemplary implementations of the disclosure, it should be obvious to a person skilled in the art that the disclosure can also be implemented in practice without these or with a variation of these specific details. The description should therefore be considered illustrative rather than restrictive.

[0052] The following examples relate to further embodiments. Specific features in the examples can be used in any one or more embodiments. All optional features of the device described herein can also be implemented in relation to a method or process.

[0053] In one example, an integrated circuit arrangement structure is provided which includes: a first transistor comprising a source region and a drain region with a channel region between them; a first dielectric layer over the first transistor; a second transistor comprising a source region and a drain region with a channel region between them, the second transistor being located over the first dielectric layer; a second dielectric layer over the second transistor; and a contact coupled to the source region or the drain region of the first transistor, the contact comprising a metal having a sidewall extending through both the first and the second dielectric layer.

[0054] In some embodiments, the contact comprises an inclined sidewall, wherein a first width of the contact within the second dielectric layer is greater than a second width of the contact within the first dielectric layer. In some embodiments, the contact is located on the source region or the drain region of the first transistor. In some embodiments, the contact is located on a metal coupled to the source region or the drain region of the first transistor. In some embodiments, the contact is located on a sidewall of the source region or the drain region of the second transistor and on the source region or the drain region of the first transistor. In some embodiments, the contact extends through the source region or the drain region of the second transistor.In some embodiments, the contact is a first contact coupled to the source region of the first transistor, the integrated circuit arrangement further comprising a second contact coupled to the drain region of the first transistor, the second contact extending through both the first and second dielectric layers. Some embodiments also include a third contact coupled to the source region of the second transistor. In some embodiments, the first transistor comprises a PMOS transistor and the second transistor comprises an NMOS transistor. Some embodiments also include a bonding layer between the first dielectric layer and the second transistor. In some embodiments, the metal comprises at least one of copper, titanium, tantalum, aluminum, or palladium.

[0055] In another example, a system is provided which includes: a display subsystem; a wireless communication interface; and an integrated circuit arrangement, wherein the integrated circuit arrangement includes: a first transistor comprising a source region and a drain region with a channel region between them; a first dielectric layer above the first transistor; a second transistor comprising a source region and a drain region with a channel region between them, the second transistor being located above the first dielectric layer; a second dielectric layer above the second transistor; and a contact coupled to the source region of the first transistor, the contact comprising a straight sidewall extending from an upper surface of the second dielectric layer into the first dielectric layer.

[0056] In some embodiments, the contact comprises an inclined side wall, wherein a first width of the contact in the second dielectric layer is greater than a second width of the contact in the first dielectric layer. In some embodiments, the contact is located on the source region of the first transistor. In some embodiments, the contact is located on a metal that is coupled to the source region of the first transistor. In some embodiments, the contact extends through the source region or the drain region of the second transistor. In some embodiments, the contact comprises a first contact and further comprises a second contact that is coupled to the drain region of the first transistor. Some embodiments also include a bonding layer between the first dielectric layer and the second transistor.In some embodiments, the first transistor comprises a PMOS transistor and the second transistor comprises an NMOS transistor.

[0057] In another example, a method for forming an integrated circuit arrangement structure is provided, comprising: forming a first transistor; forming a first dielectric layer over the first transistor; forming a second transistor over the first dielectric layer; forming a second dielectric layer over the second transistor; and forming a contact coupled to a source region or a drain region of the first transistor, wherein the contact comprises a straight side wall extending from the second dielectric layer into the first dielectric layer.

[0058] In some embodiments, forming the contact comprises: anisotropic etching of an opening through the second dielectric layer and the first dielectric layer to expose an etch-stop layer over a source or drain of the first transistor; removal of the etch-stop layer; and filling the opening with metal. In some embodiments, forming the contact comprises: laser drilling of an opening through the second dielectric layer and the first dielectric layer to expose metal coupled to a source or drain of the first transistor; and filling the opening with metal. In some embodiments, forming the contact comprises: creating an opening through the second dielectric layer, a source or drain of the second transistor, and the first dielectric layer to expose a source or drain of the first transistor; and filling the opening with metal.Some embodiments also include forming a second contact coupled to the source region or the drain region of the first transistor, wherein the second contact comprises a straight sidewall extending from an upper surface of the second dielectric layer into the first dielectric layer. In some embodiments, forming the second transistor includes depositing a bonding material over the first dielectric layer and transferring the second transistor into contact with the bonding material.

[0059] In another example, an integrated circuit assembly package is provided, comprising: a package substrate; and an integrated circuit assembly, wherein the integrated circuit assembly comprises: a first transistor comprising a source region and a drain region with a channel region between them; a first dielectric layer over the first transistor; a second transistor comprising a source region and a drain region with a channel region between them, the second transistor being located over the first dielectric layer; a second dielectric layer over the second transistor; and a contact coupled to the source region or the drain region of the first transistor, the contact comprising a metal having a straight sidewall extending through both the first and the second dielectric layers.

[0060] In some embodiments, the contact comprises an inclined sidewall, wherein a first width of the contact within the second dielectric layer is greater than a second width of the contact within the first dielectric layer. In some embodiments, the contact is located on the source region or the drain region of the first transistor. In some embodiments, the contact is located on a metal coupled to the source region or the drain region of the first transistor. In some embodiments, the contact is located on a sidewall of the source region or the drain region of the second transistor and on the source region or the drain region of the first transistor. In some embodiments, the contact extends through the source region or the drain region of the second transistor.In some embodiments, the contact is a first contact coupled to the source region of the first transistor, and the integrated circuit arrangement further comprises a second contact coupled to the drain region of the first transistor, the second contact extending through both the first and second dielectric layers. In some embodiments, the first transistor comprises a PMOS transistor and the second transistor comprises an NMOS transistor.

Claims

[1] Integrated circuit arrangement structure comprising the following: a first transistor (106; 206; 306) comprising a source region (112; 214; 314) and a drain region (114; 216; 316) with a channel region (108; 208; 308) in between; a first dielectric layer (116; 218; 318) over the first transistor (106; 206; 306); a second transistor (126; 232; 332) comprising a source region (132; 238; 338) and a drain region (134; 242; 342) with a channel region (128; 234; 334) in between, the second transistor (126; 232; 332) being located above the first dielectric layer (116; 218; 318); a second dielectric layer (136; 244; 344) over the second transistor (126; 232; 332); and a first contact (140; 347; 352), wherein the first contact (140; 347; 352) is coupled to the source region (112; 314) of the first transistor (106; 206; 306), wherein the first contact (140; 347; 352) comprises a metal with a side wall (146) extending through both the first (116; 318) and the second dielectric layer (136; 344); and a second contact (144; 348; 354), wherein the second contact (144; 348; 354) is coupled to the drain region (114; 316) of the first transistor (106; 306), wherein the second contact (144) comprises a metal and a side wall (148) that is orthogonal to a surface (138) of the second dielectric layer (136), wherein the second contact (144) extends through both the first (116) and the second dielectric layer (136); and a third contact (142; 346; 356) coupled to the source region (132; 338) or the drain region (342) of the second transistor (126; 332), wherein the third contact (142; 346; 356) comprises a metal and is formed directly on or below the surface of the source region (132; 338) or the drain region (342) of the second transistor (126; 332). [2] Integrated circuit arrangement structure according to claim 1, wherein the first contact (140) comprises an inclined side wall (146) and wherein a first width of the first contact (140) within the second dielectric layer (136) is greater than a second width of the first contact (140) within the first dielectric layer (116). [3] Integrated circuit arrangement structure according to claim 1, wherein the first contact (140) is located on a metal that is coupled to the source region (112) of the first transistor (106) and / or the second contact (144) is located on a metal that is coupled to the drain region (114) of the first transistor (106). [4] Integrated circuit arrangement structure according to claim 1, wherein the second contact (144) extends through the drain region (134) of the second transistor (126). [5] Integrated circuit arrangement structure according to any one of claims 1 to 4, wherein the first transistor (106; 206; 306) comprises a PMOS transistor and the second transistor (126; 232; 332) comprises an NMOS transistor. [6] Integrated circuit arrangement structure according to one of claims 1 to 4, which further comprises a bonding layer (122; 226; 326) between the first dielectric layer (116; 218; 318) and the second transistor (126; 232; 332). [7] Integrated circuit arrangement structure according to any one of claims 1 to 4, wherein the metal comprises at least one of copper, titanium, tantalum, aluminium or palladium. [8] System (500), which includes the following: a display subsystem (530); a wireless communication interface (572, 574); and an integrated circuit arrangement, wherein the integrated circuit arrangement comprises the following: a first transistor (106; 206; 306) comprising a source region (112; 214; 314) and a drain region (114; 216; 316) with a channel region (108; 208; 308) in between; a first dielectric layer (116; 218; 318) over the first transistor (106; 206; 306); a second transistor (126; 232; 332) comprising a source region (132; 238; 338) and a drain region (134; 242; 342) with a channel region (128; 234; 334) in between, the second transistor (126; 232; 332) being located above the first dielectric layer (116; 218; 318); a second dielectric layer (136; 244; 344) over the second transistor (126; 232; 332); and a first contact (140; 347; 352) coupled to the source region (112; 314) of the first transistor (106; 306), wherein the first contact (140) comprises a metal with a straight side wall (146) extending from an upper surface (138) of the second dielectric layer (136) into the first dielectric layer (116); and a second contact (144; 348; 354) coupled to the drain region (114; 316) of the first transistor (106; 306), wherein the second contact (144) comprises a metal and a side wall (148) that is orthogonal to a surface (138) of the second dielectric layer (136); and a third contact (142; 346; 356) coupled to the source region (132; 338) or the drain region (342) of the second transistor (126; 332), wherein the third contact (142; 346; 356) comprises a metal and is formed directly on or below the surface of the source region (132; 338) or the drain region (342) of the second transistor (126; 332). [9] System according to claim 8, wherein the first contact (140; 347; 352) comprises an inclined side wall (146) and wherein a first width of the first contact (140; 347; 352) in the second dielectric layer (136; 344) is greater than a second width of the contact (140; 347; 352) in the first dielectric layer (116; 318). [10] System according to claim 8, wherein the first contact (140) is located on a metal that is coupled to the source region (112) of the first transistor (106). [11] System according to claim 8, wherein the second contact (144) extends through the drain region (134) of the second transistor (126). [12] System according to one of claims 8 to 11, which further comprises a bonding layer (122; 326) between the first dielectric layer (116; 314) and the second transistor (126; 332). [13] System according to any one of claims 8 to 11, wherein the first transistor (106; 306) comprises a PMOS transistor and the second transistor (126; 332) comprises an NMOS transistor. [14] Method for forming an integrated circuit arrangement structure, comprising the following: Forming a first transistor (106; 206; 306); Forming a first dielectric layer (116; 218; 318) over the first transistor (106; 206; 306); Forming a second transistor (126; 232; 332) above the first dielectric layer (116; 218; 318); Forming a second dielectric layer (136; 244; 344) over the second transistor (126; 232; 332); and Forming a first contact (140; 347; 352) coupled to a source region (112; 314) or a drain region (114; 316) of the first transistor (106; 306), wherein the first contact (140) comprises a metal with a straight sidewall (146) extending from the second dielectric layer (136) to the first dielectric layer (116); and Forming a second contact (144) coupled to the source region (112) or the drain region (114) of the first transistor (106) wherein the second contact (144) comprises a metal and a side wall (148) that is orthogonal to a surface (138) of the second dielectric layer (136) and the second contact extends from an upper surface (138) of the second dielectric layer (136) into the first dielectric layer (116); Forming a third contact (142; 346; 356) coupled to the source region (132; 338) or the drain region (342) of the second transistor (126; 332), wherein the third contact (142; 346; 356) comprises a metal and is formed directly on or below the surface of the source region (132; 338) or the drain region (342) of the second transistor (126; 332). [15] Method according to claim 14, wherein forming the contact (140, 144) comprises: anisotropic etching of an opening (256) through the second dielectric layer (144; 244) and the first dielectric layer (116; 218) to expose an etch stop layer (120; 224) over a source (112; 214) or a drain (114; 216) of the first transistor (106; 206); Removal of the etch-stop layer (120; 224); and Filling the opening (256) with metal. [16] Method according to claim 14, wherein forming the contact (140, 144) comprises: Laser drilling of an opening (256) through the second dielectric layer (144; 244) and the first dielectric layer (116; 218) to expose a metal coupled to a source (112; 214) or a drain (114; 216) of the first transistor (106; 206); and Filling the opening (256) with metal. [17] Method according to claim 14, wherein forming the contact (140, 144) comprises: Creating an opening (256) through the second dielectric layer (144; 244), a source (132; 238) or a drain (134; 242) of the second transistor (126; 232) and the first dielectric layer (116; 218) to expose a source (112; 214) or a drain (114; 216) of the first transistor (106; 206); and Filling the opening (256) with metal. [18] Method according to any one of claims 14 to 17, wherein forming the second transistor (126; 232) comprises depositing a binder material (122; 226) over the first dielectric layer (116; 218) and transferring the second transistor (126; 232) into contact with the binder material (122; 226).

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