SILICON CARBIDE SEMICONDUCER UNIT

Abstract

Silicon carbide semiconductor unit (701 to 710, 701V, 706V, 709V) comprising an element region (RE) arranged on a silicon carbide semiconductor substrate (11) and a non-element region (RN) arranged outside the element region (RE), wherein a gate contact electrode (14) connected to the outside and supplied with a gate voltage from the outside is arranged in the non-element region (RN), wherein the silicon carbide semiconductor unit (701 to 710, 701V, 706V, 709V) has a drift layer (10) in the elemental region (RE) and the non-elemental region (RN) having a first conductivity type and arranged on the silicon carbide semiconductor substrate (11), and Furthermore, the following is present in the element area (RE): - a first trench (12), the bottom surface of which extends down to the drift layer (10); and - a gate electrode (1) which is arranged in the first trench (12) by means of a gate insulating layer (2) and is electrically connected to the gate contact electrode (14), and Furthermore, the non-element area (RN) exhibits the following: - at least a second trench (112) whose bottom surface extends down to the drift layer (10); - at least a second relaxation area (103) which has a second conductivity type and is located below the at least one second trench (112); - an insulating layer (102) on an inner surface, arranged on a lateral surface and on the bottom surface of at least one second trench (112); and - a low-resistance region (101) located in at least one second trench (112) by the insulating layer (102) on the inner surface and electrically insulated from the gate contact electrode (14).

Description

TECHNICAL FIELD

[0001] The present invention relates to a silicon carbide semiconductor device. STATE OF THE ART

[0002] As a switching element used in an inverter circuit or the like, a vertical power semiconductor device is often used, and in particular, a vertical power semiconductor device with a metal-oxide-semiconductor (MOS) structure is often used. Typically, an insulated-gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are used.

[0003] For example, WO 2010 / 098294 A1 (Patent Document 1) discloses a MOSFET, and Japanese Patent Application Laid-Open No. JP 2004-273647 A (Patent Document 2) discloses an IGBT. Specifically, Patent Document 1 discloses a vertical n-channel MOSFET using silicon carbide (SiC) as the semiconductor material.

[0004] Furthermore, WO 2012 / 077617 A1 (Patent Document 3) discloses a trench-gate MOSFET with the aim of further reducing the on-voltage of a vertical n-channel MOSFET using silicon carbide.

[0005] The n-channel MOSFET has an n-type drift layer and a p-type well disposed on the n-type drift layer. When the MOSFET is switched from an on-state to an off-state, the drain voltage of the MOSFET, i.e., the voltage at the drain electrode, increases sharply from nearly zero volts to several hundred volts.

[0006] In this case, a displacement current is generated by a parasitic capacitance existing between the p-type well and the n-type drift layer. A displacement current generated on the drain electrode side flows to the drain electrode, and a displacement current generated on the source electrode side flows through the p-type well to the source electrode.

[0007] In the vertical n-channel MOSFET, in addition to the p-type well forming a MOSFET cell, which effectively functions as a MOSFET, additional p-type wells are typically arranged in an outer peripheral region of a chip. Examples of such additional p-type wells include one positioned directly below a gate pad.

[0008] These p-type wells in the outer peripheral region typically have a significantly larger cross-sectional area in the horizontal plane (area in the plane layout) than the p-type well in the MOSFET cell.

[0009] Accordingly, the aforementioned displacement current in the p-type wells in the outer peripheral region must flow along a long path until it reaches the source electrode. The p-type wells thus exhibit high electrical resistance as current paths for the displacement current. As a result, an unacceptably high potential drop can occur in the p-type wells.

[0010] Thus, a relatively high potential difference with respect to a source potential is generated in the p-type wells at a position far away in the in-plane direction from a position connected to the source electrode. This may raise concerns about the occurrence of dielectric breakdown due to the potential difference.

[0011] In recent years, a semiconductor device using silicon carbide with a band gap approximately three times that of silicon, the most commonly used semiconductor material, has begun to be used as a switching element of an inverter circuit, and in particular, an n-channel MOSFET has been used.

[0012] The use of a semiconductor with a wide band gap enables a reduction in losses in an inverter circuit. To further reduce losses, it is necessary to drive a switching element at a higher speed.

[0013] In other words, to reduce losses, it is necessary to further increase dV / dt, which reflects a variation in drain voltage V with respect to time t. In such a case, the displacement current flowing into the p-type well through a parasitic capacitance is also increased. Furthermore, performing a doping treatment to reduce electrical resistance is more difficult for silicon carbide than for silicon.

[0014] Thus, when silicon carbide is used, the p-type well tends to exhibit high parasitic resistance. Such high parasitic resistance can easily lead to a high potential drop in the p-type well. Under these circumstances, as described above, the use of silicon carbide may raise greater concerns regarding the aforementioned dielectric breakdown.

[0015] In the above-described technology according to WO 2010 / 098 294 A1, a p-type semiconductor layer having a low resistance is arranged on the entire upper surface or on a part of the upper surface of the p-type well positioned below the gate pad in the outer peripheral region.

[0016] This enables a reduction in the voltage distribution in the p-type well due to a potential drop that occurs when a displacement current flows in the p-type well positioned below the gate pad. Consequently, a potential difference between the p-type well and the gate electrode is reduced. Consequently, breakdown of a gate insulating layer is reduced.

[0017] In addition, reference is made to US 2017 / 0 301 788 A1 (Patent Document 4), from which a trench-gate semiconductor device is known. The semiconductor device includes a gate trench reaching an inner part of an n-type drift layer in a cell region; an outer trench outside the cell region; a gate electrode formed within the gate trench through a gate insulating film; a gate line formed within the outer trench through an insulating layer; and a gate line guide region formed through the insulating layer to cover a corner closer to the cell region at an open end of the outer trench and electrically connect the gate electrode to the gate line. The surface layer of the drift layer, in contact with the corner, includes a second p-type impurity region that is part of the well region. PRIOR ART DOCUMENTSPatent documents Patent document 1: WO 2010 / 098 294 A1 Patent document 2: JP 2004 - 273 647 A Patent document 3: WO 2012 / 077 617 A1 Patent document 4: US 2017 / 0 301 788 A1 BRIEF DESCRIPTIONProblem to be solved by the invention

[0018] A planar MOSFET and a trench MOSFET typically have different configurations of their outer peripheral regions (more generally, their "non-element regions"). The technology described above, according to WO 2010 / 098 294 A1, refers to a planar MOSFET and is therefore not necessarily applicable to the trench type.

[0019] The present invention has been conceived to solve the above-described problem, and has an object to provide a trench type silicon carbide semiconductor device by which element breakdown at the time of switching can be reduced by reducing a potential drop that occurs when a displacement current flows. Means of solving the problemEffects of the invention

[0020] According to the present invention, by disposing the low-resistance region in the second trench through the insulating layer on the inner surface, a capacitance is formed. Consequently, at the time of high-speed switching of the silicon carbide semiconductor device, a displacement current flowing through the second relaxation region below the second trench can be branched into the low-resistance region through capacitive coupling. Consequently, the magnitude of a potential drop due to the displacement current can be reduced.

[0021] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The figures show: Fig. 1 is a plan view schematically illustrating a configuration of a silicon carbide unit according to a first embodiment of the present invention; Fig. 2 is a schematic partial cross-sectional view along a line II-II according to Fig. 1; Fig. 3 is a schematic partial cross-sectional view along a line III-III according to Fig. 1; Fig. 4 is a schematic partial cross-sectional view along a line IV-IV according to Fig. 1; Fig. 5 is a partial cross-sectional view showing a configuration of a silicon carbide unit according to a modification of the first embodiment of the present invention taken along a line VV in Fig. 6 schematically; Fig. 6 is a partial cross-sectional perspective view schematically illustrating a configuration of the silicon carbide unit according to the modification of the first embodiment of the present invention without a partial configuration on the side of an upper surface; Fig. 7 is a plan view schematically illustrating a configuration of a silicon carbide unit according to a second embodiment of the present invention; Fig. 8 is a schematic partial cross-sectional view along a line VIII-VIII according to Fig. 7; Fig. 9 is a partial cross-sectional view of a configuration of a silicon carbide unit according to a third embodiment of the present invention, taken in a cross-section similar to that taken along the line VIII-VIII of Fig. 7 is shown; Fig. 10 is a partial cross-sectional view of a configuration of a silicon carbide unit according to a fourth embodiment of the present invention, taken in a cross section similar to that taken along the line VIII-VIII of Fig. 7 is shown; Fig. 11 is a partial cross-sectional view illustrating a configuration of a silicon carbide unit according to a fifth embodiment of the present invention in a non-element region; Fig. 12 is a partial cross-sectional view illustrating a configuration of a silicon carbide unit according to a sixth embodiment of the present invention in a non-element region; Fig. 13 is a partial cross-sectional view of a configuration of a silicon carbide unit according to a modification of the sixth embodiment of the present invention, which is in a cross section similar to that taken along the line VIII-VIII in Fig. 7 is shown; Fig. 14 is a partial cross-sectional view illustrating a configuration of a silicon carbide unit according to a seventh embodiment of the present invention in a non-element region; Fig. 15 is a partial cross-sectional view illustrating a configuration of a silicon carbide semiconductor layer of a silicon carbide device according to an eighth embodiment of the present invention in a non-element region; Fig. 16 a partial cross-sectional view along a line XVI-XVI according to Fig. 15; Fig. 17 is a partial plan view illustrating a configuration of a silicon carbide semiconductor layer of a silicon carbide device according to a ninth embodiment of the present invention in a non-element region; Fig. 18 is a partial cross-sectional view along a line XVIII-XVIII according to Fig. 17; Fig. 19 is a partial plan view illustrating a configuration of a silicon carbide semiconductor layer of a silicon carbide unit according to a modification of the ninth embodiment of the present invention in a non-element region; Fig. 20 is a partial plan view illustrating a configuration of a silicon carbide semiconductor layer of a silicon carbide device according to a tenth embodiment of the present invention in a non-element region. DESCRIPTION OF EMBODIMENTS

[0023] Embodiments of the present invention will be described below with reference to the drawings. Note that the same or equivalent portions in the following drawings are denoted by the same reference numerals, and a description thereof will not be repeated. First embodiment configuration

[0024] Fig. 1 is a plan view schematically illustrating a configuration of a MOSFET 701 (silicon carbide semiconductor device) according to a first embodiment. The MOSFET 701 includes an element region RE disposed on a substrate 11 (silicon carbide semiconductor substrate), and a non-element region RN disposed outside the element region RE. In the MOSFET 701, a gate pad electrode 14, which is connected to the outside region and to which a gate voltage is supplied from the outside region, is disposed in the non-element region RN.

[0025] A wire made of a metal, such as aluminum, is connected to the gate pad electrode 14 by ultrasonic bonding or the like. The non-element region RN may include a terminal region of the MOSFET 701. The element region RE includes a region in which channels controlled by gate electrodes are arranged, and is typically a region in which a MOSFET cell is arranged, effectively functioning as a MOSFET.

[0026] Fig. 2 and Fig. 3 represent different partial cross-sections in the element area RE along a line II-II or a line III-III according to Fig. 1 schematically. Fig. Figure 4 represents a partial cross-section in the non-element region RN along a line IV-IV according to Fig. 1 schematically. It should be noted that in these cross-sectional views and other cross-sectional views to be described later, the regions exhibiting a p-type (a second conductivity type) are dotted.

[0027] In the element region RE and the non-element region RN, the MOSFET 701 includes an n-type (first conductivity type) drift layer 10 disposed on the substrate 11. Furthermore, in the element region RE, the MOSFET 701 includes a first trench 12 whose bottom surface extends to the drift layer 10, and a gate electrode 1 disposed in the first trench through a gate insulating layer 2 and electrically connected to the gate pad electrode 14.

[0028] Furthermore, the MOSFET 701 includes, in the non-element region RN, at least one second trench 112 whose bottom surface extends to the drift layer; at least one second relaxation region 103 having a p-type (a second conductivity type) and disposed below the second trench 112; an inner surface insulating layer 102 disposed on a side surface and on the bottom surface of the second trench 112; and a low resistance region 101 disposed by the inner surface insulating layer 102 in the second trench 112 and electrically insulated from the gate pad electrode 14. An epitaxial layer 30 (silicon carbide semiconductor layer) is disposed on the substrate 11.

[0029] The epitaxial layer 30 comprises a drift layer 10, a base region 7, a source region 8, a high concentration region 6, a first relaxation region 3, a second relaxation region 103 and a connection region 9. In the epitaxial layer 30, the first trench 12 ( Fig. 2 and Fig. 3) and the second ditch ( Fig. 4). Furthermore, the MOSFET 701 includes a source pad electrode 4, a drain electrode 104, an interlayer insulating layer 5, and a low-resistance region 101.

[0030] The substrate 11 extends across the element region RE and the non-element region RN. The substrate 11 has an n-type (a first conductivity type). The epitaxial layer 30 is arranged by epitaxial growth on the substrate 11 and extends across the element region RE and the non-element region RN.

[0031] The drift layer 10 is arranged on the substrate 11 such that it extends across the element region RE and the non-element region RN. The drift layer 10 is made of silicon carbide. The drift layer 10 is n-type and has a donor concentration of 1 × 10 14 cm -3 up to 1 × 10 17 cm -3 It is preferred that the donor concentration of the drift layer 10 is lower than the donor concentration of the substrate 11.

[0032] The base region 7 is arranged in the element region RE and is arranged on the drift layer 10. The base region 7 has a p-type (a second conductivity type different from the first conductivity type) and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3It should be noted that the acceptor concentration and the thickness of the base region 7 do not need to be uniform. The source region 8 is located in the element region RE and is arranged on the base region 7.

[0033] The source region 8 is of the n-type, has a donor concentration that is higher than the donor concentration of the drift layer 10, and in particular has a donor concentration of 1 × 10 18 cm -3 up to 1 × 10 20 cm -3 The high concentration region 6 is arranged in the element region RE, penetrates the source region 8 and reaches the base region 7. The high concentration region 6 is p-type, has an acceptor concentration higher than the acceptor concentration of the base region 7, and in particular has an acceptor concentration of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 on.

[0034] As in Fig. 2, in the present embodiment, a plurality of first trenches 12 are arranged at intervals in the element region RE. It should be noted that the plurality of first trenches 12, like those in Fig. 2 can be connected to each other in a specific cross section in the plane layout. The first trench 12 has a lateral surface and a bottom surface. The lateral surface of the first trench 12 penetrates the source region 8 and the base region 7. The lateral surface of the first trench 12 extends in the cross section according to Fig. 2 to the drift layer 10.

[0035] In this way, in the cross section according to Fig. 2 channels of the MOSFET. The first relaxation region 3 is arranged below the first trench 12 and is in contact with the drift layer 10. Typically, the first relaxation region 3 is in contact with the bottom surface of the first trench 12. The first relaxation region 3 is p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and the thickness of the first relaxation region 3 do not have to be uniform.

[0036] The gate insulating layer 2 is arranged on the side surface and on the bottom surface of the first trench 12. The thickness (the horizontal dimension according to Fig. 2 and Fig. 3) the gate insulating layer 2 on the side surface of the first trench 12 is, for example, equal to 10 nm or larger and equal to 300 nm or smaller.

[0037] The thickness (the vertical dimension according to Fig. 2 and Fig. 3) The thickness of the gate insulating layer 2 on the bottom surface of the first trench 12 is, for example, 10 nm or greater and 300 nm or less. The gate insulating layer 2 is mainly composed of, for example, silicon dioxide. At least a portion of the gate electrode 1 is disposed in the first trench 12 through the gate insulating layer 2.

[0038] The source pad electrode 4 is electrically connected to the source region 8 and the high-concentration region 6 by means of an ohmic junction or a Schottky junction. To achieve this electrical connection, the source pad electrode 4 is in contact with the source region 8 and the high-concentration region 6. Note that a region of the source pad electrode 4 may be silicided to contact the source region 8 and the high-concentration region 6.

[0039] In other words, the source pad electrode 4 may have a silicide layer in contact with the source region 8 and the high-concentration region 6. The source pad electrode 4 is separated from the gate electrode 1 by the interlayer insulating layer 5.

[0040] The source pad electrode 4 is electrically connected to the first relaxation region 3. In the present embodiment, the source pad electrode 4 is connected to the first relaxation region 3, which is p-type, only through a p-type semiconductor region.

[0041] As in Fig. As shown in Figure 3, the source pad electrode 4 is connected to the first relaxation region 3, in particular through the high concentration region 6, the base region 7, and the connection region 9. To achieve such an electrical connection in a region between the base region 7 and the bottom surface of the first trench 12, the connection region 9 is arranged adjacent to the lateral surface of the first trench 12.

[0042] As described above, the connection region 9 is p-type and preferably has an acceptor concentration of 1 × 10 14 cm-3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and the thickness of the connecting region 9 do not have to be uniform. In the layer layout, a plurality of connecting regions 9 may be arranged separately from one another.

[0043] Although in Fig. 3, the connecting region 9 is arranged on both sides of the first trench 12, it is also possible for the connecting region 9 to be arranged only on one of the two sides. Furthermore, an arrangement of one connecting region 9 arranged on one side of the first trench 12 and an arrangement of the other connecting region 9 arranged on the other side of the first trench 12 can be different in the longitudinal direction of the first trench 12.

[0044] The gate pad electrode 14 is arranged in the non-element region RN and is electrically connected to the gate electrode 1 by means of an ohmic junction or a Schottky junction. To achieve this electrical connection, the gate electrode 1 has, for example, a region extending from the element region RE to the non-element region RN, and this extending region is in contact with the gate pad electrode 14 in the non-element region RN. In this way, an ohmic contact or a Schottky contact is arranged between the gate pad electrode 14 and the gate electrode 1.

[0045] In the non-element region RN, an upper surface (a surface in which the second trench 112 is arranged) of the epitaxial layer 30 is insulated from the gate pad electrode 14 by the interlayer insulating layer 5.

[0046] The second trench 112 ( Fig. 4) is arranged in the non-element region RN. The second trench 112 has a side surface and a bottom surface. In the present embodiment, it is possible for the side surface of the second trench 112 to face only the drift layer 10. The second trench 112 may have a depth that is the same as the depth of the first trench 12. As shown in Fig. 4, in the present embodiment, a plurality of second trenches 112 are arranged at intervals.

[0047] It should be noted that the majority of second trenches 112 like those in Fig. 4 can be interconnected in a specific cross-section in the plane layout. It is preferred that the distances at which the second trenches 112 are arranged are equal to or less than those at which the first trenches 12 are arranged.

[0048] The second relaxation region 103 is arranged below the second trench 112 and is in contact with the drift layer 10. Typically, the second relaxation region 103 is in contact with the bottom surface of the second trench 112. The second relaxation region 103 is p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and thickness of the second relaxation region 103 do not have to be uniform. The second relaxation region 103 may also have an acceptor concentration that is the same as the acceptor concentration of the first relaxation region 3.

[0049] It should be noted that, in the present embodiment, it is preferable that the second relaxation region 103 be electrically connected to the source pad electrode 4, but the second relaxation region 103 may also be insulated from the source pad electrode 4. Furthermore, it is preferable that the second relaxation region 103 be electrically connected to the first relaxation region 3, but the second relaxation region 103 may also be insulated from the first relaxation region 3. Furthermore, the second relaxation region 103 may be directly connected to the first relaxation region 3.

[0050] The insulating layer 102 on the inner surface is arranged on the lateral surface and on the bottom surface of the second trench 112. The thickness (the horizontal dimension according to Fig. 4) the insulating layer 102 on the inner surface on the lateral surface of the second trench 112 is, for example, equal to or greater than 10 nm and equal to or less than 300 nm. The thickness (the vertical dimension according to Fig. 4) The thickness of the insulating layer 102 on the inner surface of the bottom surface of the second trench 112 is, for example, 10 nm or greater and 300 nm or less. The insulating layer 102 on the inner surface is mainly composed of, for example, silicon dioxide.

[0051] The material of the insulating layer 102 on the inner surface may be the same material as that of the gate insulating layer 2 ( Fig. 2: First Embodiment). Furthermore, the thickness of the insulating layer 102 on the inner surface disposed on the lateral surface of the second trench 112 may be the same as the thickness of the gate insulating layer 2 disposed on the lateral surface of the first trench 12. Furthermore, the thickness of the insulating layer 102 on the inner surface on the bottom surface of the second trench 112 may be the same as the thickness of the gate insulating layer 2 on the bottom surface of the first trench 12.

[0052] At least a portion of the low-resistance region 101 is disposed in the second trench 112 through the insulating layer 102 on the inner surface. The low-resistance region 101 is made of a metal or a doped semiconductor. In other words, the low-resistance region 101 is made of a conductor. Accordingly, the low-resistance region 101 may have a low electrical resistivity. A material of the low-resistance region 101 may be the same material as that of the gate electrode 1 ( Fig. 2: First Embodiment). The low-resistance region 101 is electrically insulated from the gate pad electrode 14 by the interlayer insulating layer 5.

[0053] Note that, in the present embodiment, it is preferable that the low-resistance region 101 be electrically connected to the source pad electrode 4, but the low-resistance region 101 may be isolated from the source pad electrode 4. In the latter case, a floating potential may be employed as the potential of the low-resistance region 101 by disposing the low-resistance region 101 so that it is not connected to other elements.

[0054] The drain electrode 104 is formed on a surface (a lower surface according to Fig. 2 to Fig. 4) of the substrate 11, which is opposite a surface on which the drift layer 10 is disposed. In this way, the drain electrode 104 is electrically connected to the n-type drift layer 10 through the n-type substrate 11.

[0055] In particular, at least one barrier layer (in the present embodiment, two barrier layers) forming an ohmic junction or a barrier layer forming a Schottky junction is arranged between the drain electrode 104 and the drift layer 10. It should be noted that the junction region between the drain electrode 104 and the drift layer 10 may comprise a silicide.

[0056] It should be noted that in the present embodiment, the first conductivity type is an n-type and the second conductivity type is a p-type. However, in a modification, these conductivity types may be reversed. In such a case, the terms "donor concentration" and "acceptor concentration" used in the above description with respect to impurity concentrations are to be interchanged. Furthermore, the Fig. 1 is merely illustrative, and any arrangement can be used for the non-element area RN in the layer layout. Effects

[0057] According to the present embodiment, a capacitance is formed in the second trench 112 due to the arrangement of the low-resistance region 101 through the insulating layer 102 on the inner surface. The insulating layer 102 on the inner surface of the second trench 112 can be formed to have a small thickness while maintaining its insulation reliability. Thus, the capacitance per unit area can be increased.

[0058] As a result, at the time of high-speed switching of the MOSFET 701, a displacement current flowing through the second relaxation region 103 below the second trench 112 can be sufficiently branched into the low-resistance region 101 through sufficient capacitive coupling. This reduces the effective sheet resistance for the displacement current. Consequently, the magnitude of a potential drop due to the displacement current is reduced. Consequently, the magnitude of a voltage between a potential of the second relaxation region 103 and a gate potential due to the potential drop is reduced. Consequently, a dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is reduced.

[0059] From the above perspective, it is preferable that the capacitance formed by the inner surface insulating layer 102 be high. Accordingly, it is preferable that the thickness of the inner surface insulating layer 102 be as small as possible without sacrificing reliability. When the inner surface insulating layer 102 is formed in the same process as the gate insulating layer 2, the inner surface insulating layer 102 can be formed with high reliability and a small thickness.

[0060] Furthermore, sharing the same process can reduce manufacturing costs. In such a case, the thickness of the insulating layer 102 on the inner surface is formed to be substantially the same thickness as that of the gate insulating layer 2.

[0061] To increase the capacitance formed by the inner surface insulating layer 102, it is further preferable that the absolute dielectric constant of the inner surface insulating layer 102 be high. To this end, a material having an absolute dielectric constant higher than the absolute dielectric constant of silicon dioxide may be selected as a material for the inner surface insulating layer 102. Furthermore, a material having an absolute dielectric constant higher than the absolute dielectric constant of the material for the gate insulating layer 2 may be selected as a material for the inner surface insulating layer 102. modification

[0062] Fig. 5 is a partial cross-sectional view showing a configuration of a MOSFET 701V (silicon carbide unit) according to a modification of the first embodiment taken along a line VV in Fig. 6 shows schematically. Fig. 6 is a partial cross-sectional perspective view schematically illustrating a configuration of the MOSFET 701V without a partial configuration on the side of an upper surface.

[0063] In order to achieve an electrical connection between the source pad electrode 4 and the first relaxation region 3, a p-type semiconductor region, such as the connection region 9, connects the source pad electrode 4 and the first relaxation region 3 in the MOSFET 701 ( Fig. 3). In this modification ( Fig. 5), however, the source pad electrode 4 is in contact with the first relaxation region 3. As a result of this contact, an ohmic junction or a Schottky junction is arranged between the source pad electrode 4 and the first relaxation region 3.

[0064] This contact is achieved by a configuration in which a contact 15 extending into the interlayer insulating layer 5 is arranged in the source pad electrode 4 so as to reach the first relaxation region 3. The contact 15 can be arranged in a trench arranged in the epitaxial layer 30. The trench can be arranged in the element region RE and can be integrated with the first trench 12, as in the figure.

[0065] It should be noted that in the Fig. 5, a plurality of first relaxation regions 3 are separated from one another, but are connected to one another in the plane layout. Second embodiment

[0066] Fig. 7 is a plan view schematically illustrating a configuration of a MOSFET 702 (silicon carbide semiconductor device) according to a second embodiment. In the plan view, the MOSFET 702 has a contact region RC between the element region RE and the non-element region RN.

[0067] Fig. Figure 8 is a schematic partial cross-sectional view taken along a line VIII-VIII according to Fig. 7. In the contact region RC, a drift layer 10 having the n-type (the first conductivity type) and arranged on the substrate 11, a third trench 212 whose bottom surface reaches up to the drift layer 10, and a third relaxation region 203 are arranged.

[0068] In the present embodiment, the third trench 212 is arranged in the epitaxial layer 30 at least in a region of the contact region RC. The third trench 212 has a side surface and a bottom surface. The third trench 212 may have a depth that is the same as the depth of the first trench 12.

[0069] The MOSFET 702 includes a third relaxation region 203 located in the contact region RC. Specifically, the third relaxation region 203 is located below the third trench 212 and is in contact with the drift layer 10. Typically, the third relaxation region 203 is in contact with the bottom surface of the third trench 212. The third relaxation region 203 is p-type. The third relaxation region 203 may have an acceptor concentration that is the same as the acceptor concentration of the first relaxation region 3.

[0070] The third relaxation region 203 is electrically connected to the second relaxation region 103. In particular, the third relaxation region 203 is in the cross section according to Fig. 8 is separated from the second relaxation region 103, but is connected to the second relaxation region 103 in the plane layout. It should be noted that it is preferable that the third relaxation region 203 is connected to the first relaxation region 3 in the plane layout, but the third relaxation region 203 does not have to be connected to the first relaxation region 3.

[0071] The third relaxation region 203 is electrically connected to the source pad electrode 4. To achieve this electrical connection, the source pad electrode 4 in the third trench 212 typically has a contact 215 extending into the interlayer insulating layer 5 and reaching the third relaxation region 203. When the contact 215 is in contact with the third relaxation region 203, the source pad electrode 4 and the third relaxation region 203 are connected by means of an ohmic junction or a Schottky junction. It should be noted that the source pad electrode 4 may have a silicide in the transition region between the source pad electrode 4 and the third relaxation region 203.

[0072] The above configuration enables electrical connection of the second relaxation region 103 to the source pad electrode 4. In particular, the second relaxation region 103 having the p-type is connected to the source pad electrode 4 only through the third relaxation region 203 having the p-type.

[0073] It should be noted that a portion of the gate electrode 1 and a portion of the gate pad electrode 14 may be arranged in contact with each other in the third trench 212. In this way, an electrical connection between the gate electrode 1 and the gate pad electrode 14 is achieved.

[0074] The configuration except those described above is substantially the same as the configuration of the first embodiment described above, and thus the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0075] According to the present embodiment, the second relaxation region 103 is connected to the source pad electrode 4 through the third relaxation region 203. In this way, a displacement current flowing at a high speed in the second relaxation region 103 at the time of switching can be caused to sufficiently flow toward or away from the source pad electrode 4. Consequently, the magnitude of a potential drop due to the displacement current is further reduced.

[0076] As a result, the magnitude of a voltage between a potential of the second relaxation region 103 and a gate potential is further reduced due to the potential drop. Consequently, dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is more reliably reduced.

[0077] It should be noted that the Fig. 7 is merely illustrative, and any arrangement for the non-element region RN may be used in the layer layout. Furthermore, the configuration for achieving electrical connection between the source pad electrode 4 and the second relaxation region 103 is not limited to the one shown in Fig. 8, and these may, for example, be in contact with each other. Third embodiment

[0078] Fig. 9 is a partial cross-sectional view of a configuration of a MOSFET 703 (silicon carbide semiconductor device) according to a third embodiment, which is shown in a cross section similar to that taken along the line VIII-VIII in Fig. 7. In the top view (see Fig. 7) the MOSFET 703 has a contact region RC between the element region RE and the non-element region RN, in which a region of the region 101 with a low resistance ( Fig. 9). When configured according to Fig. 9, the low resistance region 101 comprises a region disposed in the third trench 212 disposed in the contact region RC, and this region is connected to a region of the low resistance region 101 disposed in the second trench 112.

[0079] In the contact region RC, the low-resistance region 101 and the source pad electrode 4 are electrically connected. To achieve this electrical connection, the source pad electrode 4 typically has a contact 216 in the contact region RC that extends into the interlayer insulating layer 5 and reaches the low-resistance region 101. When the contact 216 is in contact with the low-resistance region 101, an ohmic junction or a Schottky junction is arranged between the source pad electrode 4 and the low-resistance region 101. In this way, the low-resistance region 101 and the source pad electrode 4 are electrically connected in the contact region RC.

[0080] It should be noted that contact 215 ( Fig. 8: Second Embodiment) is not arranged in the present embodiment. It should be noted that the third relaxation region 203 is electrically connected to the second relaxation region 103, similar to the second embodiment. In particular, the third relaxation region 203 is shown in the cross section according to Fig. 9 separated from the second relaxation region 103, but is connected to the second relaxation region 103 in the layer layout.

[0081] It should be noted that it is preferable that the third relaxation region 203 is connected to the first relaxation region 3 in the layer layout, but the third relaxation region 203 does not have to be connected to the first relaxation region 3.

[0082] The configuration except those described above is substantially the same as the configuration of the first or second embodiment described above, and thus the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0083] According to the present embodiment, the low-resistance region 101 is electrically connected to the source pad electrode 4. Thus, when a displacement current flowing at a high speed in the second relaxation region 103 at the time of switching flows through a capacitive coupling of the insulating layer 102 on the inner surface in the low-resistance region 101, the current can be caused to sufficiently flow toward or away from the source pad electrode 4.

[0084] As a result, the magnitude of a potential drop due to the displacement current is further reduced. Consequently, the magnitude of a voltage between the potential of the second relaxation region 103 and the gate potential is further reduced due to the potential drop. Consequently, dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is more reliably reduced. Fourth embodiment

[0085] Fig. 10 is a partial cross-sectional view of a configuration of a MOSFET 704 (silicon carbide semiconductor device) according to a fourth embodiment, which is shown in a cross section similar to that taken along the line VIII-VIII in FIG. Fig. 7. Similar to the MOSFET 703 ( Fig. 8: third embodiment), in the MOSFET 704, a region of the region 101 with a low resistance is arranged in the contact region RC.

[0086] When the contact 216 is in contact with the low-resistance region 101 in the contact region RC, an ohmic junction or a Schottky junction is arranged between the source pad electrode 4 and the low-resistance region 101. Furthermore, the low-resistance region 101 and the source pad electrode 4 in the MOSFET 704 ( Fig. 10) are electrically connected by contact 215 in contact region RC. As described above, MOSFET 704 includes both contact 215 described in the second embodiment and contact 216 described in the third embodiment.

[0087] This configuration produces effects similar to those of both the second and third embodiments. Note that the configuration, except for those described above, is substantially the same as the configuration of the second or third embodiment described above. Thus, the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated. Fifth embodiment

[0088] Fig. 11 is a partial cross-sectional view illustrating a configuration of a MOSFET 705 (silicon carbide device) according to a fifth embodiment in the non-element region RN. The MOSFET 705 has a configuration in which a first impurity region 107 having the p-type is added to the configuration of the first embodiment ( Fig. 4) is added. The first impurity region 107 is disposed on the drift layer 10 in the non-element region RN. In the present embodiment, the first impurity region 107 is disposed on a surface of the epitaxial layer 30 and is covered with the interlayer insulating layer 5.

[0089] It is preferable that the first impurity region 107 is connected to the source pad electrode 4, but the first impurity region 107 does not have to be connected to the source pad electrode 4. Furthermore, it is preferable that the first impurity region 107 is connected to the base region 7, but the first impurity region 107 does not have to be connected to the base region 7. It is preferable that the first impurity region 107 has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 has.

[0090] Note that the acceptor concentration and thickness of the first impurity region 107 do not need to be uniform. The configuration other than those described above is substantially the same as the configuration of the first to fourth embodiments described above, and thus, the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0091] According to the present embodiment, due to the arrangement of the first impurity region 107, an electric field applied to the interlayer insulating layer 5 and the insulating layer 102 on the inner surface can be reduced at the time of turning off the MOSFET 705. Consequently, dielectric breakdown thereof can be reduced.

[0092] Further, at the time of switching the MOSFET 705 at a high speed, a displacement current flowing in the low resistance region 101 and the second relaxation region 103 also flows in the first impurity region 107 through a capacitive coupling of the insulating layer 102 on the inner surface. Consequently, the magnitude of a potential drop along the second relaxation region 103 is reduced.

[0093] As a result, the magnitude of a voltage between a potential of the second relaxation region 103 and a gate potential is reduced due to the potential drop. Consequently, the dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is reduced. Sixth embodiment

[0094] Fig. 12 is a partial cross-sectional view illustrating a configuration of a MOSFET 706 (silicon carbide semiconductor device) according to a sixth embodiment in the non-element region RN. The MOSFET 706 includes a connection region 109. The connection region 109 is disposed adjacent to the side surface of the second trench 112 and is connected to the second relaxation region 103 and the first impurity region 107.

[0095] The connection region 109 is p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the MOSFET 706, as shown in Fig. 12, may have a cross-section in which the connecting region 109 is not arranged. Although the connecting region 109 in Fig. 12 is arranged on both sides of the second trench 112, it is further possible that the connecting region 109 is arranged only on one of the two sides thereof.

[0096] Furthermore, the arrangement of one connection region 109 located on one side of the second trench 112 and the arrangement of the other connection region 109 located on the other side of the second trench 112 may differ in the longitudinal direction of the second trench 112. The acceptor concentration and the thickness of the connection region 109 do not need to be uniform.

[0097] It should be noted that the configuration except those described above is substantially the same as the configuration of the fifth embodiment described above, and thus the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0098] The present embodiment produces effects similar to those of the fifth embodiment. Furthermore, at the time of high-speed switching of the MOSFET 706, a displacement current flowing in the low-resistance region 101 and the second relaxation region 103 also flows in the connection region 109.

[0099] As a result, the magnitude of a potential drop along the second relaxation region 103 is reduced. Consequently, the magnitude of a voltage between a potential of the second relaxation region 103 and a gate potential is reduced due to the potential drop. Consequently, a dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is reduced.

[0100] Fig. 13 is a partial cross-sectional view of a configuration of a MOSFET 706V (silicon carbide device) according to a modification of the sixth embodiment, which is shown in a cross section similar to that taken along the line VIII-VIII in Fig. 7. In this modification, the configuration described above is Fig. 12 in the second embodiment ( Fig. 8) is inserted, and a connection region 109V is arranged. The connection region 109V is arranged on a side surface of the third trench 212 opposite the non-element region RN. The connection region 109V connects the third relaxation region 203 and the first impurity region 107 to each other.

[0101] The connecting region 109V is p-type. It is preferable that the acceptor concentration of the connecting region 109V is in a range of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 falls, and the acceptor concentration may be the same as that of the connection region 109. It should be noted that the acceptor concentration and the thickness of the connection region 109V do not need to be uniform.

[0102] According to this modification, a displacement current flowing in the second relaxation region 103 can flow through the connection region 109, the first impurity region 107, and the connection region 109V into the third relaxation region 203. Consequently, the current can flow into the source pad electrode 4 in the contact 215 in contact with the third relaxation region 203. Consequently, the magnitude of a potential drop along the second relaxation region 103 can be further reduced. Seventh embodiment

[0103] Fig. 14 is a partial cross-sectional view illustrating a configuration of a MOSFET 707 (silicon carbide device) according to a seventh embodiment in the non-element region RN. The MOSFET 707 has a configuration in which a second impurity region 108 having the n-type is added to the configuration of the fifth embodiment ( Fig. 11). The second impurity region 108 is arranged on the first impurity region 107. In other words, the first impurity region 107 is arranged on the drift layer 10 at a position immediately below the second impurity region 108. It is preferable that the second impurity region 108 has a donor concentration of 1 × 10 18 cm -3 up to 1 × 10 20 cm -3 has.

[0104] It should be noted that the donor concentration and thickness of the second impurity region 108 do not need to be uniform. Furthermore, it is preferable that the second impurity region 108 be connected to the source pad electrode 4, but the second impurity region 108 does not need to be connected to the source pad electrode 4.

[0105] The configuration except those described above is substantially the same as the configuration of the fifth or sixth embodiment described above, and thus the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0106] According to the present embodiment, a displacement current flowing at a high speed in the low resistance region 101 and the second relaxation region 103 at the time of switching the MOSFET 707 can flow into the first impurity region 107 and the second impurity region 108 through a capacitive coupling of the inner surface insulating layer 102.

[0107] Specifically, when the second impurity region 108 is connected to the source pad electrode 4, electrons can flow from the second impurity region 108 into the source pad electrode 4. Even when the second impurity region 108 is not connected to the source pad electrode 4, electrons can further flow through the second impurity region 108 and the first impurity region 107 in this order and flow into the source pad electrode 4.

[0108] As a result, the magnitude of a potential drop along the second relaxation region 103 can be further reduced. Consequently, the magnitude of a voltage between the potential of the second relaxation region 103 and the gate potential due to the potential drop is further reduced. Consequently, dielectric breakdown between the second relaxation region 103 and a region having the gate potential, i.e., the gate pad electrode 14, is more reliably reduced. Eighth embodiment

[0109] Fig. 15 is a partial plan view illustrating a configuration of the epitaxial layer 30 of a MOSFET 708 (silicon carbide device) according to an eighth embodiment in the non-element region RN. Fig. 16 is a partial cross-sectional view taken along a line XVI-XVI according to Fig. 15.

[0110] In the present embodiment, a plurality of second trenches 112 are arranged at intervals. In particular, Fig. 15 each of them in the vertical direction, and in the horizontal direction they are separated from each other at intervals. The second relaxation region 103 is arranged below the second trench 112, and in particular, it is arranged on the bottom surface thereof. In this way, the plurality of second relaxation regions 103 are arranged so as to be separated from each other.

[0111] In Fig. 15, each of them extends in the vertical direction, and in the horizontal direction, they are separated from each other by the drift layer 10. Note that the configuration except those described above is substantially the same as the configuration of the first to seventh embodiments described above, and thus, the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0112] According to the present embodiment, as shown in Fig. As shown in Figure 15, a simple layer layout can be used as the layer layout of the non-element area RN. In particular, a line-and-space layer layout can be used, which has a field in one direction (the horizontal direction in Fig. 15). This allows for improved reliability of the MOSFET. Ninth embodiment

[0113] Fig. 17 is a partial plan view illustrating a configuration of the epitaxial layer 30 of a MOSFET 709 (silicon carbide device) according to a ninth embodiment in the non-element region RN. Fig. 18 is a partial cross-sectional view taken along a line XVIII-XVIII according to Fig. 17.

[0114] In the MOSFET 709, the second relaxation region 103 includes a plurality of extending relaxation regions 103X and at least one junction relaxation region 103Y. The plurality of extending relaxation regions 103X are separated from each other, and each of them extends in one direction (the vertical direction in the figure). The junction relaxation region 103Y connects adjacent ones of the plurality of extending relaxation regions 103X to each other. In the MOSFET 709, the junction relaxation region 103Y is arranged in all of the adjacent pairs of the extending relaxation regions 103X.

[0115] Fig. 19 is a partial plan view of a configuration of the epitaxial layer 30 of a MOSFET 709V (silicon carbide device) according to a modification of the ninth embodiment in the non-element region RN when viewed from a viewing angle similar to that of FIG. Fig. 17. In the MOSFET 709V, the junction relaxation region 103Y is arranged only in at least one of adjacent pairs of the extending relaxation regions 103X.

[0116] The configuration except those described above is substantially the same as the configuration of the eighth embodiment described above, and thus the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated.

[0117] According to the present embodiment, the junction relaxation region 103Y is disposed in the second relaxation region 103. This reduces the unevenness of the distribution of a displacement current flowing in the low-resistance region 101 and the second relaxation region 103 in the non-element region RN at the time of high-speed switching.

[0118] As a result, the uneven distribution of the height of a potential drop along the second relaxation region 103 is reduced. Consequently, a local increase in voltage between the second relaxation region 103 and the gate pad electrode 14 due to the potential drop is reduced. Consequently, dielectric breakdown between the second relaxation region 103 and the gate pad electrode 14 is more reliably reduced. Tenth embodiment

[0119] Fig. 20 is a partial plan view illustrating a configuration of the epitaxial layer 30 of a MOSFET 710 (silicon carbide device) according to a tenth embodiment in the non-element region RN. In the present embodiment, each of the extending relaxation regions 103X includes a plurality of regions separated from each other in its extension direction (the vertical direction in the figure). In other words, each of the extending relaxation regions 103X does not extend continuously, but extends discretely.

[0120] The configuration except those described above is substantially the same as the configuration of the ninth embodiment described above ( Fig.19), and thus, the same or corresponding elements are denoted by the same reference numerals, and a description thereof will not be repeated. The present embodiment also produces effects similar to those of the ninth embodiment due to the arrangement of the connection relaxation region 103Y. LIST OF REFERENCE SYMBOLS RC contact area RE element area RN non-element area 1 gate electrode 2 Gate insulating layer 3 first relaxation area 4 Source contact electrode 5 Intermediate insulation layer 6 Area with a high concentration 7 Basic area 8 Source area 109 Connection area 10 Drift layer 11 Substrate (silicon carbide semiconductor substrate) 12 first ditch 14 Gate contact electrode 30 epitaxial layer 101 Area with low resistance 102 Insulating layer on the inner surface 103 second relaxation region 104 Drain electrode 107 first defect area 108 second defect area 112 second ditch 203 third relaxation area 212 third ditch 701 to 710, 701V, 706V, 709V MOSFET (silicon carbide semiconductor device)

Claims

[1] A silicon carbide semiconductor device (701 to 710, 701V, 706V, 709V) comprising an element region (RE) disposed on a silicon carbide semiconductor substrate (11) and a non-element region (RN) disposed outside the element region (RE), wherein a gate pad electrode (14) connected to the outside region and supplied with a gate voltage from the outside region is disposed in the non-element region (RN), wherein the silicon carbide semiconductor unit (701 to 710, 701V, 706V, 709V) has a drift layer (10) in the element region (RE) and the non-element region (RN) which has a first conductivity type and is arranged on the silicon carbide semiconductor substrate (11), and further comprises in the element area (RE) the following: - a first trench (12), the bottom surface of which extends to the drift layer (10); and - a gate electrode (1) arranged in the first trench (12) through a gate insulating layer (2) and electrically connected to the gate pad electrode (14), and further comprises in the non-element region (RN): - at least one second trench (112) whose bottom surface extends to the drift layer (10); - at least one second relaxation region (103) having a second conductivity type and arranged below the at least one second trench (112); - an insulating layer (102) on an inner surface arranged on a lateral surface and on the bottom surface of the at least one second trench (112); and - a low resistance region (101) disposed by the insulating layer (102) on the inner surface in the at least one second trench (112) and electrically insulated from the gate pad electrode (14). [2] Silicon carbide semiconductor device (701 to 710, 701V, 706V, 709V) according to claim 1, which further comprises in the element area (RE): - a base region (7) having the second conductivity type and arranged on the drift layer (10); - a source region (8) having the first conductivity type and arranged on the base region (7); - a first relaxation region (3) having the second conductivity type and arranged below the first trench (12); and - a source contact electrode (4) electrically connected to the source region (8) and the first relaxation region (3), wherein the first trench (12) penetrates the source region (8) and the base region (7). [3] The silicon carbide semiconductor device (702, 704, 706V) according to claim 1 or 2, further comprising a contact region (RC) between the element region (RE) and the non-element region (RN), further comprising in the contact region (RC): - the drift layer (10) having the first conductivity type and arranged on the silicon carbide semiconductor substrate (11); - a third trench (212), the bottom surface of which extends to the drift layer (10); and - a third relaxation layer (203) having the second conductivity type is arranged below the third trench (212) and is electrically connected to the source contact point electrode (4) and the at least one second relaxation region (103). [4] The silicon carbide semiconductor device (704) according to claim 3, wherein a portion of the low resistance region (101) is disposed in the contact region (RC), and the low resistance region (101) and the source pad electrode (4) are electrically connected in the contact region (RC). [5] Silicon carbide semiconductor device (703, 704) according to claim 1 or 2, which further comprises a contact region (RC) between the element region (RE) and the non-element region (RN), wherein a portion of the low resistance region (101) is arranged in the contact region (RC), and the low resistance region (101) and the source pad electrode (4) in the contact region (RC) are electrically connected. [6] The silicon carbide semiconductor device (701 to 710, 701V, 706V, 709V) according to any one of claims 1 to 5, wherein the thickness of the gate insulating layer (2) disposed on a side surface of the first trench (12) and the thickness of the insulating layer (102) on the inner surface disposed on the side surface of the at least one second trench (112) are the same. [7] Silicon carbide semiconductor device (705, 706, 706V) according to one of claims 1 to 6, further comprising a first impurity region (107) having the second conductivity type and disposed on the drift layer (10) in the non-element region (RN). [8] The silicon carbide semiconductor device (706, 706V) according to claim 7, further comprising a connection region (109) having the second conductivity type, disposed adjacent to the lateral surface of the at least one second trench (112), and connected to the at least one second relaxation region (103) and the first impurity region (107). [9] The silicon carbide semiconductor device (707) according to claim 7 or 8, further comprising a second impurity region (108) having the first conductivity type and disposed on the first impurity region (107). [10] The silicon carbide semiconductor device (708) according to any one of claims 1 to 9, wherein the at least one second relaxation region (103) comprises a plurality of second relaxation regions (103), and the plurality of second relaxation regions (103) are arranged to be separated from each other. [11] The silicon carbide semiconductor device (709, 709V) according to any one of claims 1 to 9, wherein the at least one second relaxation region (103) comprises a plurality of extending relaxation regions (103X) separated from each other, and a connecting relaxation region (103Y) connecting adjacent ones of the plurality of extending relaxation regions (103X) to each other. [12] Silicon carbide semiconductor device (701 to 710, 701V, 706V, 709V) according to one of claims 1 to 11, wherein the first trench (12) and the at least one second trench (112) have the same depth. [13] The silicon carbide semiconductor device (701 to 710, 701V, 706V, 709V) according to any one of claims 1 to 12, wherein the at least one second trench (112) comprises a plurality of second trenches (112), and the plurality of second trenches (112) are arranged in the non-element region (RN).

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